Image correction method and apparatus

Abstract

The present application relates to the technical field of image processing, and discloses an image correction method and device, which comprises the following steps: obtaining original coordinate data of original pixels belonging to different first categories; determining correction coordinate data of correction pixels corresponding to the original pixels, and determining second categories to which the correction pixels belong according to a classification rule; according to the first categories to which the original pixels belong and the second categories to which the corresponding correction pixels belong, caching the coordinate data to corresponding first storage spaces; taking the first storage spaces corresponding to the same second category in each first storage space group as a group, respectively obtaining each group of to-be-processed coordinate data, respectively determining correction pixel values corresponding to each correction pixel, and generating a correction image according to the correction pixel values. The present application realizes acceleration of each processing path by using N*N first storage spaces, effectively avoids the problem of blocking, realizes an acceleration effect close to N times, and can save on-chip storage resources.

Description

Technical Field

[0001] This invention relates to the field of image processing technology, and more specifically to image correction methods and apparatus. Background Technology

[0002] Image distortion is mainly caused by factors such as camera lens distortion and non-ideal optical imaging, which leads to various deformations and distortions in the image. These deformations and distortions may affect the accuracy and reliability of the image.

[0003] Current image distortion correction algorithms are mostly deployed using ASIC (Application Specific Integrated Circuit) chips. This approach simplifies algorithm development, but achieving high processing speeds requires high-end chips. However, image distortion correction is typically only one part of an image processing project. In image processing projects based on programmable logic devices such as FPGA (Field Programmable Gate Array), using an ASIC+FPGA solution presents significant challenges due to the high computational demands of implementing high-speed distortion correction algorithms. This heterogeneous approach not only results in high complexity but also high cost. Summary of the Invention

[0004] In view of this, the present invention provides an image correction method and apparatus to solve the problem that programmable logic devices require a lot of resources to correct distortion.

[0005] In a first aspect, the present invention provides an image correction method applied to a programmable logic device, the method comprising:

[0006] Obtain the original coordinate data of the original pixels belonging to different first categories; the first category to which the original pixels belong is determined by classifying the original coordinate data of the original pixels according to a preset classification rule;

[0007] Based on the original coordinate data of the original pixel, the correction coordinate data of the correction pixel corresponding to the original pixel after distortion correction is determined, and the correction coordinate data of the correction pixel is classified according to the classification rules to determine the second category to which the correction pixel belongs.

[0008] Based on the first category to which the original pixel belongs and the second category to which the corresponding corrected pixel belongs, the corresponding coordinate data is cached in the corresponding first storage space; wherein, a corresponding first storage space group is pre-configured for each first category, and the first storage space group includes the first storage space corresponding to each second category; the coordinate data includes the original coordinate data of the original pixel and the corrected coordinate data of the corrected pixel;

[0009] Take the first storage space of the same second category in each of the first storage space groups as a group, and obtain the coordinate data to be processed in each group of the first storage space;

[0010] Based on the coordinate data to be processed in each group, the correction pixel value corresponding to each correction pixel is determined, and the correction image is generated based on the correction pixel value.

[0011] In a second aspect, the present invention provides an image correction device applied to a programmable logic device, the device comprising:

[0012] The coordinate acquisition module is used to acquire the original coordinate data of original pixels belonging to different first categories; the first category to which the original pixel belongs is determined by classifying the original coordinate data of the original pixel according to a preset classification rule;

[0013] The classification module is used to determine the correction coordinate data of the correction pixel corresponding to the original pixel after distortion correction based on the original coordinate data of the original pixel, and to classify the correction coordinate data of the correction pixel according to the classification rules to determine the second category to which the correction pixel belongs.

[0014] A coordinate caching module is used to cache the corresponding coordinate data to a corresponding first storage space according to the first category to which the original pixel belongs and the corresponding second category to which the corrected pixel belongs; wherein, a corresponding first storage space group is pre-configured for each first category, and the first storage space group includes a first storage space corresponding to each second category; the coordinate data includes the original coordinate data of the original pixel and the corrected coordinate data of the corrected pixel;

[0015] The group acquisition module is used to acquire the coordinate data to be processed in each group of first storage spaces, taking the first storage spaces of the same second category in each first storage space group as a group;

[0016] The processing module is used to determine the correction pixel value corresponding to each correction pixel according to the coordinate data to be processed in each group, and generate a correction image according to the correction pixel value.

[0017] Thirdly, the present invention provides a programmable logic device, comprising: a memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the computer instructions to perform the image correction method described in the first aspect or any corresponding embodiment thereof.

[0018] Fourthly, the present invention provides a computer-readable storage medium storing computer instructions for causing a computer to perform the image correction method described in the first aspect or any corresponding embodiment thereof.

[0019] Fifthly, the present invention provides a computer program product, including computer instructions for causing a computer to execute the image correction method described in the first aspect or any corresponding embodiment thereof.

[0020] This invention categorizes original pixels in the original image into N classes based on their coordinate data, enabling parallel distortion correction processing at a parallelism of N. This eliminates the need to store N copies of the original image, significantly reducing storage resources. Furthermore, for irregularly shaped correction pixels after distortion correction, N×N primary storage spaces are used to accelerate each processing path, effectively avoiding blocking issues and achieving parallel processing. The programmable logic device as a whole can essentially perform distortion correction on the original image at N times the speed, achieving a speedup of nearly N times. Moreover, while achieving multi-fold parallel distortion correction processing, it saves on-chip storage resources, making programmable logic devices such as FPGAs suitable for distortion correction processing of large-size, high-frame-rate images. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the specific embodiments or related technologies of the present invention, the drawings used in the description of the specific embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0022] Figure 1 This is a schematic flowchart of an image correction method according to an embodiment of the present invention;

[0023] Figure 2 This is a schematic diagram of cached coordinate data according to an embodiment of the present invention;

[0024] Figure 3 This is a schematic flowchart of another image correction method according to an embodiment of the present invention;

[0025] Figure 4 This is a system architecture diagram of a programmable logic device according to an embodiment of the present invention;

[0026] Figure 5 This is a detailed flowchart of an image correction method according to an embodiment of the present invention;

[0027] Figure 6 This is a structural block diagram of an image correction device according to an embodiment of the present invention;

[0028] Figure 7 This is a schematic diagram of the hardware structure of a programmable logic device according to an embodiment of the present invention. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0030] FPGA-based real-time image distortion correction systems are widely used in machine vision, UAV remote sensing, and other fields due to their high parallel processing capabilities and fast response.

[0031] Traditional FPGA image distortion correction processing, due to limited hardware resources, often employs single-speed processing, which is slow and unsuitable for high-frame-rate, large-size, and highly distorted image processing scenarios. Because of the irregular coordinate mapping in distortion correction algorithms, parallel processing requires significantly more logic resources, such as lookup tables, BRAM (Block Random Access Memory), and URAM (Ultra Random Access Memory). For example, a 1920×1080 grayscale image with a maximum distortion range of 100 pixels requires at least 100 rows of pixels to be cached during single-speed processing, requiring approximately 47 x 36KB BRAMs. To achieve Nx parallel processing, N copies of the image need to be stored, requiring a total of 47 x N x 36KB BRAMs. Conventional FPGA chips struggle to meet these parallel processing requirements.

[0032] The image correction method provided in this invention classifies the original pixels in the original image into N categories according to their coordinate data, enabling the distortion correction process to be performed in parallel at a parallelism of N. This eliminates the need to store N copies of the original image, significantly reducing the required storage resources. Furthermore, for the irregular correction pixels after distortion correction, N×N first storage spaces are used to accelerate each processing path, effectively avoiding blocking issues and enabling parallel processing. The programmable logic device as a whole can basically perform distortion correction on the original image at N times the speed, achieving an acceleration effect of nearly N times.

[0033] According to an embodiment of the present invention, an image correction method embodiment is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0034] This embodiment provides an image correction method that can be applied to programmable logic devices with parallel processing capabilities, such as FPGA (Field Programmable Gate Array) and CPLD (Complex Programmable Logic Device). Figure 1 This is a flowchart of an image correction method according to an embodiment of the present invention, such as... Figure 1 As shown, the process includes the following steps.

[0035] Step S101: Obtain the original coordinate data of the original pixels belonging to different first categories; the first category to which the original pixels belong is determined by classifying the original coordinate data of the original pixels according to preset classification rules.

[0036] In this embodiment, the original image is a distorted image that needs to be corrected to remove the distortion; for example, the original image is an image obtained after being captured by a camera. The original image includes multiple pixels, which, for ease of description, are referred to as original pixels.

[0037] Furthermore, each original pixel corresponds to a specific position in the original image, which can be represented in the form of coordinates. Specifically, in the original image, each original pixel has a first coordinate in a first direction and a second coordinate in a second direction. Based on the first and second coordinates, the coordinate data of the original pixel, i.e., the original coordinate data, can be determined.

[0038] For example, if the first direction is the row direction and the second direction is the column direction, then the first coordinate is the row coordinate and the second coordinate is the column coordinate. Conversely, if the first direction is the column direction and the second direction is the row direction, then the first coordinate is the column coordinate and the second coordinate is the row coordinate.

[0039] To simplify the description, this embodiment mainly uses the first coordinate as the row coordinate and the second coordinate as the column coordinate as an example. Specifically, for the original pixel in the u-th row and v-th column of the original image, its original coordinate data can be represented as: (u,v); where u is the first coordinate (row coordinate) and v is the second coordinate (column coordinate).

[0040] In this embodiment, the parallelism N of the parallel distortion correction processing of the image is preset so that the programmable logic device can perform distortion correction processing on N original pixels in parallel. N ≥ 2, for example, N = 2, 3, 4, etc., and the specific value can be determined based on requirements such as image size, FPGA logic resources, and algorithm speed.

[0041] Furthermore, a classification rule is pre-configured for classifying the coordinate data, which is used to divide the coordinate data into N categories. Specifically, this classification rule is used to classify the original coordinate data of the original pixels to divide the original pixels into N categories, thereby determining the category corresponding to each original pixel, i.e., the first category.

[0042] Optionally, the classification rule is used to classify the first coordinate into N categories. For example, if the first coordinate is a row coordinate, the classification rule is used to classify the row coordinates of each pixel.

[0043] For example, when a programmable logic device acquires the original coordinate data of an original pixel, it can acquire the original coordinate data of one original pixel in each clock cycle. For the acquired original coordinate data, it can classify each acquired original coordinate data in turn according to the classification rule, so as to determine one of the N categories to which each original coordinate data belongs. This category is called the first category.

[0044] It is understandable that, since the parallelism of programmable logic devices is N, once the first category to which an original pixel belongs is determined, the original pixel can be processed according to the first category to which it belongs, without having to wait for the next original pixel to be classified.

[0045] Optionally, to facilitate rapid classification of programmable logic devices, classification can be implemented using a remainder method. Specifically, the classification rule is as follows: with N as the divisor, perform remainder operations on the first coordinate, and different remainders correspond to different categories.

[0046] For example, given the original coordinate data (u, v), performing a modulo operation on the first coordinate u yields a result u%N that can be 0, 1, 2, ..., N-1, allowing for simple and quick classification of the original pixels. Here, % represents the modulo operation. For instance, if N = 4, the original pixels correspond to four first categories: u%4 = 0, u%4 = 1, u%4 = 2, and u%4 = 3.

[0047] Step S102: Determine the correction coordinate data of the correction pixel corresponding to the original pixel after distortion correction based on the original coordinate data of the original pixel, and classify the correction coordinate data of the correction pixel according to the classification rules to determine the second category to which the correction pixel belongs.

[0048] In this embodiment, for each category of original pixels, the original coordinate data is distorted in parallel to determine the corresponding coordinate data. Specifically, for each category of original pixels, coordinate mapping is performed in parallel to determine the corrected coordinate data that has a mapping relationship with the original coordinate data. The corrected coordinate data represents the coordinate data of the corresponding pixel in the image generated after correcting the original image (hereinafter referred to as the corrected image). This pixel is called the corrected pixel, and its coordinate data is called the corrected coordinate data. Similar to the original coordinate data, the corrected coordinate data also includes coordinates in two directions; that is, the corrected coordinate data includes the first coordinate and the second coordinate of the corrected pixel.

[0049] By performing distortion correction on the original image, the corresponding correction pixel can be determined. The coordinate data of these two types of pixels have a mapping relationship. For example, if the original coordinates of the original pixel are (u,v), after coordinate mapping processing, the distortion-corrected coordinate data (iu,iv) corresponding to the original coordinate data (u,v) can be determined. This coordinate data (iu,iv) is the correction coordinate data of the correction pixel.

[0050] For example, coordinate mapping can be implemented based on a coordinate mapping formula, which may be as follows:

[0051]

[0052] Where, r 2 =u 2 +v 2 k1, k2, k3, p1, and p2 are all camera intrinsic parameters, which can be determined through calibration.

[0053] Furthermore, since camera intrinsic parameters are generally fixed, the mapping relationship between the original coordinates (u,v) and the corrected coordinates (iu,iv) of a specific camera is also fixed. Therefore, a mapping table for recording the mapping relationship between the coordinates of each pixel can be stored in advance, and the corresponding corrected coordinates (iu,iv) can be determined by looking up the table to achieve coordinate mapping processing.

[0054] This embodiment does not limit the method of coordinate mapping processing or the coordinate mapping formula used.

[0055] By classifying the original coordinate data, different categories of original coordinate data can be processed in parallel. However, since image distortion manifests as image compression or stretching, and the changes are more pronounced closer to the edge, the distortion model is non-linear. As shown in the coordinate mapping formula above, the mapping relationship between the two coordinates is non-linear. For a certain category (i.e., the first category) of original coordinate data, after performing non-linear coordinate mapping processing, the resulting corrected coordinate data is generally irregular, which will affect the speed of parallel processing.

[0056] Therefore, for correction pixels, the correction coordinate data is also classified according to the same classification rules, thus dividing correction pixels into N categories. For ease of distinction and description, the category to which the correction pixel belongs is called the second category. It can be understood that since the same classification rules are used to classify both original and correction pixels, the determined first and second categories are both one of the N categories; furthermore, because the mapping relationship is non-linear, for an original pixel belonging to a certain first category, its corresponding correction pixel may belong to any of the N categories in the second category.

[0057] Optionally, if the classification rule is used to divide the first coordinate into N categories, the second category to which the corrected pixel belongs is determined by classifying the first coordinate of the corrected pixel according to the classification rule. Specifically, the classification rule is: taking the remainder of the first coordinate by dividing by N.

[0058] For example, the classification rule is implemented using the above modulo operation. The original coordinate data (u,v) is mapped to the corrected coordinate data (iu,iv), and u%N represents the first category, and iu%N represents the second category. Assuming that the first category to which the original coordinate data (u,v) belongs is u%N=0, then the second category to which the corresponding corrected pixel belongs, iu%N, may be any value among 0, 1, 2, etc.

[0059] Step S103: Based on the first category to which the original pixel belongs and the second category to which the corresponding corrected pixel belongs, cache the corresponding coordinate data to the corresponding first storage space; wherein, a corresponding first storage space group is pre-configured for each first category, and the first storage space group includes the first storage space corresponding to each second category; the coordinate data includes the original coordinate data of the original pixel and the corrected coordinate data of the corrected pixel.

[0060] If the corrected pixels obtained from the original pixel mapping are directly processed, the corrected coordinate data of multiple corrected pixels can be determined in parallel, and the categories of corrected pixels are out of order. This means that within one processing cycle (e.g., one clock cycle), multiple corrected pixel data belonging to the same second category (e.g., iu%N=0) may be determined. This leads to blocking problems when processing the corrected pixel data of this second category (e.g., iu%N=0), and blocking problems will also occur for other second category corrected pixels, resulting in low overall processing speed and failing to achieve the parallel processing effect of N parallelism. In this embodiment, by reclassifying the corrected pixels and setting up multiple first storage spaces for each processing path, the blocking problem can be effectively solved.

[0061] Specifically, for each first category to which the original pixel belongs, a set containing multiple storage spaces can be pre-configured for each first category. For ease of description, these storage spaces are referred to as first storage spaces, and the set is referred to as a first storage space group. Furthermore, each first storage space in the first storage space group corresponds to a second category. As mentioned above, the number of types in both the first and second categories is N, so N first storage space groups can be pre-configured, and each first storage space group contains N first storage spaces, that is, a total of N×N first storage spaces can be pre-configured.

[0062] In this system, the first storage space group corresponds one-to-one with the first category, and the first storage space within the first storage space group corresponds one-to-one with the second category. Therefore, based on the first category to which the original pixel belongs, the first storage space group corresponding to the original pixel can be determined; and based on the second category to which the corrected pixel corresponding to the original pixel belongs, the first storage space corresponding to the corrected pixel within the first storage space group corresponding to the original pixel can be determined, thereby caching the original coordinate data of the original pixel and the corrected coordinate data of the corrected pixel into the corresponding first storage space. For ease of description, the original coordinate data of the original pixel and the corrected coordinate data of the corrected pixel are collectively referred to as coordinate data.

[0063] Step S104: Take the first storage space corresponding to the same second category in each first storage space group as a group, and obtain the coordinate data to be processed in each group of first storage spaces.

[0064] In this embodiment, although N×N first storage spaces are set, since the parallelism is N, at any given time, only N coordinate data are generally processed. Furthermore, since the camera distortion range is generally small (e.g., less than 2% for industrial cameras), the number of pixels belonging to each second category is not significantly different for all correction pixels. For example, the number of correction pixels with iu%4=0 is not significantly different from the number of correction pixels with iu%4=1 or iu%4=2. Therefore, for the N groups of first storage spaces, the first storage spaces corresponding to the same second category are grouped together. In this group, generally only one first storage space of the same second category stores the data to be processed. Then, the coordinate data (i.e., the coordinate data to be processed) in each group of first storage spaces is obtained according to the regrouping, and the coordinate data to be processed in each group is then processed in parallel.

[0065] Optionally, a second storage space can be set up for each second type, and the coordinate data to be processed can be cached based on the second storage space. Specifically, step S104, "taking the first storage spaces corresponding to the same second category in each first storage space group as a group, and obtaining the coordinate data to be processed from each group of first storage spaces," can include: taking the first storage spaces corresponding to the same second category in each first storage space group as a group, reading the coordinate data to be processed from each group of first storage spaces; and caching the read coordinate data to be processed to the corresponding second storage space; wherein, a corresponding second storage space is pre-configured for each second type.

[0066] In this embodiment, N second storage spaces can be pre-configured, each corresponding to a second category. The coordinate data to be processed from each group is read and cached in the corresponding second storage space for subsequent processing.

[0067] Figure 2 This illustrates a schematic diagram of cached coordinate data. For example... Figure 2 As shown, the parallelism N = 3, where A, B, and C represent three first categories, and a, b, and c represent three second categories. Three first storage space groups can be pre-configured: first storage space group A, first storage space group B, and first storage space group C. First storage space group A includes first storage spaces Aa, Ab, and Ac; similarly, first storage space group B includes first storage spaces Ba, Bb, and Bc; and first storage space group C includes first storage spaces Ca, Cb, and Cc. Furthermore, three second storage spaces are pre-configured: second storage space a, second storage space b, and second storage space c.

[0068] The classification is based on the remainder, with remainders of 0, 1, and 2 corresponding to the first column A, B, and C, respectively, and also to the second category a, b, and c. For example... Figure 2 As shown, the original coordinate data (u1, v1), (u2, v2), and (u3, v3) correspond to different first categories, and u1%3 = 0, u2%3 = 1, and u3%3 = 2. Therefore, the three original coordinate data correspond to the first storage space group A, the first storage space group B, and the first storage space group C, respectively. Furthermore, the three original coordinate data are mapped to the corrected coordinate data (iu1, iv1), (iu2, iv2), and (iu3, iv3), respectively.

[0069] Assuming iu1%3 = 1, iu2%3 = 0, and iu3%3 = 3, then the corrected coordinate data (iu1, iv1) belongs to the second type, second category (i.e., second category b), the corrected coordinate data (iu2, iv2) belongs to the first type, second category (i.e., second category a), and the corrected coordinate data (iu3, iv3) belongs to the third type, second category (i.e., second category c). Therefore, the three corrected coordinate data correspond to the first storage space Ab, the first storage space Ba, and the first storage space Cc, respectively. Thus, the corresponding coordinate data can be stored in these three first storage spaces. For example, the coordinate data stored in the first storage space Ab is: (u1, v1, iu1, iv1).

[0070] For the second storage space a, the first storage spaces Aa, Ba, and Ca can be read, thereby retrieving the coordinate data (u2, v2, iu2, iv2) from the first storage space Ba. Similarly, for the second storage space b, the first storage spaces Ab, Bb, and Cb can be read, thereby retrieving the coordinate data (u1, v1, iu1, iv1) from the first storage space Ab. For the second storage space c, the first storage spaces Ac, Bc, and Cc can be read, thereby retrieving the coordinate data (u3, v3, iu3, iv3) from the first storage space Cc.

[0071] In this embodiment, for each processing path, a first storage space group containing N first storage spaces is set up, which is equivalent to processing the data of the processing path at N times the speed, thereby effectively avoiding the blocking of a certain processing path; and the second storage space reads the first storage space belonging to the same second category. By using multi-level storage space, it is ensured that subsequent parallel processing is still performed at a parallelism of N, without increasing the required processing resources. Overall, it can achieve an acceleration effect of nearly N times.

[0072] Due to image distortion, at certain times, a second storage space may read coordinate data from multiple (usually a maximum of two) first storage spaces, requiring serial processing. However, since the distortion range of industrial cameras is relatively small (less than 2%), this situation is less likely to occur. Compared with the traditional parallel processing method that utilizes a large amount of storage resources, this method can still approach the speed of fully parallel processing to a considerable extent. The specific speed depends on the size of the image distortion, but it can generally achieve a processing speed of no less than 80% of the fully parallel rate. That is, it can achieve a near-fully parallel processing effect with less storage resources.

[0073] It should be noted that although this embodiment uses a relatively large amount of storage space, since both the first and second storage spaces are only used for caching data, and data that has already been read can be cleaned up in a timely manner, the size of each storage space can be very small and will not occupy too much storage resources. For example, both the first and second storage spaces can use a FIFO (First Input First Output) method to cache data.

[0074] Step S105: Determine the correction pixel value corresponding to each correction pixel based on the coordinate data to be processed in each group, and generate a correction image based on the correction pixel value.

[0075] In this embodiment, the coordinate data in each processing path is classified according to the second category corresponding to the first coordinate in the correction coordinate data. Therefore, for each type of correction coordinate data in the second category, the pixel value corresponding to each correction pixel can be determined in parallel processing, that is, the correction pixel value. Then, the image generated based on the correction pixel value of each correction pixel is the correction image, thus realizing the correction image after distortion removal from the original image.

[0076] The image correction method provided in this embodiment divides the coordinate data of the original pixels in the original image into N categories, enabling parallel distortion correction processing at a parallelism of N. This eliminates the need to store N copies of the original image, significantly reducing storage resources. Furthermore, for the irregular correction pixels after distortion correction, N×N first storage spaces are used to accelerate each processing path, effectively avoiding blocking issues and achieving parallel processing. The programmable logic device as a whole can essentially perform distortion correction on the original image at N times the speed, achieving a speedup effect close to N times. This method achieves multi-fold parallel distortion correction processing while saving on-chip storage resources, making programmable logic devices such as FPGAs suitable for distortion correction processing of large-size, high-frame-rate images.

[0077] This embodiment provides an image correction method that can be applied to programmable logic devices with parallel processing capabilities, such as FPGAs and CPLDs. Figure 3 This is a flowchart of an image correction method according to an embodiment of the present invention, such as... Figure 3 As shown, the process includes the following steps.

[0078] Step S301: Obtain the original coordinate data of the original pixels belonging to different first categories; the original coordinate data includes the first coordinate and the second coordinate of the original pixel; the first category to which the original pixel belongs is determined by classifying the first coordinate of the original pixel according to a preset classification rule; the classification rule is used to divide the first coordinate into N categories, where N is a parallelism of not less than 2.

[0079] Please see details Figure 1 Step S101 of the illustrated embodiment will not be described again here.

[0080] Optionally, when acquiring the original coordinate data of the original pixels, the original coordinate data of each original pixel in the original image can be acquired sequentially. For example, the original coordinate data of each original pixel in the original image can be acquired sequentially along the first direction, so that when classifying according to the first coordinate in the subsequent process, the continuously acquired original coordinate data can be divided into different processing paths to achieve parallel processing.

[0081] First, the original coordinate data of the original pixels in the original image to be corrected can be obtained; then, the first coordinates of the original pixels can be classified according to the preset classification rules to determine the first category to which the original pixels belong.

[0082] Alternatively, the original coordinate data of each original pixel can be generated in the form of a count. Specifically, the above step S301 "obtaining the original coordinate data of original pixels belonging to different first categories" can include: performing the processing of generating the original coordinate data in parallel with a parallelism of N.

[0083] Furthermore, generating the original coordinate data may specifically include steps A1 to A3.

[0084] Step A1: Pre-set the starting coordinates and width of the first coordinate, as well as the starting coordinates and width of the second coordinate.

[0085] Step A2: In the current counting cycle, under the constraints of the width of the first coordinate and the width of the second coordinate, determine the first count of the first coordinate and the second count of the second coordinate corresponding to the current count; the step of the first count is N, and the step of the second count is 1.

[0086] Step A3: Determine the first coordinate of the original pixel acquired in the current counting cycle based on the starting coordinate of the first coordinate and the first count; determine the second coordinate of the original pixel acquired in the current counting cycle based on the starting coordinate of the second coordinate and the second count.

[0087] Since the original coordinate data consists of the row and column numbers of the original pixels, and is arranged in order, this embodiment generates the original coordinate data corresponding to each original pixel in the form of counting, so as to obtain the original coordinate data. For example, the original coordinate data can be generated after the processing start signal is detected.

[0088] Specifically, when generating raw coordinate data, the starting coordinates uv_hstart and width uv_hsize of the first coordinate are configured, as well as the starting coordinates uv_vstart and width uv_vsize of the second coordinate. For high-resolution raw images, they can be divided into multiple image blocks, and raw coordinate data of the raw pixels in each image block can be generated separately. Accordingly, the starting coordinates and corresponding width need to be determined based on the position of the image block in the raw image.

[0089] Furthermore, the counting step for the first coordinate is set to N, and the counting step for the second coordinate is set to 1. Each clock cycle can be considered as a counting cycle. In the current counting cycle, the corresponding count, i.e., the current count, can be determined. Moreover, according to the two set counting steps, the count for the first coordinate (i.e., the first count) and the count for the second coordinate (i.e., the second count) corresponding to this current count can be determined.

[0090] In this system, the width of the first coordinate is used to constrain the first count of the first coordinate, ensuring that the first count does not exceed the width of the first coordinate. Similarly, the width of the second coordinate is used to constrain the second count of the second coordinate, ensuring that the second count does not exceed the width of the second coordinate. For example, if the original coordinate data of each original pixel in the original image are generated sequentially along the first direction, then as the current count increases, the first count remains unchanged, while the second count increases by a step of 1. When the second count exceeds the width of the second coordinate, the second count resets to zero, and the first count increases by a step of N. This process is repeated until the first count also reaches the width of the first coordinate.

[0091] In each counting cycle, a first count is incremented based on the starting coordinates of the first coordinate to generate the first coordinate of the original pixel. Similarly, a second count is incremented based on the starting coordinates of the second coordinate to generate the second coordinate of the original pixel, thus generating the original coordinate data of the original pixels. This counting method allows for the simple and rapid generation of the original coordinate data to be processed, without the need to read data.

[0092] In this embodiment, corresponding modules can be configured in the programmable logic device to achieve image distortion correction based on each module. Figure 4 A system architecture diagram of a programmable logic device is shown, which performs parallel processing with a parallelism of N=4 as an example, and includes a coordinate main module U0, a mapping main module U1, a cache main module U2, a pixel processing main module U3, and an image generation main module U4.

[0093] like Figure 4 As shown, if N=4, four coordinate units can be instantiated for the coordinate master module U0, and each coordinate unit generates the original coordinate data of each category in parallel.

[0094] For each coordinate unit, the initial value of the first count can be set to N different values, such as 0, 1, 2, ..., N-1. For example, if N = 4, the initial values ​​of the first count in the four coordinate units can be set to 0, 1, 2, and 3 respectively. The initial value of the second count can be set to 0 for all of them.

[0095] Taking N=4 as an example, each coordinate unit sets the starting coordinate uv_hstart and width uv_hsize for the row coordinate (first coordinate), and the starting coordinate uv_vstart and width uv_vsize for the column coordinate (second coordinate). Each coordinate unit also sets an initial count value code for the row coordinate (i.e., the initial value of the first count). The codes for the four coordinate units can be 0, 1, 2, and 3 respectively. The row count step is 4 for all coordinates, and the column count step is 1 for all coordinates. When the original image row width is not a multiple of 4, it can be padded or truncated to a multiple of 4.

[0096] The row counts for the four coordinate units are generated according to the rule that the remainder when divided by 4 is 0, 1, 2, or 3, respectively. Examples: 0, 4, 8, 12..., 1, 5, 9, 13..., 2, 6, 10, 14..., 3, 7, 11, 15... The row coordinates are determined by adding the starting coordinate uv_hstart of the row coordinate to each row count.

[0097] Step S302: Perform coordinate mapping processing on the original pixels of each category respectively; the coordinate mapping processing is used to determine the correction coordinate data of the correction pixel corresponding to the original pixel after distortion removal based on the original coordinate data of the original pixel; the correction coordinate data includes the first coordinate and the second coordinate of the correction pixel.

[0098] like Figure 4 As shown, N=4. For the mapping master module U1, four mapping units can be instantiated. Each mapping unit performs coordinate mapping processing on the generated original coordinate data (u,v) in parallel to determine the corresponding corrected coordinate data (iu,iv).

[0099] Each original coordinate data (u,v) can be input into the corresponding mapping unit to output the corresponding corrected coordinate data (iu,iv). Furthermore, since the original coordinate data (u,v) will be used subsequently, the mapping unit can pass through the original coordinate data (u,v).

[0100] Step S303: Classify the first coordinates of the correction pixel according to the classification rules to determine the second category to which the correction pixel belongs.

[0101] Please see details Figure 1 The relevant description of step S102 in the illustrated embodiment will not be repeated here.

[0102] Step S304: Based on the first category to which the original pixel belongs and the second category to which the corresponding corrected pixel belongs, cache the corresponding coordinate data to the corresponding first storage space; wherein, a corresponding first storage space group is pre-configured for each first category, and the first storage space group includes the first storage space corresponding to each second category; the coordinate data includes the original coordinate data of the original pixel and the corrected coordinate data of the corrected pixel.

[0103] Please see details Figure 1 Step S103 of the illustrated embodiment will not be described again here.

[0104] Step S305: Take the first storage space corresponding to the same second category in each first storage space group as a group, and obtain the coordinate data to be processed in each group of first storage spaces.

[0105] Please see details Figure 1 Step S104 of the illustrated embodiment will not be described again here.

[0106] In some optional implementations, as described above, step S305 can be achieved by reading the coordinate data to be processed from each group of first storage spaces and storing the read coordinate data to be processed in a second storage space. Specifically, the process of reading the coordinate data to be processed may include: determining whether there is a non-empty first storage space in each group of first storage spaces corresponding to the same second category; if a non-empty first storage space exists, reading the coordinate data from the non-empty first storage space.

[0107] like Figure 4As shown, the cache main module U2 is configured with four first storage space groups, each containing four first storage spaces, and also has four second storage spaces. For each mapping unit, it may output four types of second-category correction coordinate data (iu,iv) where iu%4 = 0, 1, 2, and 3; and each second storage space only reads correction coordinate data of the same second category. Specifically, for each second storage space, it can obtain data from the four first storage spaces from four channels, and quickly reads the data based on whichever is not empty; when multiple first storage spaces are not empty, the second storage spaces can be processed serially without affecting other processing paths.

[0108] Each group's four first storage spaces cache the coordinate data of four pixel row coordinates iu%4 being 0, 1, 2, and 3, including u, v, iu, and iv; each second storage space caches the coordinate data of four pixel row coordinates u%4 being 0, 1, 2, and 3, including u, v, iu, and iv. For example... Figure 4 As shown, the four second storage spaces read and store the correction coordinate data (iu,iv) for iu%4=0, iu%4=1, iu%4=2, and iu%4=3, respectively.

[0109] Step S306: Read the original image data corresponding to the original image; the original image data includes the original pixel value and original coordinate data of each original pixel.

[0110] In this embodiment, the programmable logic device also needs to read the original image data corresponding to the original image. The original image data can be the data of the entire original image or the data of a certain image block in the original image. The original image data includes the original pixel values ​​and original coordinate data of each original pixel, and the original coordinate data corresponds one-to-one with the original coordinate data obtained in step S301 above.

[0111] It is understood that if the original coordinate data is obtained by generation in step S301, step S306 can be executed in parallel to read the original coordinate data of each original pixel from the original image. If the original coordinate data is also obtained by reading in step S301, then after obtaining the original image data in step S306, subsequent processing such as classification and coordinate mapping can be performed on the original coordinate data. Therefore, steps S301 and S306 can be executed sequentially or in parallel, and this embodiment does not limit the execution order.

[0112] Step S307: According to the first category to which each original pixel belongs, the original pixel value of the original pixel is cached into the corresponding first memory; wherein, a corresponding first memory is pre-configured for each first category.

[0113] In this embodiment, to ensure parallel processing, N first memories are set up, each corresponding to a first category; as mentioned above, each original pixel corresponds to a unique first category, so based on the first category to which the original pixel value belongs, the corresponding original pixel value can be cached in the corresponding first memory.

[0114] like Figure 4 As shown, the raw image data can be stored in a cache, such as a DDR (Double Data Rate) cache. The raw image data is read from the cache, and then the raw pixel values ​​can be cached based on the corresponding first category. With N=4, the four first memories store the raw pixel values ​​corresponding to u%4=0, u%4=1, u%4=2, and u%4=3, respectively. The first memories store each raw pixel value sequentially so that the corresponding storage address can be determined based on the coordinate data.

[0115] Step S308: Determine the correction pixel value corresponding to each correction pixel based on the coordinate data to be processed in each group, and generate a correction image based on the correction pixel value.

[0116] Specifically, step S308, "determine the correction pixel value corresponding to each correction pixel according to the coordinate data to be processed in each group", includes steps S3081 to S3082.

[0117] Step S3081: Determine the corresponding first storage address based on the correction coordinate data in the coordinate data to be processed.

[0118] Step S3082: Obtain the original pixel value corresponding to the first storage address from the first memory corresponding to the coordinate data to be processed, and use the original pixel value corresponding to the first storage address as the correction pixel value of the correction pixel in the coordinate data to be processed.

[0119] In this embodiment, although each first memory corresponds to a corresponding first category, since the first category and the second category are determined based on the same classification rules, each first memory also corresponds to a unique second category. Specifically, for each group of coordinate data to be processed, such as coordinate data read from the corresponding second storage space, since the corrected coordinate data (iu,iv) therein is regular and corresponds to only one type of second category, while the original coordinate data (u,v) may correspond to multiple rules, the corrected pixel value is determined based on the regular corrected coordinate data (iu,iv).

[0120] Specifically, for the corrected coordinate data (iu,iv) in the coordinate data to be processed, a corresponding storage address, namely the first storage address, can be determined based on this corrected coordinate data (iu,iv). This first storage address is used to store the original pixel values ​​of the original coordinate data being the corrected coordinate data (iu,iv). These original pixel values ​​are then used as the corrected pixel values ​​for the corresponding corrected pixels, and subsequently, a distortion-corrected image can be generated based on each corrected pixel value.

[0121] For example, the original pixels in the first row and first column of the original image (i.e., u = v = 1) are mapped to coordinates iu = 6 and iv = 7, resulting in corrected coordinate data (6, 7). A first storage address can be generated based on the corrected coordinate data (6, 7), which stores the original pixel value P in the sixth row and seventh column of the original image. 6,7 The original pixel value P 6,7 This is used as the correction pixel value. Subsequently, when generating the corrected image, the pixel value of the correction pixel in the first row and first column of the corrected image is set to this original pixel value P. 6,7 Ultimately, the corrected pixels can be obtained.

[0122] In this embodiment, a first memory is set up for each processing path to ensure that the values ​​of each corrected pixel can be determined in parallel. Furthermore, the first storage address is determined based on the corrected coordinate data to query the pixel values ​​in the first memory. This method is applicable to regular corrected coordinate data in each group of data to be processed, avoiding blocking.

[0123] In some optional implementations, step S308 above, "generating a corrected image based on the corrected pixel values", may include steps B1 to B3.

[0124] Step B1: Based on the first category to which the original pixels in the coordinate data to be processed belong and the second category to which the corrected pixels in the coordinate data to be processed belong, cache the corrected pixel values ​​to the corresponding third storage space; wherein, a corresponding third storage space group is pre-configured for each second category, and the third storage space group includes the third storage space corresponding to each first category.

[0125] Step B2: Take the third storage spaces corresponding to the same first category in each third storage space group as a group, and obtain the corrected pixel values ​​in each group of third storage spaces.

[0126] Step B3: Determine the corresponding second storage address based on the original coordinate data in the coordinate data to be processed, record the pixel value corresponding to the second storage address as the correction pixel value, and generate a correction image based on each correction pixel value.

[0127] In this embodiment, it is necessary to determine the position of the corrected pixel value in the corrected image based on the original coordinate data (u,v). However, for each set of coordinate data to be processed, the original coordinate data (u,v) belongs to different first categories. If the corrected pixels are generated directly based on the original coordinate data (u,v), there may be a blocking problem. Similar to the method of setting the first storage space group described above, another storage space group is also set, namely the third storage space group. However, this third storage space group corresponds one-to-one with each second category; and the third storage space group includes N third storage spaces, and each third storage space corresponds one-to-one with the first category. There are a total of N×N third storage spaces.

[0128] Based on the second category to which the corrected pixels belong in the coordinate data to be processed, a corresponding third storage space group can be determined. Furthermore, based on the first category to which the original pixels belong in the coordinate data to be processed, the third storage space corresponding to the original pixel within that corresponding third storage space group can be further determined, and the corresponding corrected pixel value can then be stored in that third storage space. Alternatively, the original coordinate data can also be stored in that third storage space, allowing direct reading of the original coordinate data in the third storage space to determine the corresponding second storage address, which is the address where the pixel value of a certain pixel in the corrected image is recorded.

[0129] After determining the second storage address, the corrected pixel value can be recorded at the second storage address. Since the second storage address is generated based on the original coordinate data, the corrected pixel value can be used as the pixel value of the pixel corresponding to the original coordinate data in the corrected image, thereby obtaining the distortion-free corrected image.

[0130] Optionally, step B2, "taking the third storage spaces corresponding to the same first category in each third storage space group as a group, and obtaining the corrected pixel values ​​in each group of third storage spaces respectively", may include steps B21 to B22.

[0131] Step B21: Take the third storage spaces corresponding to the same first category in each third storage space group as a group, and read the corrected pixel values ​​in each group of third storage spaces respectively.

[0132] Step B22: Cache the read corrected pixel values ​​into the corresponding fourth storage space; wherein, a corresponding fourth storage space is pre-configured for each first category.

[0133] In this embodiment, similar to the second storage space described above, a corresponding fourth storage space is also provided for each group of third storage spaces. This fourth storage space corresponds one-to-one with the first category; that is, the fourth storage space is used to store data belonging to the same first category, i.e., the corrected pixel values. Furthermore, this fourth storage space can also store the original coordinate data from the coordinate data to be processed. The first category to which this original coordinate data belongs is consistent with the first category corresponding to the fourth storage space.

[0134] The third and fourth storage spaces can also use FIFO to cache data, without requiring a large amount of storage resources.

[0135] Optionally, step B3, "recording the pixel value corresponding to the second storage address as the corrected pixel value," may include step B31.

[0136] Step B31: The second storage address is read alternately from the first buffer and the second buffer, and the corrected pixel value is written to the second storage address of the second memory. Specifically, when a read operation is performed on the first buffer, a write operation is performed on the second buffer; conversely, when a write operation is performed on the first buffer, a read operation is performed on the second buffer.

[0137] In this embodiment, a memory for storing the corrected image, namely a second memory, is provided, and the generated second storage address is a certain address in the second memory.

[0138] Furthermore, two alternating read / write buffers are set up in each processing path, namely the first buffer. When the first buffer reads a second memory address, the second buffer is used to write another second memory address it has read to the second memory address of the second memory. Conversely, when the first buffer writes a second memory address to the second memory address of the second memory, the second buffer is used to read another second memory address. By using the two buffers to alternate between read and write, read and write latency is eliminated, ensuring read and write efficiency.

[0139] like Figure 4 As shown, in the pixel processing main module U3, a corresponding first address calculation unit and a first memory are set for each processing path. The first address calculation unit is used to calculate the first storage address corresponding to the correction coordinate data, and then read the correction pixel value from the corresponding first memory.

[0140] In the main image generation module U4, a third storage space group (including N third storage spaces), a fourth storage space, and a second address calculation unit are set up for each processing path. Based on the first category u%4 to which the original coordinate data (u,v) in the coordinate data to be processed belongs, the corrected pixel values ​​and the original coordinate data (u,v) are stored in the corresponding third storage space.

[0141] Furthermore, the fourth storage space reads and records data stored in the third storage spaces belonging to the same first category within each group of third storage spaces. This data may include corrected pixel values ​​and original coordinate data. Subsequently, the corresponding second address calculation unit obtains the original coordinate data and corrected pixel values ​​from the third storage space, determines the second storage address based on the original coordinate data, and then stores the corrected pixel values ​​in the corresponding second storage address.

[0142] like Figure 4 As shown, the main image generation module U4 can also include a first buffer and a second buffer that are read alternately to ensure read and write efficiency.

[0143] It is understandable that a second and fourth storage space may not be set up, and the corresponding address calculation unit can directly read the corresponding data from each storage space group (first storage space group, third storage space group) and perform address calculation processing.

[0144] Figure 5 A detailed flowchart of this image correction method is shown. Taking N=4 as an example, combined with... Figure 4 The architecture shown illustrates the process by which programmable logic devices perform distortion correction on the original image, as detailed below.

[0145] The programmable logic device receives the raw image data to be processed and writes it into a cache, which can be, for example, a DDR cache, or other on-chip or off-chip memory.

[0146] The system continuously checks if there is enough data in the cache. If so, it reads the original image data in blocks, initiating a request to read an image block. If this is not the first time reading an image block, it also checks if the currently read image block has been processed and if it is the last image block. If the last image block has been processed, the process ends.

[0147] In this embodiment, when reading image block data, pixel values ​​can be read in parallel. For example, 16 pixel values ​​can be read per clock cycle, and the read pixel values ​​are cached in parallel to the corresponding storage area (e.g., FIFO). Furthermore, the first category to which each raw pixel belongs can be determined according to the u%4 rule, thereby writing the corresponding input to the corresponding first memory. This first memory can be, for example, RAM, such as URAM or distributed RAM, or it can be replaced by off-chip extended storage; this embodiment does not limit this.

[0148] Furthermore, when initiating a request to read a data block, a start signal can be generated, enabling each coordinate unit to generate the original coordinate data (u,v) in parallel based on this start signal. Each coordinate unit then calculates the corrected coordinate data (iu,iv) corresponding to the original coordinate data (u,v) in parallel.

[0149] For each processing path, the second category is determined according to the iu%4 rule, and the coordinate data is written to the corresponding first storage space. The second storage space reads a non-empty first storage space and writes the read coordinate data to the second storage space.

[0150] For each processing path, each first address calculation unit calculates the first storage address corresponding to the corrected coordinate data (iu,iv), and reads the corresponding first memory based on the first storage address to obtain the corrected pixel value. Furthermore, for each processing path, the corresponding first category is determined again according to the u%4 rule and written to the corresponding third storage space. The corrected pixel value is then written to the fourth storage space. Finally, the second address calculation unit calculates the second storage address, and the corrected pixel value is written to the second memory by alternately reading and writing through the first and second buffers. Ultimately, the entire corrected image is stored in the second memory.

[0151] The second memory can also be RAM, such as URAM or distributed RAM, or it can be replaced by off-chip extended memory. This embodiment does not limit this.

[0152] The image correction method provided in this embodiment sets up N first memories, each recording the original pixel values ​​of different categories, ensuring parallel processing. The first storage address is generated based on rule-based correction coordinate data, unaffected by the coordinate data of various first categories in the second storage space, enabling parallel determination of correction pixel values ​​and effectively avoiding blocking. When generating the corrected image, N×N third storage spaces are used to accelerate each processing path, effectively avoiding blocking and enabling parallel processing. The first and second storage spaces can form a cascaded storage structure, and the third and fourth storage spaces can also form a cascaded storage structure, ensuring stable data reading and writing.

[0153] This embodiment also provides an image correction device for implementing the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0154] This embodiment provides an image correction device applied to a programmable logic device, such as... Figure 6 As shown, it includes:

[0155] The coordinate acquisition module 601 is used to acquire the original coordinate data of original pixels belonging to different first categories; the first category to which the original pixel belongs is determined by classifying the original coordinate data of the original pixel according to a preset classification rule;

[0156] The classification module 602 is used to determine the correction coordinate data of the correction pixel corresponding to the original pixel after distortion correction based on the original coordinate data of the original pixel, and classify the correction coordinate data of the correction pixel according to the classification rules to determine the second category to which the correction pixel belongs.

[0157] The coordinate caching module 603 is used to cache the corresponding coordinate data to the corresponding first storage space according to the first category to which the original pixel belongs and the corresponding second category to which the corrected pixel belongs; wherein, a corresponding first storage space group is pre-configured for each first category, and the first storage space group includes the first storage space corresponding to each second category; the coordinate data includes the original coordinate data of the original pixel and the corrected coordinate data of the corrected pixel;

[0158] The group acquisition module 604 is used to acquire the coordinate data to be processed in each group of first storage spaces, taking the first storage spaces of the same second category in each first storage space group as a group;

[0159] The processing module 605 is used to determine the correction pixel value corresponding to each correction pixel according to the coordinate data to be processed in each group, and generate a correction image according to the correction pixel value.

[0160] In some optional implementations, the original coordinate data includes the first coordinate and the second coordinate of the original pixel; the corrected coordinate data includes the first coordinate and the second coordinate of the corrected pixel; the classification rule is used to divide the first coordinate into N categories, where N is a parallelism of not less than 2.

[0161] The first category to which the original pixel belongs is determined by classifying the first coordinates of the original pixel according to the classification rules;

[0162] The second category to which the corrected pixel belongs is determined by classifying the first coordinates of the corrected pixel according to the classification rules.

[0163] In some optional implementations, the coordinate acquisition module 601 acquires the original coordinate data of original pixels belonging to different first categories, including:

[0164] The process of generating the original coordinate data is performed in parallel with a parallelism of N, and the generation of the original coordinate data includes:

[0165] The starting coordinates and width of the first coordinate are predetermined, as are the starting coordinates and width of the second coordinate.

[0166] In the current counting cycle, under the constraints of the width of the first coordinate and the width of the second coordinate, the first count of the first coordinate and the second count of the second coordinate corresponding to the current count are determined; the step of the first count is N, and the step of the second count is 1.

[0167] Based on the starting coordinates of the first coordinates and the first count, the first coordinates of the original pixel acquired in the current counting cycle are determined; based on the starting coordinates of the second coordinates and the second count, the second coordinates of the original pixel acquired in the current counting cycle are determined.

[0168] In some optional implementations, the classification rule is: taking the remainder of the first coordinate with N as the divisor, and different remainders correspond to different categories.

[0169] In some optional implementations, the group acquisition module 604 takes the first storage spaces corresponding to the same second category in each of the first storage space groups as a group, and acquires the coordinate data to be processed in each group of first storage spaces, including:

[0170] Take the first storage space of the same second category in each of the first storage space groups as a group, and read the coordinate data to be processed in each group of the first storage space respectively;

[0171] The read coordinate data to be processed is cached in the corresponding second storage space; wherein, a corresponding second storage space is pre-configured for each second category.

[0172] In some optional implementations, the group acquisition module 604 takes the first storage spaces of the same second category in each of the first storage space groups as a group, and reads the coordinate data to be processed in each group of first storage spaces, including:

[0173] Determine whether there is a non-empty first storage space in each of the first storage space groups corresponding to the same second category;

[0174] If a non-empty first storage space exists, read the coordinate data in the non-empty first storage space and use the coordinate data in the non-empty first storage space as the coordinate data to be processed.

[0175] In some alternative embodiments, the apparatus further includes:

[0176] The image reading module is used to read the original image data corresponding to the original image to be corrected; the original image data includes the original pixel value and original coordinate data of each original pixel;

[0177] A pixel caching module is used to cache the original pixel values ​​of the original pixels into the corresponding first memory according to the first category to which each original pixel belongs; wherein, a corresponding first memory is pre-configured for each first category;

[0178] The processing module 605 determines the correction pixel value corresponding to each correction pixel based on the coordinate data to be processed in each group, including:

[0179] The corresponding first storage address is determined based on the corrected coordinate data in the coordinate data to be processed;

[0180] The original pixel value corresponding to the first storage address is obtained from the first memory corresponding to the coordinate data to be processed, and the original pixel value corresponding to the first storage address is used as the correction pixel value of the correction pixel in the coordinate data to be processed.

[0181] In some optional implementations, the processing module 605 generates a corrected image based on the corrected pixel values, including:

[0182] Based on the first category to which the original pixels in the coordinate data to be processed belong and the second category to which the corrected pixels in the coordinate data to be processed belong, the corrected pixel values ​​are cached in the corresponding third storage space; wherein, a corresponding third storage space group is pre-configured for each second category, and the third storage space group includes the third storage space corresponding to each first category respectively;

[0183] Each third storage space in the third storage space group that corresponds to the same first category is taken as a group, and the corrected pixel value in each group of third storage spaces is obtained respectively;

[0184] The corresponding second storage address is determined based on the original coordinate data in the coordinate data to be processed. The pixel value corresponding to the second storage address is recorded as the corrected pixel value, and a corrected image is generated based on each of the corrected pixel values.

[0185] In some optional implementations, the processing module 605 groups the third storage spaces corresponding to the same first category as a group, and obtains the corrected pixel values ​​in each group of third storage spaces, including:

[0186] Each third storage space in the third storage space group that corresponds to the same first category is taken as a group, and the corrected pixel value in each group of third storage spaces is read respectively;

[0187] The read corrected pixel values ​​are cached in the corresponding fourth storage space; wherein, a corresponding fourth storage space is pre-configured for each first category.

[0188] In some optional implementations, the processing module 605 records the pixel value corresponding to the second storage address as the corrected pixel value, including:

[0189] The second storage address is read alternately according to the first buffer and the second buffer, and the corrected pixel value is written to the second storage address of the second memory.

[0190] Specifically, when a read operation is performed in the first buffer, a write operation is performed in the second buffer; and when a write operation is performed in the first buffer, a read operation is performed in the second buffer.

[0191] Further functional descriptions of the above modules and units are the same as those in the corresponding embodiments described above, and will not be repeated here.

[0192] In this embodiment, the image correction device is presented in the form of a functional unit. Here, a unit refers to an ASIC (Application Specific Integrated Circuit) circuit, including a processor and memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0193] This invention also provides a programmable logic device having the above-described features. Figure 6 The image correction device shown.

[0194] Please see Figure 7 , Figure 7 This is a schematic diagram of the structure of a programmable logic device provided in an optional embodiment of the present invention, such as... Figure 7As shown, the programmable logic device includes one or more processors 10, a memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise as required. The processors can process instructions that execute within the programmable logic device, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interface). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories, if desired. Similarly, multiple programmable logic devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 7 Take a processor 10 as an example.

[0195] The processor 10 may be a central processing unit, a network processor, or a combination thereof. The processor 10 may further include hardware chips.

[0196] The memory 20 stores instructions executable by at least one processor 10 to cause the at least one processor 10 to perform the method shown in the above embodiments.

[0197] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and application programs required for at least one function; the data storage area may store data created based on the use of the programmable logic device. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, and these remote memories may be connected to the programmable logic device via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0198] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0199] The programmable logic device also includes a communication interface 30 for communicating with other devices or communication networks.

[0200] This invention also provides a computer-readable storage medium. The methods described above according to embodiments of the invention can be implemented in hardware or firmware, or implemented as computer code that can be recorded on a storage medium, or implemented as computer code downloaded via a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and then stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods shown in the above embodiments.

[0201] A portion of this invention can be applied as a computer program product, such as computer program instructions, which, when executed by a computer, can invoke or provide the methods and / or technical solutions according to the invention through the operation of the computer. Those skilled in the art will understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executing the instructions, or the computer compiling the instructions and then executing the corresponding compiled program, or the computer reading and executing the instructions, or the computer reading and installing the instructions and then executing the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to a computer.

[0202] Although embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations should all be covered within the protection scope of the present invention.

Claims

1. An image correction method, characterized in that, Applied to programmable logic devices, the method includes: Obtain the original coordinate data of the original pixels belonging to different first categories; the first category to which the original pixels belong is determined by classifying the original coordinate data of the original pixels according to a preset classification rule; Based on the original coordinate data of the original pixel, the correction coordinate data of the correction pixel corresponding to the original pixel after distortion correction is determined, and the correction coordinate data of the correction pixel is classified according to the classification rules to determine the second category to which the correction pixel belongs. Based on the first category to which the original pixel belongs and the second category to which the corresponding corrected pixel belongs, the corresponding coordinate data is cached in the corresponding first storage space; wherein, a corresponding first storage space group is pre-configured for each first category, and the first storage space group includes the first storage space corresponding to each second category; the coordinate data includes the original coordinate data of the original pixel and the corrected coordinate data of the corrected pixel; Take the first storage space of the same second category in each of the first storage space groups as a group, and obtain the coordinate data to be processed in each group of the first storage space; Based on the coordinate data to be processed in each group, the correction pixel value corresponding to each correction pixel is determined, and a correction image is generated based on the correction pixel value; The original coordinate data includes the first and second coordinates of the original pixel; the corrected coordinate data includes the first and second coordinates of the corrected pixel; the classification rule is used to divide the first coordinate into N categories, where N is a parallelism of not less than 2; the classification rule is: divide the first coordinate by N and perform a remainder operation, with different remainders corresponding to different categories; The first category to which the original pixel belongs is determined by classifying the first coordinates of the original pixel according to the classification rules; The second category to which the corrected pixel belongs is determined by classifying the first coordinates of the corrected pixel according to the classification rules.

2. The method according to claim 1, characterized in that, The step of obtaining the original coordinate data of original pixels belonging to different first categories includes: The process of generating the original coordinate data is performed in parallel with a parallelism of N, and the generation of the original coordinate data includes: The starting coordinates and width of the first coordinate are predetermined, as are the starting coordinates and width of the second coordinate. In the current counting cycle, under the constraints of the width of the first coordinate and the width of the second coordinate, the first count of the first coordinate and the second count of the second coordinate corresponding to the current count are determined; the step of the first count is N, and the step of the second count is 1. Based on the starting coordinates of the first coordinates and the first count, the first coordinates of the original pixel acquired in the current counting cycle are determined; based on the starting coordinates of the second coordinates and the second count, the second coordinates of the original pixel acquired in the current counting cycle are determined.

3. The method according to claim 1, characterized in that, The step of taking the first storage spaces of the same second category in each of the first storage space groups as a group, and obtaining the coordinate data to be processed in each group of first storage spaces, includes: Take the first storage space of the same second category in each of the first storage space groups as a group, and read the coordinate data to be processed in each group of the first storage space respectively; The read coordinate data to be processed is cached in the corresponding second storage space; wherein, a corresponding second storage space is pre-configured for each second category.

4. The method according to claim 3, characterized in that, The step of grouping the first storage spaces of the same second category within each of the first storage space groups into a single group and reading the coordinate data to be processed from each group of first storage spaces includes: Determine whether there is a non-empty first storage space in each of the first storage space groups corresponding to the same second category; If a non-empty first storage space exists, read the coordinate data in the non-empty first storage space and use the coordinate data in the non-empty first storage space as the coordinate data to be processed.

5. The method according to any one of claims 1 to 4, characterized in that, The method further includes: Read the original image data corresponding to the original image to be corrected; the original image data includes the original pixel value and original coordinate data of each original pixel; According to the first category to which each original pixel belongs, the original pixel value of the original pixel is cached into the corresponding first memory; wherein, a corresponding first memory is pre-configured for each first category; The step of determining the correction pixel value corresponding to each correction pixel based on the coordinate data to be processed in each group includes: The corresponding first storage address is determined based on the corrected coordinate data in the coordinate data to be processed; The original pixel value corresponding to the first storage address is obtained from the first memory corresponding to the coordinate data to be processed, and the original pixel value corresponding to the first storage address is used as the correction pixel value of the correction pixel in the coordinate data to be processed.

6. The method according to claim 5, characterized in that, The step of generating a corrected image based on the corrected pixel values ​​includes: Based on the first category to which the original pixels in the coordinate data to be processed belong and the second category to which the corrected pixels in the coordinate data to be processed belong, the corrected pixel values ​​are cached in the corresponding third storage space; wherein, a corresponding third storage space group is pre-configured for each second category, and the third storage space group includes the third storage space corresponding to each first category respectively; Each third storage space in the third storage space group that corresponds to the same first category is taken as a group, and the corrected pixel value in each group of third storage spaces is obtained respectively; The corresponding second storage address is determined based on the original coordinate data in the coordinate data to be processed. The pixel value corresponding to the second storage address is recorded as the corrected pixel value, and a corrected image is generated based on each of the corrected pixel values.

7. The method according to claim 6, characterized in that, Taking the third storage spaces corresponding to the same first category in each of the aforementioned third storage space groups as a group, the corrected pixel values ​​in each group of third storage spaces are obtained, including: Each third storage space in the third storage space group that corresponds to the same first category is taken as a group, and the corrected pixel value in each group of third storage spaces is read respectively; The read corrected pixel values ​​are cached in the corresponding fourth storage space; wherein, a corresponding fourth storage space is pre-configured for each first category.

8. The method according to claim 6, characterized in that, The step of recording the pixel value corresponding to the second storage address as the corrected pixel value includes: The second storage address is read alternately according to the first buffer and the second buffer, and the corrected pixel value is written to the second storage address of the second memory. Specifically, when a read operation is performed in the first buffer, a write operation is performed in the second buffer; and when a write operation is performed in the first buffer, a read operation is performed in the second buffer.

9. An image correction device, characterized in that, Applied to a programmable logic device, the device includes: The coordinate acquisition module is used to acquire the original coordinate data of original pixels belonging to different first categories; the first category to which the original pixel belongs is determined by classifying the original coordinate data of the original pixel according to a preset classification rule; The classification module is used to determine the correction coordinate data of the correction pixel corresponding to the original pixel after distortion correction based on the original coordinate data of the original pixel, and to classify the correction coordinate data of the correction pixel according to the classification rules to determine the second category to which the correction pixel belongs. A coordinate caching module is used to cache the corresponding coordinate data to a corresponding first storage space according to the first category to which the original pixel belongs and the corresponding second category to which the corrected pixel belongs; wherein, a corresponding first storage space group is pre-configured for each first category, and the first storage space group includes a first storage space corresponding to each second category; the coordinate data includes the original coordinate data of the original pixel and the corrected coordinate data of the corrected pixel; The group acquisition module is used to acquire the coordinate data to be processed in each group of first storage spaces, taking the first storage spaces of the same second category in each first storage space group as a group; The processing module is used to determine the correction pixel value corresponding to each correction pixel according to the coordinate data to be processed in each group, and generate a correction image according to the correction pixel value; The original coordinate data includes the first and second coordinates of the original pixel; the corrected coordinate data includes the first and second coordinates of the corrected pixel; the classification rule is used to divide the first coordinate into N categories, where N is a parallelism of not less than 2; the classification rule is: divide the first coordinate by N and perform a remainder operation, with different remainders corresponding to different categories; The first category to which the original pixel belongs is determined by classifying the first coordinates of the original pixel according to the classification rules; The second category to which the corrected pixel belongs is determined by classifying the first coordinates of the corrected pixel according to the classification rules.

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