Shift register, gate drive circuit and display panel

Abstract

This invention relates to the field of display technology, and specifically discloses a shift register, a gate driving circuit, and a display panel. The panel includes a first input module, a second input module, a first output module, and a second output module. The output terminal of the first input module is connected to the first control terminal of the first output module. The input terminal of the second input module is connected to the second control terminal of the first output module, and the output terminal of the second input module is connected to the first control terminal of the second output module. The second control terminal of the second output module is connected to the first output module. By configuring the first input module, second input module, first output module, and second output module, the shift register can output two different pulse signals, reducing the number of shift registers in the screen and thus reducing the layout space occupied by the shift registers. Furthermore, this helps to reduce the screen bezel and power consumption.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a shift register, a gate driving circuit, and a display panel. Background Technology

[0002] Currently, the driving circuits around small and medium-sized screens typically require two or more sets of Scan circuits to output different pulse signals. However, the more Scan circuits required, the more CLK (Clock) signals and TFT (Thin Film Transistor) devices are needed, resulting in a larger screen bezel. Achieving narrow bezels is currently a hot research topic in display technology, thus requiring a reduction in the number of Scan circuits within the screen. Summary of the Invention

[0003] Therefore, it is necessary to provide a shift register, gate drive circuit, and display panel to address the issue of how to reduce the number of Scan circuits in the screen.

[0004] A shift register includes a first input module, a second input module, a first output module, and a second output module. The first output module has a control terminal including a first control terminal and a second control terminal. The second output module also has a control terminal including a first control terminal and a second control terminal. The output terminal of the first input module is connected to the first control terminal of the first output module. The first input module is configured to transmit a first input signal to the first control terminal of the first output module according to a first clock signal. The input terminal of the second input module is connected to the second control terminal of the first output module, and the output terminal of the second input module is connected to the first control terminal of the second output module. The second input module is configured to transmit a second input signal to the first control terminal of the second output module according to a second clock signal. The first output module is configured to output a first output signal according to a signal at its control terminal. The second control terminal of the second output module is connected to the first output module, and the second output module is configured to output a second output signal according to a signal at its control terminal.

[0005] In one embodiment, the first output module includes a first output control unit, a second output control unit, a first output unit, and a second output unit. The control terminal of the first output control unit serves as the first control terminal of the first output module, and the control terminal of the second output control unit serves as the second control terminal of the first output module. A first terminal of the first output control unit is connected to a second clock signal, and the control terminal of the first output control unit is connected to the output terminal of the first input module. The second terminal of the first output control unit is connected to the control terminals of the first output unit and the second output unit, respectively. The first output control unit is configured to transmit the second clock signal to the control terminals of the first output unit and the second output unit based on the signal at its control terminal. A first terminal of the second output control unit is connected to a first level signal, and the control terminal of the second output control unit is connected to the second input module. The second output control unit is connected to the control terminal of the first output unit and the control terminal of the second output unit, respectively. The second output control unit is configured to transmit the first level signal to the control terminal of the first output unit and the control terminal of the second output unit according to the signal at the control terminal of the second output control unit. The first output unit is connected to the first level signal at its first terminal and to the output terminal of the first output module at its second terminal. The first output unit is configured to transmit the first level signal to the output terminal of the first output module according to the signal at the control terminal of the first output unit. The second output unit is connected to the second level signal at its first terminal and to the output terminal of the first output module at its second terminal. The second output unit is configured to transmit the second level signal to the output terminal of the first output module according to the signal at the control terminal of the second output unit.

[0006] In one embodiment, the first output control unit includes a third transistor, the first terminal of which serves as a first terminal of the first output control unit, the gate of which serves as a control terminal of the first output control unit, and the second terminal of which serves as a second terminal of the first output control unit; the second output control unit includes a fourth transistor, the first terminal of which serves as a first terminal of the second output control unit, the gate of which serves as a control terminal of the second output control unit, and the second terminal of which serves as a second terminal of the second output control unit; the first output unit includes a fifth transistor, the first terminal of which serves as a first terminal of the first output unit, the gate of which serves as a control terminal of the first output unit, and the second terminal of which serves as a second terminal of the first output unit; the second output unit includes a sixth transistor, the first terminal of which serves as a first terminal of the second output unit, the gate of which serves as a control terminal of the second output unit, and the second terminal of which serves as a second terminal of the second output unit.

[0007] In one embodiment, the conduction level of the fifth transistor is different from that of the sixth transistor.

[0008] In one embodiment, the pulse width of the first output signal is different from the pulse width of the second output signal.

[0009] In one embodiment, the first potential holding unit includes a first capacitor, a first end of which is connected to the control terminal of the second output control unit, and a second end of which is connected to the second terminal of the second output control unit.

[0010] In one embodiment, the second output module includes a third output control unit, a fourth output control unit, a third output unit, and a fourth output unit. The control terminal of the third output control unit serves as a first control terminal of the second output module, and the control terminal of the fourth output control unit serves as a second control terminal of the second output module. The first terminal of the third output control unit is connected to a first level signal, and the control terminal of the third output control unit is connected to the output terminal of the second input module. The second terminal of the third output control unit is connected to the control terminal of the fourth output unit. The third output control unit is configured to transmit the first level signal to the control terminal of the fourth output unit based on the signal at its control terminal. The first terminal of the fourth output control unit is connected to a second level signal, and the control terminal of the fourth output control unit is connected to the first output module. The second end of the third output unit is connected to the control terminal of the fourth output unit. The fourth output control unit is configured to transmit the second level signal to the control terminal of the fourth output unit according to the signal at the control terminal of the fourth output control unit. The first end of the third output unit is connected to the second level signal. The control terminal of the third output unit is connected to the output terminal of the second input module. The second end of the third output unit is connected to the output terminal of the second output module. The third output unit is configured to transmit the second level signal to the output terminal of the second output module according to the signal at the control terminal of the third output unit. The first end of the fourth output unit is connected to the first level signal. The second end of the fourth output unit is connected to the output terminal of the second output module. The fourth output unit is configured to transmit the first level signal to the output terminal of the second output module according to the signal at the control terminal of the fourth output unit.

[0011] In one embodiment, the third output control unit includes a seventh transistor, the first terminal of which serves as a first terminal of the third output control unit, the gate of which serves as a control terminal of the third output control unit, and the second terminal of which serves as a second terminal of the third output control unit; the fourth output control unit includes an eighth transistor, the first terminal of which serves as a first terminal of the fourth output control unit, the gate of which serves as a control terminal of the fourth output control unit, and the second terminal of which serves as a second terminal of the fourth output control unit; the third output unit includes a ninth transistor, the first terminal of which serves as a first terminal of the third output unit, the gate of which serves as a control terminal of the third output unit, and the second terminal of which serves as a second terminal of the third output unit; the fourth output unit includes a tenth transistor, the first terminal of which serves as a first terminal of the fourth output unit, the gate of which serves as a control terminal of the fourth output unit, and the second terminal of which serves as a second terminal of the fourth output unit.

[0012] In one embodiment, the second output module further includes a second potential holding unit, which is connected between the first terminal of the fourth output unit and the control terminal of the fourth output unit, for maintaining the potential between the first terminal of the fourth output unit and the control terminal of the fourth output unit.

[0013] In one embodiment, the second potential holding unit includes a second capacitor, the first end of which is connected to the first end of the fourth output unit, and the second end of which is connected to the control terminal of the fourth output unit.

[0014] In one embodiment, the first input module includes a first transistor, the first terminal of the first transistor is connected to the first input signal, the gate of the first transistor is connected to the first clock signal, and the second terminal of the first transistor serves as the output terminal of the first input module; the second input module includes a second transistor, the first terminal of the second transistor is connected to the second input signal, the gate of the second transistor is connected to the second clock signal, and the second terminal of the second transistor serves as the output terminal of the second input module.

[0015] In one embodiment, the shift register further includes a cascading module, the input of which is connected to a first level signal, and the output of which is connected to the first output module. The cascading module is configured to transmit the first level signal to the first output module according to the cascading signal.

[0016] In one embodiment, the cascade module includes an eleventh transistor, the first terminal of which serves as the input terminal of the cascade module, the gate of which is connected to the cascade signal, and the second terminal of which serves as the output terminal of the cascade module.

[0017] A gate driving circuit includes n cascaded shift registers as described in any of the above embodiments. Except for the nth-stage shift register, the signal output by the first output control module of the i-th-stage shift register serves as the first input signal of the (i+1)-th-stage shift register, and the second output signal output by the second output module of the i-th-stage shift register serves as the second input signal of the (i+1)-th-stage shift register; wherein n is a positive integer, i = 1, 2, 3, ..., n.

[0018] In one embodiment, in addition to the shift registers of the nth stage and the (n-1)th stage, the signal output by the first output control module of the (i+2)th stage shift register is used as the cascaded signal connected to the shift register of the ith stage.

[0019] A display panel includes the gate driving circuit described in any of the above embodiments.

[0020] In the aforementioned shift register, the first input module transmits a first input signal to the first control terminal of the first output module based on a first clock signal, and the second input module transmits a second input signal to the first control terminal of the second output module based on a second clock signal. The first output module can output a first output signal based on the signal at its control terminal, and the second output module can output a second output signal based on the potential at its control terminal. By configuring the first input module, second input module, first output module, and second output module, the shift register can output two different pulse signals. By enabling a single shift register to output two different pulse signals, the number of shift registers in the screen can be reduced, thereby reducing the layout space occupied by shift registers in the screen. Furthermore, this helps to reduce the screen bezel size and power consumption. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this specification or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this specification. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0022] Figure 1This is a schematic diagram of the shift register structure in one embodiment of this application;

[0023] Figure 2 This is a schematic diagram of the shift register structure in another embodiment of this application;

[0024] Figure 3 This is a schematic diagram of the circuit structure of the shift register in one embodiment of this application;

[0025] Figure 4 This is a schematic diagram of the shift register structure in another embodiment of this application;

[0026] Figure 5 This is a schematic diagram of the circuit structure of the shift register in another embodiment of this application;

[0027] Figure 6 This is a timing diagram of the signals in the shift register in one embodiment of this application;

[0028] Figure 7 This is a schematic diagram of the gate drive circuit in one embodiment of this application. Detailed Implementation

[0029] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0031] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0032] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this application, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0033] In this application, unless otherwise expressly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a direct connection or an indirect connection through an intermediate medium, or they can refer to the internal connection of two elements or the interaction between two elements. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0034] Existing solutions typically require two sets of Scan circuits to generate two different gate drive signals. These two Scan circuits occupy significant layout space and require a large number of CLK signals and TFT devices. The shift register provided in this application enables a single-stage Scan circuit to output two different gate drive signals. Compared to existing solutions using two sets of Scan circuits, the shift register provided in this application offers advantages such as smaller layout space, fewer CLK signals, and fewer TFT devices, while still achieving the function of outputting two different pulse signals.

[0035] Figure 1 This is a schematic diagram of the structure of a shift register in one embodiment of the present application. In one embodiment, the shift register 10 may include a first input module 100, a second input module 200, a first output module 300, and a second output module 400. The control terminal of the first output module 300 may include a first control terminal and a second control terminal, and the control terminal of the second output module 400 may include a first control terminal and a second control terminal.

[0036] The output terminal of the first input module 100 can be connected to the first control terminal of the first output module 300. The first input module 100 can be configured to transmit the first input signal SIN to the first control terminal of the first output module 300 according to the first clock signal SCK1. The input terminal of the first input module 100 can be connected to the first input signal line, and the control terminal of the first input module 100 can be connected to the first clock terminal. That is, the first input module 100 can access the first input signal SIN through the first input signal line and access the first clock signal SCK1 through the first clock terminal, so that the first input module 100 can transmit the first input signal SIN to the first control terminal of the first output module 300 according to the first clock signal SCK1.

[0037] The output terminal of the second input module 200 can be connected to the first control terminal of the second output module 400. The second input module 200 can be configured to transmit the second input signal EIN to the first control terminal of the second output module 400 according to the second clock signal SCK2. The input terminal of the second input module 200 can be connected to the second input signal line, and the control terminal of the second input module 200 can be connected to the second clock terminal. That is, the second input module 200 can access the second input signal EIN through the second input signal line and access the second clock signal SCK2 through the second clock terminal, so that the second input module 200 can transmit the second input signal EIN to the control terminal of the second output module 400 according to the second clock signal SCK2.

[0038] The second control terminal of the first output module 300 can be connected to the input terminal of the second input module 200. The output terminal of the first output module 300 can be defined as the first output terminal of the shift register 10, and the signal output by the first output terminal can be defined as the first output signal Sn_out. The first output module 300 can be configured to output the first output signal Sn_out according to the signal at the control terminal of the first output module 300, that is, the first output module 300 can output the first output signal Sn_out according to the second input signal EIN and / or the signal output by the first input module 100.

[0039] The second control terminal of the second output module 400 can be connected to the first output module 300. The output terminal of the second output module 400 can be defined as the second output terminal of the shift register 10, and the signal output by the second output terminal can be defined as the second output signal Em_out. The second output module 400 can be configured to output the second output signal Em_out based on the signal at the control terminal of the second output module 400, that is, the second output module 400 can output the second output signal Em_out based on the signal output by the second input module 200 and / or the signal at the first output module 300. In some optional embodiments, the pulse width of the first output signal Sn_out is different from the pulse width of the second output signal Em_out.

[0040] In the shift register 10 provided in this application, the first input module 100 transmits the first input signal SIN to the control terminal of the first output module 300 according to the first clock signal SCK1, and the first input module 100 transmits the second input signal EIN to the control terminal of the second output module 400 according to the second clock signal SCK2. The first output module 300 can output a first output signal Sn_out according to the signal at the control terminal of the first output module 300, and the second output module 400 can output a second output signal Em_out according to the signal at the control terminal of the second output module 400. The pulse widths of the first output signal Sn_out and the second output signal Em_out can be the same or different.

[0041] The first and second output terminals of the aforementioned shift register 10 can be used to output two different signals, a first output signal Sn_out and a second output signal Em_out, respectively. That is, the shift register 10 can achieve the pulse signal function that a two-stage shift register in the prior art can achieve with a single-stage shift register. By having one shift register output two different pulse signals, the number of shift registers in the screen can be reduced while ensuring the normal operation of the pixel circuits within the screen. This reduces the layout space occupied by the shift registers in the screen, and further helps to reduce the screen bezel and power consumption.

[0042] Figure 2 This is a schematic diagram of the shift register structure in another embodiment of this application. Figure 2 The connection point between the output terminal of the first input module 100, the control terminal of the first output control unit 310, and the first terminal of the first potential holding unit 350 is defined as the first node N1; the connection point between the output terminal of the second input module 200, the control terminal of the third output control unit 410, and the control terminal of the third output unit 430 is defined as the second node N2; the connection point between the output terminal of the third output control unit 410, the output terminal of the fourth output control unit 420, the control terminal of the fourth output unit 440, and the second terminal of the second potential holding unit 450 is defined as the third node N3; and the connection point between the output terminal of the first output control unit 310, the output terminal of the second output control unit 320, the control terminal of the first output unit 330, and the control terminal of the second output unit 340 is defined as the fourth node N4.

[0043] In one embodiment, the first output module 300 may further include a first output control unit 310, a second output control unit 320, a first output unit 330, and a second output unit 340. The control terminal of the first output control unit 310 may serve as the first control terminal of the first output module 300, and the control terminal of the second output control unit 320 may serve as the second control terminal of the first output module 300.

[0044] The first terminal of the first output control unit 310 can be connected to the second clock signal SCK2, and the first terminal of the second output control unit 320 can be connected to the second clock terminal to receive the second clock signal SCK2. The control terminal of the first output control unit 310 can be connected to the output terminal of the first input module 100, and the second terminal of the first output control unit 310 can be connected to the control terminals of the first output unit 330 and the second output unit 340, respectively. The first output control unit 310 can be configured to transmit the second clock signal SCK2 to the control terminals of the first output unit 330 and the second output unit 340 according to the signal at the control terminal of the first output control unit 310. Specifically, when the level at the first node N1 is a conducting level, the first output control unit 310 can be turned on according to the level at the gate of the first output control unit 310, thereby enabling the first output control unit 310 to transmit the second clock signal SCK2 to the control terminals of the first output unit 330 and the second output unit 340.

[0045] The first terminal of the second output control unit 320 can be connected to a first level signal VGH, and the first terminal of the second output control unit 320 can be connected to a first voltage terminal to receive the first level signal VGH. In this embodiment, the first voltage terminal can be connected to a high-level signal source, which can continuously provide the first level signal VGH, and the first level signal VGH can be a high-level signal.

[0046] The control terminal of the second output control unit 320 can be connected to the input terminal of the second input module 200, and the second terminal of the second output control unit 320 can be connected to the control terminals of the first output unit 330 and the second output unit 340, respectively. The second output control unit 320 can be configured to transmit a first level signal VGH to the control terminals of the first output unit 330 and the second output unit 340 according to the signal at its control terminal. Specifically, since the input terminal of the second input module 200 is connected to the second input signal EIN, the second output control unit 320 is turned on or off according to the second input signal EIN. When the level of the second input signal EIN is on, the second output control unit 320 can be turned on according to the second input signal EIN, thereby transmitting the first level signal VGH to the control terminals of the first output unit 330 and the second output unit 340.

[0047] The first terminal of the first output unit 330 can be connected to a first level signal VGH, and the first terminal of the first output unit 330 can be connected to a first voltage terminal to receive the first level signal VGH. The second terminal of the first output unit 330 can be connected to the output terminal of the first output module 300. The first output unit 330 can be configured to transmit the first level signal VGH to the output terminal of the first output module 300 according to the signal at the control terminal of the first output unit 330. Specifically, when the output signal of the first output control unit 310 and / or the output signal of the second output control unit 320 causes the potential of the fourth node N4 to be at the on level, the first output unit 330 can be turned on according to the potential at the control terminal of the first output unit 330, thereby transmitting the first level signal VGH to the output terminal of the first output module 300.

[0048] The first terminal of the second output unit 340 can be connected to a second level signal VGL, and the first terminal of the second output unit 340 can be connected to a second voltage terminal to receive the second level signal VGL. In this embodiment, the second voltage terminal can be connected to a low-level signal source, which can continuously provide the second level signal VGL, and the second level signal VGL can be a low-level signal.

[0049] The second terminal of the second output unit 340 can be connected to the output terminal of the first output module 300. The second output unit 340 can be configured to transmit the second level signal VGL to the output terminal of the first output module 300 according to the signal at the control terminal of the second output unit 340. Specifically, when the output signal of the first output control unit 310 and / or the output signal of the second output control unit 320 causes the potential at the fourth node N4 to be at the on level, the second output unit 340 can be turned on according to the potential at the control terminal of the second output unit 340, thereby transmitting the second level signal VGL to the output terminal of the first output module 300.

[0050] Figure 3 This is a schematic diagram of the circuit structure of the shift register in one embodiment of this application. Figure 3 The connection point between the second terminal of the first transistor M1, the gate of the fourth transistor M4, and the first terminal of the first capacitor C1 is defined as the first node N1; the connection point between the second terminal of the second transistor M2, the gate of the seventh transistor M7, and the gate of the ninth transistor M9 is defined as the second node N2; the connection point between the second terminal of the seventh transistor M7, the second terminal of the eighth transistor M8, the gate of the tenth transistor M10, and the second terminal of the second capacitor C2 is defined as the third node N3; and the connection point between the second terminal of the third transistor M3, the second terminal of the fourth transistor M4, the gate of the fifth transistor M5, and the gate of the sixth transistor M6 is defined as the fourth node N4.

[0051] In one embodiment, the first input module 100 may include a first transistor M1, and the second input module 200 may include a second transistor M2.

[0052] In the embodiments of this disclosure, a transistor refers to a device that includes at least a gate, a drain, and a source. In this disclosure, the first terminal of a transistor can be the drain and the second terminal can be the source, or vice versa. When using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. In the embodiments of this disclosure, the gate of all or part of the transistor can serve as the control terminal of the transistor, while the first and second terminals can be interchanged as needed.

[0053] The first terminal of the first transistor M1 can be connected to the first input signal SIN, and the first terminal of the first transistor M1 can be connected to the first input signal line to connect to the first input signal SIN. The gate of the first transistor M1 can be connected to the first clock signal SCK1, and the gate of the first transistor M1 can be connected to the first clock terminal to connect to the first clock signal SCK1. The second terminal of the first transistor M1 can be used as the output terminal of the first input module 100. When the level of the first clock signal SCK1 is on, the first transistor M1 can be turned on according to the first clock signal SCK1, thereby outputting the first input signal SIN.

[0054] The first terminal of the second transistor M2 can be connected to the second input signal EIN, and the first terminal of the second transistor M2 can be connected to the second input signal line to connect to the second input signal EIN. The gate of the second transistor M2 can be connected to the second clock signal SCK2, and the gate of the second transistor M2 can be connected to the second clock terminal to connect to the second clock signal SCK2. The second terminal of the second transistor M2 can be used as the output terminal of the second input module 200. When the level of the second clock signal SCK2 is on, the second transistor M2 can be turned on according to the second clock signal SCK2, thereby outputting the second input signal EIN.

[0055] In one embodiment, please refer to Figure 3 The first output control unit 310 may include a third transistor M3, the second output control unit 320 may include a fourth transistor M4, the first output unit 330 may include a fifth transistor M5, and the second output unit 340 may include a sixth transistor M6.

[0056] The first terminal of the third transistor M3 can be used as the first terminal of the first output control unit 310, connected to the second clock signal SCK2. The gate of the third transistor M3 can be used as the control terminal of the first output control unit 310, connected to the output terminal of the first input module 100. The second terminal of the third transistor M3 can be used as the second terminal of the first output control unit 310, connected to the control terminals of the first output unit 330 and the second output unit 340 respectively. Specifically, the gate of the third transistor M3 is connected to the second terminal of the first transistor M1, and the second terminal of the third transistor M3 is connected to the gates of the fifth transistor M5 and the sixth transistor M6 respectively.

[0057] The first terminal of the fourth transistor M4 can be used as the first terminal of the second output control unit 320, connected to the first level signal VGH. The gate of the fourth transistor M4 can be used as the control terminal of the second output control unit 320, connected to the input terminal of the second input module 200. The second terminal of the fourth transistor M4 can be used as the second terminal of the second output control unit 320, connected to the control terminals of the first output unit 330 and the second output unit 340 respectively. Specifically, the gate of the fourth transistor M4 is connected to the first terminal of the second transistor M2, and the second terminal of the fourth transistor M4 is connected to the gates of the fifth transistor M5 and the sixth transistor M6 respectively.

[0058] The first terminal of the fifth transistor M5 can be used as the first terminal of the first output unit 330 to connect to the first level signal VGH. The gate of the fifth transistor M5 can be used as the control terminal of the first output unit 330. The second terminal of the fifth transistor M5 can be used as the second terminal of the first output unit 330 to connect to the output terminal of the first output module 300.

[0059] The first terminal of the sixth transistor M6 can be used as the first terminal of the second output unit 340 to connect to the second level signal VGL. The gate of the sixth transistor M6 can be used as the control terminal of the second output unit 340. The second terminal of the sixth transistor M6 can be used as the second terminal of the second output unit 340 to connect to the output terminal of the first output module 300.

[0060] In a preferred embodiment, the conduction level of the fifth transistor M5 is different from that of the sixth transistor M6. For example, the fifth transistor M5 can be a P-type transistor, and the sixth transistor M6 can be an N-type transistor, that is, the conduction level of the fifth transistor M5 is low, and the conduction level of the sixth transistor M6 is high; or, the fifth transistor M5 can be an N-type transistor, and the sixth transistor M6 can be a P-type transistor, that is, the conduction level of the fifth transistor M5 is high, and the conduction level of the sixth transistor M6 is low.

[0061] Since the gates of the fifth transistor M5 and the sixth transistor M6 are both connected to the fourth node N4, that is, the fifth transistor M5 and the sixth transistor M6 are turned on or off according to the potential at the fourth node N4, by making the conduction level of the fifth transistor M5 different from that of the sixth transistor M6, it can be ensured that the fifth transistor M5 and the sixth transistor M6 will not be turned on simultaneously according to the potential at the fourth node N4, so that the first output module 300 can stably output the corresponding pulse signal.

[0062] In one embodiment, please refer to Figure 2The first output module 300 may further include a first potential holding unit 350. The first potential holding unit 350 can be connected between the control terminal of the second output control unit 320 and the second terminal of the second output control unit 320, and can be used to maintain the potential between the control terminal of the second output control unit 320 and the second terminal of the second output control unit 320. The potential at the fourth node N4 can be adjusted using the first potential holding unit 350 to ensure that the second output control unit 320 can stably output control signals.

[0063] In one embodiment, please refer to Figure 3 The first potential holding unit 350 may include a first capacitor C1. A first terminal of the first capacitor C1 can be connected to the control terminal of the second output control unit 320, and a second terminal of the first capacitor C1 can be connected to the second terminal of the second output control unit 320. Specifically, a first terminal of the first capacitor C1 can be connected to the gate of the fourth transistor M4, and a second terminal of the first capacitor C1 can be connected to the second terminal of the fourth transistor M4. The first capacitor C1 can be used to stabilize the potential at the fourth node N4.

[0064] In one embodiment, please refer to Figure 2 The second output module 400 may include a third output control unit 410, a fourth output control unit 420, a third output unit 430, and a fourth output unit 440. The control terminal of the third output control unit 410 may serve as the first control terminal of the second output module 400, and the control terminal of the fourth output control unit 420 may serve as the second control terminal of the second output module 400.

[0065] The first terminal of the third output control unit 410 can be connected to a first level signal VGH, and the first terminal of the third output control unit 410 can be connected to a first voltage terminal to receive the first level signal VGH. The control terminal of the third output control unit 410 can be connected to the output terminal of the second input module 200, and the second terminal of the third output control unit 410 can be connected to the control terminal of the fourth output unit 440. The third output control unit 410 can be configured to transmit the first level signal VGH to the control terminal of the fourth output unit 440 according to the signal at the control terminal of the third output control unit 440. Specifically, when the output signal level of the second input module 200 is a conduction level, the third output control unit 410 can be turned on according to the output signal of the second input module 200, thereby enabling the third output control unit 410 to transmit the first level signal VGH to the control terminal of the fourth output unit 440.

[0066] The first terminal of the fourth output control unit 420 can be connected to a second voltage terminal to receive the second level signal VGL. The control terminal of the fourth output control unit 420 can be connected to the first output module 300. Specifically, the control terminal of the fourth output control unit 420 can be connected to the fourth node N4, meaning the fourth output control unit 420 is turned on or off according to the potential at the fourth node N4. The second terminal of the fourth output control unit 420 can be connected to the control terminal of the fourth output unit 440. The fourth output control unit 420 can be configured to transmit the second level signal VGL to the control terminal of the fourth output unit 440 according to the signal at its control terminal. Specifically, when the level at the fourth node N4 is on, the fourth output control unit 420 can be turned on according to the level at its control terminal, thereby transmitting the second level signal VGL to the control terminal of the fourth output unit 440.

[0067] The first terminal of the third output unit 430 can be connected to a second level signal VGL, and the first terminal of the third output unit 430 can be connected to a second voltage terminal to receive the second level signal VGL. The control terminal of the third output unit 430 can be connected to the output terminal of the second input module 200, and the second terminal of the third output unit 430 can be connected to the output terminal of the second output module 400. The third output unit 430 can be configured to transmit the second level signal VGL to the output terminal of the second output module 400 according to the signal at the control terminal of the third output unit 430. Specifically, when the output signal level of the second input module 200 is a conduction level, the third output unit 430 can be turned on according to the output signal of the second input module 200, thereby transmitting the second level signal VGL to the output terminal of the second output module 400.

[0068] The first terminal of the fourth output unit 440 can be connected to a first level signal VGH, and the first terminal of the fourth output unit 440 can be connected to a first voltage terminal to receive the first level signal VGH. The control terminal of the fourth output unit 440 can be connected to the third node N3, and the second terminal of the fourth output unit 440 can be connected to the output terminal of the second output module 400. The fourth output unit 440 can be configured to transmit the first level signal VGH to the output terminal of the second output module 400 according to the signal at the control terminal of the fourth output unit 440. Specifically, when the potential at the third node N3 is at the on level, the fourth output unit 440 can be turned on according to the potential at the control terminal of the fourth output unit 440, thereby transmitting the first level signal VGH to the output terminal of the second output module 400.

[0069] In one embodiment, please refer to Figure 3The third output control unit 410 may include a seventh transistor M7, the fourth output control unit 420 may include an eighth transistor M8, the third output unit 430 may include a ninth transistor M9, and the fourth output unit 440 may include a tenth transistor M10.

[0070] The first terminal of the seventh transistor M7 can be connected to the first level signal VGH as the first terminal of the third output control unit 410. The gate of the seventh transistor M7 can be connected to the output terminal of the second input module 200 as the control terminal of the third output control unit 410. The second terminal of the seventh transistor M7 can be connected to the control terminal of the fourth output unit 440 as the second terminal of the third output control unit 410. Specifically, the gate of the seventh transistor M7 is connected to the second terminal of the second transistor M2, and the second terminal of the seventh transistor M7 is connected to the gate of the tenth transistor M10.

[0071] The first terminal of the eighth transistor M8 can be used as the first terminal of the fourth output control unit 420, connected to the first output module 300 via the second level signal VGL. The gate of the eighth transistor M8 can be used as the control terminal of the fourth output control unit 420, and the second terminal of the eighth transistor M8 can be used as the second terminal of the fourth output control unit 420, connected to the control terminal of the fourth output unit 440. Specifically, the gate of the eighth transistor M8 is connected to the second terminals of the third transistor M3 and the fourth transistor M4, and the second terminal of the eighth transistor M8 is connected to the gate of the tenth transistor M10.

[0072] The first terminal of the ninth transistor M9 can be used as the first terminal of the third output unit 430 to connect to the second level signal VGL. The gate of the ninth transistor M9 can be used as the control terminal of the third output unit 430 to connect to the output terminal of the second input module 200. The second terminal of the ninth transistor M9 can be used as the second terminal of the third output unit 430 to connect to the output terminal of the second output module 400. Specifically, the gate of the ninth transistor M9 is connected to the second terminal of the second transistor M2.

[0073] The first terminal of the tenth transistor M10 can be used as the first terminal of the fourth output unit 440 to connect to the first level signal VGH. The gate of the tenth transistor M10 can be used as the control terminal of the fourth output unit 440. The second terminal of the tenth transistor M10 can be used as the second terminal of the fourth output unit 440 to connect to the output terminal of the second output module 400.

[0074] In one embodiment, please refer to Figure 2The second output module 400 may further include a second potential holding unit 450. The second potential holding unit 450 can be connected between the first terminal of the fourth output unit 440 and the control terminal of the fourth output unit 440, and can be used to maintain the potential between the first terminal and the control terminal of the fourth output unit 440. The potential at the third node N3 can be adjusted using the second potential holding unit 450 to ensure that the fourth output unit 440 can stably output the first level signal VGH according to the potential at the third node N3.

[0075] In one embodiment, please refer to Figure 3 The second potential holding unit 450 may include a second capacitor C2. The first terminal of the second capacitor C2 can be connected to the first terminal of the fourth output unit 440, and the second terminal of the second capacitor C2 can be connected to the control terminal of the fourth output unit 440. Specifically, the first terminal of the second capacitor C2 can be connected to the gate of the tenth transistor M10, and the second terminal of the second capacitor C2 can be connected to the second terminal of the tenth transistor M10. The second capacitor C2 can stabilize the potential at the third node N3.

[0076] Figure 4 This is a schematic diagram of the shift register structure in another embodiment of this application. Figure 4 The fourth node N4 is also connected to the output of the cascade module 500. In one embodiment, the shift register 10 may further include the cascade module 500. The input of the cascade module 500 can be connected to a first level signal VGH, and the output of the cascade module 500 can be connected to the first output module 300. Specifically, the output of the cascade module 500 can be connected to the control terminal of the first output unit 330 and the control terminal of the second output unit 340. The cascade module 500 can be configured to transmit the first level signal VGH to the first output module 300 according to the cascade signal Cn. The cascade module 500 can be used to realize cascade control between each level of the shift register 10.

[0077] In some preferred embodiments, the signal waveform of the cascade signal Cn connected to the control terminal of the cascade module 500 in the i-th (i=1, 2, 3, ..., n)-th stage shift register 10 can be the same as the potential waveform at the fourth node N4_2 in the (i+2)-th stage shift register 10. In this case, the control terminal of the cascade module 500 in the i-th stage shift register 10 can be connected to the fourth node N4 in the (i+2)-th stage shift register 10, so that the potential at the fourth node N4 in the (i+2)-th stage shift register 10 can be used to control the working state of the cascade module 500 in the i-th stage shift register 10.

[0078] In some preferred embodiments, the potential waveform at the fourth node N4 in the i-th stage shift register 10 can be the same as the signal waveform of the first input signal SIN in the (i+1)-th stage shift register 10. In this case, the fourth node N4 in the i-th stage shift register 10 can be connected to the input terminal of the first input module 100 in the (i+1)-th stage shift register 10, so that the potential at the fourth node N4 in the i-th stage shift register 10 can be used as the first input signal SIN in the (i+1)-th stage shift register 10.

[0079] For example, the fourth node N4 in the third-level shift register 10 can be connected to the control terminal of the cascade module 500 in the first-level shift register 10, that is, the cascade module 500 in the first-level shift register 10 operates according to the potential at the fourth node N4 in the third-level shift register 10; the fourth node N4 in the third-level shift register 10 can also be connected to the input terminal of the first input module 100 in the fourth-level shift register 10, that is, the potential at the fourth node N4 in the third-level shift register 10 is used as the first input signal SIN in the fourth-level shift register 10.

[0080] In some preferred embodiments, the waveform of the second output signal Em_out output by the second output module 400 in the i-th stage shift register 10 can be the same as the waveform of the first input signal SIN in the (i+1)-th stage shift register 10. In this case, the output terminal of the second output module 400 in the i-th stage shift register 10 can be connected to the input terminal of the second input module 100 in the (i+1)-th stage shift register 10, so that the second output signal Em_out output by the second output module 400 in the i-th stage shift register 10 can be used as the second input signal EIN in the (i+1)-th stage shift register 10.

[0081] For example, the output of the second output module 400 in the third-level shift register 10 can be connected to the input of the second input module 100 in the fourth-level shift register 10, that is, the second output signal Em_out in the third-level shift register 10 is used as the first input signal SIN in the fourth-level shift register 10.

[0082] Figure 5 This is a schematic diagram of the circuit structure of the shift register in another embodiment of this application. Figure 5The fourth node N4 is also connected to the second terminal of the eleventh transistor M11. In one embodiment, the cascade module 500 may include the eleventh transistor M11. The first terminal of the eleventh transistor M11 can be used as the input terminal of the cascade module 500, connected to a first level signal VGH. The gate of the eleventh transistor M11 can be connected to a cascade signal Cn. The second terminal of the eleventh transistor M11 can be used as the output terminal of the cascade module 500, connected to the first output module 300. Specifically, the second terminal of the eleventh transistor M11 can be connected to the gate of the fifth transistor M5 and the gate of the sixth transistor M6.

[0083] In a preferred embodiment, the gate of the eleventh transistor M11 in the i-th stage shift register 10 can be connected to the fourth node N4_2 in the (i+2)-th stage shift register 10, and the fourth node N4 in the i-th stage shift register 10 can be connected to the first terminal of the first transistor M1 in the (i+1)-th stage shift register 10. Figure 4 As shown, when the gate of the eleventh transistor M11 in the i-th stage shift register 10 can be connected to the fourth node N4_2 in the (i+2)-th stage shift register 10, the cascaded signal connected to the gate of the eleventh transistor M11 in the i-th stage shift register 10 is N4_2, that is, the signal at the fourth node N4_2.

[0084] In some other embodiments, the cascaded signal Cn connected to the cascade module 500, the first input signal SIN connected to the first input module 100, and the second input signal EIN connected to the second input module 200 in each level of shift register 10 can all be independent input signals. The corresponding signal waveforms can be designed according to the needs of different application scenarios in specific applications. Simultaneously, the fourth node N4 in each level of shift register 10 can also be connected to other circuits to provide the signal waveforms required by those circuits.

[0085] In one embodiment, the first transistor M1, second transistor M2, third transistor M3, fourth transistor M4, fifth transistor M5, seventh transistor M7, eighth transistor M8, ninth transistor M9, tenth transistor M10, and eleventh transistor M11 in the shift register 10 provided in this application can all be P-type transistors, such as polysilicon thin-film transistors. The sixth transistor M6 can be an N-type transistor, such as a polysilicon thin-film transistor. For example, it can be an oxide thin-film transistor, exemplarily an indium gallium zinc oxide thin-film transistor. In some other embodiments, the device selection of each unit in the circuit can also be selected from other suitable functional components according to the actual application requirements.

[0086] The present invention can also provide a driving method for driving the shift register 10 as described in any of the above embodiments. One working cycle of the shift register 10 may include a first stage T1, a second stage T2, a third stage T3, a fourth stage T4, a fifth stage T5, a sixth stage T6, a seventh stage T7, and an eighth stage T8.

[0087] Figure 6 This is a timing diagram of the signals in the shift register in one embodiment of this application. Figure 6 In this diagram, SIN represents the first input signal, EIN represents the second input signal, SCK1 represents the first clock signal, SCK2 represents the second clock signal, Sn_out represents the first output signal (i.e., the signal output from the first output terminal of shift register 10), and Em_out represents the second output signal (i.e., the signal output from the second output terminal of shift register 10). In this embodiment... Figure 5 Taking the shift register 10 shown as an example, combined with Figure 6 The timing diagram shown illustrates in detail the operation of shift register 10 in one working cycle.

[0088] Figure 5 In the shift register 10 shown, transistors M1, M2, M3, M4, M5, M7, M8, M9, M10, and M11 are all P-type transistors, while transistor M6 is an N-type transistor. Transistors M1, M2, M3, M4, M5, M7, M8, M9, M10, and M11 are all P-type transistors, and transistor M6 is an N-type transistor. Transistors M1, M2, M3, M4, M5, M7, M8, M9, M10, and M11 are all turned on when the voltage level is low and turned off when the voltage level is high; transistor M6 is turned on when the voltage level is high and turned off when the voltage level is low.

[0089] In the first stage T1, the level of the first input signal SIN is controlled to be low, the level of the second input signal EIN is controlled to be high, the level of the first clock signal SCK1 is controlled to be low, and the level of the second clock signal SCK2 is controlled to be high.

[0090] When shift register 10 is operating in the first stage T1, since the first clock signal SCK1 is a low-level signal, the second clock signal SCK2 is a high-level signal, and the second input signal EIN is a high-level signal, the first transistor M1 is turned on according to the first clock signal SCK1, the second transistor M2 is turned off according to the second clock signal SCK2, and the fourth transistor M4 is turned off according to the second input signal EIN.

[0091] After the first transistor M1 is turned on, it transmits the first input signal SIN to the first node N1. At this time, the first input signal SIN is a low-level signal, so the potential at the first node N1 is VN1 = VGL - Vth. The third transistor M3 is turned on according to the potential at the first node N1, and the second clock signal SCK2 is transmitted to the fourth node N4 through the third transistor M3. At this time, the second clock signal SCK2 is a high-level signal, so the potential at the fourth node N4 is VN4 = VGH. Since the potential at the fourth node N4 is high, the fifth transistor M5 is turned off, and the sixth transistor M6 is turned on. After the sixth transistor M6 is turned on, it transmits the second-level signal VGL to the output terminal of the first output module 300. Since the fifth transistor M5 is turned off, it cannot transmit the first-level signal VGH to the output terminal of the first output module 300, that is, in the first stage T1, the first output signal Sn_out output by the first output terminal of the shift register 10 is a low-level signal.

[0092] Simultaneously, since the potential at the fourth node N4 is high (VGH), the eighth transistor M8 is turned off according to the potential at the fourth node N4. At this time, the potential at the second node N2 is VN2 = VGL - Vth, therefore, both the seventh transistor M7 and the ninth transistor M9 are turned on according to the potential at the second node N2. After the seventh transistor M7 is turned on, it transmits the first-level signal VGH to the third node N3. Since the potential at the second node N2 is VN3 = VGH, the tenth transistor M10 is turned off according to the potential at the third node N3, and therefore cannot transmit the first-level signal VGH to the output terminal of the second output module 400. After the ninth transistor M9 is turned on, it transmits the second-level signal VGL to the output terminal of the second output module 400. That is, in the first stage T1, the second output signal Em_out output from the second output terminal of the shift register 10 is also a low-level signal.

[0093] In the second stage T2, the level of the first input signal SIN is controlled to be high, the level of the second input signal EIN is controlled to be high, the level of the first clock signal SCK1 is controlled to be high, and the level of the second clock signal SCK2 is controlled to be low.

[0094] When shift register 10 is operating in the second stage T2, since the first clock signal SCK1 is a high-level signal, the second clock signal SCK2 is a low-level signal, and the second input signal EIN is a high-level signal, the first transistor M1 is turned off according to the first clock signal SCK1, the second transistor M2 is turned on according to the second clock signal SCK2, and the fourth transistor M4 is turned off according to the second input signal EIN.

[0095] After the first transistor M1 is turned off, due to the potential-holding effect of the first capacitor C1, the first node N1 is initially still a low-level signal. Therefore, the third transistor M3 turns on according to the potential at the first node N1 and transmits the second clock signal SCK2 to the fourth node N4. At this time, the second clock signal SCK2 is a low-level signal, so the potential at the fourth node N4 becomes VN4 = VGL. Due to the potential-holding effect of the first capacitor C1, that is, the potential difference between the two plates of the first capacitor C1 remains unchanged, when the potential at the second terminal of the first capacitor C1 changes to VGL with the potential change of the fourth node N4, the potential at the first terminal of the first capacitor C1 will also change accordingly. That is, the potential at the first node N1 will become VN1≈VGL-Vth+(Cgs1+1) / ((Cgs1+C1+Cother)*(VGH-VGL)). Where Cgs1 represents the parasitic capacitance between the gate and source-drain of the third transistor M3, Cother represents other parasitic capacitances in the circuit, and C1 represents the first capacitor.

[0096] Since the potential at the fourth node N4 is low, the fifth transistor M5 is turned on according to the potential at the fourth node N4, and the sixth transistor M6 is turned off according to the potential at the fourth node N4. After the fifth transistor M5 is turned on, it transmits the first level signal VGH to the output terminal of the first output module 300. Since the sixth transistor M6 is turned off, it cannot transmit the second level signal VGL to the output terminal of the first output module 300. That is, in the second stage T2, the first output signal Sn_out output from the first output terminal of the shift register 10 is a high level signal.

[0097] After the second transistor M2 is turned on, it transmits the second input signal EIN to the second node N2. Since the second input signal EIN is a high-level signal, the potential of the second node N2 is VN2=VGH. The seventh transistor M7 and the ninth transistor M9 are both turned off according to the potential at the second node N2. Therefore, the seventh transistor M7 cannot transmit the first-level signal VGH to the third node N3, and the ninth transistor M9 cannot transmit the second-level signal VGL to the output of the second output module 400. Simultaneously, since the potential at the fourth node N4 is low, the eighth transistor M8 is turned on according to the potential at the fourth node N4 and transmits the second-level signal VGL to the third node N3, meaning the potential at the third node N3 becomes VN3=VGL. The tenth transistor M10 is turned on according to the potential at the third node N3 and transmits the first-level signal VGH to the output of the second output module 400. Therefore, in the second stage T2, the second output signal Em_out output from the second output terminal of the shift register 10 is also a high-level signal.

[0098] In the third stage T3, the level of the first input signal SIN is controlled to be high, the level of the second input signal EIN is controlled to be high, the level of the first clock signal SCK1 is controlled to be low, and the level of the second clock signal SCK2 is controlled to be high.

[0099] When shift register 10 is operating in the third stage T3, since the first clock signal SCK1 is a low-level signal, the second clock signal SCK2 is a high-level signal, and the second input signal EIN is a high-level signal, the first transistor M1 is turned on according to the first clock signal SCK1, the second transistor M2 is turned off according to the second clock signal SCK2, and the fourth transistor M4 is turned off according to the second input signal EIN.

[0100] After the first transistor M1 is turned on, it transmits the first input signal SIN to the first node N1. At this time, the first input signal SIN is a high-level signal, so the potential at the first node N1 is VN1=VGH. The third transistor M3 is turned off according to the potential at the first node N1. Due to the potential holding effect of the first capacitor C1, when the potential at the first terminal of the first capacitor C1 increases with the potential at the fourth node N4, the potential at the second terminal of the first capacitor C1 will also increase accordingly, so the level at the fourth node N4 is also high. The fifth transistor M5 is turned off according to the potential at the fourth node N4, and the sixth transistor M6 is turned on according to the potential at the fourth node N4. After the fifth transistor M5 is turned off, it cannot transmit the first level signal VGH to the output terminal of the first output module 300. After the sixth transistor M6 is turned on, it transmits the second level signal VGL to the output terminal of the first output module 300. That is, in the third stage T3, the first output signal Sn_out output by the first output terminal of the shift register 10 is a low-level signal.

[0101] The second transistor M2 is turned off, and the potential of the second node N2 remains the same as in the second stage T2, with VN2 = VGH. Both the seventh transistor M7 and the ninth transistor M9 are turned off according to the potential at the second node N2. Therefore, the seventh transistor M7 cannot transmit the first-level signal VGH to the third node N3, and the ninth transistor M9 cannot transmit the second-level signal VGL to the output of the second output module 400. Simultaneously, since the potential at the fourth node N4 is high, the eighth transistor M8 is turned off according to the potential at the fourth node N4, and cannot transmit the second-level signal VGL to the third node N3. That is, the potential at the third node N3 also remains the same as in the second stage T2, with VN3 = VGL. The tenth transistor M10 is turned on according to the potential at the third node N3 and transmits the first-level signal VGH to the output of the second output module 400. Therefore, in the third stage T3, the second output signal Em_out output from the second output terminal of the shift register 10 remains a high-level signal.

[0102] In the fourth stage T4, the level of the first input signal SIN is controlled to be high, the level of the second input signal EIN is controlled to be high, the level of the first clock signal SCK1 is controlled to be high, and the level of the second clock signal SCK2 is controlled to be low.

[0103] When shift register 10 is operating in the fourth stage T4, since the first clock signal SCK1 is a high-level signal, the second clock signal SCK2 is a low-level signal, and the second input signal EIN is a high-level signal, the first transistor M1 is turned off according to the first clock signal SCK1, the second transistor M2 is turned on according to the second clock signal SCK2, and the fourth transistor M4 is turned off according to the second input signal EIN.

[0104] After the first transistor M1 is turned off, the potential at the first node N1 remains the same as in the third stage T3, and the potential at the first node N1 is VN1=VGH. The third transistor M3 is turned off according to the potential at the first node N1. In this embodiment, since the fourth node N4 of the i-th stage shift register 10 is connected to the input terminal of the first input module 100 of the (i+1)-th stage shift register 10, and the electrical signal at the fourth node N4 of the i-th stage shift register 10 is the first input signal SIN of the i-th stage shift register 10 delayed by one clock unit, the electrical signal at the fourth node N4 of the (i+2)-th stage shift register 10 is the first input signal SIN of the i-th stage shift register 10 delayed by two clock units.

[0105] Simultaneously, since the gate of the eleventh transistor M11 in the i-th shift register 10 is connected to the fourth node N4 in the (i+2)-th stage shift register 10, the potential at the gate of the eleventh transistor M11 in the fourth stage T4 of the i-th shift register 10 is the same as the potential at the fourth node N4 in the second stage T2 of the i-th shift register 10. The potential at the fourth node N4 in the second stage T2 is low, thus the potential at the gate of the eleventh transistor M11 in the fourth node T4 is also low. The eleventh transistor M11 is turned on according to the potential at its gate and transmits the first level signal VGH to the fourth node N4, i.e., the potential at the fourth node N4 is VN4 = VGH.

[0106] The fifth transistor M5 is cut off according to the potential of the fourth node N4, and the sixth transistor M6 is turned on according to the potential of the fourth node N4. After the fifth transistor M5 is cut off, it cannot transmit the first level signal VGH to the output terminal of the first output module 300. After the sixth transistor M6 is turned on, it transmits the second level signal VGL to the output terminal of the first output module 300. That is, in the fourth stage T4, the first output signal Sn_out output by the first output terminal of the shift register 10 is still a low level signal.

[0107] The second transistor M2 is turned on, transmitting the second input signal EIN to the second node N2. Since EIN is high, the potential at node N2 is VN2 = VGH. Both the seventh transistor M7 and the ninth transistor M9 are turned off based on the potential at node N2. Therefore, the seventh transistor M7 cannot transmit the first-level signal VGH to the third node N3, and the ninth transistor M9 cannot transmit the second-level signal VGL to the output of the second output module 400. Simultaneously, because the potential at the fourth node N4 is high, the eighth transistor M8 is turned off based on the potential at node N4, preventing it from transmitting the second-level signal VGL to the third node N3. Therefore, the potential at the third node N3 remains the same as in the third stage T3, VN3 = VGL. The tenth transistor M10 is turned on according to the potential at the third node N3 and transmits the first level signal VGH to the output terminal of the second output module 400. That is, in the third stage T3, the second output signal Em_out output by the second output terminal of the shift register 10 is still a high level signal.

[0108] In the fifth stage T5, the level of the first input signal SIN is controlled to be high, the level of the second input signal EIN is controlled to be low, the level of the first clock signal SCK1 is controlled to be low, and the level of the second clock signal SCK2 is controlled to be high.

[0109] When shift register 10 is operating in the fifth stage T5, since the first clock signal SCK1 is a low-level signal, the second clock signal SCK2 is a high-level signal, and the second input signal EIN is a low-level signal, the first transistor M1 is turned on according to the first clock signal SCK1, the second transistor M2 is turned off according to the second clock signal SCK2, and the fourth transistor M4 is turned on according to the second input signal EIN.

[0110] After the first transistor M1 is turned on, it transmits the first input signal SIN to the first node N1. At this time, the first input signal SIN is a high-level signal, so the potential at the first node N1 is VN1=VGH. The third transistor M3 is turned off according to the potential at the first node N1. After the fourth transistor M4 is turned on, it transmits the first-level signal VGH to the fourth node N4, that is, the potential at the fourth node N4 is VN4=VGH. The fifth transistor M5 is turned off according to the potential at the fourth node N4, and the sixth transistor M6 is turned on according to the potential at the fourth node N4. After the fifth transistor M5 is turned off, it cannot transmit the first-level signal VGH to the output terminal of the first output module 300. After the sixth transistor M6 is turned on, it transmits the second-level signal VGL to the output terminal of the first output module 300. That is, in the fifth stage T5, the first output signal Sn_out output from the first output terminal of the shift register 10 is still a low-level signal.

[0111] The second transistor M2 is turned off, and the potential of the second node N2 remains the same as in the fourth stage T4, with the potential at the second node N2 being VN2=VGH. The seventh transistor M7 and the ninth transistor M9 are both turned off according to the potential at the second node N2. Simultaneously, since the potential at the fourth node N4 is high, the eighth transistor M8 is turned off according to the potential at the fourth node N4. That is, the potential at the third node N3 also remains the same as in the second stage T2, with the potential at the third node N3 being VN3=VGL. The tenth transistor M10 is turned on according to the potential at the third node N3 and transmits the first level signal VGH to the output terminal of the second output module 400. That is, in the third stage T3, the second output signal Em_out output from the second output terminal of the shift register 10 remains a high level signal.

[0112] In the sixth stage T6, the level of the first input signal SIN is controlled to be high, the level of the second input signal EIN is controlled to be low, the level of the first clock signal SCK1 is controlled to be high, and the level of the second clock signal SCK2 is controlled to be low.

[0113] When shift register 10 is operating in the sixth stage T6, since the first clock signal SCK1 is a high-level signal, the second clock signal SCK2 is a low-level signal, and the second input signal EIN is a low-level signal, the first transistor M1 is turned off according to the first clock signal SCK1, the second transistor M2 is turned on according to the second clock signal SCK2, and the fourth transistor M4 is turned on according to the second input signal EIN.

[0114] After the first transistor M1 is turned off, the potential at the first node N1 remains the same as in the fifth stage T5, with VN1 = VGH. The third transistor M3 is turned off according to the potential at the first node N1. Due to the potential-holding effect of the first capacitor C1, the potential at the fourth node N1 is also held, the same as in the fifth stage T5, with VN4 = VGH. The fifth transistor M5 is turned off according to the potential at the fourth node N4, and the sixth transistor M6 is turned on according to the potential at the fourth node N4. After the fifth transistor M5 is turned off, the first level signal VGH cannot be transmitted to the output terminal of the first output module 300. After the sixth transistor M6 is turned on, the second level signal VGL is transmitted to the output terminal of the first output module 300. That is, in the sixth stage T6, the first output signal Sn_out output from the first output terminal of the shift register 10 is still a low level signal.

[0115] The second transistor M2 is turned on, transmitting the second input signal EIN to the second node N2. The second input signal EIN is low, meaning the potential at the second node N2 is VN2 = VGL - Vth. The seventh transistor M7 and the ninth transistor M9 are both turned on according to the potential at the second node N2. The seventh transistor M7 transmits the first level signal VGH to the third node N3, and the ninth transistor M9 transmits the second level signal VGL to the output terminal of the second output module 400. Simultaneously, since the potential at the fourth node N4 is high, the eighth transistor M8 is turned off according to the potential at the fourth node N4, and cannot transmit the second level signal VGL to the third node N3. That is, the potential at the third node N3 is VN3 = VGH. The tenth transistor M10 is turned off according to the potential at the third node N3. In the sixth stage T6, the second output signal Em_out output from the second output terminal of the shift register 10 is a low-level signal.

[0116] In the seventh stage T7, the level of the first input signal SIN is controlled to be high, the level of the second input signal EIN is controlled to be low, the level of the first clock signal SCK1 is controlled to be low, and the level of the second clock signal SCK2 is controlled to be high.

[0117] When shift register 10 is operating in stage 7 T7, since the first clock signal SCK1 is low, the second clock signal SCK2 is high, and the second input signal EIN is low, the first transistor M1 is turned on according to the first clock signal SCK1, the second transistor M2 is turned off according to the second clock signal SCK2, and the fourth transistor M4 is turned on according to the second input signal EIN.

[0118] After the first transistor M1 is turned on, it transmits the first input signal SIN to the first node N1. At this time, the first input signal SIN is a high-level signal, and the potential at the first node N1 is VN1=VGH. The third transistor M3 is turned off according to the potential at the first node N1. After the fourth transistor M4 is turned on, it transmits the first-level signal VGH to the fourth node N4, that is, the potential at the fourth node N4 is VN4=VGH. The fifth transistor M5 is turned off according to the potential at the fourth node N4, and the sixth transistor M6 is turned on according to the potential at the fourth node N4. In the fifth stage T5, the first output signal Sn_out output from the first output terminal of the shift register 10 is still a low-level signal.

[0119] The second transistor M2 is turned off, and the potential of the second node N2 remains the same as in stage T6, with the potential at the second node N2 being VN2 = VGL - Vth. The seventh transistor M7 and the ninth transistor M9 are both turned on according to the potential at the second node N2. The seventh transistor M7 transmits the first-level signal VGH to the third node N3, and the ninth transistor M9 transmits the second-level signal VGL to the output of the second output module 400. Simultaneously, since the potential at the fourth node N4 is high, the eighth transistor M8 is turned off according to the potential at the fourth node N4, and cannot transmit the second-level signal VGL to the third node N3. That is, the potential at the third node N3 is VN3 = VGH. The tenth transistor M10 is turned off according to the potential at the third node N3. In stage T6, the second output signal Em_out output from the second output terminal of the shift register 10 is a low-level signal.

[0120] In the eighth stage T8, the level of the first input signal SIN is controlled to be high, the level of the second input signal EIN is controlled to be low, the level of the first clock signal SCK1 is controlled to be high, and the level of the second clock signal SCK2 is controlled to be low.

[0121] When shift register 10 is operating in stage T8, since the first clock signal SCK1 is a high-level signal, the second clock signal SCK2 is a low-level signal, and the second input signal EIN is a low-level signal, the first transistor M1 is turned off according to the first clock signal SCK1, the second transistor M2 is turned on according to the second clock signal SCK2, and the fourth transistor M4 is turned on according to the second input signal EIN.

[0122] After the first transistor M1 is turned off, the potential at the first node N1 remains the same as in stage T5, with VN1 = VGH. The third transistor M3 is turned off according to the potential at the first node N1. Due to the potential-holding effect of the first capacitor C1, the potential at the fourth node N1 is also held, the same as in stage T5, with VN4 = VGH. The fifth transistor M5 is turned off according to the potential at the fourth node N4, and the sixth transistor M6 is turned on according to the potential at the fourth node N4. After the fifth transistor M5 is turned off, the first level signal VGH cannot be transmitted to the output terminal of the first output module 300. After the sixth transistor M6 is turned on, the second level signal VGL is transmitted to the output terminal of the first output module 300. That is, in stage T8, the first output signal Sn_out output from the first output terminal of the shift register 10 is still a low level signal.

[0123] The second transistor M2 is turned on, transmitting the second input signal EIN to the second node N2. The second input signal EIN is low, meaning the potential at the second node N2 is VN2 = VGL - Vth. The seventh transistor M7 and the ninth transistor M9 are both turned on according to the potential at the second node N2. The seventh transistor M7 transmits the first level signal VGH to the third node N3, and the ninth transistor M9 transmits the second level signal VGL to the output terminal of the second output module 400. Simultaneously, since the potential at the fourth node N4 is high, the eighth transistor M8 is turned off according to the potential at the fourth node N4, and cannot transmit the second level signal VGL to the third node N3. That is, the potential at the third node N3 is VN3 = VGH. The tenth transistor M10 is turned off according to the potential at the third node N3. In the eighth stage T8, the second output signal Em_out output from the second output terminal of the shift register 10 is a low-level signal.

[0124] In this embodiment, preferably, the fourth node N4 in the i-th level shift register 10 is connected to the input terminal of the first input module 100 in the (i+1)-th level shift register 10, and the output terminal of the second output module 400 in the i-th level shift register 10 is connected to the input terminal of the second input module 200 in the (i+1)-th level shift register 10.

[0125] The above-described shift register driving method is applied to the shift register 10 in any of the above embodiments. The first input module 100 and the first output module 300 cooperate to output a first output signal Sn_out. The first output signal Sn_out can be transmitted to the pixel circuit as a gate driving signal to drive the functional modules in the pixel circuit. The second input module 200 and the second output module 200 cooperate to output a second output signal Em_out. The second output signal Em_out can also be transmitted to the pixel circuit as a gate driving signal to drive the functional modules in the pixel circuit.

[0126] according to Figure 6 As shown in the timing diagram, both the first output signal Sn_out and the second output signal Em_out are high-level pulse signals, differing only in their pulse widths. Simultaneously, the pulse width of the second output signal Em_out, output from shift register 10, is controlled by the second input signal EIN. Therefore, the high-level output time of the second output signal Em_out can be adjusted by regulating the duration of the high-level signal EIN. By making the high-level time of the second output signal Em_out adjustable, the screen's illumination effect can be ensured during subsequent screen debugging by adjusting the high-level duration of the second output signal Em_out.

[0127] This application provides a novel shift register 10 circuit structure, which can simultaneously output high-level pulse signals with different pulse widths, ensuring the normal operation of the pixel circuit within the screen while guaranteeing the output reliability of the shift register 10. Compared to existing solutions that require two Scan circuits to simultaneously output high-level pulse signals with different pulse widths, this application only requires one shift register 10. Therefore, when the shift register 10 provided in this application is applied to a display device, the number of shift register 10 groups, CLK signals, and TFT devices in the display device can be reduced, thereby reducing the layout space occupied by the shift register 10 and facilitating the achievement of narrow bezels and low power consumption.

[0128] It should be understood that although the steps in the flowcharts of the accompanying drawings are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some of the steps in the flowcharts of the accompanying drawings may include multiple steps or stages, which are not necessarily completed at the same time, but may be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0129] This invention also provides a gate driving circuit, which may include a plurality of cascaded shift registers as described in any of the above embodiments. Figure 7 This is a schematic diagram of the gate driving circuit in one embodiment of this application. In one embodiment, the gate driving circuit may include n-stage shift registers 10, where n is an integer greater than zero. Each stage of shift register 10 may include a first input module 100, a second input module 200, a first output module 300, and a second output module 400. The first output module 300 may include a first output control module 310. In the n-stage shift registers 10, except for the nth stage shift register 10, the signal output by the first output control module 310 of the i-th stage shift register is used as the first input signal SIN of the (i+1)-th stage shift register 10, and the second output signal Em_out output by the second output module 400 of the i-th stage shift register 10 can be used as the second input signal EIN of the (i+1)-th stage shift register 10; where n is an integer greater than zero, i = 1, 2, 3, ..., n.

[0130] like Figure 7 As shown, the first output signal Sn_out output by the first output module 300 in the first-stage shift register 10 can be used as the first input signal SIN connected to the first input module 100 in the second-stage shift register 10; the second output signal Em_out output by the second output module 400 in the first-stage shift register 10 can be used as the second input signal connected to the second input module 200 in the second-stage shift register 10.

[0131] In the aforementioned gate drive circuit, the first input signal SIN connected to the input terminal of the first input module 100 in the first-stage shift register 10 can be an independent input signal or a signal output by the first output control module 310 in the nth-stage shift register 10; the second input signal EIN connected to the input terminal of the second input module 200 in the first-stage shift register 10 can be an independent input signal or a second output signal Em_out output by the second output module 400 in the nth-stage shift register 10. The first input signal SIN connected to the input terminal of the first input module 100 in the ith-stage shift register 10 can be a signal output by the first output control module 310 in the (i-1)th-stage shift register 10 (where i = 2, 3, 4, ..., n); the second input signal EIN connected to the input terminal of the second input module 200 in the ith-stage shift register 10 can be the second output signal Em_out output by the second output module 400 in the (i-1)th-stage shift register 10.

[0132] In the aforementioned gate driving circuit, each stage of the shift register 10 can output two pulse signals with different pulse widths, reducing the space occupied by the gate driving circuit. When this gate driving circuit is applied to a display panel, it can greatly save space on the left and right bezels, achieving a narrow bezel effect. Simultaneously, the cascaded shift triggering between each stage of the shift register 10 provides high circuit stability.

[0133] In one embodiment, besides the nth-level shift register 10 and the (n-1)th-level shift register 10, the signal N4_2 output by the first output control module 310 of the (i+2)th-level shift register 10 can be used as the cascaded signal Cn connected to the i-th-level shift register 10. That is, the fourth node N4 of the (i+2)th-level shift register 10 can be connected to the control terminal of the cascade module 500 in the i-th-level shift register 10. For example, as Figure 7 As shown, the signal at the fourth node N4 in the third-stage shift register 10 is used as the cascaded signal Cn connected to the i-th-stage shift register 10.

[0134] In the aforementioned gate drive circuit, the cascade signal Cn connected to the control terminal of the cascade module 500 in the (n-1)th stage shift register 10 can be an independent input signal or a signal output by the first output control module 310 in the first stage shift register 10. Similarly, the cascade signal Cn connected to the control terminal of the cascade module 500 in the nth stage shift register 10 can be an independent input signal or a signal output by the first output control module 310 in the second stage shift register 10. The cascade signal Cn connected to the control terminal of the cascade module 500 in the i-th stage shift register 10 can be a signal output by the first output control module 310 in the (i+2)-th stage shift register 10 (where i = 2, 3, 4, ..., n).

[0135] This invention also provides a display panel that includes the gate driving circuit described in any of the above embodiments. The display panel may include one or more sets of gate driving circuits. The gate driving circuit can be configured to generate a gate driving signal and use the gate driving signal to change the conduction state of the switching devices in the pixel circuit. This display panel can be applied to any product or component with display functionality, including but not limited to the following categories: mobile phones, televisions, digital cameras, tablet computers, laptops, desktop monitors, smart bracelets, smart glasses, automotive displays, medical devices, industrial control equipment, touch interactive terminals, etc. This invention does not impose any special limitations on these categories.

[0136] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0137] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0138] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A shift register, characterized in that, It includes a first input module, a second input module, a first output module, and a second output module. The control terminals of the first output module include a first control terminal and a second control terminal, and the control terminals of the second output module also include a first control terminal and a second control terminal. The output terminal of the first input module is connected to the first control terminal of the first output module, and the first input module is configured to transmit a first input signal to the first control terminal of the first output module according to a first clock signal; The input terminal of the second input module is connected to the second control terminal of the first output module, and the output terminal of the second input module is connected to the first control terminal of the second output module. The second input module is configured to transmit a second input signal to the first control terminal of the second output module according to a second clock signal. The first output module is configured to output a first output signal based on the signal at the control terminal of the first output module; The second control terminal of the second output module is connected to the first output module, and the second output module is configured to output a second output signal according to the signal at the control terminal of the second output module.

2. The shift register according to claim 1, characterized in that, The first output module includes a first output control unit, a second output control unit, a first output unit, and a second output unit. The control terminal of the first output control unit serves as the first control terminal of the first output module, and the control terminal of the second output control unit serves as the second control terminal of the first output module. The first terminal of the first output control unit is connected to the second clock signal, the control terminal of the first output control unit is connected to the output terminal of the first input module, the second terminal of the first output control unit is connected to the control terminal of the first output unit and the control terminal of the second output unit respectively, and the first output control unit is configured to transmit the second clock signal to the control terminal of the first output unit and the control terminal of the second output unit according to the signal at the control terminal of the first output control unit. The first terminal of the second output control unit is connected to a first level signal, the control terminal of the second output control unit is connected to the input terminal of the second input module, the second terminal of the second output control unit is connected to the control terminal of the first output unit and the control terminal of the second output unit respectively, and the second output control unit is configured to transmit the first level signal to the control terminal of the first output unit and the control terminal of the second output unit according to the signal at the control terminal of the second output control unit; The first terminal of the first output unit is connected to a first level signal, and the second terminal of the first output unit is connected to the output terminal of the first output module. The first output unit is configured to transmit the first level signal to the output terminal of the first output module according to the signal at the control terminal of the first output unit. The first terminal of the second output unit is connected to a second level signal, and the second terminal of the second output unit is connected to the output terminal of the first output module. The second output unit is configured to transmit the second level signal to the output terminal of the first output module according to the signal at the control terminal of the second output unit.

3. The shift register according to claim 2, characterized in that, The first output control unit includes a third transistor, the first terminal of the third transistor serves as the first terminal of the first output control unit, the gate of the third transistor serves as the control terminal of the first output control unit, and the second terminal of the third transistor serves as the second terminal of the first output control unit. The second output control unit includes a fourth transistor, the first terminal of the fourth transistor serves as the first terminal of the second output control unit, the gate of the fourth transistor serves as the control terminal of the second output control unit, and the second terminal of the fourth transistor serves as the second terminal of the second output control unit; The first output unit includes a fifth transistor, the first terminal of the fifth transistor serves as the first terminal of the first output unit, the gate of the fifth transistor serves as the control terminal of the first output unit, and the second terminal of the fifth transistor serves as the second terminal of the first output unit. The second output unit includes a sixth transistor, the first terminal of which serves as the first terminal of the second output unit, the gate of which serves as the control terminal of the second output unit, and the second terminal of which serves as the second terminal of the second output unit.

4. The shift register according to claim 3, characterized in that, The conduction level of the fifth transistor is different from that of the sixth transistor.

5. The shift register according to claim 1, characterized in that, The pulse width of the first output signal is different from the pulse width of the second output signal.

6. The shift register according to claim 2, characterized in that, The first output module further includes a first potential holding unit, which is connected between the control terminal of the second output control unit and the second terminal of the second output control unit, and is used to maintain the potential between the control terminal of the second output control unit and the second terminal of the second output control unit.

7. The shift register according to claim 6, characterized in that, The first potential holding unit includes a first capacitor, the first end of which is connected to the control terminal of the second output control unit, and the second end of which is connected to the second terminal of the second output control unit.

8. The shift register according to claim 1 or 2, characterized in that, The second output module includes a third output control unit, a fourth output control unit, a third output unit, and a fourth output unit. The control terminal of the third output control unit serves as the first control terminal of the second output module, and the control terminal of the fourth output control unit serves as the second control terminal of the second output module. The first terminal of the third output control unit is connected to a first level signal, the control terminal of the third output control unit is connected to the output terminal of the second input module, the second terminal of the third output control unit is connected to the control terminal of the fourth output unit, and the third output control unit is configured to transmit the first level signal to the control terminal of the fourth output unit according to the signal at the control terminal of the third output control unit. The first terminal of the fourth output control unit is connected to a second level signal, the control terminal of the fourth output control unit is connected to the first output module, the second terminal of the fourth output control unit is connected to the control terminal of the fourth output unit, and the fourth output control unit is configured to transmit the second level signal to the control terminal of the fourth output unit according to the signal at the control terminal of the fourth output control unit. The first terminal of the third output unit is connected to a second level signal, the control terminal of the third output unit is connected to the output terminal of the second input module, the second terminal of the third output unit is connected to the output terminal of the second output module, and the third output unit is configured to transmit the second level signal to the output terminal of the second output module according to the signal at the control terminal of the third output unit. The first terminal of the fourth output unit is connected to a first level signal, and the second terminal of the fourth output unit is connected to the output terminal of the second output module. The fourth output unit is configured to transmit the first level signal to the output terminal of the second output module according to the signal at the control terminal of the fourth output unit.

9. The shift register according to claim 8, characterized in that, The third output control unit includes a seventh transistor, the first terminal of the seventh transistor serves as the first terminal of the third output control unit, the gate of the seventh transistor serves as the control terminal of the third output control unit, and the second terminal of the seventh transistor serves as the second terminal of the third output control unit; The fourth output control unit includes an eighth transistor, the first terminal of the eighth transistor serves as the first terminal of the fourth output control unit, the gate of the eighth transistor serves as the control terminal of the fourth output control unit, and the second terminal of the eighth transistor serves as the second terminal of the fourth output control unit; The third output unit includes a ninth transistor, the first terminal of the ninth transistor serves as the first terminal of the third output unit, the gate of the ninth transistor serves as the control terminal of the third output unit, and the second terminal of the ninth transistor serves as the second terminal of the third output unit. The fourth output unit includes a tenth transistor, the first terminal of the tenth transistor serves as the first terminal of the fourth output unit, the gate of the tenth transistor serves as the control terminal of the fourth output unit, and the second terminal of the tenth transistor serves as the second terminal of the fourth output unit.

10. The shift register according to claim 8, characterized in that, The second output module further includes a second potential holding unit, which is connected between the first terminal of the fourth output unit and the control terminal of the fourth output unit, for maintaining the potential between the first terminal of the fourth output unit and the control terminal of the fourth output unit.

11. The shift register according to claim 10, characterized in that, The second potential holding unit includes a second capacitor, the first end of which is connected to the first end of the fourth output unit, and the second end of which is connected to the control terminal of the fourth output unit.

12. The shift register according to claim 2, characterized in that, The first input module includes a first transistor, the first terminal of the first transistor is connected to the first input signal, the gate of the first transistor is connected to the first clock signal, and the second terminal of the first transistor serves as the output terminal of the first input module. The second input module includes a second transistor, the first terminal of the second transistor is connected to the second input signal, the gate of the second transistor is connected to the second clock signal, and the second terminal of the second transistor serves as the output terminal of the second input module.

13. The shift register according to claim 1 or 2, characterized in that, The shift register further includes a cascading module, the input of which is connected to a first level signal, and the output of which is connected to the first output module. The cascading module is configured to transmit the first level signal to the first output module according to the cascading signal.

14. The shift register according to claim 13, characterized in that, The cascade module includes an eleventh transistor. The first terminal of the eleventh transistor serves as the input terminal of the cascade module, the gate of the eleventh transistor is connected to the cascade signal, and the second terminal of the eleventh transistor serves as the output terminal of the cascade module.

15. A gate driving circuit, characterized in that, The system comprises n cascaded shift registers as described in any one of claims 1 to 14, wherein, except for the shift register of the nth stage, the signal output by the first output control module of the shift register of the i-th stage serves as the first input signal of the shift register of the (i+1)-th stage, and the second output signal output by the second output module of the shift register of the i-th stage serves as the second input signal of the shift register of the (i+1)-th stage; wherein n is a positive integer, i = 1, 2, 3, ..., n.

16. The gate driving circuit according to claim 15, characterized in that, In addition to the shift registers of the nth stage and the (n-1)th stage, the signal output by the first output control module of the (i+2)th stage shift register is used as the cascaded signal connected to the shift register of the ith stage.

17. A display panel, characterized in that, Includes the gate drive circuit as described in any one of claims 15 to 16.

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