Partition display driving method, display driving circuit and display screen

Abstract

The application discloses a partition display driving method, a display driving circuit and a display screen. The absolute value of the gate-off voltage received by the switching transistor in the pixel driving unit corresponding to the second display area is reduced according to the pixel range of the second display area by acquiring the pixel ranges of the first display area and the second display area. The gate-on voltage received by the switching transistor in the pixel driving unit corresponding to the first display area is reduced according to the pixel range of the first display area, so that the positive voltage and the negative voltage of the gate of the switching transistor can be differentiated when the display panel starts the partition refresh function, and the purpose of reducing the brightness difference caused by PBS or NBS is achieved.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a partitioned display driving method, a display driving circuit, and a display screen. Background Technology

[0002] As people's living standards improve, electronic products play an important role in people's lives. Display panels are an important component of electronic products, so the demand for display panels is increasing.

[0003] Ordinary display effects can no longer meet people's quality of life, and people's demand for high refresh rate display panels is increasing. However, under the condition of zone refresh, display panels will cause brightness differences in different areas. Summary of the Invention

[0004] In view of the above problems, this application provides a partitioned display driving method, a display driving circuit, and a display screen, aiming to provide a partitioned refresh scheme to solve the problem that the display panel will cause brightness differences in different areas under partitioned refresh conditions.

[0005] A first aspect of this application provides a partitioned display driving method, the partitioned display driving method comprising:

[0006] Obtain the pixel range of the first display area and the second display area;

[0007] The absolute value of the gate turn-off voltage received by the switching transistor in the pixel driving unit corresponding to the second display area is controlled to decrease according to the pixel range of the second display area.

[0008] The gate conduction voltage received by the switching transistor in the pixel driving unit corresponding to the first display area is reduced according to the pixel range of the first display area.

[0009] In some embodiments, the greater the difference in refresh rates between the first display area and the second display area, the greater the decrease in the absolute value of the gate turn-off voltage received by the switching transistor in the pixel driving unit corresponding to the second display area.

[0010] In some embodiments, the decrease in the gate conduction voltage received by the switching transistor in the pixel driving unit corresponding to the first display area is related to the refresh rate difference between the second display area and the first display area.

[0011] In some embodiments, the greater the difference in refresh rates between the first display area and the second display area, the greater the decrease in the gate conduction voltage received by the switching transistor in the pixel driving unit corresponding to the first display area.

[0012] In some embodiments, the partition display driving method further includes:

[0013] Obtain the difference in refresh rates between the first display area and the second display area;

[0014] The decrease in the gate conduction voltage received by the switching transistor in the pixel driving unit corresponding to the first display area is determined based on the difference in refresh rates between the first display area and the second display area.

[0015] In some embodiments, determining the decrease in the gate on-state voltage received by the switching transistor in the pixel driving unit corresponding to the first display area based on the difference in refresh rates between the first display area and the second display area includes:

[0016] The gate conduction voltage received by the switching transistor in the pixel driving unit corresponding to the first display area is determined based on the difference in refresh rates between the first display area and the second display area and a preset refresh rate-gate voltage relationship table.

[0017] In some embodiments, determining the decrease in the gate on-state voltage received by the switching transistor in the pixel driving unit corresponding to the first display area based on the difference in refresh rates between the first display area and the second display area includes:

[0018] The gate conduction voltage received by the switching transistor in the pixel driving unit corresponding to the first display area is gradually reduced according to the difference in refresh rates between the first display area and the second display area.

[0019] In some embodiments, the partition display driving method further includes:

[0020] The high-level pulse width of the gate pulse signal of the switching transistor in the pixel driving unit corresponding to the first display area is reduced.

[0021] A second aspect of this application also provides a display driving circuit, which includes a plurality of pixel driving units and a main control circuit. The main control circuit is used to execute the partitioned display driving method as described in any of the above embodiments.

[0022] The plurality of pixel driving units are used to drive the plurality of display pixels to light up respectively.

[0023] A third aspect of this application also provides a display screen, the display screen including the display driving circuit as described in any of the above embodiments.

[0024] The beneficial effects of this application embodiment are as follows: By obtaining the pixel range of the first display area and the second display area, the absolute value of the gate turn-off voltage received by the switching transistor in the pixel driving unit corresponding to the second display area is controlled to decrease according to the pixel range of the second display area; the gate turn-on voltage received by the switching transistor in the pixel driving unit corresponding to the first display area is controlled to decrease according to the pixel range of the first display area, so that when the display panel enables the partition refresh function, the gate positive voltage and negative voltage of the switching transistor can be differentiated, thereby reducing the brightness difference caused by PBS or NBS.

[0025] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0026] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiments below. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0027] Figure 1 This is a first schematic diagram of the partition display driving method provided in the embodiments of this application;

[0028] Figure 2 A schematic diagram of a pixel driving unit provided in an embodiment of this application;

[0029] Figure 3 This is a second schematic diagram of the partition display driving method provided in the embodiments of this application;

[0030] Figure 4 This is a third schematic diagram of the partition display driving method provided in the embodiments of this application;

[0031] Figure 5a and Figure 5b The timing diagrams for the first scan control signal SN1, the second scan control signal SN2, the first data control signal SP1, the second data control signal SP2, and the dimming control signal EM within the first display area are shown before and after modification.

[0032] Figure 6 This is a schematic diagram of a display driving circuit provided in an embodiment of this application. Detailed Implementation

[0033] The embodiments of the technical solution of this application will now be described in detail with reference to the accompanying drawings. These embodiments are only used to more clearly illustrate the technical solution of this application and are therefore merely examples, and should not be used to limit the scope of protection of this application.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims, and foregoing description of the drawings are intended to cover non-exclusive inclusion.

[0035] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.

[0036] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The phrase "second connection port" at various locations in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0037] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0038] In the description of the embodiments of this application, the term "multiple frames" refers to two or more (including two).

[0039] In the description of the embodiments of this application, the technical terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of this application and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application.

[0040] In related technologies, to achieve better power efficiency and extend the usage time of electronic products, different refresh rates can be set for different areas of the screen. However, when the display screen refreshes in sections, different refresh rates in each display area can cause brightness differences in different areas due to the different characteristic offsets of the switching transistors in the pixel driving circuit of the thin-film transistor (TFT) device at different refresh rates. For example, at 120Hz, the switching transistors performing scan driving are in a cyclic state of positive bias stress (PBS) / negative bias stress (NBS). At low refresh rates, the switching transistors are in a long-term NBS state. In the PBS state, the gate of one of the switching transistors has a positive voltage of about 8V, which causes electrons in the thin film to be attracted to the interface between indium gallium zinc oxide (IGZO) and the gate insulating layer (GI), and thus captured by defects at the interface. This causes the transfer characteristic curve of the device to shift towards the positive value of the gate-source voltage (Vgs). In the NBS state, holes in the thin film are attracted to defects near the interface and captured, causing the TFT characteristic drift Vgs to shift in the negative direction, resulting in brightness differences under partitioned refresh.

[0041] To address the aforementioned technical problems, this application provides a partitioned display driving method, see below. Figure 1 As shown, the partition display driving method in this embodiment includes steps S100 to S300.

[0042] In step S100, the pixel ranges of the first display area and the second display area are obtained.

[0043] In this embodiment, the second display area refers to an area of ​​the display panel that uses a lower refresh rate, and the first display area refers to an area of ​​the display panel that uses a higher refresh rate. The refresh rate of the first display area is higher than that of the second display area. When displaying an image, the display panel can display certain areas at a lower refresh rate according to user needs or image display requirements. For example, in areas where only text needs to be displayed, the refresh rate of that area can be reduced to lower display power consumption.

[0044] In some embodiments, the refresh rate of the second display area may be less than 30Hz.

[0045] In some embodiments, the refresh rate of the second display area can be 1Hz.

[0046] In some embodiments, the refresh rate of the first display area may be greater than 60Hz.

[0047] In some embodiments, the refresh rate of the first display area can be 120Hz.

[0048] In step S200, the absolute value of the gate turn-off voltage received by the switching transistor in the pixel driving unit corresponding to the second display area is controlled to decrease according to the pixel range of the second display area.

[0049] In this embodiment, the display panel includes multiple display pixels, which can be arranged in an array. Each display pixel is driven by a corresponding pixel driving unit. The pixel driving unit can generate a pixel driving signal based on the received gate scan signal, thereby driving the corresponding display pixel to light up. When the multiple display pixels are driven to light up, they can display the corresponding image. Under low refresh rate conditions, because the switching transistor is in the NBS effect for a longer time, the low refresh rate area has a higher stress level than the high refresh rate area, and the gate voltage of the driving transistor (DTFT) is higher, resulting in a negative bias of the threshold voltage (Vth). This weakens the degree to which the switching transistor is pulled from PVGL_N (off gate voltage) to PVGH_N (on gate voltage) and coupled to the DTFT gate, causing the high refresh rate area to be brighter. Therefore, the absolute value of the gate off voltage received by the switching transistor in the corresponding pixel driving unit can be controlled to decrease according to the pixel range of the second display area, reducing the influence of NBS, thereby achieving the purpose of balancing the brightness of display areas with different refresh rates.

[0050] In step S300, the gate conduction voltage received by the switching transistor in the pixel driving unit corresponding to the first display area is controlled to decrease according to the pixel range of the first display area.

[0051] In this embodiment, when the partition refresh function of the display panel is enabled, the refresh rate of the display screen in each area may be inconsistent. For example, the refresh rates of the display screen in the upper, middle and lower areas of the display panel are 1Hz, 120Hz and 1Hz respectively. At a refresh rate of 120Hz, the turn-on time of the switching transistor is longer. The PBS effect causes the high refresh rate area in the middle to be more stressed than the low refresh rate areas at the top and bottom, resulting in a positive bias of Vth. Therefore, by reducing the gate conduction voltage received by the switching transistor in the pixel driving unit, the influence of PBS can be reduced, thereby achieving the purpose of balancing the brightness of the display areas with different refresh rates.

[0052] In some embodiments, see Figure 2As shown, the pixel driving unit includes: a first P-type transistor T1, a second P-type transistor T2, a first switching transistor T3, a second switching transistor T4, a third P-type transistor T5, a fourth P-type transistor T6, and a storage capacitor Cst.

[0053] In this embodiment, the first terminal of the second P-type transistor T2 is used to receive the display data signal, and the control terminal of the second P-type transistor T2 is used to receive the first data control signal Data; the control terminal of the second switching transistor T4 is used to receive the first scan control signal SN1, and the control terminal of the first switching transistor T3 is used to receive the second scan control signal SN2. The second scan control signal SN2 can be provided by the level conversion circuit, and the partition enable signal can be output to the control terminal of the first switching transistor T3 via the output terminal GOUT of the level conversion circuit as the second scan control signal SN2, thereby realizing the partition refresh control of the pixel driving unit 530.

[0054] The control terminal of the third P-type transistor T5 and the controller terminal of the fourth P-type transistor T6 are connected together to receive the dimming control signal EM; the control terminal of the seventh switch T7 and the control terminal of the eighth switch T8 are connected together to receive the second data control signal SP2. The first terminal of the third P-type transistor T5 and the first terminal of the storage capacitor Cst are connected to the first power supply terminal ELVDD. The second terminals of the second P-type transistor T2, the third P-type transistor T5, and the first terminal of the first P-type transistor T1 are connected together. The second terminal of the storage capacitor Cst, the control terminal of the first P-type transistor T1, and the first terminal of the first switching transistor T3 are connected together. The second terminal of the first switching transistor T3, the first terminal of the second switching transistor T4, the second terminal of the first P-type transistor T1, the first terminal of the fourth P-type transistor T6, and the first terminal of the eighth switching transistor T8 are connected together. The second terminal of the second switching transistor T4 is connected to the first reference signal terminal Vrefn1. The second terminal of the fourth P-type transistor T6 and the first terminal of the seventh switching transistor T7 are connected to the positive terminal of the display diode OLED. The negative terminal of the display diode is connected to the reference ground. The second terminal of the seventh switching transistor T7 is connected to the second reference signal terminal Vrefn2. The second terminal of the eighth switching transistor T8 is connected to the third reference signal terminal Vrefp.

[0055] In this embodiment, in the high refresh rate region, the first switching transistor T3 is in a state with a longer on time. The PBS effect of the first switching transistor T3 causes the stress level of the high refresh rate region to be higher than that of the low refresh rate region. This causes the threshold voltage (Vth) of the first switching transistor T3 to be positively biased, which weakens the coupling of the first switching transistor T3 from the gate on voltage (PVGH_N) to the gate off voltage (PVGL_N) to the DTFT gate. As a result, the high refresh rate region is darker. Therefore, by reducing the gate on voltage (PVGH_N) of the first switching transistor T3, the influence of PBS can be reduced, thereby achieving the purpose of balancing the brightness of display areas with different refresh rates.

[0056] In this embodiment, in the low refresh rate region, the first switching transistor T3 is in the NBS effect for a longer time, resulting in a higher stress level (higher DTFT gate) in the low refresh rate region compared to the high refresh rate region. This causes the threshold voltage (Vth) of the first switching transistor T3 to become negatively biased, weakening the coupling of the first switching transistor T3 from the gate turn-off voltage (PVGL_N) to the gate turn-on voltage (PVGH_N) to the DTFT gate (lower DTFT gate). Consequently, the high refresh rate region is brighter. Therefore, by reducing the gate turn-off voltage (PVGL_N) of the first switching transistor T3, the NBS effect is reduced, achieving the goal of balancing the brightness of display regions with different refresh rates.

[0057] In some embodiments, the second P-type transistor T2, the seventh switch T7, the eighth switch T8, the third P-type transistor T5, and the fourth P-type transistor T6 are P-type MOS transistors.

[0058] The first switching transistor T3 and the second switching transistor T4 are N-type MOS transistors.

[0059] In some embodiments, the magnitude of the decrease in the absolute value of the gate turn-off voltage received by the switching transistor in the pixel driving unit corresponding to the second display area is related to the refresh rate difference between the second display area and the first display area.

[0060] In this embodiment, combined with Figure 2As shown, the characteristic offset of the switching transistors (e.g., the first switching transistor T3 and the second switching transistor T4) in the pixel driving unit is related to the refresh rate of the display area where they are located. That is, the PBS / NBS effect of the first switching transistor T3 and the second switching transistor T4 will cause a brightness difference between regions with different refresh rates. The greater the difference in refresh rates, the greater the impact of the brightness difference, and the greater the impact on the optical visual effect. Therefore, when multiple sub-regions in the display area have different refresh rates, the brightness difference between the second display area and the first display area can be balanced by matching the absolute value of the gate turn-off voltage received by the switching transistor in the pixel driving unit corresponding to the second display area with the refresh rate difference between the second display area and the first display area.

[0061] In some embodiments, the greater the difference in refresh rates between the first display area and the second display area, the greater the decrease in the absolute value of the gate turn-off voltage received by the switching transistor in the pixel driving unit corresponding to the second display area.

[0062] In this embodiment, combined with Figure 2 As shown, the characteristic offsets of the first switching transistor T3 and the second switching transistor T4 are related to the refresh rate of their respective display areas. That is, the PBS / NBS effects of the first switching transistor T3 and the second switching transistor T4 are different for different refresh rate areas, which will lead to brightness differences between different refresh rate areas. The greater the difference in refresh rates, the greater the impact of the brightness difference, and the greater the impact on optical visual effects. Therefore, when multiple sub-regions within the display area have different refresh rates, by calculating the refresh rate difference between the second display area and the first display area, the greater the difference in refresh rates between the first display area and the second display area, the greater the decrease in the absolute value of the gate turn-off voltage received by the switching transistor in the pixel driving unit corresponding to the second display area, and the smaller the absolute value of the gate turn-off voltage provided to the first switching transistor T3 and the second switching transistor T4, which can reduce the brightness difference between the second display area and the first display area.

[0063] In some embodiments, the decrease in the gate conduction voltage received by the switching transistor in the pixel driving unit corresponding to the first display area is related to the refresh rate difference between the second display area and the first display area.

[0064] In this embodiment, combined with Figure 2As shown, the characteristic offset of the switching transistors (e.g., first switching transistor T3 and second switching transistor T4) within the pixel driving unit is related to the refresh rate of its display area. That is, the PBS / NBS effect of the first switching transistor T3 and the second switching transistor T4 leads to brightness differences between regions with different refresh rates. The greater the difference in refresh rates, the greater the impact of the brightness difference, and consequently, the greater the impact on optical visual effects. Therefore, when multiple sub-regions within the display area have different refresh rates, the brightness difference between the second and first display areas can be balanced by matching the decrease in the gate on-state voltage received by the first switching transistor T3 and the second switching transistor T4 within the pixel driving unit corresponding to the first display area, through the refresh rate difference between the second and first display areas.

[0065] In some embodiments, the greater the difference in refresh rates between the first display area and the second display area, the greater the decrease in the gate conduction voltage received by the switching transistor in the pixel driving unit corresponding to the first display area.

[0066] In this embodiment, combined with Figure 2 As shown, the characteristic offsets of the first switching transistor T3 and the second switching transistor T4 are related to the refresh rate of their respective display areas. That is, the PBS / NBS effects of the first switching transistor T3 and the second switching transistor T4 are different for different refresh rate areas, which will lead to brightness differences between different refresh rate areas. The greater the difference in refresh rates, the greater the impact of the brightness difference, and the greater the impact on optical visual effects. Therefore, when multiple sub-regions within the display area have different refresh rates, by calculating the refresh rate difference between the second display area and the first display area, the greater the difference in refresh rates between the first display area and the second display area, the greater the decrease in the gate conduction voltage received by the first switching transistor T3 and the second switching transistor T4 in the pixel driving unit corresponding to the second display area, and the smaller the absolute value of the gate conduction voltage provided to the first switching transistor T3 and the second switching transistor T4, which can reduce the brightness difference between the second display area and the first display area.

[0067] In some embodiments, the gate turn-on voltage received by the first switching transistor T3 and the second switching transistor T4 in the pixel driving unit in the first display area (high refresh rate area) can be reduced from 7.8V to 6.8V.

[0068] In some embodiments, the gate turn-off voltage received by the first switching transistor T3 and the second switching transistor T4 in the pixel driving unit in the second display area (low refresh rate area) can be adjusted from -9.8V to -8.8V.

[0069] In some embodiments, such as Figure 3 As shown, the partition display driving method further includes steps S410 and S420.

[0070] In step S410, the difference between the refresh rates of the first display area and the second display area is obtained.

[0071] In step S420, the decrease in the gate conduction voltage received by the switching transistor in the pixel driving unit corresponding to the first display area is determined based on the difference in refresh rates between the first display area and the second display area.

[0072] In this embodiment, the difference in refresh rates between the first display area and the second display area can be directly proportional to the decrease in the gate conduction voltage received by the switching transistor in the pixel driving unit corresponding to the first display area. The decrease in the gate conduction voltage received by the switching transistor in the pixel driving unit corresponding to the first display area is determined based on the difference in refresh rates between the first display area and the second display area, thereby effectively balancing the brightness difference between the first display area and the second display area.

[0073] In some embodiments, step S420, determining the decrease in the gate conduction voltage received by the switching transistor in the pixel driving unit corresponding to the first display area based on the difference in refresh rates between the first display area and the second display area, includes: determining the gate conduction voltage received by the switching transistor in the pixel driving unit corresponding to the first display area based on the difference in refresh rates between the first display area and the second display area and a preset refresh rate-gate voltage relationship table.

[0074] In this embodiment, a refresh rate-gate voltage relationship table can be established through prior testing. The refresh rate-gate voltage relationship table can represent the correspondence between the difference in refresh rates between the first display area and the second display area and the change in gate conduction voltage. Therefore, after obtaining the difference in refresh rates between the first display area and the second display area, the corresponding gate voltage is read from the preset refresh rate-gate voltage relationship table according to the difference, and the gate conduction voltage received by the switching transistor in the pixel driving unit corresponding to the first display area is set as the gate voltage read from the refresh rate-gate voltage relationship table.

[0075] In some embodiments, step S420, determining the decrease in the gate on-state voltage received by the switching transistor in the pixel driving unit corresponding to the first display area based on the difference in refresh rates between the first display area and the second display area, includes: progressively reducing the gate on-state voltage received by the switching transistor in the pixel driving unit corresponding to the first display area based on the difference in refresh rates between the first display area and the second display area.

[0076] In some embodiments, the partitioned display driving method in this embodiment further includes: generating a corresponding partition enable signal based on the pixel range of the second display area.

[0077] In this embodiment, the scanning area where the display refresh rate needs to be reduced is determined by the pixel range of the second display area, thereby generating a corresponding partition enable signal. The partition enable signal is used to control the corresponding pixel driving unit to reduce the duty cycle of the pixel driving signal, thereby reducing the switching duty cycle of the pixels in the corresponding area.

[0078] In some embodiments, combined with Figure 4 As shown, the partition display driving method in this embodiment further includes step S500.

[0079] In step S500, the high-level pulse width of the gate pulse signal of the switching transistor in the pixel driving unit corresponding to the first display area is reduced.

[0080] In a partitioned refresh scheme, different display areas have different refresh rates, which may lead to different operating conditions for transistors, such as turn-on time and threshold voltage drift. By setting different PVGH / PVGL voltages for different display areas, these differences can be compensated for, ensuring that the first switching transistor T3 and the second switching transistor T4 maintain consistent performance across different refresh rate areas and reducing display unevenness issues.

[0081] In this embodiment, based on voltage differentiation, the high-level pulse width of the gate pulse signal of the switching transistor in the pixel driving unit corresponding to the first display area is reduced. For example, Figure 5a This is a timing diagram of the first scan control signal SN1, the second scan control signal SN2, the first data control signal SP1, the second data control signal SP2, and the dimming control signal EM within the first display area before modification. Figure 5b As shown, the timing of the scan control signals received by the gates of the first switching transistor T3 and the second switching transistor T4 is modified. Specifically, the high-level pulse width of the first scan control signal SN1 received by the gate of the first switching transistor T3 is reduced from 10H to 2H, and the high-level pulse width of the second switching transistor T4 is reduced from 22H to 18H. The high-level pulse widths of the first data control signal SP1, the second data control signal SP2, and the dimming control signal EM remain unchanged. By reducing the duration of the high-level pulse width of the gate pulse signals of the first switching transistor T3 and the second switching transistor T4, the on-time of the PBS / NBS for the first display area (high refresh rate area) is reduced, thereby mitigating the impact of the threshold voltage (Vth) bias caused by the PBS / NBS on the brightness differences of different areas under partitioned refresh.

[0082] In some embodiments, combined with Figure 6 As shown, the partition enable signal can also be ANDed with the scan drive signal output by the scan drive module 520 to adjust the duty cycle of the scan drive signal output to the gate scan line 501, thereby controlling the corresponding pixel drive unit to reduce the duty cycle of the pixel drive signal and realizing the partition refresh display of the display panel.

[0083] In some embodiments, the main control circuit 510 can provide corresponding partition scanning signals to the scanning drive module 520 according to the content to be displayed on the display panel, thereby adjusting the refresh rate of the display screen accordingly. For example, based on the coordinates of the display screen and the refresh rate requirements, by providing corresponding partition scanning signals to the partition display driving method, the refresh rate of the display screen can be set according to frequency distributions such as 60Hz-120Hz-60Hz, 30Hz-120Hz-30Hz, 1Hz-120Hz-1Hz, etc. Specifically, in implementing the function of displaying different refresh rates in multiple areas of the mobile phone, if the mobile phone is simultaneously watching videos (requiring high refresh rate display) and reading text (requiring low refresh rate display), the refresh rate of the text display area in the display screen can be set to a low refresh rate (e.g., 1Hz, 30Hz, etc.) to reduce the power consumption of the display panel without affecting the display effect.

[0084] This application also provides a display driving circuit, see [link to relevant documentation] Figure 6 As shown, the display driving circuit in this embodiment includes a plurality of pixel driving units 530 and a main control circuit 510. The main control circuit 510 is used to execute the partitioned display driving method as described in any of the above embodiments; the plurality of pixel driving units 530 are used to drive a plurality of display pixels to light up respectively.

[0085] In this embodiment, the display panel includes multiple display pixels, which can be arranged in an array. Each display pixel is driven by a corresponding pixel driving unit 530. The pixel driving unit 530 can generate a pixel driving signal based on the received gate scan signal, thereby driving the corresponding display pixel to light up. When the multiple display pixels are driven to light up, they can display the corresponding image. The main control circuit 510 can control the corresponding pixel driving unit 530 to generate a pixel driving signal with a low duty cycle based on the pixel range of the second display area, thereby reducing the refresh rate of the display screen in the second display area.

[0086] In some embodiments, combined with Figure 6As shown, the display driving circuit also includes multiple scan driving modules 520, and multiple gate scan lines 501 are respectively connected to multiple scan driving modules 520; the scan driving module 520 is controlled by the main control circuit 510 to provide gate scan signals to multiple gate scan lines 501, and multiple pixel driving units 530 are respectively connected to the corresponding gate scan lines 501; each pixel driving unit 530 is used to drive the corresponding display pixel to light up according to the received gate scan signal and data signal.

[0087] This application also provides a display screen, which includes a display driving circuit as described in any of the above embodiments.

[0088] In this embodiment, the display screen includes a display panel and a display driving circuit. The display panel includes multiple display pixels, and each display pixel includes at least one display diode. When the display diode is lit, it can emit a corresponding color, such as red, blue, or green light. The three colors of display diodes can form a display pixel. By obtaining the pixel range of the first display area and the second display area, the absolute value of the gate turn-off voltage received by the switching transistor in the pixel driving unit corresponding to the second display area is controlled to decrease according to the pixel range of the second display area; and the gate turn-on voltage received by the switching transistor in the pixel driving unit corresponding to the first display area is controlled to decrease according to the pixel range of the first display area. Thus, when the display panel enables the partition refresh function, the gate positive and negative voltages of the switching transistors can be differentiated, thereby reducing the brightness difference caused by PBS or NBS.

[0089] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0090] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0091] In the embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the electronic device embodiments described above are merely illustrative. For example, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0092] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0093] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0094] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A method for driving a display in zones, characterized in that, The partition display driving method comprises: acquiring pixel ranges of a first display area and a second display area; wherein a refresh rate of the first display area is greater than a refresh rate of the second display area; controlling, according to the pixel range of the second display area, a decrease in an absolute value of a gate-off voltage received by a switching transistor in a pixel driving unit corresponding to the second display area; the decrease in the absolute value of the gate-off voltage received by the switching transistor in the pixel driving unit corresponding to the second display area is related to a difference between the refresh rates of the second display area and the first display area; controlling, according to the pixel range of the first display area, a decrease in a gate-on voltage received by a switching transistor in a pixel driving unit corresponding to the first display area; the decrease in the gate-on voltage received by the switching transistor in the pixel driving unit corresponding to the first display area is in a positive correlation with the difference between the refresh rates of the second display area and the first display area; the greater the difference between the refresh rates of the first display area and the second display area, the greater the decrease in the absolute value of the gate-off voltage received by the switching transistor in the pixel driving unit corresponding to the second display area.

2. The method of claim 1, wherein, The partition display driving method further comprises: acquiring a difference between the refresh rates of the first display area and the second display area; determining, according to the difference between the refresh rates of the first display area and the second display area, a decrease in a gate-on voltage received by a switching transistor in a pixel driving unit corresponding to the first display area.

3. The method of claim 2, wherein, The determining, according to the difference between the refresh rates of the first display area and the second display area, of the decrease in the gate-on voltage received by the switching transistor in the pixel driving unit corresponding to the first display area comprises: determining, according to the difference between the refresh rates of the first display area and the second display area and a preset refresh rate-gate voltage relationship table, the gate-on voltage received by the switching transistor in the pixel driving unit corresponding to the first display area.

4. The method of claim 3, wherein, The determining, according to the difference between the refresh rates of the first display area and the second display area, of the decrease in the gate-on voltage received by the switching transistor in the pixel driving unit corresponding to the first display area comprises: gradually reducing, according to the difference between the refresh rates of the first display area and the second display area, the gate-on voltage received by the switching transistor in the pixel driving unit corresponding to the first display area.

5. The method of claim 1-4, wherein, The partition display driving method further comprises: controlling a high-level pulse width of a gate pulse signal of the switching transistor in the pixel driving unit corresponding to the first display area to be reduced.

6. A display driving circuit, characterized by comprising: The display driving circuit comprises a plurality of pixel driving units and a master control circuit, and the master control circuit is configured to execute the partition display driving method according to any one of claims 1-5 to control the plurality of pixel driving units to drive a plurality of display pixels to be brightened.

7. A display screen, characterized by The display screen comprises the display driving circuit according to claim 6.

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