Integrated circuit and method of sensing current and providing digital output

Abstract

The invention provides an integrated circuit and a method for sensing current and providing digital output. The integrated circuit includes a memory cell array including a plurality of bit lines and a plurality of word lines; a sensing circuit configured to sense a difference between the first current and the second current on different ones of the selected bit lines, and generate an output of the selected bit line according to the difference; and a global counter configured to continuously provide a count value to each of the sensing circuits in accordance with the clock signal. Each of the sensing circuits may generate an output based on (i) a difference between the first current and the second current and (ii) a stored count value received from the global counter, the count value being stored based on a value of the difference between the first current and the second current.

Description

Technical Field

[0001] The present invention relates to memory sensors (e.g., sensing circuits of a memory) using global counters. More particularly, the present invention relates to compute in memory (CIM) for performing compute in memory (CIM) operations that implement memory sensors that share global counters rather than individual memory sensors having local analog-to-digital converters. Background Art

[0002] Conventional in-memory computing components that perform CIM operations implement thousands of independent sensors (e.g., local sensing circuits) to detect analog currents and / or voltages on the bit lines of a memory array. The local sensing circuits may add or subtract the currents sensed across a selected pair of bit lines. For example, the local sensing circuit may add two currents detected on two bit lines and / or may subtract one current from another current detected on the two bit lines to provide an analog output current value. The local sensing circuit may further convert the analog output value into a digital signal that may be used by other portions of the in-memory computing components using a local analog-to-digital converter (ADC). More specifically, each independent local sensing circuit may include: (i) a current / voltage operator to detect the difference between the current / voltage on a selected bit line pair (e.g., adding or subtracting the current / voltage value) to provide an analog current or voltage measurement; (ii) an analog-to-digital converter (ADC) to convert the analog measurement into a digital signal; and (iii) a storage device (such as a latch or a flip-flop) to store the output of the analog-to-digital converter and provide a data output.

[0003] The physical size and power consumption of components within these in-memory computing devices can make it difficult to provide smaller and more efficient electronic devices. The conventional use of local analog-to-digital converters (ADCs) in each local sensing circuit of an in-memory computing device causes the in-memory computing device to consume an undesirable amount of power and occupy an undesirable amount of space because the analog-to-digital converter (ADC) can occupy most of the physical space and can consume most of the power required for the sensing circuit.

[0004] Therefore, it is desirable to provide local sensing circuits in memory or other types of computing devices that occupy less physical space and are more energy efficient. Summary of the invention

[0005] The present invention provides a circuit and method for sensing current in a bit line of a memory cell array.

[0006] The circuit may include: a memory cell array including a plurality of bit lines and a plurality of word lines; a sensing circuit configured to sense a difference between a first current and a second current on different bit lines among selected bit lines and generate an output of the selected bit line according to the difference; and a global counter configured to continuously provide a count value to each of the sensing circuits according to a clock signal. Each sensing circuit in the sensing circuit may generate an output according to (i) the difference between the first current and the second current and (ii) a stored count value received from the global counter, the count value being stored according to the value of the difference between the first current and the second current.

[0007] In an embodiment, the global counter may be configured to continuously increment or decrement the count value over time. For a particular time, the same particular count value may be provided to each of the sensing circuits.

[0008] In another embodiment, each of the sensing circuits may include a local detector circuit configured to receive a detection voltage (V c ), receiving reference voltage (V ref ) and based on the detection voltage (V c ) and reference voltage (V ref ) generates a trigger signal.

[0009] In another embodiment, each of the sensing circuits may include a storage configured to store a specific count value provided by the global counter, and the storage of the specific count value may be performed according to a trigger signal.

[0010] In an embodiment, the storage may include a latch that stores a specific count value provided by the global counter.

[0011] In another embodiment, the memory may include a flip-flop for storing a specific count value provided by the global counter.

[0012] In another embodiment, the local detector circuit may include a comparator configured to (i) compare the detection voltage (V c ) and reference voltage (V ref ) and (ii) due to the detection voltage (V c ) reaches or exceeds the reference voltage (V ref ) or drops to the reference voltage (V ref ) below to generate a trigger signal.

[0013] In another embodiment, the trigger signal generated by the comparator may be caused by the detection voltage (V c ) reaches or exceeds the reference voltage (V ref ) or drops to the reference voltage (V ref ) and below and are edge triggered.

[0014] In one embodiment, the trigger signal generated by the comparator may be generated by detecting the voltage (V c ) reaches or exceeds the reference voltage (V ref ) and is level triggered.

[0015] In another embodiment, the local detector circuit may include a circuit configured to detect the voltage (V c ) and reference voltage (V ref )A differential amplifier that generates a trigger signal.

[0016] In another embodiment, the local detector circuit may include a circuit configured to detect the voltage (V c ) and reference voltage (V ref )An inverter that generates a trigger signal.

[0017] In an embodiment, the reference voltage (V ref ) can be received by each sensing circuit in the sensing circuit from a global fixed reference voltage source, so that each sensing circuit receives the same reference voltage (V ref ).

[0018] In another embodiment, the reference voltage (V ref ) can be received by each sensing circuit in the sensing circuit from a globally adjustable reference voltage source, so that each sensing circuit receives the same reference voltage (V ref ).

[0019] In another embodiment, each of the sensing circuits may operate based on the same global counter and local detector circuits rather than implementing a local analog-to-digital converter.

[0020] In an embodiment, each of the sensing circuits does not include a local analog-to-digital converter.

[0021] In another embodiment, the count value provided by the global counter may be a binary value of at least two bits.

[0022] In another embodiment, the global counter may be one of a regular counter and a non-regular counter.

[0023] In an embodiment, each of the sensing circuits may include: a current operator circuit configured to sense a first sensing current (I 0 ) and the second sensing current (I 1 ) and the output current (I cell ); and a capacitor configured to receive a current (I cell ), according to the received current (I cell ) stores charge, and generates a detection voltage (V c) is provided to a detector circuit that triggers storage of a count value received from a global counter.

[0024] In addition, a method for sensing current on a bit line of a memory cell array including a plurality of bit lines and a plurality of word lines and providing a digital output is provided. The method may include: using a sensing circuit to sense a difference between a first current and a second current on different bit lines among selected bit lines; continuously receiving a count value provided by a global counter according to a clock signal by the sensing circuit; and generating a digital output of the selected bit line by the sensing circuit according to the difference and the count value, wherein the digital output is generated by each sensing circuit in the sensing circuit according to (i) the difference between the first current and the second current and (ii) a stored count value received from the global counter, the count value being stored according to the value of the difference between the first current and the second current.

[0025] In addition, a circuit is provided to include: a sensing circuit configured to sense a difference between a first current and a second current on different bit lines of a memory cell array in a selected bit line and generate an output for the selected bit line based on the difference, and wherein each sensing circuit in the sensing circuit generates an output based on (i) the difference between the first current and the second current and (ii) a stored count value received from a global counter, wherein the global counter is configured to continuously provide a count value to each of the sensing circuits based on a clock signal, and the count value is stored based on the value of the difference between the first current and the second current.

[0026] Other aspects and advantages of the present invention may be seen after reviewing the following drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a simplified block diagram of an integrated circuit device including a memory array configured for in-memory operations with, for example, signed inputs and weights according to an embodiment of the invention.

[0028] Figure 2 is a schematic diagram of a set of memory cells and local sensing circuits configured to store and output data for in-memory operations according to an embodiment of the present invention.

[0029] Figure 3 FIG. 1 is a schematic diagram of a memory array and thousands of local sensing circuits with local analog-to-digital converters for in-memory operations according to an embodiment of the present invention.

[0030] Figure 4 Schematic diagram of a memory array for in-memory operations having local sensing circuits without local analog-to-digital converters and including a global counter used by each of the local sensing circuits according to an embodiment of the present invention.

[0031] Figure 5FIG. 4 is a more detailed schematic diagram of a local sensing circuit for in-memory operations according to an embodiment of the present invention.

[0032] Description of reference numerals:

[0033] 100: Integrated circuit devices

[0034] 105: Input / output circuit

[0035] 110: Controller

[0036] 120: Block

[0037] 140: Driver circuit

[0038] 141: Input buffer

[0039] 142: Decoder

[0040] 145.WL0 M 、WL1 M : Word line

[0041] 160: Memory array

[0042] 165: Global bit line

[0043] 170, 220, 220i, 220ii, 220n, 402, 402i, 402n: Local sensing circuit

[0044] 180: Page Buffer

[0045] 185, 191, 193: Bus

[0046] 190: Cache memory

[0047] 200, 201: memory unit set

[0048] 200-1: First memory unit

[0049] 200-2: Second memory unit

[0050] 200-3: Third memory cell

[0051] 200-4: Fourth memory cell

[0052] 210, SL: shared source line

[0053] 222, 222i, 222ii, 222n, 404, 404i, 404n: Current operator circuits

[0054] 223: Analog output

[0055] 224, 224i, 224ii, 224n: Analog-to-digital converters

[0056] 225: Digital output

[0057] 226, 226i, 226ii, 226n, 408, 408i, 408n, L0, L1, L2, L3: Latches

[0058] 227, 409i, 409n: Data output

[0059] 400: Global counter

[0060] 401: Global counter output data / count value

[0061] 405i, 405n, 407i, 407n: Output

[0062] 406, 406i, 406n: Detector circuit

[0063] 500: Global fixed V ref source

[0064] 502: Charging circuit

[0065] 504: Switch

[0066] 506: Capacitor

[0067] 508: Comparator

[0068] a0, a1, a2, a3: bits

[0069] BL0 1 : First line

[0070] BL1 1 : Second bit line

[0071] I ref : Reference current

[0072] I cell ,I cell0 ,I cell0i ,I cell0ii ,I cell0n ,I cell1 ,I cell1i ,I cell1ii ,I cell1n : Current

[0073] V c :Detection voltage

[0074] V ref : Reference voltage

[0075] VT1, VT2, VT3, VT4: Threshold

[0076] W 1 , Wi: coefficient / weight

[0077] WL0 1 : First word line

[0078] WL1 1 : Second word line

[0079] W i [1] W i [N]: Weight value

[0080] X i [1] X i [M]: variable value DETAILED DESCRIPTION

[0081] refer to Figures 1 to 5 A detailed description of embodiments of the disclosed technology is provided.

[0082] Figure 1 is a simplified block diagram of an integrated circuit device including a memory array configured for in-memory operations with, for example, signed inputs and weights according to an embodiment of the invention.

[0083] Specifically, Figure 1 is a simplified block diagram of an integrated circuit device 100 including a memory array 160 configured for operation-in-memory (CIM) operations (eg, signed product-sum operations). The integrated circuit device 100 may be implemented on a single die or on a multi-die module.

[0084] The device 100 includes input / output circuits 105 for communicating control signals, data, addresses, and commands with other data processing resources, such as a central processing unit (CPU) or a memory controller.

[0085] Input / output data is applied to the controller 110 and the cache memory 190 via bus 191. In addition, addresses are applied to the decoder 142 and the controller 110 via bus 193. In addition, bus 191 and bus 193 are operatively connected to data sources within the integrated circuit device 100, such as a general-purpose processor or a dedicated application circuit, or a combination of modules that provide, for example, system-on-a-chip functions.

[0086] The memory array 160 may include an array of memory cells in a NOR architecture or in an AND architecture, such that the memory cells are arranged in rows along bit lines and in columns along word lines, and the memory cells in a given row are connected in parallel between the bit line and a source reference. The source reference may include a ground terminal or a source line connected to a source side bias resource. The memory cells may include charge trapping transistor cells arranged in a 3D structure.

[0087] The bit lines may be connected by block selection circuits to global bit lines 165 configured for selective connection to page buffers 180 and local sensing circuits 170 (eg, CIM sensing circuits).

[0088] The page buffer 180 in the illustrated embodiment is connected to the cache memory 190 by a bus 185. The page buffer 180 may include storage elements and additional sensing circuits for memory operations including read and write operations. For flash memories including dielectric charge trapping memory and floating gate charge trapping memory, write operations include programming and erasing operations.

[0089] Driver circuit 140 is coupled to word lines 145 in memory array 160 and applies a word line voltage to a selected word line in response to decoder 142 decoding an address on bus / pipeline 193 or in response to input data stored in input buffer 141 in arithmetic operations.

[0090] The controller 110 is coupled to the cache memory 190 and the memory array 160 , as well as other peripheral circuits for memory access and CIM operations.

[0091] The controller 110 , using, for example, a state machine, controls the application of supply voltages and currents generated or provided via voltage supplies or current sources in block 120 for memory operations and CIM operations.

[0092] The controller 110 includes control and state registers, and control logic that may be implemented using dedicated logic circuits including state machines and combinatorial logic known in the art. In alternative embodiments, the control logic includes a general purpose processor that may be implemented on the same integrated circuit, which executes a computer program to control the operation of the device. In still other embodiments, a combination of dedicated logic circuits and a general purpose processor may be used to implement the control logic.

[0093] The memory array 160 includes memory cells arranged in rows and columns, where the memory cells in the rows are connected to corresponding bit lines and the memory cells in the columns are connected to corresponding word lines. For CIM operation, the memory array 160 can be programmable to store signed coefficients (weights Wi) in a set of memory cells.

[0094] In CIM mode, word line driver circuit 140 includes a driver configured to drive a signed input Xi from input buffer 141 by a selection pattern of voltages on selected word lines and unselected word lines. Local sensing circuit 170 may be configured to sense a difference between a first current and a second current on different bit lines in a selected bit line pair (and / or a single bit line), and to generate an output for the selected bit line pair (and / or a single bit line) based on the difference. Sensing of the difference may include subtracting current or voltage values ​​from different bit lines, and may include adding current or voltage values ​​from different bit lines. The output may be applied to storage elements in page buffer 180 and cache memory 190.

[0095] Implementation of memory array 160 may be based on charge trapping memory cells, such as floating gate memory cells that may include a polysilicon charge trapping layer, or dielectric charge trapping memory cells that may include a silicon nitride charge trapping layer. Other types of memory technologies may be applied in various embodiments of the technology described herein.

[0096] Figure 2 is a schematic diagram of a set of memory cells and local sensing circuits configured to store and output data for in-memory operations according to an embodiment of the present invention.

[0097] Specifically, Figure 2 2. A set of memory cells 200 are shown, which in this example are implemented by charge trapping memory transistors, configured to store bits (eg, signed or unsigned bits). Figure 2 The memory cell set 200 in FIG. 1 may be one of many memory cell sets for storing multiple bits in a memory array having multiple word lines and multiple bit lines. Figure 2 The plurality of memory cell sets 200 of memory cell sets may be used to store vectors of M coefficients Wi (or weights) (for i, from 1 to M) used in product-sum operations, or multiple coefficient arrays for efficient CIM operations. These are merely examples of CIM operations, and the techniques disclosed herein may be implemented in any type of in-memory computing device, as well as other types of memory devices.

[0098] Figure 2The memory cell set 200 in the embodiment includes a first memory cell 200-1, a second memory cell 200-2, a third memory cell 200-3, and a fourth memory cell 200-4. Each of the first memory cell 200-1, the second memory cell 200-2, the third memory cell 200-3, and the fourth memory cell 200-4 can be implemented by a charge trapping memory transistor. Other embodiments will be apparent to those skilled in the art. For notational purposes, the memory cell set 200 may be referred to as storing coefficients W in a vector 1 Other implementations for CIM operations will be apparent to those skilled in the art.

[0099] The first memory cell 200-1 is connected to the first bit line BL0 1 and the first word line WL0 1 The second memory cell 200-2 is on the second bit line BL1 1 and the first word line WL0 1 The third memory cell 200-3 is on the first bit line BL0 1 and the second word line WL1 1 The fourth memory cell 200-4 is on the second bit line BL1 1 and the second word line WL1 1 The source sides (source lines or SL sides) of the first memory cell 200-1, the second memory cell 200-2, the third memory cell 200-3, and the fourth memory cell 200-4 may be connected to a source reference circuit, which may include a ground terminal or source line (SL) connected to a source side bias resource operable for memory operations such as programming and erasing. In the example shown, the source reference circuit includes a common source line (SL) 210 connected to a source side bias circuit (not shown).

[0100] Another memory cell set 201 is consistent with the memory cell set 200 in form and structure, but for the purpose of clarity, less details are shown. Each of the memory cell set 200 and the memory cell set 201 can be used to store a weight value W respectively. i [1] and weight value W i [N] Each of the memory unit set 200 and the memory unit set 201 can receive a different variable value X respectively. i [1] and variable value X i [M] Each of the variable values ​​is represented by a word line pair (for X i [1]WL0 1 With WL1 1 And for X i [M]WLOM and WL1 M Each of the memory unit set 200 and the memory unit set 201 can perform an arithmetic operation (eg, multiplication (X)) using the stored weight value and the provided variable value. i [1]*W i [1])) and provide the operation result as a reflection of I cell0 and I cell1 part of the current.

[0101] Any suitable encoding may be used to encode weight values ​​on memory cell 200-1, memory cell 200-2, memory cell 200-3, and memory cell 200-4 using thresholds (VT1, VT2, VT3, and VT4), respectively. Any suitable encoding may be used to encode weight values ​​on WL0 using a particular voltage pair. 1 and WL1 1 For memory cell set 201, the encoding of weight values ​​and variable values ​​is the same. Memory cell set 201 represents similarly to bit line BL0. 1 and bit line BL1 1 One or more such units connected in parallel.

[0102] Use VT1, VT2, VT3 and VT4 and the first bit line BL0 1 , the second bit line BL1 1 , first word line WL0 1 and the second word line WL1 1 It will be apparent to those skilled in the art that the CIM operation can be performed by adjusting the current and / or voltage on the CIM.

[0103] like Figure 2 As shown in FIG. , bit line BL0 1 and bit line BL1 1 The pair is connected to the local sensing circuit 220. The bit line BL0 1 The current I cell0 Provided to the local sensing circuit 220, and the bit line BL1 1 The current I cell1 Provided to the local sensing circuit 220. In addition, the same bit line (such as BL0 1 or BL1 1 ) provides and / or detects current I cell0 and current I cell1 This is to maintain authenticity of all descriptions of providing and / or sensing current on the bit lines described herein.

[0104] In addition, the local sensing circuit 220 may include a current I cell0 and current Icell1 The current operator circuit 222 provides an analog output 223 (current or voltage) based on the value of the current I. For example, the current operator circuit 222 can be a circuit that generates a current I cell0 With current I cell1 The local sensing circuit 220 may also include an analog-to-digital converter (ADC) 224 that converts the analog output 223 into a digital output 225 that is stored in a memory (such as a latch 226 of the local sensing circuit 220) that may then provide a data output 227.

[0105] In-memory computing devices require thousands of local sensing circuits (e.g. Figure 1 The use of local sensing circuitry 170), and an analog-to-digital converter (such as, ADC 224) consumes an undesirable amount of power (e.g., reduces performance) and occupies an undesirable amount of physical space, which may reduce the amount of CIM operations that can be performed in a space of a particular size or that can be performed under power consumption constraints.

[0106] For example, Figure 3 is a schematic diagram of a memory array 160 for in-memory operations and thousands of local sensing circuits with local analog-to-digital converters that consume an undesirable amount of power and occupy an undesirable amount of space in accordance with an embodiment of the present invention.

[0107] Specifically, Figure 3 Local sensing circuits 220i, 220ii, 220n are shown, where n can be an integer up to hundreds of thousands or even higher. Figure 2 , Figure 3 It is shown that (i) local sensing circuit 220i includes current operator circuit 222i, ADC 224i, and latch 226i that provides data output; (ii) local sensing circuit 220ii includes current operator circuit 222ii, ADC 224ii, and latch 226ii that provides data output; and (iii) local sensing circuit 220n includes current operator circuit 222n, ADC 224n, and latch 226n that provides data output. ADC 224i-224n can be one of the largest physical components and one of the highest power consuming resources of local sensing circuits 220i-220n. Therefore, for the reasons discussed herein, it is desirable to implement local sensing circuits that do not require independent ADCs.

[0108] Figure 4Schematic diagram of a memory array for in-memory operations having local sensing circuits without local analog-to-digital converters and including a global counter used by each of the local sensing circuits according to an embodiment of the present invention.

[0109] Specifically, as shown, global counter 400 provides global counter output data 401, which may be referred to as a count value, to local sensing circuits 402i to 402n, where n may be an integer up to hundreds of thousands or even higher. Figure 2 The local sensing circuit 220 includes a (local) current operator circuit 404i (e.g., a local current operator circuit) that provides an output 405i, such as an analog output, to a (local) detector circuit 406i (e.g., a local detector circuit). The current operator circuit 404i can be connected to Figure 2 The local sensing circuit 402i can operate in the same manner as the current operator circuit 222 of the memory array 160. For example, the local sensing circuit 402i can receive the current I from the bit line pair (or a single bit line) of the memory array 160. cell0i and current I cell1i , and can sense the current I cell0i With current I cell1i The difference between the current I cell0i With current I cell1i The difference between the currents 404i and 405i may be reflected as one current minus the other current or one current added to the other current. The current operator circuit 404i may then provide an output 405i based on the sensed or detected difference.

[0110] The detector circuit 406i receives the output 405i and can compare the output 405i with a reference voltage such as V ref When the detector circuit 406i determines that the output 405i has reached, exceeded, and / or fallen below the other known value, the detector circuit 406i may provide an output 407i such as a trigger signal to a (local) latch 408i that triggers the storage of the global counter output data 401. Figure 4 The local sensing circuit 402i is shown as including a latch 408i, but other storage components such as flip-flops may replace the latch 408i to store the global counter output data 401. The data stored in the latch 408i may be provided as a data output 409i resulting from a CIM operation.

[0111] By replacing the detector circuit 406i and the global counter 400 providing the global counter output data 401 Figure 2 By using the ADC 224, the power consumption and size of the in-memory computing device can be greatly reduced and / or the performance of the in-memory computing device can be greatly improved.

[0112] like Figure 4 As shown, there may be n number of local sensing circuits. Specifically, Figure 4 The bit line pair (or a single bit line) of the memory array 160 receives a current I cell0n and current I cell1n A local sensing circuit 402n is provided, wherein the local sensing circuit 402n includes a current operator circuit 404n that provides an output 405n to a detector circuit 406n, wherein the detector circuit 406n provides an output 407n to be stored by a latch 408n that can provide a data output 409n such as a CIM operation.

[0113] The global counter 400 may continuously provide global counter output data 401 as a count value 401. As shown, the same count value 401 is received by each of the local sensing circuits 402i-402n (e.g., each of the sensing circuits 402i-402n may operate according to the same global counter 400 and the count value 401 provided thereby). Specifically, the count value 401 is received by a respective latch 408i-408n, which may be triggered to respectively store the count value 401, as triggered by a respective trigger signal 407i-407n. The latches 408i-408n may be any type of component that may store or latch data. In addition, the global counter 400 can be any type of counter, such as a regular counter that increments or decrements the count value at regular intervals, an irregular counter that increments or decrements the count value at irregular intervals, a bit number counter that counts a number of received bits and increments or decrements the count value accordingly over time, etc.

[0114] The global counter 400 may provide the count value 401 in a binary value or other form. For example, the count value 401 may be a 2-bit, 3-bit, 4-bit, 5-bit, etc. value received by the latches 408i to 408n. The latches 408i to 408n will have, for example, a number of storage locations that are at least the same as the number of bits of the count value 401, so that all count values ​​401 received from the global counter 400 can be stored. As the global counter 400 continues to provide the count value 401 to the latches 408i to 408n, the count value 401 (e.g., a particular count value) may be stored (latched) by the latches 408i to 408n at different times because the latches 408i to 408n are triggered by the trigger signals 407i to 407n, respectively. The count values ​​401 stored by the different latches 408i-408n are then provided to the data outputs 409i-409n of the local sensing circuits 402i-402n.

[0115] refer to Figure 5 More details regarding the specific structure and specific operation of local sensing circuits 402i-402n are provided below.

[0116] Figure 5 FIG. 1 is a more detailed schematic diagram of a local sensing circuit for in-memory operation according to an embodiment of the present invention. Figure 4 As discussed, an in-memory computing device may include thousands of local sensing circuits. Figure 5 The structure of only one of the local sensing circuits is shown, but all the local sensing circuits of the computing device in the memory may have the same structure as that of the local sensing circuits in the memory. Figure 5 The same structure as discussed.

[0117] Specifically, Figure 5More details about the output of the global counter 400 and the circuit structure of the local sensing circuit 402 are shown. The global counter 400 may output 4 bits as a count value. For example, the global counter 400 may output bit a0, bit a1, bit a2, and bit a3 as four-bit values. The latch 408 of the local sensing circuit 402 may include four latches, including latch L0, latch L1, latch L2, and latch L3. As shown, latch L0 may receive the bit value a0 provided by the global counter 400, latch L1 may receive the bit value a1 provided by the global counter 400, latch L2 may receive the bit value a2 provided by the global counter 400, and latch L3 may receive the bit value a3 provided by the global counter 400. The number of bits provided by the global counter 400 and the number of latches included in the latch 408 are only examples. The techniques disclosed herein may use any number of bits and latches. Optionally, there is at least one latch included in latch 408. The number of latches included in latch 408 should be at least equal to the number of bits provided as count values ​​from global counter 400.

[0118] like Figure 5 As shown in the figure, the binary values ​​represented by bit a0, bit a1, bit a2 and bit a3 are between 0 and 15 (for example, binary value 0000, binary value 0001, binary value 0010, binary value 0011, binary value 0100, binary value 0101, binary value 0110, binary value 0111, binary value 1000, binary value 1001, binary value 1010, binary value 1011, binary value 1100, binary value 1101, binary value 1110 and binary value 1111) increment (count) as unsigned integers. Figure 5 The count from 0 to 15 is shown to be incremented continuously by an integer over time. As discussed herein this is only an example, such that the counter may count forward and / or backward, count in conventional or unconventional number patterns, and count according to conventional or unconventional clock cycles. Global counter 400 may operate based on a clock such as a high speed clock or some other mechanism that will be apparent to one skilled in the art. The value output from detector circuit 406 may trigger latch 408 to store the current count value provided by global counter 400.

[0119] In addition, if Figure 5 As shown in FIG. 4 , the local sensing circuit 402 includes a current sensing circuit 402 receiving a current from a current operator circuit 404 (as described above with respect to FIG. 4 ). Figure 2 and Figure 4 The current I provided by cell Specifically, the current I cellReceived as a current source to charging circuit 502. Charging circuit 502 may further include an optional switch 504 and one or more capacitors 506. In addition, there may be multiple switches 504. For example, there may be one or more switches 504 for each capacitor in one or more capacitors 506. The term "switch 504" may encompass one or more switches 504. Switch 504 may be used to allow one or more capacitors 506 to fully discharge and / or prevent one or more capacitors 506 from further charging. In addition, one or more additional switches within charging circuit 502 may be used to switch V c Connected to GND to discharge the one or more capacitors 506 and I cell Connected to GND. For example, in synchronization with the global counter 400, the switch 504 is used to discharge the one or more capacitors 506 before counting begins. For another example, the switch 504 is used to pass the current I cell To realize charging of one or more capacitors 506, such as and with the detection voltage V c For another example, the switch 504 is used to disconnect the current I for further charging the one or more capacitors 506. cell , and the detection voltage V c For another example, when preparing the current I cell When measuring the current I, the switch 504 is used to release any stored charge in the one or more capacitors 506. cell The one or more capacitors 506 are charged for a specific amount of time, for example, the switch 504 is closed at the beginning of the specific amount of time and then opened at the end of the specific amount of time. c will reach the current I cell , the capacitance value of the one or more capacitors 506, and a value proportional to a particular amount of time. The one or more capacitors 506 can be within a range of values. An example capacitor can be 50 femtofarads. Since the one or more capacitors 506 receive the current I cell , the one or more capacitors 506 begin to charge and can provide a voltage V that can be detected by the detector circuit 406 c (For example, the detection voltage V c ). Over time, due to the one or more capacitors 506 drawing current I cell Charging, detecting voltage V c The value will increase.

[0120] The computing device in the memory also includes a reference voltage V ref The global fixed V ref Source 500. Reference voltage V ref It can be any voltage that can be used in the computing device in the memory. refAn example value of is 0.6 volts. Global fixed V ref Source 500 can provide a reference voltage V ref Provided to all sensing circuits of the computing device in the memory. Alternatively, the reference voltage V can be adjusted according to various factors. ref The full range of values ​​can be adjusted V ref The detector circuit 406 can ref The value of the detection voltage V c This comparison can be performed using comparator 508. Any other type of circuit can be implemented to perform the reference voltage V ref The value of the detection voltage V c For example, the comparator 508 may be replaced by one or more differential amplifiers and / or one or more inverters. Figure 5 In the case of the structure of the detector circuit 406 and the comparator 508 shown in FIG. c Lower than the reference voltage V ref When the detection voltage V c Higher than the reference voltage V ref When , comparator 508 may provide a high output (eg, 1). Other types of logic may be implemented by detector circuit 406, and this is shown as just one example.

[0121] In this example, initially, when the reference voltage V ref Higher than the detection voltage V c , the comparator 508 will output a value of 0, so that the latch 408 that latches (stores) the count value 401 (provided by bits a0 to a3) is not triggered. cell Charge one or more capacitors 506 and detect the voltage V c will increase sufficiently so that the detection voltage V c Reach or exceed the reference voltage V ref The output of the detector circuit 406 and / or the comparator 508 may be referred to as a trigger signal (triggering the latch 408 that latches / stores the count value 401). c Reach or exceed the reference voltage V ref value (or decrease / drop to the reference voltage V ref The trigger signal may change from a value of 0 to a value of 1 or from a value of 1 to a value of 0. The detector circuit 406 may include a plurality of comparator configurations. The comparator 508 may be configured to be edge-triggered or level-triggered, or may have other configurations known to those skilled in the art.

[0122] Although Figure 5 The current operator circuit 404, charging circuit 502, detector circuit 406, and latch 408 are shown as being local to the local sensing circuit 402, but other configurations are possible such that each of the current operator circuit 404, charging circuit 502, detector circuit 406, and latch 408 need not be local to the local sensing circuit 402. Alternatively, without using the charging circuit 502 and / or the one or more capacitors 506, the self-current I cell The generated current or voltage is used as the detection voltage V c (or simply as a detection current) is provided to the detector circuit 406. For example, the detector circuit 406 can directly detect the current I provided by the current operator circuit 404. cell , or the detector circuit 406 can detect the current I provided by the memory array 160 cell0 and / or current I cell1 In addition, the reference current I ref is provided to the detector circuit 406 to perform current I cell 、Current I cell0 and / or current I cell1 comparison, rather than the reference voltage V ref Provided to the detector circuit 406.

[0123] The techniques disclosed herein are not limited to only in-memory computing devices, but can be used to sense in any type of memory cell where different cell currents can represent different data values. In addition, the techniques disclosed herein are not limited to only sensing current in memory devices, and can be implemented in any device that senses current. In view of these additional configurations, the detector circuit 406 can be any type of detector that can detect current and / or voltage. For example, the detector circuit 406 can detect cell current from a memory cell, mirror current, and / or current from a charging voltage in a capacitor. The disclosed techniques (such as sensing circuits) can be implemented in a system process control block (PCB) and do not necessarily have to be implemented in a memory chip or in-memory computing devices.

[0124] Other implementations of the methods described in this section may include a non-transitory computer-readable storage medium storing instructions executable by a processor to perform any of the methods described above. Yet another implementation of the methods described in this section may include a system including a memory and one or more processors operable to execute instructions stored in the memory to perform any of the methods described above.

[0125] Any data structures and program codes described or referred to above are stored according to numerous implementations on a computer-readable storage medium, which may be any device or medium that can store program codes and / or data for use by a computer system. This includes, but is not limited to, volatile memory, non-volatile memory, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), magnetic and optical storage devices (such as disk drives, tapes, compact discs (CDs), digital versatile discs or digital video discs (DVDs)), or other media now known or later developed that are capable of storing computer-readable media.

[0126] Several flow charts showing logic executed by a memory controller or by a memory device are described herein. The logic can be implemented by a processor programmed with a computer program stored in a memory accessible to a computer system, and can be executed by a processor, by dedicated logic hardware including a field-programmed integrated circuit, and by a combination of dedicated logic hardware and a computer program. Through all the flow charts herein, it will be understood that many steps can be combined, executed in parallel, or executed in different sequences without affecting the functions achieved. In some cases, as the reader will understand, the reconfiguration of the steps will achieve the same results as long as certain other changes are also made. In other cases, as the reader will understand, the reconfiguration of the steps will achieve the same results as long as certain conditions are met. In addition, it will be understood that the flow charts herein only illustrate steps related to understanding the present invention, and it will be understood that a large number of additional steps for implementing other functions can be performed before, after, and between the steps illustrated.

[0127] Although the present invention is disclosed with reference to the preferred embodiments and examples described in detail above, it should be understood that these examples are intended to be illustrative rather than restrictive. It will be readily apparent to those skilled in the art that modifications and combinations will be within the spirit of the present invention and the scope of the appended claims.

Claims

1. An integrated circuit, characterized in that: include: A memory cell array including a plurality of bit lines and a plurality of word lines; a sensing circuit configured to sense a difference between the first current and the second current on different ones of the selected bit lines and generate an output for the selected bit line according to the difference; as well as a global counter configured to continuously provide a count value to each of the sensing circuits according to a clock signal, Each of the sensing circuits generates an output based on (i) the difference between the first current and the second current and (ii) a stored count value received from the global counter, the count value being stored based on the value of the difference between the first current and the second current.

2. The integrated circuit according to claim 1, characterized in that wherein the global counter is configured to continuously increase or decrease the count value over time, and Wherein, for a specific time, the same specific count value is provided to each of the sensing circuits.

3. The integrated circuit according to claim 1, characterized in that Each of the sensing circuits comprises a local detector circuit, wherein the local detector circuit is configured as follows: Receive a detection voltage (V c ); Receive reference voltage (V ref );as well as According to the detection voltage (V c ) and the reference voltage (V ref ) generates a trigger signal.

4. The integrated circuit according to claim 3, characterized in that wherein each of the sensing circuits comprises a storage configured to store a specific count value provided by the global counter, and The storing of the specific count value is performed according to the trigger signal.

5. The integrated circuit according to claim 4, characterized in that The storage includes a latch for storing the specific count value provided by the global counter.

6. The integrated circuit according to claim 4, characterized in that The storage includes a flip-flop for storing the specific count value provided by the global counter.

7. The integrated circuit according to claim 4, characterized in that The local detector circuit includes a comparator, wherein the comparator is configured to (i) compare the detection voltage (V c ) and the reference voltage (V ref ), and (ii) due to the detection voltage (V c ) reaches or exceeds the reference voltage (V ref ) or drops to the reference voltage (V ref ) below to generate the trigger signal.

8. The integrated circuit according to claim 7, characterized in that The trigger signal generated by the comparator is due to the detection voltage (V c ) reaches or exceeds the reference voltage (V ref ) or drops to the reference voltage (V ref ) and below and are edge triggered.

9. The integrated circuit according to claim 7, characterized in that: The trigger signal generated by the comparator is due to the detection voltage (V c ) reaches or exceeds the reference voltage (V ref ) and is level triggered.

10. The integrated circuit according to claim 3, characterized in that The local detector circuit includes a circuit configured to detect the detection voltage (V c ) and the reference voltage (V ref ) generates a differential amplifier for generating the trigger signal.

11. The integrated circuit according to claim 3, characterized in that The local detector circuit includes a circuit configured to detect the detection voltage (V c ) and the reference voltage (V ref ) generates an inverter for generating the trigger signal.

12. The integrated circuit according to claim 3, characterized in that The reference voltage (V ref ) is received by each of the sensing circuits from a global fixed reference voltage source, so that each sensing circuit receives the same reference voltage (V ref ).

13. The integrated circuit according to claim 3, characterized in that The reference voltage (V ref ) is received by each of the sensing circuits from a globally adjustable reference voltage source, so that each sensing circuit receives the same reference voltage (V ref ).

14. The integrated circuit according to claim 3, characterized in that Each of the sensing circuits operates according to the same global counter and the local detector circuit instead of implementing a local analog-to-digital converter.

15. The integrated circuit according to claim 1, characterized in that Each of the sensing circuits does not include a local analog-to-digital converter.

16. The integrated circuit according to claim 1, characterized in that The count value provided by the global counter is a binary value of at least two bits.

17. The integrated circuit according to claim 1, characterized in that The global counter is one of a regular counter and a non-regular counter.

18. The integrated circuit according to claim 1, characterized in that Each of the sensing circuits comprises: A current operator circuit is configured to sense a difference between a first sense current (I0) and a second sense current (I1), and output a current (I cell ); as well as capacitor, configured to receive the current (I cell ), according to the received current (I cell ) stores charge, and generates a detection voltage (V c ) is provided to a detector circuit that triggers storage of the count value received from the global counter.

19. A method for sensing current on a bit line of a memory cell array comprising a plurality of bit lines and a plurality of word lines and providing a digital output, characterized in that: The method comprises: sensing a difference between the first current and the second current on different ones of the selected bit lines using a sensing circuit; The sensing circuit continuously receives a count value provided by the global counter according to a clock signal; and generating the digital output of the selected bit line by the sensing circuit according to the difference and the count value, wherein a digital output is generated by each of the sensing circuits based on (i) the difference between the first current and the second current and (ii) a stored count value received from the global counter, the count value being stored based on the value of the difference between the first current and the second current.

20. An integrated circuit, characterized in that: include: a sensing circuit configured to sense a difference between a first current and a second current on different bit lines of a memory cell array in a selected bit line and generate an output for the selected bit line according to the difference, and Each of the sensing circuits generates an output based on (i) the difference between the first current and the second current and (ii) a stored count value received from a global counter, and the global counter is configured to continuously provide a count value to each of the sensing circuits based on a clock signal, and the count value is stored based on the value of the difference between the first current and the second current.

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