Chip packaging structure and forming method thereof

Abstract

A chip package structure is provided. The chip package structure includes a wiring substrate. The chip package structure includes a chip structure over a routing substrate. The chip package structure includes a first ring structure over the wiring substrate and surrounding the chip structure, where a first coefficient of thermal expansion of the first ring structure is less than a second coefficient of thermal expansion of the wiring substrate. The chip package structure includes an anti-warpage structure over the first ring structure. The third coefficient of thermal expansion of the anti-warping structure is greater than the first coefficient of thermal expansion of the first ring structure. The embodiment of the invention also provides a method for forming the chip packaging structure.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a chip packaging structure and a method for forming the same. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers over a semiconductor substrate, and patterning the various material layers using photolithography and etching processes to form circuit components and elements thereon.

[0003] Many integrated circuits are typically manufactured on semiconductor wafers. The die of the wafer may be processed and packaged. Since the chip package structure may need to include chips and wiring substrates with different coefficients of thermal expansion (CTE), it is challenging to form a reliable chip package structure. Summary of the invention

[0004] Some embodiments of the present disclosure provide a chip packaging structure, which includes: a wiring substrate; a chip structure located above the wiring substrate; a first ring structure located above the wiring substrate and surrounding the chip structure, wherein a first thermal expansion coefficient of the first ring structure is smaller than a second thermal expansion coefficient of the wiring substrate; and an anti-warping structure located above the first ring structure, wherein a third thermal expansion coefficient of the anti-warping structure is larger than the first thermal expansion coefficient of the first ring structure.

[0005] Other embodiments of the present disclosure provide a chip packaging structure, which includes: a wiring substrate; a chip structure located above the wiring substrate; a ring structure located above the wiring substrate and surrounding the chip structure, wherein a first thermal expansion coefficient of the ring structure is smaller than a second thermal expansion coefficient of the wiring substrate; and an anti-warping structure located above the ring structure, wherein a third thermal expansion coefficient of the anti-warping structure is larger than the second thermal expansion coefficient of the wiring substrate.

[0006] Another embodiment of the present disclosure provides a method for forming a chip packaging structure, the method comprising: bonding the chip structure to a wiring substrate; bonding a ring structure to the wiring substrate, wherein the ring structure surrounds the chip structure and a first thermal expansion coefficient of the ring structure is less than a second thermal expansion coefficient of the wiring substrate; and bonding an anti-warping structure to the ring structure, wherein a third thermal expansion coefficient of the anti-warping structure is greater than the first thermal expansion coefficient of the ring structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, aspects of the present disclosure can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figures 1A to 1E are cross-sectional views of various stages of a process of forming a chip package structure according to some embodiments.

[0009] Figure 1E-1 According to some embodiments Figure 1E A top view of a chip packaging structure.

[0010] Figure 2A is a cross-sectional view of a chip packaging structure according to some embodiments.

[0011] Figure 2B According to some embodiments Figure 2A A top view of a chip packaging structure.

[0012] Figure 3A is a cross-sectional view of a chip packaging structure according to some embodiments.

[0013] Figure 3B According to some embodiments Figure 3A A top view of a chip packaging structure.

[0014] Figure 4A is a cross-sectional view of a chip packaging structure according to some embodiments.

[0015] Figure 4B According to some embodiments Figure 4A A top view of a chip packaging structure.

[0016] Figure 5A is a cross-sectional view of a chip packaging structure according to some embodiments.

[0017] Figure 5B According to some embodiments Figure 5A A top view of a chip packaging structure.

[0018] Fig. 6A is a cross-sectional view of a chip packaging structure according to some embodiments.

[0019] Figure 6B According to some embodiments Fig. 6A A top view of a chip packaging structure.

[0020] Figure 7 is a flow chart illustrating a process of forming a chip package structure according to some embodiments. DETAILED DESCRIPTION

[0021] The following disclosure provides many different embodiments or examples for implementing the different components of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the individual embodiments and / or configurations discussed.

[0022] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0023] Those skilled in the art will understand the term "substantially" in the specification, such as "substantially flat" or "substantially coplanar", etc. In some embodiments, the adjective substantially can be removed. Where applicable, the term "substantially" can also include embodiments with "completely", "completely", "all", etc. The term "substantially" can vary in different technologies and is within the range of deviations understood by those skilled in the art. For example, the term "substantially" can also refer to a specified 90% or higher, such as a specified 95% or higher, especially a specified 99% or higher, including a specified 100%, but the present disclosure is not limited thereto. In addition, terms such as "substantially parallel" or "substantially perpendicular" can be interpreted as not excluding minor deviations from the specified arrangement and can include, for example, deviations of up to 10°. The term "substantially" does not exclude "completely", for example, a composition that is "substantially free of" Y can be completely free of Y.

[0024] The term "about" may vary in different technologies and is within the range of deviations understood by those skilled in the art. The term "about" used in conjunction with a specified distance or size should be interpreted as not excluding insignificant deviations from the specified distance or size. For example, the term "about" may include deviations up to 10% of the specified value, but the disclosure is not limited thereto. The term "about" associated with a numerical value x may mean x ± 5 or 10% of the specified value, but the disclosure is not limited thereto.

[0025] Some embodiments of the present disclosure are described. Additional operations may be provided before, during, and / or after the stages described in these embodiments. Some of the stages described may be replaced or eliminated for different embodiments. Additional components may be added to the chip packaging structure. Some of the components described below may be replaced or eliminated for different embodiments. Although some embodiments are discussed with operations performed in a specific order, these operations may be performed in another logical order.

[0026] The present disclosure relates to chip packaging structures and methods of forming the same, which are advantageous for controlling package warpage and mitigating stress within semiconductor packages. As electronic devices continue to evolve, there is an increasing demand for semiconductor packages that can maintain structural integrity and reliability as package size increases and substrate thickness decreases. The technology of the present disclosure addresses these challenges by introducing a hybrid ring and lid structure that manages package stress, warpage, and coplanarity more effectively than conventional packaging solutions.

[0027] In some embodiments, the chip package structure combines a first ring structure characterized by high stiffness and low coefficient of thermal expansion (CTE). This first ring structure is combined with a substrate to form an equivalent body with low CTE, which is used as the basis of the chip package. The present disclosure includes adding a second ring structure or anti-warpage cover, which has a higher CTE than the first ring structure. The CTE contrast between these components introduces a controlled step-by-step warpage management method, which helps to reduce the overall stress experienced by the package during thermal cycling and other reliability testing.

[0028] The disclosed chip packaging structure can be applied to chip-on-wafer-on-substrate (CoWoS) and integrated fan-out (InFO) packaging technologies, where it can be used for layouts based on core substrates and coreless substrates. By implementing a hybrid structure with a specific CTE combination, the disclosed technology controls warpage and also enhances the coplanarity of the package, improving the yield and performance of semiconductor devices.

[0029] The following detailed description further illustrates various embodiments of the chip package structure. Advantages of the disclosed technology include improved structural integrity of semiconductor packages, reduced packaging stress, and enhanced reliability.

[0030] Figures 1A to 1E is a cross-sectional view of various stages of a process for forming a chip package structure according to some embodiments. Figure 1A As shown, according to some embodiments, a wiring substrate 110 is provided.

[0031] According to some embodiments, the wiring substrate 110 includes a dielectric layer, a conductive pad, a wiring layer, and a conductive via (not shown). According to some embodiments, the conductive pad is embedded in the dielectric layer.

[0032] According to some embodiments, the wiring layers of the wiring substrate 110 and the conductive vias are formed in the dielectric layers of the wiring substrate 110. According to some embodiments, the conductive vias electrically connect between different wiring layers and between the wiring layers and the conductive pads.

[0033] According to some embodiments, the dielectric layer is made of an insulating material, such as a polymer material (e.g., polybenzoxazole or polyimide), a nitride (e.g., silicon nitride), an oxide (e.g., silicon oxide), silicon oxynitride, etc. According to some embodiments, the dielectric layer is formed using a lamination process (or a deposition process), a photolithography process, and an etching process.

[0034] According to some embodiments, the conductive pad is made of a conductive material, such as a metal (e.g., copper, aluminum, or tungsten) or an alloy thereof. According to some embodiments, the wiring layer is made of a conductive material, such as a metal (e.g., copper, aluminum, or tungsten) or an alloy thereof. According to some embodiments, the conductive via is made of a conductive material, such as a metal (e.g., copper, aluminum, or tungsten) or an alloy thereof.

[0035] In some embodiments, the conductive pads, the wiring layers, and the conductive vias are made of the same material. In some embodiments, the conductive pads, the wiring layers, and the conductive vias are made of different materials.

[0036] Figure 7 FIG. 1 is a flow chart showing a process of forming a chip package structure according to some embodiments. Figure 1A and Figure 7 As shown, according to some embodiments, step 10 is performed to bond the chip structure 120 to the wiring substrate 110 through the conductive bump 130. In some embodiments, the chip structure 120 includes a chip. According to some embodiments, the chip structure 120 includes a substrate. In some embodiments, the substrate is made of an elemental semiconductor material including silicon or germanium in a single crystal structure, a polycrystalline structure, or an amorphous structure.

[0037] In some other embodiments, the substrate is made of a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, or indium arsenide; an alloy semiconductor, such as SiGe or GaAsP; or a combination thereof. The substrate may also include a multilayer semiconductor, a semiconductor on insulator (SOI) (such as silicon on insulator or germanium on insulator), or a combination thereof.

[0038] In some embodiments, the substrate includes various device elements. In some embodiments, various device elements are formed in and / or above the substrate. For the purpose of simplicity and clarity, device elements are not shown in the figure. Examples of various device elements include active devices, passive devices, other suitable elements or combinations thereof. Active devices may include transistors or diodes (not shown) formed at the surface of the substrate. Passive devices include resistors, capacitors or other suitable passive devices.

[0039] For example, the transistor can be a metal oxide semiconductor field effect transistor (MOSFET), a complementary metal oxide semiconductor (CMOS) transistor, a bipolar junction transistor (BJT), a high voltage transistor, a high frequency transistor, a p-channel and / or n-channel field effect transistor (PFET / NFET), etc.

[0040] Various processes, such as front-end-of-line (FEOL) semiconductor manufacturing processes, are performed to form various device elements. The FEOL semiconductor manufacturing processes may include deposition, etching, implantation, photolithography, annealing, planarization, one or more other suitable processes, or a combination thereof.

[0041] In some embodiments, an isolation feature (not shown) is formed in the substrate. The isolation feature is used to define the active area, and the isolation feature electrically isolates various device elements formed in and / or above the substrate in the active area. In some embodiments, the isolation feature includes a shallow trench isolation (STI) feature, a local oxidation of silicon (LOCOS) feature, other suitable isolation features, or a combination thereof.

[0042] In some other embodiments, the chip structure 120 includes a chip package, such as a dynamic random access memory (DRAM) package. The chip package includes a chip-scale package, such as a wafer-level chip scale package. In some embodiments, the chip package includes one chip. In some other embodiments, the chip package includes a plurality of chips arranged side by side or stacked on each other (e.g., a 3D package or a 3DIC device).

[0043] In some embodiments, the chip structure 120 is a chip, such as a central processing unit (CPU) chip. According to some embodiments, the conductive bumps 130 are made of tin (Sn) or another suitable conductive material.

[0044] like Figure 1A As shown, according to some embodiments, the device 140 is bonded to the wiring substrate 110 by, for example, surface mount technology (SMT). The device 140 includes a passive device, other suitable devices, or a combination thereof. The passive device includes a resistor, a capacitor, an inductor, or other suitable passive devices.

[0045] like Figure 1A As shown, according to some embodiments, an underfill layer 150 is formed between the chip structure 120 and the wiring substrate 110. According to some embodiments, the underfill layer 150 surrounds the conductive bumps 130 and the chip structure 120. According to some embodiments, the underfill layer 150 is made of an insulating material such as a polymer material.

[0046] like Figure 1BAs shown, according to some embodiments, an adhesive layer 160 is formed over the wiring substrate 110. According to some embodiments, the adhesive layer 160 has an opening 162. According to some embodiments, the chip structure 120 is located in the opening 162.

[0047] According to some embodiments, the adhesive layer 160 is made of a polymer material such as epoxy or silicone. According to some embodiments, the adhesive layer 160 is formed using a dispensing process.

[0048] like Figure 1C and Figure 7 As shown, according to some embodiments, step 11 is performed to bond the ring structure 170 to the wiring substrate 110 through the adhesive layer 160. According to some embodiments, the adhesive layer 160 is located between the ring structure 170 and the wiring substrate 110. According to some embodiments, the ring structure 170 surrounds the chip structure 120. According to some embodiments, the ring structure 170 has an opening 171. According to some embodiments, the chip structure 120 is located in the opening 171.

[0049] According to some embodiments, the thermal expansion coefficient of the ring structure 170 is smaller than the thermal expansion coefficient of the wiring substrate 110. According to some embodiments, the rigidity of the ring structure 170 is greater than the rigidity of the wiring substrate 110.

[0050] Therefore, according to some embodiments, the ring structure 170 and the wiring substrate 110 together form an equivalent body having a lower coefficient of thermal expansion than the wiring substrate 110 and a greater rigidity than the wiring substrate 110 .

[0051] According to some embodiments, the ring structure 170 is made of a rigid and low CTE material, such as ceramic or alloy (e.g., Ni-Fe alloy or Ni-Fe-Co alloy), or another suitable material having a lower CTE than the wiring substrate 110 and a higher rigidity than the wiring substrate 110. In some other embodiments, according to some embodiments, the ring structure 170 is made of metal (e.g., copper or iron), their alloys (e.g., stainless steel), or another suitable material that is more rigid than the wiring substrate 110. According to some embodiments, the bonding process includes a heat clamping process and a curing process.

[0052] like Figure 1D As shown, according to some embodiments, an adhesive layer 180 is formed over the ring structure 170. According to some embodiments, the adhesive layer 180 has an opening 182. According to some embodiments, the chip structure 120 is located under the opening 182 (or in the opening 182).

[0053] According to some embodiments, the adhesive layer 180 is made of a combination of a polymer and a metal (eg, silver paste) or a polymer (eg, epoxy or silicone). According to some embodiments, the adhesive layer 180 is formed using a dispensing process.

[0054] Figure 1E-1 According to some embodiments Figure 1E A top view of a chip packaging structure. Figure 1E is a diagram showing the Figure 1E-1 A cross-sectional view of the chip packaging structure along the cross-sectional line II' in FIG. Figure 1E , Figure 1E-1 and Figure 7 As shown, according to some embodiments, step 12 is performed to bond the warping prevention structure 190 to the ring structure 170 via the adhesive layer 180 .

[0055] According to some embodiments, the thermal expansion coefficient of the warpage prevention structure 190 is greater than that of the ring structure 170. According to some embodiments, the thermal expansion coefficient (CTE) of the warpage prevention structure 190 is greater than that of the wiring substrate 110.

[0056] According to some embodiments, the warpage prevention structure 190 includes a ring structure surrounding the chip structure 120. According to some embodiments, the warpage prevention structure 190 has an opening 192. According to some embodiments, the chip structure 120 is located under the opening 192 (or in the opening 192).

[0057] According to some embodiments, the adhesive layer 180 is located between the warping prevention structure 190 and the ring structure 170. According to some embodiments, the adhesive layer 180 is thinner than the warping prevention structure 190 and the ring structure 170. According to some embodiments, the adhesive layer 180 is softer than the warping prevention structure 190 and the ring structure 170. Therefore, according to some embodiments, the adhesive layer 180 can buffer the stress between the warping prevention structure 190 and the ring structure 170.

[0058] According to some embodiments, the warpage prevention structure 190 is made of a high CTE and high thermal conductivity material, such as a metal material (aluminum or copper), an alloy material (e.g., stainless steel), aluminum silicon carbide (AlSiC), or another suitable material having a higher CTE than the ring structure 170 and the wiring substrate 110. According to some embodiments, the bonding process includes a thermal clamping process and a curing process.

[0059] like Figure 1E As shown, according to some embodiments, a conductive bump 210 is formed over the surface 112 of the wiring substrate 110. According to some embodiments, the conductive bump 210 is formed over a conductive pad of the wiring substrate 110.

[0060] According to some embodiments, the conductive bump 210 is electrically connected to the chip structure 120 through the wiring substrate 110 and the conductive bump 130. According to some embodiments, the conductive bump 210 is made of tin (Sn) or another suitable conductive material. According to some embodiments, in this step, the chip package structure 100 is basically formed.

[0061] According to some embodiments, the thermal expansion coefficient of the warpage preventing structure 190 is greater than the thermal expansion coefficient of an equivalent body including the ring structure 170 and the wiring substrate 110 .

[0062] Since the equivalent body has a lower thermal expansion coefficient than the wiring substrate 110 , according to some embodiments, the thermal expansion coefficient (CTE) mismatch between the equivalent body and the (high CTE) warpage prevention structure 190 is greater than the CTE mismatch between the wiring substrate 110 and the warpage prevention structure 190 .

[0063] Since CTE mismatch can reduce the warpage of the chip package structure, according to some embodiments, forming an equivalent body with a lower CTE can increase the CTE mismatch, thereby reducing the warpage of the chip package structure 100. In addition, according to some embodiments, a high-rigidity equivalent body can also reduce the warpage of the chip package structure 100. Therefore, according to some embodiments, the yield of the chip package structure 100 is improved.

[0064] Figure 2A is a cross-sectional view of a chip package structure 200 according to some embodiments. Figure 2B According to some embodiments Figure 2A FIG. 1 is a top view of a chip package structure 200 . Figure 2A is a diagram showing the Figure 2B FIG. 2 is a cross-sectional view of the chip package structure 200 along the cross-sectional line II′ in FIG.

[0065] According to some embodiments, Figure 2A and Figure 2B As shown, the chip packaging structure 200 and Figure 1E The chip package structure 100 is similar to the embodiment of the present invention, and in this embodiment, the anti-warpage structure 190 exposes a portion 172a of the top surface 172 of the ring structure 170. Figure 2B As shown, according to some embodiments, portion 172a surrounds the anti-warping structure 190 and the chip structure 120. According to some embodiments, the inner sidewalls of the anti-warping structure 190 and the ring structure 170 are coplanar. According to some embodiments, the outer sidewalls of the anti-warping structure 190 and the ring structure 170 are separated by the exposed top surface 172.

[0066] According to some embodiments, the ring structure 170 has a width W1 and the anti-warping structure 190 has a width W2. The widths W1 and W2 are measured between the sidewalls of the same portion of the structures 170 and 190. According to some embodiments, the width W2 is less than the width W1. According to some embodiments, the outer sidewalls of the opposing portions of the ring structure 170 are separated by a width W3. According to some embodiments, the outer sidewalls of the opposing portions of the anti-warping structure 190 are separated by a width W4. According to some embodiments, the width W4 is less than the width W3.

[0067] According to some embodiments, since the thermal expansion coefficient of the warpage prevention structure 190 is greater than that of the ring structure 170, after the annealing process, the shrinkage amount of the warpage prevention structure 190 is greater than that of the ring structure 170. Therefore, the warpage prevention structure 190 may be narrower than the ring structure 170.

[0068] Figure 3A is a cross-sectional view of a chip package structure 300 according to some embodiments. Figure 3B According to some embodiments Figure 3A FIG. 1 is a top view of a chip packaging structure 300 . Figure 3A is a diagram showing the Figure 3B FIG. 5 is a cross-sectional view of the chip package structure 300 taken along the cross-sectional line II′ in FIG.

[0069] According to some embodiments, Figure 3A and Figure 3B As shown, the chip packaging structure 300 and Figure 2A and Figure 2B , and in this embodiment, the anti-warping structure 190 exposes portions 172a and 172b of the top surface 172 of the ring structure 170. According to some embodiments, the anti-warping structure 190 is located above the portion 172c of the top surface 172 of the ring structure 170. According to some embodiments, the portion 172c is located between the portions 172a and 172b.

[0070] like Figure 3B As shown, according to some embodiments, portion 172a surrounds portions 172b and 172c, the anti-warping structure 190, and the chip structure 120. Figure 3B As shown, portion 172 b surrounds chip structure 120 in accordance with some embodiments.

[0071] Figure 4A is a cross-sectional view of a chip package structure 400 according to some embodiments. Figure 4B According to some embodiments Figure 4A FIG. 4 is a top view of a chip packaging structure 400 . Figure 4A is a diagram showing the Figure 4BFIG. 4 is a cross-sectional view of the chip package structure 400 along the cross-sectional line II′ in FIG.

[0072] According to some embodiments, Figure 4A and Figure 4B As shown, the chip packaging structure 400 is similar to Figure 1E The chip packaging structure 100, the chip packaging structure 400 and Figure 1E The chip package structure 100 is similar to the chip package structure 100 of FIG. 1 , and in this embodiment, the anti-warpage structure 410 of the chip package structure 400 includes a cover structure. According to some embodiments, the anti-warpage structure 410 covers the chip structure 120 , the conductive bump 130 , the device 140 , the underfill layer 150 , and the ring structure 170 .

[0073] According to some embodiments, the anti-warping structure 410 is made of a high CTE and high thermal conductivity material, such as a metal material (aluminum or copper), an alloy material (e.g., stainless steel), aluminum silicon carbide (AlSiC), or another suitable material having a higher CTE than the ring structure 170 and the wiring substrate 110.

[0074] According to some embodiments, the chip package structure 400 further includes a heat conductive layer 420. According to some embodiments, the heat conductive layer 420 is formed over the chip structure 120. According to some embodiments, the thermal conductivity of the heat conductive layer 420 is greater than the thermal conductivity of the chip structure 120. According to some embodiments, the heat conductive layer 420 is in direct contact with the chip structure 120 and the anti-warpage structure 410, and heat is transferred from the chip structure 120 to the anti-warpage structure 410 through the heat conductive layer 420.

[0075] According to some embodiments, the thermally conductive layer 420 is made of a polymer material including silicone or epoxy. According to some embodiments, the polymer material is doped with particles made of aluminum oxide or zinc oxide. According to some embodiments, the thermally conductive layer 420 is formed using a dispensing process.

[0076] Figure 5A is a cross-sectional view of a chip package structure 500 according to some embodiments. Figure 5B According to some embodiments Figure 5A FIG. 5 is a top view of a chip packaging structure 500 . Figure 5A is a diagram showing the Figure 5B FIG. 5 is a cross-sectional view of the chip package structure 500 along the cross-sectional line II′ in FIG.

[0077] According to some embodiments, Figure 5A and Figure 5B As shown, the chip packaging structure 500 and Figure 1E The chip package structure 500 is similar to the chip package structure 100 , and in this embodiment, the chip package structure 500 further includes an adhesive layer 510 and an anti-warping structure 520 .

[0078] According to some embodiments, the adhesive layer 510 is formed over the warpage prevention structure 190. According to some embodiments, the adhesive layer 510 is made of a polymer material such as epoxy or silicone. According to some embodiments, the adhesive layer 510 is formed using a dispensing process.

[0079] According to some embodiments, the warping prevention structure 520 includes a cap structure. According to some embodiments, the warping prevention structure 520 is bonded to the adhesive layer 510. According to some embodiments, the adhesive layer 510 is located between the warping prevention structure 520 and the warping prevention structure 190.

[0080] According to some embodiments, the warpage prevention structure 520 covers the chip structure 120 , the conductive bumps 130 , the device 140 , the underfill layer 150 , the ring structure 170 , the warpage prevention structure 190 , and the adhesive layers 160 , 180 , and 510 .

[0081] According to some embodiments, the anti-warping structure 190 is located between the ring structure 170 and the anti-warping structure 520. According to some embodiments, the thermal expansion coefficient of the anti-warping structure 190 is greater than the thermal expansion coefficient of the ring structure 170. According to some embodiments, the thermal expansion coefficient of the anti-warping structure 520 is greater than the thermal expansion coefficient of the ring structure 170.

[0082] According to some embodiments, the anti-warping structure 520 is made of a material with high CTE and high thermal conductivity, such as a metal material (aluminum or copper), an alloy material (e.g., stainless steel), aluminum silicon carbide (AlSiC), or another suitable material having a higher CTE than the ring structure 170 and the wiring substrate 110.

[0083] In some embodiments, the anti-warping structure 520 and the anti-warping structure 190 are made of the same material. In some embodiments, the anti-warping structure 520 and the anti-warping structure 190 are made of different materials. According to some embodiments, the CTE of the anti-warping structure 520 is greater than the CTE of the anti-warping structure 190.

[0084] Fig. 6A is a cross-sectional view of a chip packaging structure according to some embodiments. Figure 6B According to some embodiments Fig. 6A A top view of a chip packaging structure. Fig. 6A is a diagram showing the Figure 6B A cross-sectional view of the chip packaging structure along the cross-sectional line II' in FIG.

[0085] According to some embodiments, Fig. 6A and Figure 6B As shown, the chip packaging structure 600 and Figure 4AThe chip package structure 400 is similar to the embodiment, and in this embodiment, the anti-warping structure 410 of the chip package structure 600 further has a groove 412 .

[0086] According to some embodiments, the heat conducting layer 420 is located in the groove 412 of the warpage prevention structure 410. According to some embodiments, the chip structure 120 is partially located in the groove 412 or below the groove 412.

[0087] The processes and materials used to form the chip package structures 200, 300, 400, 500 and 600 may be similar to or the same as the processes and materials used to form the chip package structure 100. Figures 1A to 6B The elements denoted by the same or similar reference numerals in the present invention have the same or similar structures and materials. Therefore, their detailed descriptions will not be repeated here.

[0088] According to some embodiments, a chip packaging structure and a method for forming the same are provided. The method (for forming the chip packaging structure) forms a ring structure with low CTE and high rigidity above a wiring substrate to form an equivalent body with low CTE and high rigidity. The method forms a high CTE anti-warping structure above the equivalent body. Since the equivalent body has a low CTE, the CTE mismatch between the anti-warping structure and the equivalent body increases, which reduces the warping of the chip packaging structure.

[0089] According to some embodiments, a chip packaging structure is provided. The chip packaging structure includes a wiring substrate. The chip packaging structure includes a chip structure located above the wiring substrate. The chip packaging structure includes a first ring structure located above the wiring substrate and surrounding the chip structure. The first thermal expansion coefficient of the first ring structure is less than the second thermal expansion coefficient of the wiring substrate. The chip packaging structure includes an anti-warping structure located above the first ring structure. The third thermal expansion coefficient of the anti-warping structure is greater than the first thermal expansion coefficient of the first ring structure. In some embodiments, the anti-warping structure includes a ring structure surrounding the chip structure. In some embodiments, the chip packaging structure also includes: a first adhesive layer located between the anti-warping structure and the first ring structure, wherein the first adhesive layer is softer than the anti-warping structure and the first ring structure. In some embodiments, the chip packaging structure also includes: a second adhesive layer located between the first ring structure and the wiring substrate. In some embodiments, the first rigidity of the first ring structure is greater than the second rigidity of the wiring substrate. In some embodiments, the anti-warping structure includes a cover structure covering the chip structure and the first ring structure. In some embodiments, the anti-warping structure exposes a portion of the top surface of the first ring structure. In some embodiments, the chip packaging structure further includes: a second ring structure located between the first ring structure and the anti-warping structure, wherein the fourth thermal expansion coefficient of the second ring structure is greater than the first thermal expansion coefficient of the first ring structure. In some embodiments, the chip packaging structure further includes: a first adhesive layer located between the anti-warping structure and the second ring structure. In some embodiments, the chip packaging structure further includes: a second adhesive layer located between the second ring structure and the first ring structure.

[0090] According to some embodiments, a chip packaging structure is provided. The chip packaging structure includes a wiring substrate. The chip packaging structure includes a chip structure located above the wiring substrate. The chip packaging structure includes a ring structure located above the wiring substrate and surrounding the chip structure. A first thermal expansion coefficient of the ring structure is less than a second thermal expansion coefficient of the wiring substrate. The chip packaging structure includes an anti-warping structure located above the ring structure. A third thermal expansion coefficient of the anti-warping structure is greater than the second thermal expansion coefficient of the wiring substrate. In some embodiments, the anti-warping structure includes a cover structure covering the chip structure and the ring structure. In some embodiments, the anti-warping structure has a groove, and the chip structure is partially located in the groove. In some embodiments, the first rigidity of the ring structure is greater than the second rigidity of the wiring substrate.

[0091] According to some embodiments, a method for forming a chip packaging structure is provided. The method includes bonding the chip structure to a wiring substrate. The method includes bonding a ring structure to the wiring substrate. The ring structure surrounds the chip structure, and the first thermal expansion coefficient of the ring structure is less than the second thermal expansion coefficient of the wiring substrate. The method includes bonding an anti-warping structure to the ring structure. The third thermal expansion coefficient of the anti-warping structure is greater than the first thermal expansion coefficient of the ring structure. In some embodiments, the third thermal expansion coefficient of the anti-warping structure is greater than the second thermal expansion coefficient of the wiring substrate. In some embodiments, the first rigidity of the ring structure is greater than the second rigidity of the wiring substrate. In some embodiments, the anti-warping structure exposes a portion of the top surface of the ring structure. In some embodiments, the method for forming a chip packaging structure also includes: an adhesive layer, located between the anti-warping structure and the ring structure, wherein the adhesive layer is thinner than the anti-warping structure and the ring structure.

[0092] Some embodiments of the present application provide a chip packaging structure, including: a wiring substrate; a chip structure located above the wiring substrate; a first ring structure located above the wiring substrate and surrounding the chip structure, wherein a first thermal expansion coefficient of the first ring structure is smaller than a second thermal expansion coefficient of the wiring substrate; and an anti-warping structure located above the first ring structure, wherein a third thermal expansion coefficient of the anti-warping structure is larger than the first thermal expansion coefficient of the first ring structure.

[0093] In some embodiments, the anti-warping structure includes a ring structure surrounding the chip structure. In some embodiments, the chip packaging structure further includes: a first adhesive layer located between the anti-warping structure and the first ring structure, wherein the first adhesive layer is softer than the anti-warping structure and the first ring structure. In some embodiments, the chip packaging structure further includes: a second adhesive layer located between the first ring structure and the wiring substrate. In some embodiments, the first rigidity of the first ring structure is greater than the second rigidity of the wiring substrate. In some embodiments, the anti-warping structure includes a cover structure covering the chip structure and the first ring structure. In some embodiments, the anti-warping structure exposes a portion of the top surface of the first ring structure. In some embodiments, the chip packaging structure further includes: a second ring structure located between the first ring structure and the anti-warping structure, wherein the fourth thermal expansion coefficient of the second ring structure is greater than the first thermal expansion coefficient of the first ring structure. In some embodiments, the chip packaging structure further includes: a first adhesive layer located between the anti-warping structure and the second ring structure. In some embodiments, the chip packaging structure further includes: a second adhesive layer located between the second ring structure and the first ring structure.

[0094] Other embodiments of the present application provide a chip packaging structure, comprising: a wiring substrate; a chip structure located above the wiring substrate; a ring structure located above the wiring substrate and surrounding the chip structure, wherein a first thermal expansion coefficient of the ring structure is smaller than a second thermal expansion coefficient of the wiring substrate; and an anti-warping structure located above the ring structure, wherein a third thermal expansion coefficient of the anti-warping structure is larger than the second thermal expansion coefficient of the wiring substrate.

[0095] In some embodiments, the anti-warping structure includes a cover structure covering the chip structure and the ring structure. In some embodiments, the anti-warping structure has a groove, and the chip structure is partially located in the groove. In some embodiments, the anti-warping structure is narrower than the ring structure. In some embodiments, the first rigidity of the ring structure is greater than the second rigidity of the wiring substrate.

[0096] Still other embodiments of the present application provide a method for forming a chip packaging structure, comprising: bonding a chip structure to a wiring substrate; bonding a ring structure to the wiring substrate, wherein the ring structure surrounds the chip structure and a first thermal expansion coefficient of the ring structure is smaller than a second thermal expansion coefficient of the wiring substrate; and bonding an anti-warping structure to the ring structure, wherein a third thermal expansion coefficient of the anti-warping structure is larger than the first thermal expansion coefficient of the ring structure.

[0097] In some embodiments, the third thermal expansion coefficient of the anti-warping structure is greater than the second thermal expansion coefficient of the wiring substrate. In some embodiments, the first rigidity of the ring structure is greater than the second rigidity of the wiring substrate. In some embodiments, the anti-warping structure exposes a portion of the top surface of the ring structure. In some embodiments, the method of forming a chip packaging structure further includes: an adhesive layer located between the anti-warping structure and the ring structure, wherein the adhesive layer is thinner than the anti-warping structure and the ring structure.

[0098] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A chip packaging structure, comprising: Wiring substrate; A chip structure, located above the wiring substrate; a first ring structure located above the wiring substrate and surrounding the chip structure, wherein a first thermal expansion coefficient of the first ring structure is smaller than a second thermal expansion coefficient of the wiring substrate; and The anti-warping structure is located above the first ring structure, wherein a third thermal expansion coefficient of the anti-warping structure is greater than a first thermal expansion coefficient of the first ring structure.

2. The chip packaging structure according to claim 1, wherein: The warpage prevention structure includes a ring structure surrounding the chip structure.

3. The chip packaging structure according to claim 1, further comprising: A first adhesive layer is located between the anti-warping structure and the first ring structure, wherein the first adhesive layer is softer than the anti-warping structure and the first ring structure.

4. The chip packaging structure according to claim 3, further comprising: A second adhesive layer is located between the first ring structure and the wiring substrate.

5. The chip packaging structure according to claim 1, wherein: A first rigidity of the first ring structure is greater than a second rigidity of the wiring substrate.

6. The chip packaging structure according to claim 1, wherein: The warpage prevention structure includes a cover structure covering the chip structure and the first ring structure.

7. The chip packaging structure according to claim 1, wherein: The warping prevention structure exposes a portion of a top surface of the first ring structure.

8. The chip packaging structure according to claim 1, further comprising: The second ring structure is located between the first ring structure and the anti-warping structure, wherein the fourth thermal expansion coefficient of the second ring structure is greater than the first thermal expansion coefficient of the first ring structure.

9. A chip packaging structure, comprising: Wiring substrate; A chip structure, located above the wiring substrate; a ring structure located above the wiring substrate and surrounding the chip structure, wherein a first thermal expansion coefficient of the ring structure is smaller than a second thermal expansion coefficient of the wiring substrate; and The anti-warping structure is located above the ring structure, wherein a third thermal expansion coefficient of the anti-warping structure is greater than the second thermal expansion coefficient of the wiring substrate.

10. A method for forming a chip packaging structure, comprising: bonding the chip structure to a wiring substrate; bonding a ring structure to the wiring substrate, wherein the ring structure surrounds the chip structure and a first thermal expansion coefficient of the ring structure is smaller than a second thermal expansion coefficient of the wiring substrate; and A warpage prevention structure is bonded to the ring structure, wherein a third coefficient of thermal expansion of the warpage prevention structure is greater than the first coefficient of thermal expansion of the ring structure.

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