Integrated circuit device

Abstract

An integrated circuit device and a method of manufacturing the same are provided. The integrated circuit device includes: a substrate having a plurality of active regions; a bit line extending on the substrate in a horizontal direction parallel to an upper surface of the substrate; a direct contact, electrically connected to a first active region of the plurality of active regions, and electrically connected to a bit line; a contact plug electrically connected to a second active region adjacent to the first active region of the plurality of active regions; and an outer insulating spacer between the bit line and the contact plug and overlapping the bit line in a vertical direction perpendicular to the upper surface of the substrate. The outer insulating spacer includes a doped region doped with a metal element.

Description

Technical Field

[0001] The inventive concept generally relates to an integrated circuit device, and more particularly, to an integrated circuit device including a conductive line and a landing pad over the conductive line. Background Art

[0002] Recently, due to the rapid scaling down of integrated circuit devices, the gaps between adjacent conductive lines in the plurality of conductive lines in the integrated circuit devices have narrowed, and thus the distances between the plurality of conductive lines and the landing pads above the plurality of conductive lines have gradually decreased. Since the insulating structure separating the plurality of conductive lines and the landing pads is consumed in a subsequent etching process, it is necessary to develop a technology to realize a structure capable of maintaining the reliability of the plurality of conductive lines. Summary of the invention

[0003] As shown in one or more embodiments of the present inventive concept, the present inventive concept provides an integrated circuit device with improved reliability by preventing an insulating structure separating a plurality of conductive lines from a plurality of landing pads over the plurality of conductive lines from being excessively consumed during a subsequent etching process.

[0004] In addition, technical objectives to be achieved by the present disclosure are not limited to the above-mentioned technical objectives, and a person of ordinary skill in the art can clearly understand other technical objectives from the following description.

[0005] According to one aspect of the inventive concept, there is provided an integrated circuit device comprising: a substrate having a plurality of active regions; a bit line extending on the substrate in a horizontal direction parallel to an upper surface of the substrate; a direct contact connected to a first active region selected from among the plurality of active regions and connected to the bit line; a contact plug connected to a second active region adjacent to the first active region; and an outer insulating spacer extending between the bit line and the contact plug and overlapping with the bit line in a vertical direction perpendicular to the upper surface of the substrate, wherein the outer insulating spacer comprises a doped region doped with a metal element.

[0006] According to another aspect of the inventive concept, an integrated circuit device is provided, comprising: a substrate having a plurality of active areas; a bit line extending in a horizontal direction on the substrate; a direct contact connected to a first active area selected from among the plurality of active areas and connected to the bit line; a contact plug connected to a second active area adjacent to the first active area; a conductive landing pad extending in a vertical direction on the contact plug and electrically connected to the second active area through the contact plug; an external insulating spacer extending between the bit line and the contact plug, overlapping with the bit line in a vertical direction and including a doped area; and an insulating cap film between the conductive landing pad and the external insulating spacer.

[0007] According to another aspect of the inventive concept, an integrated circuit device is provided, comprising: a substrate having a plurality of active areas; a direct contact connected to a first active area selected from the plurality of active areas; a contact plug connected to a second active area adjacent to the first active area in a first horizontal direction parallel to an upper surface of the substrate; a bit line extending longitudinally in a second horizontal direction on the substrate, the second horizontal direction being parallel to the upper surface of the substrate and intersecting with the first horizontal direction, the bit line being electrically connected to the direct contact; a conductive landing pad extending on the contact plug in a vertical direction perpendicular to the upper surface of the substrate and spaced apart from the bit line; an insulating cover pattern on the bit line between the bit line and the conductive landing pad; an inner insulating spacer extending along the sidewalls of the direct contact and the bit line and covering the top surface of the insulating cover pattern (i.e., on or above the top surface of the insulating cover pattern); an outer insulating spacer between the conductive landing pad and the inner insulating spacer; and an intermediate insulating spacer disposed between the inner insulating spacer and the outer insulating spacer, wherein the upper portion of the outer insulating spacer is doped with a metal element. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which like reference numerals (when used) indicate corresponding elements throughout the several views, and in which:

[0009] Figure 1 is a schematic layout diagram (ie, top view) of an example integrated circuit device according to one or more embodiments;

[0010] Figure 2A is along Figure 1 The line A-A' in Figure 1 A schematic cross-sectional view of an integrated circuit device shown in ;

[0011] Figure 2B is along Figure 1 The line B-B' in Figure 1 A schematic cross-sectional view of an integrated circuit device shown in ;

[0012] Figure 2C yes Figure 2A An enlarged cross-sectional view of area EX1;

[0013] Figure 3 is a schematic cross-sectional view of a region of an integrated circuit device according to other embodiments;

[0014] Figure 4 is a schematic cross-sectional view of a region of an integrated circuit device according to other embodiments;

[0015] Figure 5A , FIG. 5B to FIG. 14A , Fig. 14B , Fig.15A , Fig. 15B , Fig. 15C , Fig.16A , Fig. 16B , Fig. 16C and Fig.17A , FIG. 17B to FIG. 21A , Fig.21B is a schematic cross-sectional view depicting an intermediate process in an example method of manufacturing an integrated circuit device according to an embodiment,

[0016] Among them, in detail, FIG. 5A to FIG. 21A Each of the Figure 1 The line A-A' intercepts Figure 1 A schematic cross-sectional view of some components of the cross-sectional area of ​​the integrated circuit device shown in FIG. 1 according to the process sequence, and FIG. 5B to FIG. 21B Each of the Figure 1 The line B-B' intercepts Figure 1 Schematic cross-sectional views of some components of the region of the cross section of the integrated circuit device shown in FIG. 1 according to the process sequence; Fig. 15C yes Fig.15A is an enlarged cross-sectional view of region EX2, and Fig. 16C yes Fig.16A A magnified view of area EX3. DETAILED DESCRIPTION

[0017] Figure 1 is a schematic layout diagram (ie, top view) of an integrated circuit device according to one or more embodiments.

[0018] Reference Figure 1 The integrated circuit device 10 may include a plurality of active regions ACT. The plurality of active regions ACT may be arranged in a diagonal direction with respect to the first horizontal direction X and the second horizontal direction Y.

[0019] A plurality of word lines WL may extend parallel to each other in a first horizontal direction X across a plurality of active areas ACT. A plurality of bit lines BL may extend parallel to each other in a second horizontal direction Y intersecting (i.e., intersecting) the first horizontal direction X over the plurality of word lines WL. A plurality of bit lines BL may be connected to a plurality of active areas ACT via direct contact DC. As may be used herein, the term "connected" (or "connected to" or similar terms, such as "contact" or "contacting to") is intended to refer to a physical and / or electrical connection between two or more elements, and may include other intervening elements. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items.

[0020] A plurality of buried contacts BC may be formed between two bit lines BL adjacent to each other among the plurality of bit lines BL. According to an embodiment, the plurality of buried contacts BC may be linearly arranged in a first horizontal direction X and a second horizontal direction Y. A plurality of conductive landing pads LP may be formed on the plurality of buried contacts BC, respectively. The buried contacts BC and the conductive landing pads LP may connect a bottom electrode (not shown) of a capacitor formed above the plurality of bit lines BL to the active area ACT. At least some of the plurality of conductive landing pads LP may each overlap with the buried contact BC in a vertical direction. As may be used herein, the term "overlap" (or "overlapping..." or similar terms) is intended to broadly refer to a portion of the conductive landing pads LP overlapped with the buried contact BC in a vertical direction (i.e., Figure 2A The first element may be a first element that intersects at least a portion of a second element in a first horizontal direction X (or a second horizontal direction Y), but the first element and the second element are not required to be completely aligned with each other in a horizontal plane (ie, in the first horizontal direction X and / or the second horizontal direction Y).

[0021] Next, refer to Figure 2A , Figure 2B and Figure 2C Example configurations of integrated circuit elements according to embodiments are described. Figure 2A and Figure 2B The integrated circuit device shown in FIG. 1 may have Figure 1 The layout of the integrated circuit device 10 is shown in FIG.

[0022] Figure 2A is along Figure 1 The line A-A' in Figure 1 A schematic cross-sectional view of an integrated circuit device shown in FIG.

[0023] Figure 2B is along Figure 1 The line B-B' in Figure 1 A schematic cross-sectional view of an integrated circuit device shown in FIG.

[0024] Figure 2C yes Figure 2A An enlarged cross-sectional view of area EX1.

[0025] Reference Figure 2A , Figure 2B and Figure 2C , the integrated circuit device 100 includes a substrate 110, wherein a plurality of active areas ACT are defined by a device isolation layer 112. The device isolation layer 112 is formed in a device isolation trench T1 formed in the substrate 110.

[0026] The substrate 110 may include silicon, such as single crystal silicon, polycrystalline silicon, or amorphous silicon, but embodiments are not limited thereto. According to other embodiments, the substrate 110 may include at least one material selected from Ge, SiGe, SiC, GaAs, InAs, and InP, but embodiments are not limited thereto. According to embodiments, the substrate 110 may include a conductive region, such as an impurity-doped well or an impurity-doped structure. The device isolation layer 112 may include an oxide film, a nitride film, or a combination thereof, but embodiments are not limited thereto.

[0027] A plurality of word line trenches T2 extending in the first horizontal direction X are formed in the substrate 110, and within the plurality of word line trenches T2, a plurality of gate dielectric layers 116, a plurality of word lines 118, and a plurality of buried insulating layers 120 are formed. The plurality of word lines 118 may correspond to Figure 1 The multiple word lines WL shown in FIG.

[0028] The gate dielectric layer 116 may include at least one material selected from a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an oxide / nitride / oxide (ONO) film, and a high dielectric constant (high-k) dielectric film having a dielectric constant higher than that of the silicon oxide film, but the embodiment is not limited thereto. The high-k dielectric film may include, for example, hafnium oxide (HfO 2 ), aluminum oxide (Al 2 O 3 ), hafnium aluminum oxide (HfAlO 3 ), Tantalum Oxide (Ta 2 O 3 ), titanium oxide (TiO 2 ) or a combination thereof. The plurality of word lines 118 may include, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), titanium silicon nitride (TiSiN), tungsten silicon nitride (WSiN) or a combination thereof. The plurality of buried insulating layers 120 may each include a silicon oxide film, a silicon nitride film, a silicon oxynitride film or a combination thereof, but the embodiment is not limited thereto.

[0029] The buffer layer 122 is formed on the substrate 110. The buffer layer 122 may be formed to cover the top surfaces of the plurality of active regions ACT, the top surfaces of the device isolation layer 112, and the top surfaces of the plurality of buried insulating layers 120. As may be used herein, the term "covering" (or "covering ... ", "covering" or similar terms) is intended to broadly refer to an element, structure or layer that is directly on or over another element, structure or layer or has one or more other intervening elements, structures or layers therebetween. The buffer layer 122 may include a first silicon oxide film, a silicon nitride film, and a second silicon oxide film sequentially formed on the substrate 110, but is not limited thereto.

[0030] A plurality of bit lines BL extending parallel to each other in the second horizontal direction Y may be formed on the buffer layer 122. The plurality of bit lines BL are spaced apart from each other in the first horizontal direction X. A direct contact DC is formed on a portion of each of the plurality of active regions ACT. The plurality of bit lines BL may be connected to the plurality of active regions ACT via a plurality of direct contacts DC, respectively. The direct contact DC may include, for example, silicon (Si), germanium (Ge), W, tungsten nitride (WN), cobalt (Co), nickel (Ni), aluminum (Al), molybdenum (Mo), ruthenium (Ru), Ti, Ta, TaN, copper (Cu), or a combination thereof. According to an embodiment, the direct contact DC may include a doped polysilicon film.

[0031] The plurality of bit lines BL may each include a lower conductive layer 130, an intermediate conductive layer 132, and an upper conductive layer 134 sequentially stacked on the substrate 110 in the vertical direction Z. Each of the plurality of bit lines BL is covered by an insulating capping pattern 136. The insulating capping pattern 136 may be disposed above the upper conductive layer 134 in the vertical direction Z. The top surface of the lower conductive layer 130 of the bit line BL and the top surface of the direct contact DC may be arranged on the same plane (i.e., coplanar) with respect to the upper surface of the substrate 110 as a reference layer. Although Figure 2A and Figure 2B It is shown that each of the plurality of bit lines BL has a three-conductive layer structure including a lower conductive layer 130, an intermediate conductive layer 132, and an upper conductive layer 134, but the inventive concept is not limited thereto. For example, the plurality of bit lines BL may each be formed to include a single conductive layer, include a double conductive layer, or have a stacked structure including a plurality of conductive layers (four or more conductive layers).

[0032] According to an embodiment, the lower conductive layer 130 may include a doped polysilicon film. The intermediate conductive layer 132 and the upper conductive layer 134 may each include a material including Ti, TiN, TiSiN, tungsten (W), WN, tungsten silicide (WSi x ), tungsten silicon nitride (WSi x N y ), ruthenium (Ru), or a combination thereof. For example, the middle conductive layer 132 may include a TiN film and / or a TiSiN film, and the upper conductive layer 134 may include a film containing Ti, TiN, W, WN, WSi x N y The insulating capping pattern 136 may include a silicon nitride film.

[0033] A plurality of recessed spaces R1 may be formed in the active area ACT in a portion of the substrate 110. A plurality of contact plugs 150 may be arranged in the plurality of recessed spaces R1. The plurality of contact plugs 150 may each contact one active area ACT selected from the plurality of active areas ACT. The lower ends of the plurality of contact plugs 150 may be arranged at a vertical level lower than the vertical level of the top surface of the substrate 110, so that the lower ends of the plurality of contact plugs 150 are buried in the substrate 110. As used herein, the term "vertical level" refers to a height in a vertical direction Z or -Z. The plurality of contact plugs 150 may include a semiconductor material doped with impurities, a metal, a conductive metal nitride, or a combination thereof, but the inventive concept is not limited thereto.

[0034] In the integrated circuit device 100, one direct contact DC and a pair of contact plugs 150 facing each other with the one direct contact DC therebetween may be respectively connected to different active regions ACT among a plurality of active regions ACT. According to an embodiment, when the direct contact DC is connected to a first active region ACT selected from among a plurality of active regions ACT, the pair of contact plugs 150 facing each other with the direct contact DC therebetween may be respectively connected to a second active region ACT and a third active region ACT adjacent to the first active region ACT.

[0035] A plurality of contact plugs 150 may be linearly arranged between a pair of bit lines BL adjacent to each other among the plurality of bit lines BL in the second horizontal direction Y. A plurality of insulating fences 149 may be arranged between the plurality of contact plugs 150 linearly arranged along the second horizontal direction Y. The plurality of contact plugs 150 may be insulated from each other by the plurality of insulating fences 149. The plurality of insulating fences 149 may each have a columnar shape extending in the vertical direction Z on the substrate 110. According to an embodiment, the plurality of insulating fences 149 may each include a silicon nitride film.

[0036] The integrated circuit device 100 may include a plurality of spacer structures SP1 between the plurality of bit lines BL and the plurality of conductive landing pads LP and between the plurality of bit lines BL and the plurality of contact plugs 150. For example, one spacer structure SP1 may be provided between one bit line BL selected from among the plurality of bit lines BL and the plurality of contact plugs 150 arranged in a row in the second horizontal direction Y. The plurality of spacer structures SP1 may each include an inner insulating spacer 142, an intermediate insulating spacer 146, an outer insulating spacer 148, and an insulating capping film CAP.

[0037] The inner insulating spacer 142 may contact the sidewalls of the direct contact DC and the sidewalls of the lower conductive layer 130 of the bit line BL. The inner insulating spacer 142 may extend in the vertical direction Z along the sidewalls of the intermediate conductive layer 132 and the upper conductive layer 134 of the bit line BL. The inner insulating spacer 142 may cover from the highest level of both sidewalls of the insulating cap pattern 136 on the bit line BL to the lowest level of both sidewalls of the lower conductive layer 130 of the bit line BL in the vertical direction Z. In addition, the inner insulating spacer 142 may cover from the highest level of both sidewalls of the insulating cap pattern 136 directly contacting DC to the lowest level of both sidewalls directly contacting DC in the vertical direction Z. The inner insulating spacer 142 may cover the top surface of the insulating cap pattern 136. In addition, the inner insulating spacer 142 may surround the lower portion of the gap-filling insulating pattern 144 and extend until the inner insulating spacer 142 contacts the lower end of the adjacent contact plug 150. Alternatively, the inner insulating spacer 142 may surround the lower portion of the middle insulating spacer 146 (i.e., extend around the lower portion of the middle insulating spacer 146) and extend until the inner insulating spacer 142 contacts the sidewalls of the outer insulating spacer 148. As may be used herein, the term "surrounding" (or "surrounding" or similar terms) is intended to broadly refer to an element, structure, or layer that extends around, encapsulates, surrounds, or encloses another element, structure, or layer on all sides, although breaks or gaps may also exist. Thus, for example, a material layer having a void or gap therein may still "surround" another layer that it surrounds. The inner insulating spacer 142 may include a nitride film, such as a silicon nitride film.

[0038] The intermediate insulating spacer 146 may extend in the vertical direction Z along the sidewall of the inner insulating spacer 142. The bottom surface of the intermediate insulating spacer 146 may be surrounded by the inner insulating spacer 142 or the gap filling insulating pattern 144. The intermediate insulating spacer 146 may be provided between the inner insulating spacer 142 and the outer insulating spacer 148. The intermediate insulating spacer 146 may be spaced apart from the bit line BL and the direct contact DC, and the inner insulating spacer 142 is located between the intermediate insulating spacer 146 and the bit line BL and the direct contact DC. The intermediate insulating spacer 146 may include a silicon oxide film, an air spacer, or a combination thereof. The term "air" used herein may refer to an atmosphere or other gas that may be present during a manufacturing process.

[0039] A gap-filling insulating pattern 144 may be provided between the lower end of the contact plug 150 and the direct contact DC. A portion of the gap-filling insulating pattern 144 provided between the contact plug 150 and the inner insulating spacer 142 may be formed to be thicker in a horizontal direction (e.g., a first horizontal direction X) than a portion of the gap-filling insulating pattern 144 provided between the outer insulating spacer 148 and the inner insulating spacer 142. One sidewall of the gap-filling insulating pattern 144 may be covered by the lower end of the contact plug 150. The other sidewalls and the bottom surface of the gap-filling insulating pattern 144 may be surrounded by the inner insulating spacer 142.

[0040] The outer insulating spacer 148 may cover a portion of the sidewall of the contact plug 150. In detail, the outer insulating spacer 148 may cover a portion of the sidewall of the contact plug 150 that is not buried in the substrate 110. The outer insulating spacer 148 may cover a portion of the sidewall of the adjacent contact plug 150 and extend to cover the sidewall and top surface of the intermediate insulating spacer 146 and the top surface of the inner insulating spacer 142. In other words, the outer insulating spacer 148 may include a portion overlapping the bit line BL, the insulating capping pattern 136, the inner insulating spacer 142, and the intermediate insulating spacer 146 in the vertical direction Z.

[0041] The outer insulating spacer 148 may be spaced apart from the bit line BL in the first horizontal direction X, and the inner insulating spacer 142 and the intermediate insulating spacer 146 are between the outer insulating spacer 148 and the bit line BL. The outer insulating spacer 148 may be spaced apart from the direct contact DC in the first horizontal direction X, and the inner insulating spacer 142 and the intermediate insulating spacer 146 are between the outer insulating spacer 148 and the direct contact DC. In addition, the outer insulating spacer 148 may be spaced apart from the bit line BL in the vertical direction Z, and the insulating capping pattern 136 and the inner insulating spacer 142 are between the outer insulating spacer 148 and the bit line BL.

[0042] According to an embodiment, the outer insulating spacer 148 may include a dopant DP and may include a silicon nitride film including the dopant DP. The dopant DP may include a metal, such as Al, Ga, In, Ti, Sn, Pb, Cu, or Fe, but the embodiment is not limited thereto. In this specification, a portion of the outer insulating spacer 148 including the dopant DP may be referred to as a doped region A1, and a portion of the outer insulating spacer 148 not including the dopant DP may be referred to as an undoped region A2. According to an embodiment, the doped region A1 may further include a dopant DP in addition to Si and N, and the undoped region A2 may include Si and N. Since the doped region A1 includes the dopant DP and the dopant DP may include a metal, the doped region A1 may exhibit higher etching resistance than the undoped region A2.

[0043] According to an embodiment, the doping region A1 of the outer insulating spacer 148 may be a resultant structure of performing an ion implantation process on the top surface of the outer insulating spacer 148. In this case, as shown in FIG. Figure 2C As shown in FIG. 1 , an upper portion of the outer insulating spacer 148 may include a doped region A1 , and a lower portion of the outer insulating spacer 148 may include an undoped region A2 .

[0044] The insulating cap film CAP may be disposed on the outer insulating spacer 148 (e.g., on at least a portion of the doping region A1 of the outer insulating spacer 148). The insulating cap film CAP may be between at least a portion of the outer insulating spacer 148 and the conductive landing pad LP to separate the conductive landing pad LP from the top of the outer insulating spacer 148. The sidewalls of the insulating cap film CAP and the sidewalls of the outer insulating spacer 148 may contact the sidewalls of the conductive landing pad LP. According to an embodiment, the insulating cap film CAP may have a shape in which the thickness of the insulating cap film CAP (between the outer insulating spacer 148 and the conductive landing pad LP) decreases from the center of the insulating cap film CAP toward the edge of the insulating cap film CAP.

[0045] According to an embodiment, the step coverage of the insulating capping film CAP may be lower than the step coverage of the outer insulating spacer 148. According to an embodiment, the insulating capping film CAP may cover the top surface of the outer insulating spacer 148, such as Figure 2A and Figure 2B , and may not extend onto the sidewalls of the outer insulating spacer 148. In other words, the sidewalls of the outer insulating spacer 148 and the sidewalls of the insulating cap film CAP may be located on the same plane. According to another embodiment, the insulating cap film CAP may cover the top surface of the outer insulating spacer 148 and partially extend onto the sidewalls of the outer insulating spacer 148. The insulating cap film CAP may cover the doped region A1 of the outer insulating spacer 148.

[0046] The insulating capping film CAP may include a silicon nitride film. According to an embodiment, the insulating capping film CAP may be a product obtained by depositing a silicon precursor and a nitrogen precursor through a plasma enhanced atomic layer deposition (PEALD) process, but the embodiment is not limited thereto.

[0047] The inner insulating spacer 142 , the middle insulating spacer 146 , the outer insulating spacer 148 , and the insulating capping film CAP constituting each of the plurality of spacer structures SP1 may extend in the second horizontal direction Y in parallel with the bit line BL.

[0048] The metal silicide film 172 and the plurality of conductive landing pads LP may be sequentially arranged on the plurality of contact plugs 150. The plurality of conductive landing pads LP may be connected to the plurality of contact plugs 150 through the metal silicide film 172. The plurality of conductive landing pads LP may extend from the spaces between the plurality of insulating cap patterns 136 to the tops of the plurality of insulating cap patterns 136 to overlap with some of the plurality of bit lines BL in the vertical direction Z. The plurality of conductive landing pads LP may each include a conductive barrier film 174 and a conductive layer 176.

[0049] According to an embodiment, an insulating cap film CAP may be provided between the conductive landing pad LP and the outer insulating spacer 148. A portion of the conductive landing pad LP overlapping the outer insulating spacer 148 in the vertical direction Z may be spaced apart from the outer insulating spacer 148, with the insulating cap film CAP between the portion and the outer insulating spacer 148. The conductive landing pad LP extends along the outer insulating spacer 148, contacts a side of the outer insulating spacer 148, and may be spaced apart from a top of the outer insulating spacer 148, with the insulating cap film CAP between the conductive landing pad LP and the top of the outer insulating spacer 148.

[0050] According to an embodiment, the metal silicide film 172 may include cobalt silicide, nickel silicide or manganese silicide, but is not limited thereto. According to some embodiments, the metal silicide film 172 may be omitted. The conductive barrier film 174 may have a Ti / TiN stacked structure. The conductive layer 176 may include doped polysilicon, a metal, a metal silicide, a conductive metal nitride or a combination thereof. For example, the conductive layer 176 may include tungsten (W). When viewed from above (i.e., in a plan view), the plurality of conductive landing pads LP may have a pattern shape like a plurality of islands. The plurality of conductive landing pads LP may be electrically insulated from each other by an insulating film 180 that fills the space around them. As may be used herein, the term "fill" (or "filled with", "filled" or similar terms) is intended to broadly refer to completely filling a defined space (e.g., the space around the conductive landing pad LP) or partially filling a defined space; that is, the defined space does not need to be completely filled, but may, for example, be partially filled or have a void or other space everywhere. Figure 2A An example is shown in which a triple conductive layer structure including a metal silicide film 172 , a conductive barrier film 174 , and a conductive layer 176 is disposed on each of the plurality of contact plugs 150 , but the inventive concept is not limited thereto. For example, only a single conductive layer may be disposed on each of the plurality of contact plugs 150 .

[0051] According to an embodiment, since the outer insulating spacer 148 includes the doped region A1 having improved etching resistance, the doped portion of the outer insulating spacer 148 and the insulating cap pattern 136, the inner insulating spacer 142, and the intermediate insulating spacer 146 surrounded by the outer insulating spacer 148 can be prevented from being consumed together during the etching process for forming the contact plug 150.

[0052] In addition, since the insulating capping film CAP is disposed on the outer insulating spacer 148, the outer insulating spacer 148 can be prevented from being consumed together during the etching process for forming the contact plug 150. As a result, leakage current between the landing pad LP and the bit line BL that occurs when the insulating capping pattern 136, the inner insulating spacer 142, the middle insulating spacer 146, and the outer insulating spacer 148 are consumed by the etching process can be prevented, and thus an integrated circuit device with improved reliability can be provided.

[0053] Figure 3 is a schematic diagram of an integrated circuit device 200 according to other embodiments. Figure 3 Shows the corresponding Figure 2A The integrated circuit device 200 and Figure 2A , Figure 2B and Figure 2C The integrated circuit device 100 shown in FIG. 1 is different only in that the integrated circuit device 200 includes an outer insulating spacer 148 a instead of the outer insulating spacer 148 , and thus the following description will focus on the differences between the integrated circuit device 100 and the integrated circuit device 200 .

[0054] Reference Figure 3 , the plurality of spacer structures SP1 may each include an inner insulating spacer 142 , a middle insulating spacer 146 , an outer insulating spacer 148 a , and an insulating capping film CAP.

[0055] The outer insulating spacer 148a may cover a portion of the sidewall of the contact plug 150. In detail, the outer insulating spacer 148a may cover a portion of the sidewall of the contact plug 150 that is not buried in the substrate 110. The outer insulating spacer 148a may cover a portion of the sidewall of the adjacent contact plug 150, and extend to cover the sidewall and top surface of the intermediate insulating spacer 146 and the top surface of the inner insulating spacer 142. In other words, the outer insulating spacer 148a may include a portion overlapping the bit line BL, the insulating capping pattern 136, the inner insulating spacer 142, and the intermediate insulating spacer 146 in the vertical direction Z.

[0056] The outer insulating spacer 148a may be spaced apart from the bit line BL in the first horizontal direction X, and the inner insulating spacer 142 and the middle insulating spacer 146 are between the outer insulating spacer 148a and the bit line BL. The outer insulating spacer 148a may be in direct contact with the DC in the first horizontal direction X (see Figure 2A ) is separated, and the inner insulating spacer 142 and the middle insulating spacer 146 are between the outer insulating spacer 148a and the direct contact DC. In addition, the outer insulating spacer 148a may be spaced apart from the bit line BL (see Figure 2A ) are spaced apart, and the insulating capping pattern 136 and the inner insulating spacer 142 are between the outer insulating spacer 148a and the bit line BL.

[0057] According to an embodiment, the outer insulating spacer 148a may include a dopant DP and may include a silicon nitride film including the dopant DP, but the embodiment is not limited thereto. The dopant DP may include a metal, such as Al, Ga, In, Ti, Sn, Pb, Cu, or Fe. In this specification, a portion of the outer insulating spacer 148a including the dopant DP may be referred to as a doped region A1, and a portion of the outer insulating spacer 148a not including the dopant DP may be referred to as an undoped region A2. According to an embodiment, the doped region A1 may further include a dopant DP in addition to Si and N, and the undoped region A2 may include Si and N. Since the doped region A1 includes the dopant DP and the dopant DP includes a metal, the doped region A1 may exhibit higher etching resistance than the undoped region A2.

[0058] According to an embodiment, the doping region A1 of the outer insulating spacer 148a may be a resultant structure of performing an ion implantation process on the top surface of the outer insulating spacer 148a. Figure 3 As shown in FIG. 1 , an upper portion of the outer insulating spacer 148 a may include a doped region A1 , and a lower portion of the outer insulating spacer 148 a may include an undoped region A2 .

[0059] According to an embodiment, a thickness W1 of the doped region A1 of the outer insulating spacer 148a in the vertical direction Z may be greater than a thickness W2 of the undoped region A2 of the outer insulating spacer 148a in the first horizontal direction X. For example, the thickness W1 of the doped region A1 of the outer insulating spacer 148a may be in a range of about 3 nanometers to about 5 nanometers, and the thickness W2 of the undoped region A2 of the outer insulating spacer 148a may be in a range of about 1 nanometer to about 3 nanometers. For example, when the upper portion of the outer insulating spacer 148a is the doped region A1, the thickness of the upper portion of the outer insulating spacer 148a may be greater than the thickness of the lower portion of the outer insulating spacer 148a.

[0060] According to other embodiments, the thickness W1 of the portion of the outer insulating spacer 148a in contact with the insulating cap film CAP may be greater than the thickness W2 of the portion of the outer insulating spacer 148a not in contact with the insulating cap film CAP. For example, the thickness W1 of the portion of the outer insulating spacer 148a in contact with the insulating cap film CAP may be in the range of about 3 nanometers to about 5 nanometers, and the thickness of the portion of the outer insulating spacer 148a not in contact with the insulating cap film CAP may be in the range of about 1 nanometer to about 3 nanometers. For example, when the upper portion of the outer insulating spacer 148a is covered by the insulating cap film CAP, the thickness of the upper portion of the outer insulating spacer 148a may be greater than the thickness of the lower portion of the outer insulating spacer 148a. The portion of the outer insulating spacer 148a in contact with the insulating cap film CAP may be the same as the doping region A1 of the outer insulating spacer 148a.

[0061] Figure 4 is a schematic diagram of an integrated circuit device 300 according to other embodiments. Figure 4 Shows the corresponding Figure 2A Area "EX1" Figure 2A A portion of the integrated circuit device shown in FIG. Figure 2A , Figure 2B and Figure 2C Unlike the integrated circuit device 100 shown in FIG. 1 , the integrated circuit device 300 does not include an insulating capping film CAP, and thus the following description will focus on the difference between the integrated circuit device 100 and the integrated circuit device 300 .

[0062] Reference Figure 4 , the plurality of spacer structures SP1 may each include an inner insulating spacer 142 , a middle insulating spacer 146 , and an outer insulating spacer 148 .

[0063] The inner insulating spacers 142, the middle insulating spacers 146, and the outer insulating spacers 148 constituting each of the plurality of spacer structures SP1 may be aligned with the bit line BL (see Figure 2A ) extends parallel to the second horizontal direction Y.

[0064] exist Figure 4 In the case of the integrated circuit device 300 shown in FIG. Figure 2A , Figure 2B and Figure 2C Unlike the integrated circuit device 100 shown in FIG. 1 , the insulating capping film CAP may not be disposed on the outer insulating spacer 148. In other words, the insulating capping film CAP may not be provided between the outer insulating spacer 148 and the conductive barrier film 174. According to an embodiment, Figure 4 The integrated circuit device 300 shown in FIG. 1 may be a device that is formed when the insulating cap film CAP is completely consumed by an etching process to form Figure 2A , Figure 2B and Figure 2C The resulting structure is obtained when the contact plug 150 is formed in the cavity.

[0065] According to an embodiment, the conductive landing pad LP may be located on the outer insulating spacer 148, and there is no other component between the outer insulating spacer 148 and the conductive landing pad LP, so the outer insulating spacer 148 may be in direct contact with the conductive landing pad LP (i.e., without any intervening layer therebetween). For example, a portion of the conductive landing pad LP that overlaps with the outer insulating spacer 148 in the vertical direction Z may contact the outer insulating spacer 148. The conductive landing pad LP extends along the side of the outer insulating spacer 148, contacts the side of the outer insulating spacer 148, and may cover the top of the outer insulating spacer 148.

[0066] The plurality of conductive landing pads LP may each include a conductive barrier film 174 and a conductive layer 176. For example, a portion of the conductive barrier film 174 overlapping the outer insulating spacer 148 in the vertical direction Z may contact the outer insulating spacer 148. The conductive barrier film 174 extends along a side of the outer insulating spacer 148, contacts the side of the outer insulating spacer 148, and may cover a top of the outer insulating spacer 148.

[0067] With reference Figure 2A , Figure 2B and Figure 2C The integrated circuit device 100 described is similar, since reference is made to Figure 3 and Figure 4 The described integrated circuit device 200 and the integrated circuit device 300 each include an outer insulating spacer 148 with improved etching resistance, thereby preventing the doped region A1 of the outer insulating spacer 148 and the insulating cap pattern 136, the inner insulating spacer 142 and the intermediate insulating spacer 146 surrounded by the outer insulating spacer 148 from being consumed during an etching process for forming a plurality of contact plugs 150.

[0068] In addition, Figure 3 In the integrated circuit device 200 shown in FIG. 1 , the insulating capping film CAP is disposed on the outer insulating spacer 148 , and thus the outer insulating spacer 148 may be prevented from being consumed during an etching process for forming the plurality of contact plugs 150 .

[0069] As a result, leakage current between the landing pad LP and the bit line BL that occurs when the insulating capping pattern 136 , the inner insulating spacers 142 , the middle insulating spacers 146 , and the outer insulating spacers 148 are consumed by an etching process may be prevented, and thus an integrated circuit device with improved reliability may be provided.

[0070] Figure 5A , FIG. 5B to FIG. 14A , Fig. 14B , Fig.15A , Fig. 15B , Fig. 15C , Fig.16A , Fig. 16B , Fig. 16C and Fig.17A , FIG. 17B to FIG. 21A , Fig. 21B is a schematic diagram depicting an intermediate process in an example method of fabricating an integrated circuit device according to an embodiment.

[0071] In detail, FIG. 5A to FIG. 21A Each of the Figure 1 The line A-A' intercepts Figure 1 1 is a schematic cross-sectional view of some components of the illustrative integrated circuit device 10 in a cross-sectional area according to a process sequence, and FIG. 5B to FIG. 21B Each of the Figure 1 The line B-B' intercepts Figure 1 1 is a schematic cross-sectional view of some components according to process sequence of an area of ​​a cross section of an illustrative integrated circuit device 10 shown in FIG. Fig. 15C yes Fig.15A A magnified view of region EX2 in FIG. 1 , and Fig. 16C yes Fig.16A Magnified view of area EX3.

[0072] In the following, reference will be made to Figure 5A , FIG. 5B to FIG. 14A , Fig. 14B , Fig.15A , Fig. 15B , Fig. 15C , Fig.16A , Fig. 16B , Fig. 16C and Fig.17A , FIG. 17B to FIG. 21A , Fig. 21B Description of manufacturing Figure 2A , Figure 2B and 2C The method of the integrated circuit device 100 shown in FIG.

[0073] Reference Figure 5A and Figure 5B A device isolation trench T1 may be formed in the substrate 110 , and a device isolation layer 112 may be formed in the device isolation trench T1 . A plurality of active areas ACT may be defined in the substrate 110 by the device isolation layer 112 .

[0074] A plurality of word line trenches T2 may be formed in the substrate 110. The plurality of word line trenches T2 may extend parallel to each other in the first horizontal direction X, may be spaced apart from each other in the second horizontal direction Y, and may have a linear shape extending across the active area ACT. In order to form a plurality of word line trenches T2 forming steps at their bottom surfaces, the device isolation layer 112 and the substrate 110 may be etched separately in separate etching processes so that the device isolation layer 112 and the substrate 110 are etched to different depths. After cleaning the resulting structure in which the plurality of word line trenches T2 are formed, a gate dielectric layer 116, a word line 118, and a buried insulating layer 120 may be sequentially formed in each of the plurality of word line trenches T2. Before or after forming the plurality of word lines 118, an ion implantation process may be performed to form a plurality of source / drain regions (not explicitly shown) on the plurality of active areas ACT.

[0075] A buffer layer 122 may be formed on the substrate 110. The buffer layer 122 may be formed to cover top surfaces of the plurality of active regions ACT, top surfaces of the device isolation layer 112, and top surfaces of the plurality of buried insulating layers 120. To form the buffer layer 122, a first silicon oxide film, a silicon nitride film, and a second silicon oxide film may be sequentially formed on the substrate 110, but the inventive concept is not limited thereto.

[0076] Reference Fig. 6A and Figure 6B , a lower conductive layer 130 may be formed on the buffer layer 122. The lower conductive layer 130 may include, for example, a doped polysilicon film, but the embodiment is not limited thereto.

[0077] Reference Fig. 7A and Figure 7B , after the mask pattern MP1 is formed on the lower conductive layer 130, the lower conductive layer 130 is exposed through the opening MH in the mask pattern MP1, and the exposed lower conductive layer 130 and the portions of the buffer layer 122, the substrate 110, and the device isolation layer 112 below the exposed lower conductive layer 130 can be etched to form a direct contact hole DCH exposing the active area ACT of the substrate 110. The term "exposed" (or "exposed" or similar terms) may be used herein to describe the relationship between elements and / or refer to intermediate processes when manufacturing an integrated circuit device, but it may not be necessary to expose a specific element in the completed device. Similarly, the term "unexposed" may be used to describe the relationship between elements and / or refer to intermediate processes when manufacturing an integrated circuit device, but it may not be necessary to not expose a specific element in the completed device. The mask pattern MP1 may include an oxide film, a nitride film, or a combination thereof, but is not limited thereto.

[0078] Reference Fig. 8A and Figure 8B , can be obtained from Fig. 7A and Figure 7BThe mask pattern MP1 is removed from the resulting structure, and a direct contact DC may be formed in the direct contact hole DCH.

[0079] In order to form the direct contact DC, a conductive layer having a thickness sufficient to fill the direct contact hole DCH (see FIG. 1 ) may be formed inside the direct contact hole DCH and on the lower conductive layer 130. Fig. 7A ) thickness, and unnecessary portions of the doped polysilicon film may be removed so that the doped polysilicon film remains only in the direct contact hole DCH; that is, the upper surface of the direct contact DC and the upper surface of the lower conductive layer 130 may be made coplanar with each other (e.g., relative to the upper surface of the substrate 110 as a reference layer), such as using, for example, a chemical mechanical polishing / planarization (CMP) process. According to an embodiment, the direct contact DC may include a polysilicon film doped with an n-type dopant. The n-type dopant may include a material selected from phosphorus (P), arsenic (As), and antimony (Sb), but the embodiment is not limited thereto.

[0080] Reference Fig.9A and Fig. 9B , an intermediate conductive layer 132, an upper conductive layer 134, and a plurality of insulating capping patterns 136 may be sequentially formed on the lower conductive layer 130 and the direct contact DC. The plurality of insulating capping patterns 136 may each be formed as a line pattern extending longitudinally in the second horizontal direction Y.

[0081] Reference Fig. 10A and Fig. 10B ,exist Fig.9A and Fig. 9B In the resulting structure, the upper conductive layer 134, the middle conductive layer 132, the lower conductive layer 130, and the portion directly contacting the DC can be etched using the insulating cap pattern 136 as an etching mask, thereby forming a plurality of bit lines BL on the substrate 110. The plurality of bit lines BL may include the remaining portions of the lower conductive layer 130, the middle conductive layer 132, and the upper conductive layer 134.

[0082] After forming a plurality of bit lines BL, the direct contact holes DCH (see Fig. 7A A portion of the bit line BL may be exposed again around the direct contact DC. The bit line BL and the insulating capping pattern 136 may constitute a bit line structure. A line space LS extending longitudinally in the second horizontal direction Y may be defined between the plurality of bit line structures.

[0083] Reference Fig.11A and Fig. 11B , an inner insulating spacer 142 may be formed to conformally cover the Fig. 10A and Fig. 10BAs may be used herein in the context of a material layer or coating, the term "conformally" (or "conformal" or similar terms) is intended to broadly refer to a material layer or coating having a substantially uniform cross-sectional thickness relative to the contours of the surface to which the material layer is applied.

[0084] The inner insulating spacer 142 may be formed to conformally cover each of the direct contact DC, the lower conductive layer 130, the middle conductive layer 132, the upper conductive layer 134, and the plurality of insulating capping patterns 136. The inner insulating spacer 142 may also extend to the direct contact hole DCH (see Fig. 7A ) and at least a portion of the upper surface of the buffer layer 122. The inner insulating spacer 142 may include a silicon nitride film. To form the inner insulating spacer 142, a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process may be used.

[0085] Reference Fig. 12A and Fig. 12B , you can Fig.11A and Fig. 11B A gap-filling insulating film P144 filling the remaining space of the direct contact holes DCH and covering the plurality of bit lines BL, the plurality of insulating capping patterns 136 and the sidewalls of the plurality of direct contacts DC is formed on the inner insulating spacers 142 of the resulting structure shown in FIG.

[0086] According to an embodiment, gap-filling insulating film P144 may include, for example, a silicon nitride film. Gap-filling insulating film P144 may be formed using a CVD process or an ALD process.

[0087] Reference Fig.13A and Fig. 13B , can be etched isotropically Fig. 12A and Fig. 12B The gap-filling insulating film P144 in the resulting structure is removed to form a gap-filling insulating pattern 144, which includes the remaining portion of the gap-filling insulating film P144 extending around the direct contact DC and filling the direct contact hole DCH. During the isotropic etching of the gap-filling insulating film P144, the inner insulating spacer 142 can be used as an etching stop layer. The gap-filling insulating pattern 144 includes a portion of the gap-filling insulating film P144 filling the inside of the direct contact hole DCH and a portion of the gap-filling insulating film P144 covering the entrance of the direct contact hole DCH from the outside of the entrance side of the direct contact hole DCH.

[0088] Reference Fig.14A and Fig. 14B , a conformal ground cover is formed by a CVD process or an ALD process. Fig.13A and Fig. 13BAfter the intermediate insulating spacer film is exposed on the surface of the resulting structure, a plurality of intermediate insulating spacers 146 may be formed from the intermediate insulating spacer film by anisotropically etching the intermediate insulating spacer film.

[0089] A portion of the inner insulating spacer 142 and a portion of the buffer layer 122 may be removed while the intermediate insulating spacer film is anisotropically etched to form a plurality of intermediate insulating spacers 146. As a result, a portion of the substrate 110, a portion of the inner insulating spacer 142, and a portion of the gap-filling insulating pattern 144 may be exposed through a plurality of line spaces LS. The plurality of intermediate insulating spacers 146 may each cover sidewalls of the bit lines BL and sidewalls of the insulating capping pattern 136 on the inner insulating spacers 142.

[0090] The plurality of intermediate insulating spacers 146 may include a material different from that constituting the inner insulating spacers 142 and the gap-filling insulating patterns 144. The plurality of intermediate insulating spacers 146 may include a material having an etching selectivity with respect to each of the inner insulating spacers 142 and the gap-filling insulating patterns 144. For example, the plurality of intermediate insulating spacers 146 may include a silicon oxide film.

[0091] Reference Fig.15A , Fig. 15B and Fig. 15C , can form a conformal coverage Fig.14A and Fig. 14B The outer insulating spacer 148 of the resulting structure is formed. The outer insulating spacer 148 may include a material having an etching selectivity relative to the plurality of intermediate insulating spacers 146. For example, the outer insulating spacer 148 may include a silicon nitride film. To form the outer insulating spacer 148, an ALD process or a PEALD process may be used.

[0092] According to an embodiment, in the case where the outer insulating spacer 148 is formed by an ALD process, the process of forming the outer insulating spacer 148 may include a first operation of forming an adsorption layer of a silicon precursor, a second operation of removing unnecessary by-products by supplying a purge gas including an inert gas such as nitrogen or argon to the resulting structure on which the adsorption layer of the silicon precursor is formed, a third operation of forming a silicon nitride layer by supplying a nitrogen precursor to the adsorption layer of the silicon precursor, and a fourth operation of removing unnecessary by-products by supplying a purge gas to the resulting structure on which the silicon nitride layer is formed. At this time, the silicon precursor and the nitrogen precursor may be separately supplied to perform the ALD process. For example, the silicon precursor may include a precursor selected from SiCl 4 、Si 2 Cl 6 、SiH 2 Cl 2 、SiH 4 、Si(C2 H 5 O) 4 、Si(NCO) 4 and SiH 2 I 2 any one of the group consisting of, and the nitrogen precursor may include N 2 or NH 3 .

[0093] According to an embodiment, in the case of forming the outer insulating spacer 148 by the PEALD process, the above-mentioned first to fourth operations are sequentially performed, wherein in the third operation of forming the silicon nitride layer by supplying the nitrogen precursor to the adsorption layer of the silicon precursor, the nitrogen precursor may be plasmatized to trigger a reaction between the molecules of the nitrogen precursor and the adsorption layer of the silicon precursor. For example, the nitrogen precursor may be plasmatized by using a method such as direct current (DC) plasma, alternating current (AC) plasma, capacitively coupled plasma (CCP), inductively coupled plasma (ICP), ultra-high density plasma, or radio frequency (RF) plasma.

[0094] Thereafter, the plasmatized nitrogen precursor is supplied to the adsorption layer of the silicon precursor, wherein a bias may be applied thereto to apply a downward force so that the plasmatized nitrogen precursor is adsorbed to the adsorption layer of the silicon precursor.

[0095] According to an embodiment, SiH 2 I 2 Can be used as silicon precursor, N 2 A nitrogen precursor may be used, and the outer insulating spacer 148 may be formed using a CCP method. At this time, the supply pulse of the silicon precursor may be about 0.2 seconds to about 0.4 seconds. The plasma power may be at a power level of about 500 W to about 700 W, and the plasma power pulse duration may be about 4 seconds to about 6 seconds.

[0096] According to an embodiment, a doping process of implanting a dopant DP onto the outer insulating spacer 148 may be further performed. The dopant DP may include a metal such as Al, Ga, In, Ti, Sn, Pb, Cu, or Fe. For example, the doping process may be performed as an ion implantation process. In the case where the ion implantation process is performed on the top surface of the outer insulating spacer 148, the upper portion of the outer insulating spacer 148 may include a doped region, and the lower portion of the outer insulating spacer 148 may include an undoped region. The doping process may be performed in situ.

[0097] Reference Fig.16A , Fig. 16B and Fig. 16C, a preliminary insulating capping film PCAP may be formed on top of the outer insulating spacer 148. The preliminary insulating capping film PCAP may include the same material as the outer insulating spacer 148. For example, the preliminary insulating capping film PCAP may include a silicon nitride film. According to an embodiment, the step coverage of the preliminary insulating capping film PCAP may be lower than the step coverage of the outer insulating spacer 148. According to an embodiment, the preliminary insulating capping film PCAP may be thickly deposited on the top surface of the outer insulating spacer 148 and may not be deposited on the sidewalls of the outer insulating spacer 148, such as Fig.16A and Fig. 16B According to another embodiment, the preliminary insulating capping film PCAP may be thickly deposited on the top surface of the outer insulating spacer 148, and may be partially deposited on the sidewalls of the outer insulating spacer 148. According to an embodiment, the preliminary insulating capping film PCAP may be formed using a PEALD process.

[0098] According to an embodiment, in the case where the preliminary insulating cap film PCAP is formed by a PEALD process, the process of forming the preliminary insulating cap film PCAP may include a first operation of forming an adsorption layer of a silicon precursor, a second operation of removing unnecessary by-products by supplying a purge gas including an inert gas such as nitrogen or argon to the resulting structure on which the adsorption layer of the silicon precursor is formed, a third operation of forming a silicon nitride layer by supplying a nitrogen precursor to the adsorption layer of the silicon precursor, and a fourth operation of removing unnecessary by-products by supplying a purge gas to the resulting structure on which the silicon nitride layer is formed. At this time, the silicon precursor and the nitrogen precursor may be separately supplied to perform the ALD process. For example, the silicon precursor may include a precursor selected from SiCl 4 、Si 2 Cl 6 、SiH 2 Cl 2 、SiH 4 、Si(C 2 H 5 O) 4 and Si(NCO) 4 any one of the group consisting of, and the nitrogen precursor may include N 2 or NH 3 .

[0099] At this time, in the third operation of forming the silicon nitride layer by supplying a nitrogen precursor onto the adsorption layer of the silicon precursor, the nitrogen precursor may be plasmatized to trigger a reaction between the molecules of the nitrogen precursor and the adsorption layer of the silicon precursor. The method of plasmatizing the nitrogen precursor is similar to the method described above in the description of the outer insulating spacer 148.

[0100] Thereafter, the plasmatized nitrogen precursor is supplied to the adsorption layer of the silicon precursor, wherein a bias may be applied thereto to apply a downward force so that the plasmatized nitrogen precursor is adsorbed to the adsorption layer of the silicon precursor.

[0101] According to an embodiment, SiH 2 I 2 Can be used as silicon precursor, N 2 It can be used as a nitrogen precursor, and a preliminary insulating cap film PCAP can be formed using the CCP method. At this time, the supply pulse of the silicon precursor can be about 0.01 seconds to about 0.2 seconds. The plasma power can be at a power level of about 150W to about 400W, and the plasma power pulse duration can be about 0.1 seconds to about 0.2 seconds.

[0102] In this specification, for the convenience of explanation, the PEALD process for forming the outer insulating spacer 148 is referred to as the first process, and the PEALD process for forming the preliminary insulating cap film PCAP is referred to as the second process. According to an embodiment, the supply pulse of the silicon precursor in the second process may be shorter than the supply pulse of the silicon precursor in the first process. For example, the supply pulse of the silicon precursor in the second process may be about 1 / 10 to about 1 / 3 of the supply pulse of the silicon precursor in the first process. In addition, the plasma power of the second process may be lower than the plasma power of the first process, and the plasma power pulse of the second process may be shorter than the plasma power pulse of the first process. For example, the plasma power pulse of the second process may be about 1 / 50 to about 1 / 10 of the plasma power pulse of the first process. Since the supply pulse of the silicon precursor in the second process is lower than the supply pulse of the silicon precursor in the first process, and the plasma power pulse of the second process is lower than the plasma power pulse of the first process, the preliminary insulating cap film PCAP may be mainly formed on the outer insulating spacer 148.

[0103] Reference Fig.17A and Fig. 17B ,exist Fig.16A , Fig. 16B and Fig. 16C In the resulting structure, a plurality of insulating fences 149 spaced apart from each other in the first horizontal direction X may be formed in the line space LS defined by the outer insulating spacers 148 between the plurality of bit lines BL, thereby dividing the line space LS into a plurality of contact spaces CS.

[0104] A plurality of insulating fences 149 may each be formed on the word line 118 to overlap the word line 118 in the vertical direction Z. The plurality of insulating fences 149 may include a silicon nitride film. According to an embodiment, while forming the plurality of insulating fences 149, portions of the plurality of insulating capping patterns 136 and the insulating film surrounding the plurality of insulating capping patterns 136 may be consumed, and thus the heights of the plurality of insulating capping patterns 136 and the insulating film surrounding the plurality of insulating capping patterns 136 may be reduced.

[0105] Thereafter, portions of the structure exposed by the plurality of contact spaces CS may be removed to form a plurality of recessed spaces R1 exposing a plurality of active areas ACT of the substrate 110 between the plurality of bit lines BL. In order to form the plurality of recessed spaces R1, an anisotropic etching process or a combination of an anisotropic etching process and an isotropic etching process may be used. For example, the plurality of recessed spaces R1 may be formed by anisotropically etching the outer insulating spacers 148 exposed by the plurality of contact spaces CS between the plurality of bit lines BL and portions of the substrate 110 below the exposed outer insulating spacers 148 and isotropically etching some of the active areas ACT of the substrate 110 exposed as a result of the anisotropic etching. The plurality of recessed spaces R1 may be connected to the contact spaces CS, respectively. While performing the etching process to form the plurality of recessed spaces R1, portions of the inner insulating spacers 142 and the gap-filling insulating pattern 144 may be consumed in an area adjacent to the top surface of the substrate 110.

[0106] A portion of the active area ACT of the substrate 110 , a portion of the inner insulating spacer 142 , and a portion of the gap-filling insulating pattern 144 may be exposed through the plurality of recess spaces R1 .

[0107] According to an embodiment, while forming the plurality of insulating fences 149 and performing an etching process to form the plurality of recess spaces R1, Fig.16A and Fig. 16B The preliminary insulating cap film PCAP may be partially or completely consumed. When the preliminary insulating cap film PCAP is partially consumed, an insulating cap film CAP including the remaining preliminary insulating cap film PCAP may be formed.

[0108] According to an embodiment, while forming the plurality of insulating fences 149 and performing an etching process to form the plurality of recessed spaces R1, undoped regions of the outer insulating spacers 148 may be consumed. For example, when the upper portions of the outer insulating spacers 148 are doped, while forming the plurality of insulating fences 149 and performing an etching process to form the plurality of recessed spaces R1, the lower portions of the outer insulating spacers 148 may be partially consumed.

[0109] Reference Fig.18A and Fig.18B ,exist Fig.17A and Fig. 17BIn the resulting structure, a conductive layer 150L may be formed to at least partially fill the plurality of recessed spaces R1 and the plurality of contact spaces CS between the plurality of bit lines BL. The conductive layer 150L may include a portion covering the top surface of the plurality of insulating capping patterns 136 outside the plurality of contact spaces CS. The conductive layer 150L may include a doped polysilicon film. For example, the conductive layer 150L may include a polysilicon film doped with an n-type dopant, but embodiments are not limited thereto.

[0110] According to an embodiment, after forming a doped polysilicon film filling the plurality of recessed spaces R1 and the plurality of contact spaces CS to form the conductive layer 150L, ​​a laser annealing process may be performed to densify the doped polysilicon film (i.e., make it denser). By performing the laser annealing process on the doped polysilicon film, voids included in the doped polysilicon film may be removed, thereby obtaining a doped polysilicon film having a dense film quality.

[0111] Reference Fig.19A and Fig.19B ,exist Fig.18A and Fig.18B In the resulting structure, the conductive layer 150L may be etched back to form a plurality of contact plugs 150 filling the plurality of recessed spaces R1 between the plurality of bit lines BL and filling portions of the contact spaces CS. As a result of the etch-back process, the upper surfaces of the contact plugs 150 may be at a level lower than the upper surface of the insulating cap film CAP relative to the upper surface of the substrate 110.

[0112] Reference Fig. 20A and Fig. 20B , you can Fig.19A and Fig.19B A metal silicide film 172 is formed on the plurality of contact plugs 150 of the resulting structure shown in FIG. The contact plugs 150 and the metal silicide film 172 may constitute Figure 1 At least a portion of the buried contact BC shown in .

[0113] Reference Fig.21A and Fig. 21B , you can Fig. 20A and Fig. 20B A plurality of conductive landing pads LP are formed on the resulting structure. The plurality of conductive landing pads LP may fill the plurality of contact spaces CS on the metal silicide film 172 and extend onto the top of the insulating cap pattern 136 to vertically overlap with some of the plurality of bit lines BL. The plurality of conductive landing pads LP may each include a conductive barrier film 174 and a conductive layer 176.

[0114] In order to form a plurality of conductive landing pads LP, a conductive barrier film 174 and a conductive layer 176 may be formed on the entire surface of the resultant structure having the metal silicide film 172 formed thereon, a mask pattern (not shown) exposing a portion of the conductive layer 176 may be formed on the conductive layer 176, and an upper recessed space R2 may be formed by etching the conductive layer 176, the conductive barrier film 174, and the insulating layer around the conductive barrier film 174 using the mask pattern as an etching mask. The mask pattern may include a silicon nitride film, but is not limited thereto.

[0115] The plurality of conductive landing pads LP may have a pattern shape like a plurality of islands. Among the plurality of conductive landing pads LP, a portion extending in a horizontal direction outside the contact space CS may constitute Figure 1 A plurality of conductive landing pads LP are shown in FIG.

[0116] The upper recessed space R2 around the plurality of conductive landing pads LP may be filled with an insulating film 180 to electrically insulate the plurality of conductive landing pads LP from each other. Thereafter, a plurality of capacitor lower electrodes electrically connected to the plurality of conductive landing pads LP may be formed on the insulating film 180 .

[0117] According to an embodiment, a doping process may be performed on the outer insulating spacer 148 to improve the etching resistance of the outer insulating spacer 148 and prevent the outer insulating spacer 148, the insulating cap pattern 136 surrounded by the outer insulating spacer 148, the inner insulating spacer 142, and the intermediate insulating spacer 146 from being consumed while forming a plurality of insulating fences 149 and while performing an etching process to form a plurality of recessed spaces R1.

[0118] In addition, the preliminary insulating cap film PCAP may be formed on the top of the outer insulating spacer 148, thereby preventing the outer insulating spacer 148, the insulating cap pattern 136 surrounded by the outer insulating spacer 148, the inner insulating spacer 142, and the intermediate insulating spacer 146 from being consumed while forming the plurality of insulating fences 149 and while performing the etching process to form the plurality of recessed spaces R1. Therefore, leakage current between the landing pad LP and the bit line BL, which may occur when the insulating cap pattern 136, the inner insulating spacer 142, the intermediate insulating spacer 146, and the outer insulating spacer 148 are consumed, may be prevented, and thus a method of manufacturing an integrated circuit device with improved reliability may be provided.

[0119] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

[0120] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0137039 filed in the Korean Intellectual Property Office on October 13, 2023, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. An integrated circuit device, comprising: a substrate having a plurality of active regions; a bit line extending on the substrate in a horizontal direction parallel to an upper surface of the substrate; a direct contact electrically connected to a first active region among the plurality of active regions and electrically connected to the bit line; a contact plug electrically connected to a second active region adjacent to the first active region among the plurality of active regions; as well as an outer insulating spacer between the bit line and the contact plug and overlapping the bit line in a vertical direction perpendicular to the upper surface of the substrate, The outer insulating spacer includes a doped region doped with a metal element. 2 . The integrated circuit device according to claim 1 , wherein an upper portion of the outer insulating spacer facing away from the substrate corresponds to the doped region.

3. The integrated circuit device of claim 1 , further comprising a conductive landing pad extending longitudinally in the vertical direction over the contact plug and electrically connected to the contact plug, The conductive landing pad is spaced apart from the bit line, and the outer insulating spacer is between the conductive landing pad and the bit line. 4 . The integrated circuit device according to claim 1 , wherein a cross-sectional thickness of the doped region of the outer insulating spacer is greater than a cross-sectional thickness of an undoped region of the outer insulating spacer. 5 . The integrated circuit device according to claim 1 , wherein a cross-sectional thickness of an upper portion of the outer insulating spacer facing away from the substrate is greater than a cross-sectional thickness of a lower portion of the outer insulating spacer facing toward the substrate.

6. The integrated circuit device according to claim 1, wherein the outer insulating spacer comprises a silicon nitride film, the silicon nitride film comprises the doped region, and The integrated circuit device further comprises: an inner insulating spacer between the outer insulating spacer and the bit line and including a silicon nitride film; as well as An intermediate insulating spacer is between the outer insulating spacer and the inner insulating spacer and includes a silicon oxide film.

7. The integrated circuit device according to claim 1, further comprising: a conductive landing pad on the outer insulating spacer and contacting the contact plug; as well as An insulating cover film is between the outer insulating spacer and the conductive landing pad.

8. The integrated circuit device according to claim 7, wherein the outer insulating spacer comprises a silicon nitride film, the silicon nitride film comprises the doped region, and The insulating cap film includes an undoped silicon nitride film. 9 . The integrated circuit device according to claim 7 , wherein a cross-sectional thickness of the insulating cap film decreases in a direction from a center of the insulating cap film toward an edge of the insulating cap film. 10 . The integrated circuit device of claim 7 , wherein a sidewall of the insulating capping film and a sidewall of the outer insulating spacer contact a sidewall of the conductive landing pad.

11. An integrated circuit device comprising: a substrate having a plurality of active regions; a bit line extending on the substrate in a horizontal direction parallel to an upper surface of the substrate; a direct contact electrically connected to a first active region of the plurality of active regions and electrically connected to the bit line; a contact plug electrically connected to a second active region among the plurality of active regions, wherein the second active region is adjacent to the first active region in the horizontal direction; a conductive landing pad extending on the contact plug in a vertical direction perpendicular to the upper surface of the substrate and electrically connected to the second active region through the contact plug; an outer insulating spacer between the bit line and the contact plug, the outer insulating spacer overlapping the bit line in the vertical direction and including a doped region; and An insulating cover film is between the conductive landing pad and the outer insulating spacer.

12. The integrated circuit device of claim 11, wherein the doped regions of the outer insulating spacers are doped with metal. 13 . The integrated circuit device according to claim 11 , wherein the insulating capping film is on the doping region of the outer insulating spacer.

14. The integrated circuit device according to claim 11, wherein the insulating capping film is on the outer insulating spacer. 15 . The integrated circuit device according to claim 11 , wherein a cross-sectional thickness of a portion of the outer insulating spacer in contact with the insulating capping film is greater than a cross-sectional thickness of a portion of the outer insulating spacer not in contact with the insulating capping film.

16. An integrated circuit device comprising: a substrate having a plurality of active regions; a direct contact electrically connected to a first active region of the plurality of active regions; a contact plug electrically connected to a second active region among the plurality of active regions, the second active region being adjacent to the first active region in a first horizontal direction parallel to an upper surface of the substrate; a bit line extending longitudinally on the substrate in a second horizontal direction, the second horizontal direction being parallel to the upper surface of the substrate and intersecting the first horizontal direction, the bit line being electrically connected to the direct contact; a conductive landing pad extending on the contact plug in a vertical direction perpendicular to the upper surface of the substrate and spaced apart from the bit line; an insulating cap pattern on the bit line and between the bit line and the conductive landing pad; an inner insulating spacer on the sidewall of the direct contact and the sidewall of the bit line and on a top surface of the insulating capping pattern; an outer insulating spacer between the conductive landing pad and the inner insulating spacer; as well as an intermediate insulating spacer, between the inner insulating spacer and the outer insulating spacer, The upper portion of the outer insulating spacer facing away from the substrate is doped with a metal element.

17. The integrated circuit device according to claim 16, further comprising an insulating capping film between the conductive landing pad and the bit line, The insulating capping film is on the outer insulating spacer. 18 . The integrated circuit device according to claim 17 , wherein a sidewall of the insulating capping film is coplanar with a sidewall of the outer insulating spacer. 19 . The integrated circuit device of claim 16 , wherein the outer insulating spacer includes a portion at least partially overlapping the insulating capping pattern, the inner insulating spacer, and the middle insulating spacer in the vertical direction. 20 . The integrated circuit device of claim 16 , wherein the upper portion of the outer insulating spacer overlaps the insulating capping pattern, the inner insulating spacer, and the middle insulating spacer in the vertical direction.

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