FPGA-based X-waveband low-cost wave control system and wave control method

Abstract

The invention discloses an X-waveband low-cost wave control system and method based on an FPGA, and belongs to the technical field of phased-array antennae, and the system comprises an FPGA module which is used for receiving and analyzing a control instruction from an upper computer, and executing a processing thread of a corresponding mode according to an analysis result; a FLASH module is mounted outside the FPGA module and used for achieving real-time programming curing and reconfiguration of storage parameters, the FPGA module is connected with a plurality of T / R assemblies in parallel through a plurality of data lines, the T / R assemblies on a single data line are mounted in a daisy chain mode, multi-channel data frames are sequentially sent into a first assembly shifting register in a serial mode, and the first assembly shifting register is connected with a second assembly shifting register in parallel. And the first T / R component serially outputs the data frame and transmits the data frame to the next component, and when the data frame shifts into a register of the corresponding T / R component, the data frame is read by controlling a time sequence.

Description

Technical Field

[0001] The present invention belongs to the technical field of phased array antennas, and in particular relates to an X-band low-cost beam control system and a beam control method based on FPGA. Background Art

[0002] Phased array radar electronically controls the phase and amplitude of the feed signal of each radiating unit channel in the array antenna, thereby realizing rapid changes in the antenna beam direction and shape. It has the advantages of fast, flexible, almost inertial beam scanning, small blind spots, and strong multi-target capabilities. It has been widely used in military and civilian related radar, communications, aerospace and other fields. The main function of the beam control system is to calculate the phase shift code of each antenna unit according to the control instruction requirements and control its phase shifter to respond to the corresponding phase distribution, synthesize the specified beam, and realize beam control.

[0003] With the development of active phased array radar technology, the number of channels has continued to increase from dozens or hundreds to thousands or even more, and the beam control system has become more complex. Under this trend, the demand for low-cost, low-power, flexible reuse, and convenient debugging and maintenance of beam control systems continues to increase.

[0004] Patent CN112259964A proposes a multi-subarray phased array antenna beam control device, which adopts a distributed solution of multiple subarray beam control boards. The increase in the amount of equipment leads to increased costs and power consumption, and complex debugging and maintenance.

[0005] Patent CN106450761A provides a centralized phased array antenna control device, which uses a centralized solution to parallelly calculate the phase of each antenna array. The FPGA resource usage is large, making it difficult to achieve multi-channel control, and the parameter configuration is inflexible and difficult to apply to complex scenarios. Summary of the invention

[0006] The purpose of the present invention is to provide a low-cost X-band wave control system method based on FPGA in view of the above-mentioned problems and shortcomings.

[0007] In order to achieve the above-mentioned purpose, the technical solution adopted by the present invention is: an X-band low-cost wave control system based on FPGA, comprising: an FPGA module, used to receive and parse control instructions from a host computer, and execute a processing thread of a corresponding mode according to the parsing result; a FLASH module is externally mounted on the FPGA module to realize real-time burning, solidification and reconfiguration of storage parameters, the FPGA module is connected to multiple T / R components in parallel through multiple data lines, and multiple T / R components on a single data line are mounted in a daisy chain manner, and multi-channel data frames are sequentially sent to the first component shift register in serial manner, and then transmitted from the first T / R component to the next component, and when the data frame is shifted to the corresponding T / R component register, it is read by controlling the timing.

[0008] The FPGA module specifically includes: an instruction receiving module: communicating with the host computer to obtain control instruction information. According to different working modes, the control instruction includes working mode, azimuth / elevation increment, working frequency, transmitting / receiving amplitude attenuation value, phase shift value, row and column number, compensation calibration data, transmitting wave gate period and duty cycle parameters;

[0009] Instruction parsing module: parses the control instructions received from the host computer, parses the corresponding working parameters according to the working mode information contained therein, and selects to send to different functional modules for processing;

[0010] Phase-shift code calculation module: calculates the phase-shift code through the parsed azimuth / elevation increment and working frequency, the row and column numbers read from the FLASH module, and the compensation calibration data;

[0011] According to the beam pointing formula of phased array radar principle, the phase shift code is realized through multiplication and addition operation. In order to reduce the FPGA resource occupation, a pipeline method is adopted to multiply first and then add, and the phase shift code of each channel is calculated and compensated in turn. After the calculation is completed, the result is cached in RAM.

[0012] Parameter management module: reads the parameters in the FLASH module to the RAM soft core of the FPGA, and the phase-shift code calculation module reads the corresponding parameters to participate in the calculation, or writes the parameters in the RAM soft core into the FLASH for solidification;

[0013] Data frame reassembly module: In order to realize the wave control scheme of connecting multiple T / R components in series with a single data line, the calculated phase shift codes and amplitude attenuation compensation of multiple channels and the transmit / receive switch control data are spliced ​​and reassembled into corresponding data frames according to a specific protocol;

[0014] Configuration parameter sending module: Send the spliced ​​and reorganized data frames into the T / R component in a specific timing, use multiple data lines for parallel transmission, each data line is connected in series with multiple T / R components in a daisy chain manner, and the data frames are serially entered into the shift register of each T / R component and then serially output to the next component;

[0015] Control timing generation module: Based on the transmission gate period and duty cycle parameters, and under the premise of meeting the over-pulse width and over-duty cycle protection requirements, it generates the transceiver control timing, data transmission and chip control timing, and sends them to the T / R components;

[0016] After the control timing is output, the system uses a bus to connect the control signal to all components, control the effective state of each component configuration parameter and switch selection, and realize synchronous control of all channels.

[0017] BIT receiving module: reads back the configuration parameter data from the last stage T / R component shift register connected in series to each data line;

[0018] BIT information packaging module: packages the read BIT information with the FPGA's own temperature information and version number information into a specific data frame;

[0019] BIT information return module: transmits the data frames packaged by the BIT information packaging module back to the host computer through communication with the host computer.

[0020] The present invention also provides an X-band low-cost wave control method based on FPGA, comprising the following steps:

[0021] Instruction receiving and parsing step: receiving and parsing the control instructions from the host computer, and executing the processing thread of the corresponding mode according to the parsing results;

[0022] Phase shift code calculation steps: read the increment and working frequency of the azimuth / elevation beam control digital extracted by the instruction parsing module, and read the row and column numbers and compensation calibration parameters of the RAM cache at the same time, and realize the phase shift code calculation through fixed multiplication and addition operations;

[0023] Data frame reorganization module and control timing generation step: the calculated phase shift codes and amplitude attenuation compensation of multiple channels and the transmission / reception switch control data are spliced ​​and reorganized into corresponding data frames according to a specific protocol; and then the control timing is generated according to the specific protocol;

[0024] BIT receiving, packaging and feedback steps: send the working parameters of the last-level T / R components mounted on multiple parallel data lines to the BIT information receiving module in the FPGA, and receive data according to the control timing; send the received multiple groups of multi-channel data frames to the BIT information packaging module and package them with the FPGA's own parameters; the BIT information feedback module communicates with the host computer through the asynchronous serial port and transmits the BIT information back to the host computer.

[0025] The instruction receiving and parsing steps specifically include:

[0026] Step 1: The instruction receiving module in the FPGA module drives the serial port and reads the instructions sent by the host computer through the asynchronous serial port;

[0027] Step 2: The instruction parsing module recognizes the instruction header of the data received by the serial port, and determines to start receiving the instruction content when the specified header is recognized through the state machine, and the state machine jumps to the next state;

[0028] Step 3: Determine the working mode field in the control instruction to determine the working mode to be executed, jump different working modes to different states through the state machine method, and execute the corresponding processing thread; the operation mode performs real-time phase shift code operation on the working parameters contained in the control instruction and the compensation parameters stored in FLASH, and calculates the corresponding phase shift code of each T / R component; the monitoring mode uses the control instruction to contain row and column numbers, phase shift codes and compensation calibration data to achieve separate control of specific channels; the internal control mode configures the duty cycle and period parameters through the working instruction, and the FPGA generates the transmission excitation and receiving wave gate signals inside;

[0029] Step 4: Different working modes parse and extract the required corresponding working parameters from the control instructions, and put the working parameters into the corresponding registers by establishing a receiving byte counter; among them, the operation mode parses the increment of the azimuth / elevation wave control digital, the working frequency and the channel switch signal parameters; the monitoring mode parses the row and column numbers, phase shift values, amplitude attenuation values ​​and channel switch signal parameters; the internal control mode parses the duty cycle and period parameters of the transmitting excitation and receiving wave gates; the parameter management mode parses the effective word length of the parameters to be solidified, the solidified row and column numbers and the compensation calibration parameters;

[0030] Step 5: Different working modes send the parsed and extracted working parameters to the corresponding processing thread for processing.

[0031] The phase shift code calculation step specifically includes:

[0032] Step 1: The phase-shift code calculation module reads the row and column numbers and compensation correction parameters cached in the RAM. The data cached in the RAM is read from the FLASH into the RAM when the FPGA is powered on. At the same time, the phase-shift code calculation module reads the increment and operating frequency parameters of the azimuth / elevation beam control digital number extracted from the instruction parsing module.

[0033] Step 2: Using pipeline processing, first multiply then add, send the wave control parameters of all channels to the multiplier in turn for multiplication, output the calculation result when the multiplication of the previous channel is completed, and calculate the multiplication of the next channel parameter at the same time;

[0034] Step 3: Send the output multiplication results to the adder in sequence for addition operation to obtain the phase shift code parameter results required by the T / R component.

[0035] The data frame reorganization module and the control timing generation step specifically include:

[0036] Step 1: The data frame reorganization module reads the phase shift code result of the phase shift code calculation module, splices the channel switch signal and compensation calibration parameters cached in the RAM into the working parameter data frame required for a single channel; splices multiple single-channel data frames into multi-channel working parameter data frames in sequence, and controls the timing generation module to generate the control timing according to the corresponding protocol;

[0037] Step 2: The spliced ​​multi-channel data frame is sent to the first T / R component mounted on each data line in parallel through multiple data signal lines, and the control timing is connected to all T / R components in the form of a bus to achieve synchronous control;

[0038] Step 3: A single data line uses a daisy chain to mount multiple T / R components. Multi-channel data frame data is sent serially and sent to the shift register of the T / R component in turn. The high bit of the data frame is sent first, and the control timing controls the shift register of the T / R component to shift the data frame. Each T / R component shifts the received data in turn and delivers it to the next component. When the data frame is shifted to the corresponding register required by each T / R component, the control signal controls the T / R component to read and enable, and all component parameter configurations are completed synchronously.

[0039] Compared with the prior art, the technical solution adopted by the present invention has the following beneficial effects:

[0040] 1. The present invention adopts a centralized wave control solution, which requires fewer components and has high system reliability. The control link uses a daisy chain connection to connect multiple chip components in series on a single data line; the compensation calibration parameters and FPGA configuration files share a single FLASH, effectively reducing costs.

[0041] 2. The present invention adopts a pipeline method to first multiply and then add to cyclically calculate the phase shift code of each channel, which effectively reduces the FPGA resource occupation, reduces power consumption, and realizes the control of more channels within limited resources.

[0042] 3. The present invention realizes the data interaction between the external FLASH and the RAM soft core through the parameter management module, and realizes the real-time burning, curing and reconfiguration of the compensation calibration parameters and the row and column number parameters through the working instructions. The parameter configuration is more flexible and has good versatility, and can be applied to complex scenarios.

[0043] 4. The present invention is designed with multiple working modes, including full array operation mode, monitoring (single channel direct pass, single channel operation) mode, internal control mode, parameter management mode, and has a BIT information feedback function to facilitate array debugging and maintenance.

[0044] 5. All hardware described in the present invention are domestically produced devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 The present invention provides a block diagram of an X-band low-cost wave control system based on FPGA.

[0046] Figure 2 It is a schematic diagram of the instruction receiving and parsing process provided by an embodiment of the present invention.

[0047] Figure 3It is a schematic diagram of the phase shift code operation flow provided by an embodiment of the present invention.

[0048] Figure 4 It is a schematic diagram of the control timing and data frame reorganization and sending process provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0049] In order to make the technical solution of the present invention, its features and advantages clearer, Figure 1~Figure 4 The preferred embodiments of the present invention are described in detail.

[0050] See also Figure 1 The present invention provides an X-band low-cost wave control system based on FPGA, including: an FPGA module, wherein the FPGA module adopts the domestic low-cost FPGA of Fudan Micro JFMK50 model to realize the functions of receiving and parsing the work instructions sent by the host computer, working mode processing thread scheduling, FLASH storage parameter management, T / R component phase shift code calculation, wave control parameter data frame reorganization, T / R component control timing generation, BIT receiving packaging and return transmission. FPGA communicates with the host computer through the differential full-duplex asynchronous serial port RS422 to realize the data interaction between the work instructions and the BIT return transmission.

[0051] The FPGA is expanded with a FLASH, and the FLASH module adopts the Fudan Micro EFM25QL256 low-cost FLASH chip. The FLASH module is configured to store row and column numbers and antenna array element compensation calibration parameters, and is reused to store FPGA configuration files. The two types of data are stored in different address areas of FLASH. The FLASH module interacts with the soft-core RAM data in the FPGA through the parameter management module. The changed configuration parameters can be written into FLASH through instructions sent by the host computer, and the stored parameters can be updated to achieve real-time burning, solidification and reconfiguration of the stored parameters. When the FPGA is powered on, the row and column numbers and compensation calibration parameters stored in FLASH are read into the RAM cache, which is convenient for the calculation module and the data frame reorganization module to call.

[0052] In a preferred embodiment of the present invention, the FPGA module is connected to the T / R components through 16 parallel data lines, and 16 channels constitute one array element. The array element is daisy-chained in series on each data line. A single data line mounts 4 T / R components, and each component has 4 channels. The component control timing is generated by the control timing generation module, and all T / R components are connected in a bus manner to achieve synchronous control of all components. The BIT return code data is read and received by the BIT information receiving module in a parallel manner using 16 return code data lines, and is packaged and transmitted back to the host computer.

[0053] See also Figure 2 , the instruction receiving and parsing module steps include:

[0054] 1. The instruction receiving module in the FPGA module drives the serial port and reads the instructions sent by the host computer through the asynchronous serial port.

[0055] 2. The command parsing module recognizes the command header of the data received by the serial port, and determines to start receiving the command content when the specified header is recognized through the state machine, and the state machine jumps to the next state.

[0056] 3. Determine the working mode field in the control instruction to determine the working mode to be executed, jump different working modes to different states through the state machine method, and execute the corresponding processing thread. The operation mode performs real-time phase shift code calculation on the working parameters contained in the control instruction and the compensation parameters stored in FLASH, and calculates the corresponding phase shift code of each T / R component. The monitoring mode uses the control instruction to contain row and column numbers, phase shift codes, and compensation calibration data to achieve separate control of specific channels, which is convenient for debugging and maintenance. The internal control mode can configure the duty cycle and period parameters through the working instruction, and the FPGA generates the transmission excitation and receiving wave gate signals inside.

[0057] 4. Different working modes parse and extract the corresponding working parameters from the control instructions, and put the working parameters into the corresponding registers by establishing a receiving byte counter. Among them, the operation mode parses the increment of the azimuth / elevation wave control digital, the working frequency, and the channel switch signal parameters. The monitoring mode parses the row and column numbers, phase shift values, amplitude attenuation values, and channel switch signal parameters. The internal control mode parses the duty cycle and period parameters of the transmitting excitation and receiving wave gates. The parameter management mode parses the effective word length of the parameters to be solidified, the solidified row and column numbers, and the compensation calibration parameters.

[0058] 5. Different working modes send the parsed and extracted working parameters to the corresponding processing thread for processing.

[0059] See also Figure 3 , the phase shift code calculation module steps include:

[0060] 1. The phase-shift code calculation module reads the row and column numbers and compensation correction parameters cached in the RAM. The data cached in the RAM is read from the FLASH into the RAM when the FPGA is powered on. At the same time, the phase-shift code calculation module reads the increment and working frequency parameters of the azimuth / pitch direction wave control digital extracted from the instruction parsing module.

[0061] 2. Use pipeline processing, multiply first and then add. Send the wave control parameters of 256 channels to the multiplier in turn for multiplication. When the multiplication operation of the previous channel is completed, the operation result is output, and the multiplication operation of the next channel parameter is calculated at the same time.

[0062] 3. Send the output multiplication results to the adder for addition operation in sequence to obtain the phase shift code parameter results required by the T / R component. The pipeline operation saves FPGA resource usage, power consumption and cost while ensuring real-time performance.

[0063] See also Figure 4 The steps of the data frame reorganization module and the control timing generation module include:

[0064] 1. The data frame reorganization module reads the phase shift code result of the phase shift code calculation module, reads the cached channel switch signal and the compensation calibration parameters in the RAM, and splices them into the working parameter data frame required for a single channel. Since multiple T / R components are designed with a daisy chain solution, a single data line mounts 4 T / R components, including 16 channels. Multiple single-channel data frames are spliced ​​in sequence into multi-channel working parameter data frames. At the same time, the control timing generation module generates control timings such as synchronous clock, chip select signal, cache enable signal, etc. according to the corresponding protocol.

[0065] 2. The spliced ​​multi-channel data frame is sent to the first T / R component mounted on each data line in parallel through 16 data signal lines. At the same time, the control timing is connected to all T / R components through the bus to achieve synchronous control.

[0066] 3. A single data line uses a daisy chain to mount 4 T / R components, with a total of 16 channels. Multi-channel data frame data is sent serially and sent to the shift register of the T / R component in sequence. The high bit of the data frame is sent first, and the control timing controls the shift register of the T / R component to shift the data frame. Each T / R component shifts the received data in sequence and delivers it to the next component. When the data frame is shifted to the corresponding register required by each T / R component, the control signal controls the T / R component to read and enable, and all component parameter configurations are completed synchronously.

[0067] The BIT receiving, packaging and returning module steps include:

[0068] The working parameters of the last-level T / R components mounted on the 16 parallel data lines are sent to the BIT information receiving module in the FPGA, and the data is received according to the control timing. The 16 groups of multi-channel data frames received are sent to the BIT information packaging module to be packaged with the FPGA's own temperature parameters, version number and other parameters. The BIT information return module communicates with the host computer through the asynchronous serial port and returns the BIT information to the host computer.

[0069] Although the invention has been disclosed as above in terms of preferred embodiments, the embodiments and drawings are not intended to limit the invention. Anyone familiar with the art can make various changes or modifications without departing from the spirit and scope of the invention, but they are also within the scope of protection of the invention. Therefore, the scope of protection of the invention shall be based on the scope of protection of the claims of this application.

Claims

1. An X-band low-cost wave control system based on FPGA, characterized in that: include: FPGA module, used to receive and analyze control instructions from the host computer, and execute the processing thread of the corresponding mode according to the analysis results; The FPGA module is externally mounted with a FLASH module for realizing real-time burning, solidification and reconfiguration of storage parameters. The FPGA module is connected to multiple T / R components in parallel through multiple data lines. Multiple T / R components on a single data line are mounted in a daisy chain manner. Multi-channel data frames are sequentially sent to the first component shift register in serial manner, and then transmitted from the first T / R component to the next component. When the data frame is shifted to the corresponding T / R component register, it is read by controlling the timing.

2. The FPGA-based X-band low-cost wave control system according to claim 1, characterized in that: The FPGA module includes: Command receiving module: communicates with the host computer to obtain control command information. According to different working modes, the control command includes working mode, azimuth / elevation increment, working frequency, transmitting / receiving amplitude attenuation value, phase shift value, row and column number, compensation calibration data, transmitting gate period and duty cycle parameters; Instruction parsing module: parses the control instructions received from the host computer, parses the corresponding working parameters according to the working mode information contained therein, and selects to send to different functional modules for processing; Phase-shift code calculation module: calculates the phase-shift code through the parsed azimuth / elevation increment and working frequency, the row and column numbers read from the FLASH module, and the compensation calibration data; Parameter management module: reads the parameters in the FLASH module to the RAM soft core of the FPGA, and the phase-shift code calculation module reads the corresponding parameters to participate in the calculation, or writes the parameters in the RAM soft core into the FLASH for solidification; Data frame reassembly module: splices and reassembles the calculated phase shift codes and amplitude attenuation compensation of multiple channels and the transmit / receive switch control data into corresponding data frames according to a specific protocol; Configuration parameter sending module: Send the spliced ​​and reorganized data frames into the T / R component in a specific timing, use multiple data lines for parallel transmission, each data line is connected in series with multiple T / R components in a daisy chain manner, and the data frames are serially entered into the shift register of each T / R component and then serially output to the next component; Control timing generation module: Based on the transmission gate period and duty cycle parameters, and under the premise of meeting the over-pulse width and over-duty cycle protection requirements, it generates the transceiver control timing, data transmission and chip control timing, and sends them to the T / R components; BIT receiving module: reads back the configuration parameter data from the last stage T / R component shift register connected in series to each data line; BIT information packaging module: packages the read BIT information with the FPGA's own temperature information and version number information into a specific data frame; BIT information return module: transmits the data frames packaged by the BIT information packaging module back to the host computer through communication with the host computer.

3. The FPGA-based X-band low-cost wave control system according to claim 1, characterized in that: The FPGA module adopts Fudan Micro JFMK50 model FPGA, and the FPGA communicates with the host computer through the differential full-duplex asynchronous serial port RS422 to realize the data interaction between the working instructions and the BIT return.

4. The FPGA-based X-band low-cost wave control system according to claim 1, characterized in that: The FLASH module adopts the Fudan Micro EFM25QL256 chip; the FLASH module is configured to store row and column numbers and antenna array element compensation calibration parameters, and is also reused to store FPGA configuration files. The two types of data are stored in different address areas of the FLASH.

5. The FPGA-based X-band low-cost wave control system according to claim 2, characterized in that: The FLASH module interacts with the soft-core RAM data in the FPGA through the parameter management module, writes the changed configuration parameters into the FLASH through instructions sent by the host computer, updates the storage parameters, and realizes real-time burning, curing and reconfiguration of the storage parameters.

6. The FPGA-based X-band low-cost wave control system according to claim 5, characterized in that: When the FPGA module is powered on, the row and column numbers and compensation calibration parameters stored in the FLASH module are read into the RAM cache for the phase shift code calculation module and the data frame reassembly module to call.

7. A low-cost X-band wave control method based on FPGA according to any one of claims 1-6, characterized in that: The following steps are involved: Instruction receiving and parsing step: receiving and parsing the control instructions from the host computer, and executing the processing thread of the corresponding mode according to the parsing results; Phase shift code calculation steps: read the increment and working frequency of the azimuth / elevation beam control digital extracted by the instruction parsing module, and read the row and column numbers and compensation calibration parameters of the RAM cache at the same time, and realize the phase shift code calculation through fixed multiplication and addition operations; Data frame reassembly module and control timing generation step: the calculated phase shift codes and amplitude attenuation compensation of multiple channels and the transmit / receive switch control data are spliced ​​and reassembled into corresponding data frames according to a specific protocol; Then the control timing is generated according to the specific protocol; BIT receiving, packaging and feedback steps: send the working parameters of the last-level T / R components mounted on multiple parallel data lines to the BIT information receiving module in the FPGA, and receive data according to the control timing; send the received multiple groups of multi-channel data frames to the BIT information packaging module and package them with the FPGA's own parameters; the BIT information feedback module communicates with the host computer through the asynchronous serial port and transmits the BIT information back to the host computer.

8. The X-band low-cost wave control method based on FPGA according to claim 7, characterized in that: The instruction receiving and parsing steps specifically include: Step 1: The instruction receiving module in the FPGA module drives the serial port and reads the instructions sent by the host computer through the asynchronous serial port; Step 2: The instruction parsing module recognizes the instruction header of the data received by the serial port, and determines to start receiving the instruction content when the specified header is recognized through the state machine, and the state machine jumps to the next state; Step 3: Determine the working mode field in the control instruction to determine the working mode to be executed, jump different working modes to different states through the state machine method, and execute the corresponding processing thread; the operation mode performs real-time phase shift code operation on the working parameters contained in the control instruction and the compensation parameters stored in FLASH, and calculates the corresponding phase shift code of each T / R component; the monitoring mode uses the control instruction to contain row and column numbers, phase shift codes and compensation calibration data to achieve separate control of specific channels; the internal control mode configures the duty cycle and period parameters through the working instruction, and the FPGA generates the transmission excitation and receiving wave gate signals inside; Step 4: Different working modes parse and extract the required corresponding working parameters from the control instructions, and put the working parameters into the corresponding registers by establishing a receiving byte counter; among them, the operation mode parses the increment of the azimuth / elevation wave control digital, the working frequency and the channel switch signal parameters; the monitoring mode parses the row and column numbers, phase shift values, amplitude attenuation values ​​and channel switch signal parameters; the internal control mode parses the duty cycle and period parameters of the transmitting excitation and receiving wave gates; the parameter management mode parses the effective word length of the parameters to be solidified, the solidified row and column numbers and the compensation calibration parameters; Step 5: Different working modes send the parsed and extracted working parameters to the corresponding processing thread for processing.

9. The X-band low-cost wave control method based on FPGA according to claim 7, characterized in that: The phase shift code calculation step specifically includes: Step 1: The phase-shift code calculation module reads the row and column numbers and compensation correction parameters cached in the RAM. The data cached in the RAM is read from the FLASH into the RAM when the FPGA is powered on. At the same time, the phase-shift code calculation module reads the increment and operating frequency parameters of the azimuth / elevation beam control digital number extracted from the instruction parsing module. Step 2: Using pipeline processing, first multiply then add, send the wave control parameters of all channels to the multiplier in turn for multiplication, output the calculation result when the multiplication of the previous channel is completed, and calculate the multiplication of the next channel parameter at the same time; Step 3: Send the output multiplication results to the adder in sequence for addition operation to obtain the phase shift code parameter results required by the T / R component.

10. The X-band low-cost wave control method based on FPGA according to claim 7, characterized in that: The data frame reorganization module and the control timing generation step specifically include: Step 1: The data frame reorganization module reads the phase shift code result of the phase shift code calculation module, splices the channel switch signal and compensation calibration parameters cached in the RAM into the working parameter data frame required for a single channel; splices multiple single-channel data frames into multi-channel working parameter data frames in sequence, and controls the timing generation module to generate the control timing according to the corresponding protocol; Step 2: The spliced ​​multi-channel data frame is sent to the first T / R component mounted on each data line in parallel through multiple data signal lines, and the control timing is connected to all T / R components in the form of a bus to achieve synchronous control; Step 3: A single data line uses a daisy chain to mount multiple T / R components. Multi-channel data frame data is sent serially and sent to the shift register of the T / R component in turn. The high bit of the data frame is sent first, and the control timing controls the shift register of the T / R component to shift the data frame. Each T / R component shifts the received data in turn and delivers it to the next component. When the data frame is shifted to the corresponding register required by each T / R component, the control signal controls the T / R component to read and enable, and all component parameter configurations are completed synchronously.

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