Level conversion device
By adopting four sets of parallel eight-channel bidirectional transmission level conversion modules in the level conversion device and optimizing the layout layout, the problems of limited integration and large signal delay differences in existing level conversion devices are solved, and higher integration and smaller signal delay differences are achieved.
Patent Information
- Application Number
- CN202411894093.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-20
- Publication Date
- 2025-04-15
AI Technical Summary
The existing level conversion devices have limited integration and large differences in signal delays, resulting in an increased risk of signal identification errors.
Four sets of eight-channel bidirectional transmission level conversion modules are adopted, each set of modules includes an enable control unit and eight sets of bidirectional transmission level conversion units. By optimizing the layout, it is necessary to ensure that the distances of level conversion elements transmitted in different directions in the same channel to the enable control unit are equal, reducing signal delay differences.
Improves integration, reduces signal delay differences, reduces the risk of signal identification errors, and reduces the overall area in parallel with multiple chips.
Smart Images
Figure CN119834790A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of integrated circuits, and in particular to a level conversion device. Background Art
[0002] A level shifter is an integrated circuit used to convert signals between different voltage levels and is a key component to ensure normal communication between different modules. In order to adapt to the situation where the transmitter and receiver are interchangeable in electronic devices, a level shifter chip capable of bidirectional transmission has been proposed in the related art.
[0003] As the integration of integrated circuits increases, the number of signals that need to be transmitted synchronously has also increased dramatically, and the number of channels of the corresponding level conversion chips has also gradually increased. At present, the more common scenario is the 16-channel bidirectional transmission level conversion scenario, and more complex data signals require a 32-channel bidirectional transmission level conversion chip. For this, two 16-channel bidirectional transmission level conversion chips or four 8-channel bidirectional transmission level conversion chips are usually connected in parallel. However, since multiple chips occupy a large area, and the length and direction of the metal bonding wires for wire bonding when each chip is packaged cannot be completely consistent, resulting in differences in signal delays between different channels. Taking into account the line loss and interference when the chip is working, the difference in the above signal delay will be further amplified, further increasing the risk of signal recognition errors.
[0004] Therefore, there is an urgent need for a level conversion device with higher integration and smaller signal delay difference. Summary of the invention
[0005] In order to solve the technical problems of limited integration and large signal delay difference of the existing level conversion device, the embodiment of the present application provides a level conversion device, including four groups of eight-channel bidirectional transmission level conversion modules connected in parallel, the eight-channel bidirectional transmission level conversion modules include an enabling control unit and eight groups of bidirectional transmission level conversion units, the enabling control unit is configured to receive a transmission direction control signal and a three-state output control signal, and generate a transmission control signal based on the received transmission direction control signal and the three-state output control signal to control each group of the eight groups of bidirectional transmission level conversion units;
[0006] Each group of bidirectional transmission level conversion units includes a level conversion element transmitting in a first direction and a level conversion element transmitting in a second direction, the first direction and the second direction being opposite signal transmission directions; the level conversion element includes an input-level sub-element, a first level conversion sub-element and an output-level sub-element connected in series in sequence;
[0007] Each group of eight-channel bidirectional transmission level conversion modules is arranged in a layout area, and each layout area includes a first area, a second area and a middle area, wherein the first area and the second area are located on both sides of the middle area and are symmetrically arranged; in each group of eight-channel bidirectional transmission level conversion modules, the enabling control unit is arranged in the middle area, the level conversion element transmitting along the first direction is arranged in the first area, and the level conversion element transmitting along the second direction is arranged in the second area, and the level conversion elements transmitting along different directions in the same channel are at the same distance from the enabling control unit.
[0008] Optionally, the four aforementioned layout areas are arranged in a 2×2 or 1×4 manner.
[0009] Optionally, in the same layout area, the level conversion elements transmitting along the first direction are arranged in an array in a first area, and the level conversion elements transmitting along the second direction are arranged in an array in a second area.
[0010] Optionally, the wiring length from the enable control unit to the level conversion element of each group of eight-channel bidirectional transmission level conversion modules is the same; in the eight groups of bidirectional transmission level conversion units, the wiring length between the level conversion elements in each group of bidirectional transmission level conversion units is the same.
[0011] Optionally, each group of eight-channel bidirectional transmission level conversion modules further includes a power supply unit, which is arranged in the middle area; the power supply unit is configured to supply power to each of the eight groups of bidirectional transmission level conversion units.
[0012] Optionally, the enabling control unit includes a second level conversion sub-element, a third level conversion sub-element, a fourth level conversion sub-element and a control sub-element;
[0013] The control sub-element is configured to receive a transmission direction control signal and a three-state output control signal, and is used to process the transmission direction control signal based on the three-state output control signal, and output the processed transmission direction control signal to the second level conversion sub-element for level conversion; the second level conversion sub-element is used to output the transmission control signal EN_AB after level conversion; and,
[0014] The control sub-element is also used to process the three-state output control signal based on the transmission direction control signal, and output the processed three-state output control signal to the third level conversion sub-element for level conversion; the output of the third level conversion sub-element is inverted by the control sub-element and input into the fourth level conversion sub-element for level conversion, and the fourth level conversion sub-element is used to output the transmission control signal EN_BA after level conversion.
[0015] Optionally, the input stage sub-element includes a first NOT gate M1 and a second NOT gate M2 connected in series; power supply terminals of the first NOT gate M1 and the second NOT gate M2 are used to connect to the input stage voltage Vin.
[0016] Optionally, the first level conversion sub-element, the second level conversion sub-element, the third level conversion sub-element or the fourth level sub-element includes a first PMOS tube P1, a second PMOS tube P2, a third PMOS tube P3, a first NMOS tube N1, a second NMOS tube N2 and a third NOT gate M3; wherein:
[0017] The source of the first PMOS tube P1, the substrate of the first PMOS tube P1, the substrate of the second PMOS tube P2, the source of the second PMOS tube P2, the source of the third PMOS tube, the substrate of the third PMOS tube P3 and the power supply end of the third NOT gate M3 are used to connect the output stage voltage Vout; the gate of the third PMOS tube is used to connect the input stage voltage Vin;
[0018] The gate of the first PMOS transistor P1, the drain of the second PMOS transistor P2, the drain of the third PMOS transistor P3 and the drain of the second NMOS transistor N2 are connected to the input end of the third NOT gate M3;
[0019] The drain of the first PMOS transistor P1, the gate of the second PMOS transistor P2 and the drain of the first NMOS transistor N1 are connected;
[0020] The output end of the first NOT gate M1 is connected to the gate of the first NMOS transistor N1;
[0021] The output end of the second NOT gate M2 is connected to the gate of the second NMOS transistor N2;
[0022] The source and substrate of the first NMOS transistor N1 and the source and substrate of the second NMOS transistor N2 are grounded.
[0023] Optionally, the output stage sub-element includes a first NAND gate M6, a fourth NOT gate M4, a first NOR gate M5, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a third NMOS transistor N3, a fourth NMOS transistor N4 and a fifth NMOS transistor N5;
[0024] Among them, one input end of the first NAND gate M6 and one input end of the first NOR gate M5 are connected to the output end of the third NOR gate; another input end of the first NAND gate M6, the input end of the fourth NOR gate M4 and the gate of the fifth NMOS transistor N5 are connected to the enable control unit; another input end of the first NOR gate M5 is connected to the output end of the fourth NOR gate M4;
[0025] The power supply terminal of the fourth NOT gate M4, the power supply terminal of the first NOR gate M5, the source of the fourth PMOS transistor P4, the gate of the fifth PMOS transistor P5, the gate of the fourth NMOS transistor N4 and the drain of the sixth PMOS transistor P6 are used to connect the output stage voltage Vout;
[0026] The output end of the first NAND gate M6 is connected to the gate of the fourth PMOS transistor P4; the drain of the fourth PMOS transistor P4, the drain of the third NMOS transistor N3, the source of the fifth PMOS transistor P5 are connected, and connected to the output port of the output stage sub-element;
[0027] The output end of the first NOR gate M5 is connected to the gate of the third NMOS transistor N3; the source of the third NMOS transistor N3, the substrate of the third NMOS transistor N3, the substrate of the fourth NMOS transistor N4, the substrate of the fifth NMOS transistor N5 and the source of the fifth NMOS transistor N5 are grounded;
[0028] The power supply end of the first NAND gate M6, the substrate of the fourth PMOS tube P4, the substrate of the fifth PMOS tube P5, the substrate of the sixth PMOS tube P6 and the source of the sixth PMOS tube P6 are connected;
[0029] The drain of the fifth PMOS tube P5, the drain of the fourth NMOS tube N4 and the gate of the sixth PMOS tube P6 are connected;
[0030] The source of the fourth NMOS transistor N4 is connected to the drain of the fifth NMOS transistor N5.
[0031] Optionally, the control sub-element includes a fifth NOT gate M7, a sixth NOT gate M8, a seventh NOT gate M9, a second NOR gate M10, a second NAND gate M11, an eighth NOT gate M12, a ninth NOT gate M13 and a tenth NOT gate M14;
[0032] The fifth NOT gate M7 is used to receive a three-state output control signal, the output end of the fifth NOT gate M7 is respectively connected to the input end of the sixth NOT gate M8 and one input end of the second NAND gate M11, and the output end of the sixth NOT gate M8 is connected to one input end of the second NOR gate M10;
[0033] The seventh NOT gate M9 is used to receive the transmission direction control signal, and the output end of the seventh NOT gate M9 is respectively connected to the other input end of the second NAND gate M11 and the other input end of the second NOR gate M10; the output end of the second NAND gate M11 is connected to the input end of the ninth NOT gate M13; the output end of the second NOR gate M10 is connected to the input end of the eighth NOT gate M12;
[0034] The output ends of the ninth NOT gate M13 and the second NAND gate M11 are used to connect to the second level conversion sub-element; the output ends of the second NOR gate M10 and the eighth NOT gate M12 are used to connect to the third level conversion sub-element;
[0035] The tenth NOT gate M14 is located between the third level conversion sub-element and the fourth level conversion sub-element, and is used to control unidirectional transmission between the third level conversion sub-element and the fourth level conversion sub-element.
[0036] The level conversion device provided in the embodiment of the present application adopts a modular design, and 8 groups of bidirectional transmission level conversion units and an enabling control unit are set as a group of eight-channel bidirectional transmission level conversion modules, and four groups of eight-channel bidirectional transmission level conversion modules are connected in parallel to achieve thirty-two-channel bidirectional transmission level conversion. By using eight channels as a group, the transmission efficiency can be guaranteed; by using four groups of the same eight-channel bidirectional transmission level conversion modules, the balance and consistency between the groups are ensured, which is conducive to suppressing the difference in signal delay.
[0037] On this basis, by optimizing the layout of the level conversion device, each group of eight-channel bidirectional transmission level conversion modules is set in a layout area, the level conversion elements transmitting in the same direction are set in the same area, and the distances from the geometric centers of the areas corresponding to the two directions to the enabling control unit are equal, and the distances from the level conversion elements in different directions in the same channel to the enabling control unit are the same. This not only reduces the signal delay difference, but also improves the integration of the overall layout, reducing the overall area compared to the multi-chip parallel method. BRIEF DESCRIPTION OF THE DRAWINGS
[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the background technology, the drawings required for use in the embodiments of the present application or the background technology will be described below.
[0039] Figure 1 A schematic diagram of the layout of a level conversion device provided in an embodiment of the present application is shown;
[0040] Figure 2 A schematic diagram showing an optional layout of an eight-channel bidirectional transmission level conversion module provided in an embodiment of the present application;
[0041] Figure 3 A schematic diagram showing an optional circuit of an eight-channel bidirectional transmission level conversion module provided in an embodiment of the present application;
[0042] FIG. 4( a ) and FIG. 4( b ) are schematic diagrams respectively showing an optional transmission mode of the level conversion element provided in an embodiment of the present application;
[0043] Figure 5 A schematic diagram showing an optional pad layout of an eight-channel bidirectional transmission level conversion module in the level conversion device provided in an embodiment of the present application;
[0044] Figure 6 An optional circuit diagram of a level conversion element transmitting in different directions provided in an embodiment of the present application is shown;
[0045] Figure 7 An optional circuit diagram of an enabling control unit provided in an embodiment of the present application is shown. DETAILED DESCRIPTION
[0046] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing the following embodiments is to make the disclosure of the present application more thorough and comprehensive.
[0047] It should be noted that when a component / unit / module is considered to be "connected" to another component / unit / module, it can be directly connected to the other component / unit / module, or there may be an intermediate component / unit / module at the same time.
[0048] See also Figure 1 As shown in FIG4 , an embodiment of the present application provides a level conversion device. The level conversion device includes four groups of eight-channel bidirectional transmission level conversion modules connected in parallel, which are respectively recorded as the first to fourth groups of eight-channel bidirectional transmission level conversion modules for the convenience of description. Figure 1 As shown, the level conversion device includes four layout areas 100, each of which is provided with a set of eight-channel bidirectional transmission level conversion modules. The four layout areas 100 can be arranged in a 2×2 manner, or the four layout areas 100 can be arranged in sequence along a certain direction, such as Figure 1 In the figure, the four layout areas 100 are arranged in sequence along the longitudinal direction in the figure, that is, in a 1×4 array. Relatively speaking, the layout adopts a 1×4 sequence distribution, which is more conducive to symmetrically distributing the pins corresponding to each group of eight-channel bidirectional transmission level conversion modules on both sides of the layout area 100, so that the routing lengths of each eight-channel bidirectional transmission level conversion module are consistent, thereby reducing the position deviation between each other and reducing the delay difference between modules caused by the routing length difference.
[0049] Each set of eight-channel bidirectional transmission level conversion modules includes an enabling control unit and eight sets of bidirectional transmission level conversion units; wherein each set of bidirectional transmission level conversion units includes a level conversion element transmitting in a first direction and a level conversion element transmitting in a second direction, and the first direction and the second direction are opposite signal transmission directions. Figure 2As shown, each layout area 100 includes a first area 111, a second area 112 and a middle area 120, the first area 111 and the second area 112 are respectively located on both sides of the middle area 120 and are symmetrically arranged relative to the middle area 120; the enabling control unit is arranged in the middle area 120, eight level conversion elements transmitting along the first direction (for example, A1 to B1) are arranged in the first area 111 (the left area in the figure), and eight level conversion elements transmitting along the second direction (for example, B1 to A1) are arranged in the second area 112 (the right area in the figure); the geometric center of the first area 111 and the geometric center of the second area 112 are at the same distance from the middle area 120.
[0050] In each layout area 100, eight level conversion elements transmitting along the first direction are arranged in an array in the first area 111, and eight level conversion elements transmitting along the second direction are also arranged in an array in the second area 112. Figure 2 In the embodiment, eight level conversion elements from An to Bn are arranged in a 2×4 array on the left side of the enabling control unit, and eight level conversion elements from Bn to An are arranged in a 2×4 array on the right side of the enabling control unit, where n is 1 to 8.
[0051] The level conversion elements transmitting in the first direction and the level conversion elements transmitting in the second direction are symmetrically distributed on both sides of the enabling control unit according to the transmission direction, that is, the level conversion elements transmitting in different directions in the same channel (for example, A2 to B2 and B2 to A2, A7 to B7 and B7 to A7) are at the same distance from the enabling control unit. In this way, the routing lengths of the level conversion elements transmitting in different directions in the same channel are equal, thereby reducing the delay difference of signal transmission in different directions of the same channel.
[0052] Furthermore, based on the maximum length of the routing lengths of all channels, the routing lengths of the remaining channels can be increased so that the routing lengths corresponding to each channel are equal, thereby reducing the delay difference between each channel. It should be noted that in this application, the routing length difference is less than or equal to ±5% and can be considered equal.
[0053] like Figure 3 As shown, the enabling control unit is configured to receive a transmission direction control signal and a tri-state output control signal, and generate a transmission control signal based on the received signals to control each of the eight groups of bidirectional transmission level conversion units.
[0054] As mentioned above, each of the eight groups of bidirectional transmission level conversion units includes a level conversion element that transmits along a first direction and a level conversion element that transmits along a second direction, and the first direction and the second direction are opposite signal transmission directions. The level conversion element includes an input stage sub-element, a first level conversion sub-element, and an output stage sub-element that are sequentially connected in series. FIG4(a) shows a schematic diagram of the level conversion element transmitting along the first direction; FIG4(b) shows a schematic diagram of the level conversion element transmitting along the second direction.
[0055] According to the implementation mode of this application, Figure 2 As shown, each group of eight-channel bidirectional transmission level conversion modules also includes a power supply unit, which is arranged in the middle area 120 of the layout area 100 corresponding to each group of eight-channel bidirectional transmission level conversion modules; the power supply unit is configured to supply power to each of the eight groups of bidirectional transmission level conversion units. Exemplarily, the power supply unit is arranged on the symmetry axis of each group of level conversion elements, so that the first transmission unit transmitting in the first direction and the second transmission unit transmitting in the second direction are symmetrically distributed on both sides of the power supply unit.
[0056] Figure 5 FIG. 1 is a schematic diagram showing an optional pad (PAD) layout of a level conversion device provided by the present application. Figure 5 As shown, the pad layout of each group of eight-channel bidirectional transmission level conversion modules adopts a 6×4 array layout. Among them, from right to left, the 1st and 2nd columns are pads corresponding to the level conversion elements that can be transmitted in the second direction (transmitted from port B to port A); the 3rd and 4th columns are pads corresponding to the enable control unit and the power supply unit, and the 5th and 6th columns are pads corresponding to the level conversion elements that can be transmitted in the first direction (transmitted from port A to port B); and the pads corresponding to the two level conversion elements of the same channel are arranged in the same row. Exemplarily, the enable control unit corresponds to the direction control signal pad (DIR) and the three-state output control signal pad (OE). Exemplarily, the power supply unit corresponds to the ground pad (GND) and the power pad (VCCA and VCCB). The power supply unit provided in the present application supplies power to the first direction and the second direction respectively through the VCCA power supply and the VCCB power supply.
[0057] Based on the above layout design and layout, by measuring the total routing length between the modules of each channel, the longest routing length is used as the standard to increase the routing length of the remaining channels, so that the total routing length of each channel is similar, thereby reducing the signal delay difference between the channels.
[0058] Figure 6 An optional circuit diagram of a level conversion element provided in an embodiment of the present application is shown. In the figure, dashed boxes are used to respectively show an input stage sub-element, a level conversion sub-element and an output stage sub-element.
[0059] See also Figure 6 The input stage sub-element includes a first NOT gate M1 and a second NOT gate M2 connected in series; the power supply terminals of the first NOT gate M1 and the second NOT gate M2 are used to connect the input stage voltage Vin. The input terminal of the first NOT gate M1 serves as an input port IN of the input stage sub-element.
[0060] The first level conversion sub-element specifically includes a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a first NMOS transistor N1, a second NMOS transistor N2 and a third NOT gate M3.
[0061] Among them, the source of the first PMOS tube P1, the substrate of the first PMOS tube P1, the substrate of the second PMOS tube P2, the source of the second PMOS tube P2, the source of the third PMOS tube P3, the substrate of the third PMOS tube P3 and the power supply end of the third NOT gate M3 are used to connect the output stage voltage Vout; the gate of the third PMOS tube P3 is used to connect the input stage voltage Vin. The gate of the first PMOS tube P1, the drain of the second PMOS tube P2, the drain of the third PMOS tube P3 and the drain of the second NMOS tube N2 are connected to the input end of the third NOT gate M3. The drain of the first PMOS tube P1, the gate of the second PMOS tube P2 and the drain of the first NMOS tube N1 are connected; the output end of the first NOT gate M1 is connected to the gate of the first NMOS tube N1; the output end of the second NOT gate M2 is connected to the gate of the second NMOS tube N2; the source and substrate of the first NMOS tube N1 and the source and substrate of the second NMOS tube N2 are grounded.
[0062] The output stage sub-element includes a first NAND gate M6, a fourth NOT gate M4, a first NOR gate M5, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a third NMOS transistor N3, a fourth NMOS transistor N4 and a fifth NMOS transistor N5.
[0063] Among them, one input end of the first NAND gate M6 and one input end of the first NOR gate M5 are connected to the output end of the third NOR gate M3; the other input end of the first NAND gate M6, the input end of the fourth NOR gate M4 and the gate of the fifth NMOS tube N5 are connected to the enable control unit; the other input end of the first NOR gate M5 is connected to the output end of the fourth NOR gate M4.
[0064] The power supply terminal of the fourth NOT gate M4, the power supply terminal of the first NOR gate M5, the source of the fourth PMOS tube P4, the gate of the fifth PMOS tube P5, the gate of the fourth NMOS tube N4 and the drain of the sixth PMOS tube P6 are used to connect the output stage voltage Vout. The output terminal of the first NAND gate M6 is connected to the gate of the fourth PMOS tube P4; the drain of the fourth PMOS tube P4, the drain of the third NMOS tube N3, the source of the fifth PMOS tube P5 are connected, and connected to the output port OUT of the output stage sub-element.
[0065] The output end of the first NOR gate M5 is connected to the gate of the third NMOS tube N3; the source of the third NMOS tube N3, the substrate of the third NMOS tube N3, the substrate of the fourth NMOS tube N4, the substrate of the fifth NMOS tube N5 and the source of the fifth NMOS tube N5 are grounded.
[0066] The power supply end of the first NAND gate M6 , the substrate of the fourth PMOS transistor P4 , the substrate of the fifth PMOS transistor P5 , the substrate of the sixth PMOS transistor P6 , and the source of the sixth PMOS transistor P6 are connected.
[0067] The drain of the fifth PMOS transistor P5, the drain of the fourth NMOS transistor N4 and the gate of the sixth PMOS transistor P6 are connected. The source of the fourth NMOS transistor N4 and the drain of the fifth NMOS transistor N5 are connected.
[0068] According to the implementation mode of this application, Figure 7 As shown, the enabling control unit includes a second level conversion sub-element, a third level conversion sub-element, a fourth level conversion sub-element and a control sub-element.
[0069] The control sub-element is configured to receive a transmission direction control signal DIR and a three-state output control signal OE. The control sub-element processes the transmission direction control signal based on the three-state output control signal, and outputs the processed signal to the second level conversion sub-element for level conversion; the second level conversion sub-element is used to output the transmission control signal EN_AB; and the control sub-element also processes the three-state output control signal based on the transmission direction control signal, and outputs the processed signal to the third level conversion sub-element for level conversion; the output signal of the third level conversion sub-element is inverted by the control sub-element and input to the fourth level conversion sub-element, and the fourth level conversion sub-element is used to output the transmission control signal EN_BA after level conversion.
[0070] According to the embodiment of the present application, the circuit structure of the second level conversion sub-element, the third level conversion sub-element, the fourth level conversion sub-element and the first level conversion sub-element may be the same. For example, the second to fourth level conversion sub-element may adopt the following circuit structure: Figure 6 The circuit structure of the first level conversion sub-element shown in FIG. Figure 6Only one exemplary structure of the level conversion sub-element is shown. The first to fourth level conversion sub-elements may also adopt other circuit structures capable of realizing level conversion.
[0071] According to the implementation mode of this application, Figure 7 As shown, the control sub-element includes a fifth NOT gate M7, a sixth NOT gate M8, a seventh NOT gate M9, a second NOR gate M10, a second NAND gate M11, an eighth NOT gate M12, a ninth NOT gate M13 and a tenth NOT gate M14.
[0072] The fifth NOT gate M7 is used to receive the three-state output control signal OE, the output end of the fifth NOT gate M7 is respectively connected to the input end of the sixth NOT gate M8 and one input end of the second NAND gate M11, and the output end of the sixth NOT gate M8 is connected to one input end of the second NOR gate M10. The seventh NOT gate M9 is used to receive the transmission direction control signal DIR, and the output end of the seventh NOT gate M9 is respectively connected to the other input end of the second NAND gate M11 and the other input end of the second NOR gate M10. The output end of the second NAND gate M11 is connected to the input end of the ninth NOT gate M13. The output end of the second NOR gate M10 is connected to the input end of the eighth NOT gate M12.
[0073] The output ends of the ninth NOT gate M13 and the second NAND gate M11 are used to connect the second level conversion sub-element; the second NOR gate M10 and the eighth NOT gate M12 are used to connect the third level conversion sub-element. The tenth NOT gate M14 is located between the third level conversion sub-element and the fourth level conversion sub-element, and is used to control the unidirectional transmission between the third level conversion sub-element and the fourth level conversion sub-element.
[0074] Optionally, the gate of the first NMOS tube N1 in the second level conversion sub-element is used to connect the input end of the ninth NOT gate M13 in the control sub-element; the gate of the second NMOS tube N2 is used to connect the output end of the ninth NOT gate M13 in the control sub-element. Optionally, the gate of the first NMOS tube N1 in the third level conversion sub-element is used to connect the input end of the eighth NOT gate M12 in the control sub-element; the gate of the second NMOS tube N2 is used to connect the output end of the eighth NOT gate M12 in the control sub-element. Optionally, the gate of the first NMOS tube N1 in the fourth level conversion sub-element is used to connect the input end of the tenth NOT gate M14 in the control sub-element; the gate of the second NMOS tube N2 is used to connect the output end of the tenth NOT gate M14 in the control sub-element.
[0075] According to the implementation of the present application, the enabling control unit outputs a transmission control signal EN_AB signal to control the transmission state from port A to port B, and outputs a transmission control signal EN_BA signal to control the transmission state from port B to port A (hereinafter collectively referred to as EN signal). The level conversion element receives the EN_AB / EN_BA signal through the EN port of the output stage sub-element. When the signal received at the EN port is low level, the output of the EN signal after the first NAND gate M6 is fixed to a high level, and the fourth PMOS tube P4 is turned off; the output of the EN signal after the fourth NOT gate M4 and the first NOR gate M5 is fixed to a low level, and the third NMOS tube N3 is turned off; at this time, the output port OUT of the output stage sub-element is in a high impedance state.
[0076] When the EN signal is at a high level, the output of the EN signal after passing through the first NAND gate M6 is controlled by another input signal of the first NAND gate M6; the output of the EN signal after passing through the fourth NAND gate M4 and the first NOR gate M5 is controlled by another input of the first NOR gate M5. The other inputs of the first NAND gate M6 and the first NOR gate M5 are the same signal, and the fourth PMOS transistor P4 and the third NMOS transistor N3 remain in a state where one is turned off and the other is turned on, so that the signal is normally transmitted to the output port OUT of the output stage sub-element.
[0077] Based on the different states of the enable control signal DIR and the three-state output control signal OE, the level conversion element provided in the embodiment of the present application forms three operating modes. Next, a single level conversion element is used as an example for explanation. Assuming that the level conversion element is provided with an A port and a B port, it is possible to transmit a level signal in two directions from the A port to the B port or from the B port to the A port.
[0078] When the three-state output control signal OE is low and the enable control signal DIR is low, the EN_AB signal is low, so that the output port OUT of the corresponding output stage sub-element in the direction from port A to port B is in high impedance state; the EN_BA signal is high, so that the corresponding output stage sub-element in the direction from port B to port A transmits normally. At this time, the B port signal is transmitted to the A port, and the VCCB level signal is converted to the VCCA level signal.
[0079] Specifically, the B port is connected to the input port IN of the input-stage sub-element, and the A port is connected to the output port OUT of the output-stage sub-element. The VCCB power supply supplies power to the first NOT gate M1 and the second NOT gate M2 of the input-stage sub-element, and the VCCA power supply supplies power to the first level conversion sub-element and the output-stage sub-element. The signal of the B port enters the input-stage sub-element from the input port IN, then enters the first level conversion sub-element, is converted into a signal output powered by VCCA, then enters the output-stage sub-element, and is finally transmitted from the output port OUT of the output-stage sub-element to the A port as a VCCA level signal.
[0080] When the three-state output control signal OE is low and the enable control signal DIR is high, the EN_BA signal is low, so that the output port OUT of the corresponding output stage sub-element in the direction from port B to port A is in high impedance state; the EN_AB signal is high, so that the corresponding output stage sub-element in the direction from port A to port B outputs normally. At this time, the signal of port A is transmitted to port B, and the VCCA level signal is converted to the VCCB level signal.
[0081] Specifically, the A port is connected to the input port IN of the input-stage sub-element, and the B port is connected to the output port OUT of the output-stage sub-element. VCCA supplies power to the first NOT gate M1 and the second NOT gate M2 of the input-stage sub-element, and the VCCB power supply supplies power to the first level conversion sub-element and the output-stage sub-element. The signal of the A port enters the input-stage sub-element from the input port IN, then enters the first level conversion sub-element, is converted into a signal output powered by VCCB, then enters the output-stage sub-element, and is finally transmitted from the output port OUT of the output-stage sub-element to the B port as a VCCB level signal.
[0082] When the three-state output control signal OE is at a high level, no matter the enable control signal DIR is at a low level or a high level, the EN_BA signal and the EN_AB signal are both at a low level, so that the output ports OUT of the corresponding output stage sub-elements in the direction from port A to port B and from port A to port B are both in a high impedance state. At this time, both port A and port B are in a high impedance state, and no signal is transmitted in the level conversion element.
[0083] See also Figure 6 In the level conversion element provided in the embodiment of the present application, there is no diode or diode-connected MOS tube structure between the input port IN of the input-level sub-element and the power supply of the input-level sub-element. When the input voltage at the input port IN is higher than the power supply voltage Vin of the input-level sub-element (i.e., the input-level voltage), there will be no impact on the power supply voltage Vin, thereby realizing the input port anti-power-injection function.
[0084] See also Figure 6In the level conversion element provided in the embodiment of the present application, the fifth PMOS tube P5, the sixth PMOS tube P6, the fourth NMOS tube N4 and the fifth NMOS tube N5 of the output-stage sub-element form an independent substrate circuit, form an independent substrate potential, and supply power to the substrates of the first NAND gate M6 and the fourth PMOS tube P4. The source of the fourth PMOS tube P4 is connected to the power supply voltage Vout (i.e., the output stage voltage) of the output-stage sub-element, the substrate is connected to the independent substrate potential, and the drain is connected to the output terminal OUT of the output-stage sub-element, forming a hedge diode of Vout-independent substrate potential-OUT. In this way, when the output port OUT of the output-stage sub-element is externally connected to a voltage higher than the output-stage voltage Vout, the output-stage voltage Vout will not be impacted, thereby realizing the output port anti-power injection function.
[0085] According to the implementation method of this application, see Figure 6 and Figure 7 There is no direct path between the input port IN, the output port OUT, the input stage voltage Vin and the output stage voltage Vout. Therefore, when the VCCA power supply and the VCCB power supply are powered off at the same time, the external voltages of the input port IN and the output port OUT cannot impact the input stage voltage Vin and the output stage voltage Vout, thereby realizing the cold backup function.
[0086] According to the implementation method of this application, see Figure 6 and Figure 7 , when the VCCA power supply is powered and the VCCB power supply is powered off, from the A port to the B port, the input stage voltage Vin is VCCA, the output stage voltage Vout is VCCB, the output stage voltage Vout is not powered, the output stage sub-element does not work, and no matter what voltage is connected to the output port OUT, it will not have an impact on the output stage voltage Vout. From the B port to the A port, the input stage voltage Vin is VCCB, the output stage voltage Vout is VCCA, the input stage voltage Vin is not powered, the input stage sub-element does not work, and the third PMOS tube P3 in the fourth level conversion sub-element downstream of the tenth NOT gate M14 of the enable control unit is turned on, and VCCA is transmitted to the input end of the third NOT gate M3. After being inverted by the third NOT gate M3, the output transmission control signal EN_BA is low level, so that the output stage sub-element from the B port to the A port is in a high impedance state. At the same time, due to the independent substrate circuit in the output stage sub-element, no matter what voltage is connected to the output port OUT, it will not have an impact on Vout. Therefore, the hot backup of the VCCB single-side power failure is realized.
[0087] According to the implementation mode of the present application, when the VCCB power supply is powered and the VCCA power supply is powered off, from the B port to the A port, the input stage voltage Vin is VCCB, the output stage voltage Vout is VCCA, the output stage voltage Vout is not powered, the output stage sub-element does not work, and no matter what voltage is externally connected to the output port OUT, there will be no impact on the output stage voltage Vout. From the A port to the B port, the input stage voltage Vin is VCCA, the output stage voltage Vout is VCCB, the input stage voltage Vin is not powered, the input stage sub-element does not work, and the third PMOS tube P3 in the second level conversion sub-element downstream of the ninth NOT gate M13 of the enable control unit is turned on, and VCCA is transmitted to the input end of the third NOT gate M3. After the third NOT gate M3 is inverted, the output side transmission control signal EN_AB is low level, so that the output stage sub-element from the A port to the B port is in a high impedance state. At the same time, due to the independent substrate circuit in the output stage sub-element, no matter what voltage is externally connected to the output port OUT, there will be no impact on the output stage voltage Vout. Therefore, the hot backup of the VCCA single-side power failure is realized.
[0088] It is not difficult to see that when any power supply of the VCCA power supply and the VCCB power supply is powered off, the bidirectional transmission level conversion unit provided in the embodiment of the present application will not have an impact on the input stage voltage Vin and the output stage voltage Vout, no matter what voltage is externally connected to the input port IN and the output port OUT, thereby achieving hot backup.
[0089] According to the implementation mode of the present application, the level conversion device adopts a modular design, in which the circuit of each level conversion element in the 32 groups of bidirectional transmission level conversion units is exactly the same from the input level sub-element to the output level sub-element, thereby ensuring the circuit consistency between each channel and eliminating design errors.
[0090] According to the implementation of the present application, the level conversion device further includes a metal wiring layer, which is used to lead the port of the logic circuit to the corresponding pad (PAD). It is not difficult to understand that the PAD layout can be reasonably adjusted according to different packaging processes. For example, Figure 5 The PAD layout shown in is suitable for the ball implantation process. For another example, 24 pads can be arranged around the periphery of the layout module, or 48 pads can be arranged on both sides of the periphery of the layout.
[0091] In summary, the level conversion device provided in the embodiment of the present application adopts a modular design, and sets 8 groups of bidirectional transmission level conversion units and an enabling control unit as a group of eight-channel bidirectional transmission level conversion modules, and realizes thirty-two-channel bidirectional transmission level conversion through four groups of eight-channel bidirectional transmission level conversion modules in parallel. In addition, eight channels are used as a group to ensure transmission efficiency; four groups of the same eight-channel bidirectional transmission level conversion modules are used to ensure the balance and consistency between the groups, which is conducive to suppressing the difference in signal delay.
[0092] On this basis, by reasonably designing the layout of the level conversion device and adopting a modular layout, each group of eight-channel bidirectional transmission level conversion modules is located in a layout area, and the level conversion elements used for transmission in the same direction in each group of eight-channel bidirectional transmission level conversion modules are arranged in the same area, and the enable control unit is arranged in the middle position of the layout area. This can not only make the overall layout more regular and compact, realize the miniaturization of the chip, but also help to reduce the difference in signal delay.
[0093] Moreover, as mentioned above, since the level conversion device provided in the present application adopts a modular layout, users can connect the transmission direction control ports and the output three-state control ports of each group in parallel according to their needs to realize a 32-channel bidirectional transmission level conversion function, or realize 4 independent 8-channel bidirectional transmission level conversion functions, one group of 8-channel bidirectional transmission level conversion functions plus one group of 24-channel bidirectional transmission level conversion functions or two groups of 16-channel bidirectional transmission level conversion functions, etc., and therefore has a very broad application prospect.
[0094] Furthermore, by controlling the distances from the level conversion elements in different directions in the same channel to the enabling control unit to be equal, the wiring lengths of the level conversion elements in the same channel are equal, so as to further reduce the difference in signal delay. By adopting the circuit structure of the specially designed level conversion element, anti-power-injection, cold backup and hot backup are realized, and the stability, safety and reliability of the level conversion device are improved.
[0095] The above is only a specific implementation of the embodiment of the present application, but the protection scope of the embodiment of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the embodiment of the present application, which should be included in the protection scope of the embodiment of the present application. Therefore, the protection scope of the embodiment of the present application shall be based on the protection scope of the claims.
Claims
1. A level conversion device, characterized in that: The invention comprises four groups of eight-channel bidirectional transmission level conversion modules connected in parallel, wherein the eight-channel bidirectional transmission level conversion modules include an enabling control unit and eight groups of bidirectional transmission level conversion units, wherein the enabling control unit is configured to receive a transmission direction control signal and a three-state output control signal, and generate a transmission control signal based on the received transmission direction control signal and the three-state output control signal to control each group of the eight groups of bidirectional transmission level conversion units; Each group of bidirectional transmission level conversion units includes a level conversion element transmitting in a first direction and a level conversion element transmitting in a second direction, wherein the first direction and the second direction are opposite signal transmission directions; the level conversion element includes an input-level sub-element, a first level conversion sub-element and an output-level sub-element connected in series in sequence; Each group of eight-channel bidirectional transmission level conversion modules is arranged in a layout area, and each layout area includes a first area, a second area and a middle area, wherein the first area and the second area are located on both sides of the middle area and are symmetrically arranged; in each group of eight-channel bidirectional transmission level conversion modules, the enabling control unit is arranged in the middle area, the level conversion element transmitting along the first direction is arranged in the first area, and the level conversion element transmitting along the second direction is arranged in the second area, and the level conversion elements transmitting along different directions in the same channel are at the same distance from the enabling control unit.
2. The level conversion device according to claim 1, characterized in that: The four layout areas are arranged in a 2×2 or 1×4 manner.
3. The level conversion device according to claim 1, characterized in that: In the same layout area, the level conversion elements transmitting along the first direction are arranged in an array in the first area, and the level conversion elements transmitting along the second direction are arranged in an array in the second area.
4. The level conversion device according to claim 1 or 3, characterized in that: The wiring length from the enabling control unit to the level conversion element of each group of eight-channel bidirectional transmission level conversion modules is the same; In the eight groups of bidirectional transmission level conversion units, the wiring lengths between the level conversion elements in each group of bidirectional transmission level conversion units are the same.
5. The level conversion device according to any one of claims 1 to 4, characterized in that: The eight-channel bidirectional transmission level conversion module further includes a power supply unit, which is disposed in the middle area; the power supply unit is configured to supply power to each of the eight groups of bidirectional transmission level conversion units.
6. The level conversion device according to claim 1, characterized in that: The enabling control unit includes a second level conversion sub-element, a third level conversion sub-element, a fourth level conversion sub-element and a control sub-element; Among them, the control sub-element is configured to receive a transmission direction control signal and a three-state output control signal, and is used to process the transmission direction control signal based on the three-state output control signal, and output the processed transmission direction control signal to the second level conversion sub-element for level conversion, and the second level conversion sub-element is used to output the transmission control signal EN_AB after level conversion; the control sub-element is also used to process the three-state output control signal based on the transmission direction control signal, and output the processed three-state output control signal to the third level conversion sub-element for level conversion; the output of the third level conversion sub-element is inverted by the control sub-element and input into the fourth level conversion sub-element for level conversion, and the fourth level conversion sub-element is used to output the transmission control signal EN_BA after level conversion.
7. The level conversion device according to any one of claims 1 to 6, characterized in that: The input stage sub-element comprises a first NOT gate M1 and a second NOT gate M2 connected in series; power supply terminals of the first NOT gate M1 and the second NOT gate M2 are used to connect to an input stage voltage Vin.
8. The level conversion device according to claim 7, characterized in that: The first level conversion sub-element, the second level conversion sub-element, the third level conversion sub-element or the fourth level sub-element comprises a first PMOS tube P1, a second PMOS tube P2, a third PMOS tube P3, a first NMOS tube N1, a second NMOS tube N2 and a third NOT gate M3; wherein: The source of the first PMOS tube P1, the substrate of the first PMOS tube P1, the substrate of the second PMOS tube P2, the source of the second PMOS tube P2, the source of the third PMOS tube P3, the substrate of the third PMOS tube P3 and the power supply end of the third NOT gate M3 are used to connect the output stage voltage Vout; the gate of the third PMOS tube is used to connect the input stage voltage Vin; The gate of the first PMOS transistor P1, the drain of the second PMOS transistor P2, the drain P3 of the third PMOS transistor and the drain of the second NMOS transistor N2 are connected to the input end of the third NOT gate M3; The drain of the first PMOS transistor P1, the gate of the second PMOS transistor P2 and the drain of the first NMOS transistor N1 are connected; The output end of the first NOT gate M1 is connected to the gate of the first NMOS transistor N1; The output end of the second NOT gate M2 is connected to the gate of the second NMOS transistor N2; The source and substrate of the first NMOS transistor N1 and the source and substrate of the second NMOS transistor N2 are grounded.
9. The level conversion device according to any one of claims 1 to 6, characterized in that: The output stage sub-element includes a first NAND gate M6, a fourth NOT gate M4, a first NOR gate M5, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a third NMOS transistor N3, a fourth NMOS transistor N4 and a fifth NMOS transistor N5; Among them, one input end of the first NAND gate M6 and one input end of the first NOR gate M5 are connected to the output end of the third NOR gate M3; another input end of the first NAND gate M6, the input end of the fourth NOR gate M4 and the gate of the fifth NMOS transistor N5 are connected to the enabling control unit; another input end of the first NOR gate M5 is connected to the output end of the fourth NOR gate M4; The power supply terminal of the fourth NOT gate M4, the power supply terminal of the first NOR gate M5, the source of the fourth PMOS transistor P4, the gate of the fifth PMOS transistor P5, the gate of the fourth NMOS transistor N4 and the drain of the sixth PMOS transistor P6 are used to connect the output stage voltage Vout; The output end of the first NAND gate M6 is connected to the gate of the fourth PMOS transistor P4; the drain of the fourth PMOS transistor P4, the drain of the third NMOS transistor N3, the source of the fifth PMOS transistor P5 are connected, and connected to the output port of the output stage sub-element; The output end of the first NOR gate M5 is connected to the gate of the third NMOS transistor N3; the source of the third NMOS transistor N3, the substrate of the third NMOS transistor N3, the substrate of the fourth NMOS transistor N4, the substrate of the fifth NMOS transistor N5 and the source of the fifth NMOS transistor N5 are grounded; The power supply end of the first NAND gate M6, the substrate of the fourth PMOS tube P4, the substrate of the fifth PMOS tube P5, the substrate of the sixth PMOS tube P6 and the source of the sixth PMOS tube P6 are connected; The drain of the fifth PMOS tube P5, the drain of the fourth NMOS tube N4 and the gate of the sixth PMOS tube P6 are connected; The source of the fourth NMOS transistor N4 is connected to the drain of the fifth NMOS transistor N5.
10. The level conversion module according to any one of claims 1 to 6, characterized in that: The control sub-element includes a fifth NOT gate M7, a sixth NOT gate M8, a seventh NOT gate M9, a second NOR gate M10, a second NAND gate M11, an eighth NOT gate M12, a ninth NOT gate M13 and a tenth NOT gate M14; The fifth NOT gate M7 is used to receive a three-state output control signal, the output end of the fifth NOT gate M7 is respectively connected to the input end of the sixth NOT gate M8 and one input end of the second NAND gate M11, and the output end of the sixth NOT gate M8 is connected to one input end of the second NOR gate M10; The seventh NOT gate M9 is used to receive the transmission direction control signal, and the output end of the seventh NOT gate M9 is respectively connected to the other input end of the second NAND gate M11 and the other input end of the second NOR gate M10; the output end of the second NAND gate M11 is connected to the input end of the ninth NOT gate M13; the output end of the second NOR gate M10 is connected to the input end of the eighth NOT gate M12; The output ends of the ninth NOT gate M13 and the second NAND gate M11 are used to connect to the second level conversion sub-element; the output ends of the second NOR gate M10 and the eighth NOT gate M12 are used to connect to the third level conversion sub-element; The tenth NOT gate M14 is located between the third level conversion sub-element and the fourth level conversion sub-element, and is used to control unidirectional transmission between the third level conversion sub-element and the fourth level conversion sub-element.