Mining differential signal intrinsic safety isolation data processing system and method

Abstract

The invention belongs to the technical field of electronic and electrical engineering, and discloses a mining differential signal intrinsic safety isolation data processing system which comprises a power supply circuit unit, a photoelectric isolation unit, a communication interface unit and a CPU data processing unit. The system adopts a double-isolation power supply design, so that physical isolation of intrinsic safety and non-intrinsic safety sides is ensured, the safety and reliability of the circuit are improved, physical isolation and differential transmission of data signals are realized through the photoelectric isolation unit and the differential signal conversion circuit, energy transmission and interference are effectively prevented, the circuit is protected from being damaged, and the reliability of the circuit is improved. Secondly, the CPU data processing unit can efficiently execute logical operation and data processing tasks, data receiving and transmitting and seamless communication with external equipment are achieved by controlling the optoelectronic isolation and communication interface unit, and finally, a CPU operation indicating circuit and a program downloading and debugging interface are further designed in the system.

Description

Technical Field

[0001] The invention belongs to the technical field of electronic and electrical engineering, and specifically relates to a mine-used differential signal intrinsically safe isolation data processing system and method. Background Art

[0002] At present, the remote control pilot circuits of mining explosion-proof electrical equipment generally rely on relay components, which are inductive loads. When the wire length requirement of the remote control button is large, the relay components may not move or jitter, which will affect the normal start and stop of the equipment. To solve this problem, although isolation with isolation barriers is effective, it is expensive and cannot achieve differential signal data isolation. The use of coil transmitter isolation requires additional voltage and current limiting circuits, otherwise it is difficult to meet the intrinsic safety design requirements. These problems not only increase the complexity of the equipment, but also increase the maintenance cost, and more economical and effective solutions are urgently needed. Summary of the invention

[0003] The object of the present invention is to provide a mining differential signal intrinsically safe isolation data processing system and method to solve the problems raised in the above background technology.

[0004] In order to achieve the above object, the present invention provides the following technical solutions: a mine-used differential signal intrinsically safe isolation data processing system, the system comprising a power supply circuit unit, a photoelectric isolation unit, a communication interface unit and a CPU data processing unit; The power circuit unit provides two types of output power, intrinsically safe and non-intrinsically safe, with overvoltage, overcurrent and short-circuit protection, and can suppress common-mode voltage; the photoelectric isolation unit uses a photoelectric isolation chip to achieve physical isolation of data signals on the intrinsically safe side and the non-intrinsically safe side, ensuring that energy is not transferred and that the signals on both sides are not grounded; the communication interface unit converts logic signals into differential signals and communicates with external devices through 485 and CAN bus chips; the CPU data processing unit is responsible for data processing, and controls the photoelectric isolation and communication interface units to achieve data transmission and reception.

[0005] Preferably, the specific steps of the data processing method are as follows: S1: Power supply circuit unit design: dual isolated power supply, physical isolation between intrinsically safe and non-intrinsically safe sides, all designed according to intrinsically safe standards, AC127V to DC5V / 3.3V power supply; S2: Design of differential bus photoelectric isolation circuit: Use the optical coupler TLP521 and ACSL-6420 to isolate intrinsically safe and non-intrinsically safe signals, design 485 / CAN differential circuit, and protect against interference; S3: 485 bus data reception: CPU sets 485TR1 low level, 485 chip receives, A / B differential is converted to logic level, and is isolated and transmitted to CPU through optocoupler U4; S4: 485 bus data transmission: CPU sets 485TR1 high level, 485 chip sends, data is isolated by optocoupler U4, and differential signal is output; S5: CAN bus data transmission and reception: CAN bus data transmission and reception is automatically controlled by SIT65HVD235DR, and the signal is isolated from the intrinsically safe side and the non-intrinsically safe side through the photoelectric isolator; S6: CPU data processing: STC8H8K64U processes data, controls optoelectronic isolation and communication interface, clock, reset, and filter to ensure stable operation; S7: System indication and debugging: Design CPU operation indication circuit, LED status display, and program download debugging interface to facilitate system debugging and maintenance.

[0006] Preferably, the specific steps of designing the power circuit unit in S1 are as follows: Step 1: Power supply isolation and input: First, use two completely isolated power supplies, one for the intrinsically safe side and the other for the non-intrinsically safe side; Step 2: Input voltage processing: Take AC127V as input voltage, first pass through the protection circuit for overcurrent and overvoltage protection, and then filter out clutter and interference through the filter; Step 3: Voltage conversion and output: The processed AC voltage will be converted into DC 5V and 3.3V. The two DC voltages are specifically used to power the intrinsically safe circuit. During the conversion process, it is necessary to ensure that the output voltage is stable and meets the intrinsically safe circuit design standards to improve the reliability and safety of the entire circuit.

[0007] Preferably, the specific steps of designing the differential bus photoelectric isolation circuit in S2 are as follows: Step 1: Photoelectric signal isolation: Use the optocoupler TLP521 and the high-speed logic optocoupler ACSL-6420-00TE to photoelectrically isolate the data signals on the intrinsically safe side from those on the non-intrinsically safe side, ensuring that the circuits on both sides are physically completely disconnected, thereby preventing energy transfer and interference; Step 2: Differential signal conversion circuit design: Design a differential signal conversion circuit for the 485 bus and CAN bus. This circuit converts the logic signal into a differential signal and transmits it to external devices through the bus. At the same time, the common-mode filter and surge voltage ESD device in the circuit can effectively suppress common-mode interference and surge voltage, protecting the circuit from interference and damage. Step 3: Circuit testing and optimization: After completing the design of the optoelectronic signal isolation and differential signal conversion circuit, conduct circuit testing; verify through testing whether the function and performance of the circuit meet the design requirements. If problems or deficiencies are found, make necessary optimizations and improvements to ensure the reliability and stability of the circuit.

[0008] Preferably, the 485 bus data reception in S3 means that when the CPU control signal 485TR1 is set to a low level, the 485 communication chip immediately enters the receiving state. At this time, the chip monitors the differential signals on buses A and B, and converts them into corresponding logic levels based on the level relationship between the two signals to ensure signal isolation and transmission safety. The converted logic levels will be isolated by the optocoupler U4 and then sent to the CPU for processing.

[0009] Preferably, the 485 bus data transmission in S4 means that when the CPU control signal 485TR1 is set to a high level, the 485 communication chip will immediately enter the sending state. At this time, the data that the CPU is ready to send will first be isolated by the optocoupler U4 to ensure the data transmission security and circuit stability. The isolated data will be received by the 485 chip, and according to the logical state of the data, the chip will output the corresponding differential signal to the bus.

[0010] Preferably, the specific steps of CAN bus data transmission and reception in S5 are as follows: Step 1: Automatic control of data direction: The data receiving and sending process of the CAN bus is automatically controlled by the chip SIT65HVD235DR, without the need for external CPU intervention, which simplifies the circuit design; Step 2: Photoelectric isolation of data signals: In order to ensure electrical isolation between the intrinsically safe side and the non-intrinsically safe side, the CAN bus signal will be isolated and transmitted through a photoelectric isolator to prevent energy transfer and interference; Step 3: Data transmission and reception execution: When sending data, the SIT65HVD235DR chip will automatically convert the data output by the CPU into CAN differential signals and send them to the bus; when receiving data, the chip will monitor the differential signals on the bus, convert them into logic levels, and send them to the CPU for processing.

[0011] Preferably, the specific steps of the CPU data processing in S6 are as follows: Step 1: Logical operations and data processing: STC8H8K64U, as the core processor, is responsible for performing logical operations and data processing tasks, receiving data from input devices or communication interfaces, performing necessary calculations and processing, and then outputting the results to output devices or communication interfaces; Step 2: Control photoelectric isolation and communication interface: STC8H8K64U realizes electrical isolation between the intrinsically safe side and the non-intrinsically safe side by controlling the photoelectric isolation circuit unit to ensure the security of data transmission. At the same time, it also controls the communication interface unit to realize the data receiving and sending function and exchange data with external devices. Step 3: Ensure stable operation: To ensure the stable operation of the STC8H8K64U, the system is equipped with a clock circuit to provide an accurate clock signal, a reset circuit to restart the CPU when necessary, and a power filter capacitor to smooth the power supply voltage and reduce the impact of voltage fluctuations on the CPU.

[0012] Preferably, the system indication and debugging in S7 refers to real-time monitoring of the operating status of the CPU. A CPU operation indication circuit is designed, which intuitively displays whether the CPU is in a normal working state by turning on and off an LED indicator light. In addition, in order to facilitate the debugging and maintenance of the system, a CPU program download and debugging interface is specially provided. Through this interface, users can easily download the program to the CPU and perform real-time debugging and modification, which greatly improves the maintainability and flexibility of the system.

[0013] The beneficial effects of the present invention are as follows: The present invention ensures the physical isolation of the intrinsically safe and non-intrinsically safe sides by adopting a dual-isolation power supply design, thereby improving the safety and reliability of the circuit. The physical isolation and differential transmission of data signals are achieved through the photoelectric isolation unit and the differential signal conversion circuit, effectively preventing energy transfer and interference, and protecting the circuit from damage. Secondly, the CPU data processing unit can efficiently perform logical operations and data processing tasks, and realize data transmission and reception by controlling the photoelectric isolation and communication interface unit, and communicate seamlessly with external devices. Finally, the system is also designed with a CPU operation indication circuit and a program download and debugging interface, which is convenient for users to monitor the CPU status in real time and perform system debugging and maintenance, greatly improving the maintainability and flexibility of the system. These advantages enable the system to perform well in complex environments such as mining, meeting the requirements of high safety and high reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a system structure diagram of the present invention; Figure 2 This is the principle diagram of the intrinsically safe power supply circuit of the present invention; Figure 3 This is a differential bus photoelectric isolation circuit diagram of the present invention; Figure 4 The circuit diagram of the CPU data processing unit of the present invention; Figure 5 It is a flow chart of the program of the present invention. DETAILED DESCRIPTION

[0015] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0016] like Figures 1 to 5 As shown, an embodiment of the present invention provides a differential signal intrinsically safe isolation data processing system for mining, which includes a power supply circuit unit, a photoelectric isolation unit, a communication interface unit and a CPU data processing unit.

[0017] The power circuit unit provides two types of output power, intrinsically safe and non-intrinsically safe, with overvoltage, overcurrent and short-circuit protection, and can suppress common-mode voltage; the photoelectric isolation unit uses a photoelectric isolation chip to achieve physical isolation of data signals on the intrinsically safe side and the non-intrinsically safe side, ensuring that energy is not transferred and that the signals on both sides are not grounded; the communication interface unit converts logic signals into differential signals and communicates with external devices through 485 and CAN bus chips; the CPU data processing unit is responsible for data processing, and controls the photoelectric isolation and communication interface units to achieve data transmission and reception.

[0018] The specific steps of the processing method are as follows: S1: Power supply circuit unit design: dual isolated power supply, physical isolation between intrinsically safe and non-intrinsically safe sides, all designed according to intrinsically safe standards, AC127V to DC5V / 3.3V power supply; S2: Design of differential bus photoelectric isolation circuit: Use optocoupler TLP521 and ACSL-6420 to isolate intrinsically safe and non-intrinsically safe signals, design 485 / CAN differential circuit, and protect against interference.

[0019] S3: 485 bus data reception: CPU sets 485TR1 low level, 485 chip receives, A / B differential is converted to logic level, and is isolated and transmitted to CPU through optocoupler U4; S4: 485 bus data transmission: CPU sets 485TR1 high level, 485 chip sends, data is isolated by optocoupler U4, and differential signal is output; S5: CAN bus data transmission and reception: CAN bus data transmission and reception is automatically controlled by SIT65HVD235DR, and the signal is isolated from the intrinsically safe side and the non-intrinsically safe side through the photoelectric isolator; S6: CPU data processing: STC8H8K64U processes data, controls optoelectronic isolation and communication interface, clock, reset, and filter to ensure stable operation; S7: System indication and debugging: Design CPU operation indication circuit, LED status display, and program download debugging interface to facilitate system debugging and maintenance.

[0020] The specific steps of designing the power circuit unit in S1 are as follows: Step 1: Power supply isolation and input: First, use two completely isolated power supplies, one for the intrinsically safe side and the other for the non-intrinsically safe side; ensure that the DC sides of the two are completely physically isolated to improve the safety and reliability of the circuit; Step 2: Input voltage processing: Take AC127V as input voltage, first pass it through the protection circuit for overcurrent, overvoltage and other protection processing, then filter out clutter and interference through the filter to ensure voltage stability; Step 3: Voltage conversion and output: The processed AC voltage will be converted into DC 5V and 3.3V. These two DC voltages are specifically used to power the intrinsically safe circuit. During the conversion process, it is necessary to ensure that the output voltage is stable and meets the intrinsically safe circuit design standards to improve the reliability and safety of the entire circuit.

[0021] The dual-circuit isolated power supply ensures the safe isolation between the intrinsically safe and non-intrinsically safe sides; the input voltage undergoes multiple protection processes to filter out interference and ensure stability; the voltage conversion output is stable DC, which meets the intrinsically safe standards and improves the circuit reliability. This design not only enhances the safety of the circuit, but also ensures the stability and reliability of the voltage, provides efficient and stable power support for the entire system, and improves the overall performance and stability of the system.

[0022] The specific steps of designing the differential bus photoelectric isolation circuit in S2 are as follows: Step 1: Photoelectric signal isolation: Use the optocoupler TLP521 and the high-speed logic optocoupler ACSL-6420-00TE to photoelectrically isolate the data signals on the intrinsically safe side from those on the non-intrinsically safe side, ensuring that the circuits on both sides are physically completely disconnected, thereby preventing energy transfer and interference; Step 2: Differential signal conversion circuit design: Design a differential signal conversion circuit for the 485 bus and CAN bus. This circuit converts the logic signal into a differential signal and transmits it to external devices through the bus. At the same time, the common-mode filter and surge voltage ESD device in the circuit can effectively suppress common-mode interference and surge voltage, protecting the circuit from interference and damage. Step 3: Circuit testing and optimization: After completing the design of the optoelectronic signal isolation and differential signal conversion circuit, conduct circuit testing. Through testing, verify whether the function and performance of the circuit meet the design requirements. If problems or deficiencies are found, make necessary optimizations and improvements to ensure the reliability and stability of the circuit.

[0023] Optocouplers and high-speed logic optocouplers are used to achieve signal isolation to ensure circuit safety; differential signal conversion circuits effectively suppress interference and protect circuit stability; circuit testing and optimization steps ensure design reliability and stability. This design not only improves the security and efficiency of data transmission, but also strengthens the circuit's anti-interference ability, providing users with a more reliable and efficient differential bus communication solution to meet the needs of various complex application scenarios.

[0024] Among them, the bus data reception of 485 in S3 means that when the control signal 485TR1 of the CPU is set to a low level, the 485 communication chip immediately enters the receiving state. At this time, the chip will monitor the differential signal on the bus A and B, and convert it into the corresponding logic level according to the level relationship between the two signals to ensure the isolation and transmission safety of the signal. The converted logic level will be isolated by the optocoupler U4 and then sent to the CPU for processing. This process ensures the accurate transmission of data and the safe isolation of the circuit.

[0025] The control signal triggers the 485 chip to enter the receiving state immediately and respond quickly; differential signal monitoring and logic level conversion ensure data accuracy; optocoupler U4 isolates and protects the circuit stability and enhances safety. This process not only improves the efficiency and accuracy of data reception, but also strengthens the isolation and stability of the system, providing users with a more reliable and efficient 485 bus data reception solution.

[0026] Among them, when the CPU control signal 485TR1 is set to a high level during the 485 bus data transmission in S4, the 485 communication chip will immediately enter the sending state. At this time, the data that the CPU is about to send will first be isolated by the optocoupler U4 to ensure the data transmission security and circuit stability. The isolated data will be received by the 485 chip, and according to the logical state of the data, the chip will output the corresponding differential signal to the bus. This process ensures the accurate transmission of data and the effective isolation of the circuit.

[0027] When the CPU control signal is triggered, the 485 chip quickly enters the sending state to ensure timely response; the data is isolated by the optocoupler U4, which not only protects the circuit stability but also enhances the security of data transmission; the 485 chip outputs differential signals according to the data logic to achieve accurate transmission. This process not only improves the accuracy of data transmission, but also strengthens the stability and security of the system, providing users with a more reliable and efficient 485 bus communication solution.

[0028] The specific steps of CAN bus data transmission and reception in S5 are as follows: Step 1: Automatic control of data direction: The data receiving and sending process of the CAN bus is automatically controlled by the chip SIT65HVD235DR, without the need for external CPU intervention, which simplifies the circuit design; Step 2: Photoelectric isolation of data signals: In order to ensure electrical isolation between the intrinsically safe side and the non-intrinsically safe side, the CAN bus signal will be isolated and transmitted through a photoelectric isolator to prevent energy transfer and interference; Step 3: Data transmission and reception execution: When sending data, the SIT65HVD235DR chip will automatically convert the data output by the CPU into CAN differential signals and send them to the bus; when receiving data, the chip will monitor the differential signals on the bus, convert them into logic levels, and send them to the CPU for processing.

[0029] The chip SIT65HVD235DR automatically controls the data direction, simplifying the circuit design; the photoelectric isolator ensures the electrical isolation between the intrinsically safe and non-intrinsically safe sides, improving the system safety; the chip automatically converts the data format to achieve efficient and accurate transmission and reception. These features not only improve the reliability and efficiency of data transmission, but also reduce the complexity of system design, bringing users a more stable, safe and efficient CAN bus communication experience.

[0030] Among them, the CPU data processing in S6: Step 1: Logical operations and data processing: STC8H8K64U, as the core processor, is responsible for performing logical operations and data processing tasks, receiving data from input devices or communication interfaces, performing necessary calculations and processing, and then outputting the results to output devices or communication interfaces; Step 2: Control photoelectric isolation and communication interface: STC8H8K64U realizes electrical isolation between the intrinsically safe side and the non-intrinsically safe side by controlling the photoelectric isolation circuit unit to ensure the security of data transmission. At the same time, it also controls the communication interface unit (such as CAN bus, 485 bus) to realize the data receiving and sending function and exchange data with external devices; Step 3: Ensure stable operation: To ensure the stable operation of STC8H8K64U, the system is equipped with a clock circuit to provide accurate clock signals, a reset circuit to restart the CPU when necessary, and a power filter capacitor to smooth the power supply voltage and reduce the impact of voltage fluctuations on the CPU. Together, these auxiliary circuits ensure that the CPU can reliably perform data processing and communication tasks.

[0031] With STC8H8K64U as the core, it can efficiently perform logic operations and data processing to ensure accurate data flow; through optoelectronic isolation and communication interface control, it can achieve safe data transmission and seamless interaction between devices; auxiliary circuits such as clock, reset and power supply filtering can further ensure the stable operation of the CPU, improve the overall reliability of the system and data processing efficiency, and provide users with a more stable and efficient data processing solution.

[0032] Among them, the system indication and debugging in S7 refers to real-time monitoring of the operating status of the CPU. A CPU operation indication circuit is designed, which intuitively displays whether the CPU is in normal working condition by turning on and off the LED indicator. In addition, in order to facilitate the debugging and maintenance of the system, a CPU program download and debugging interface is specially provided. Through this interface, users can easily download the program to the CPU and perform real-time debugging and modification, which greatly improves the maintainability and flexibility of the system.

[0033] The LED indicator light intuitively displays the CPU working status, making it easy to find abnormalities immediately; at the same time, the integrated CPU program download and debugging interface simplifies the program deployment and debugging process, and improves the system maintenance efficiency and flexibility. These designs not only enhance the reliability of the system, but also significantly reduce maintenance costs, bringing users a more convenient and efficient system experience.

[0034] Figure 2 The circuit on the upper side of the dotted line shown: the power supply terminal is connected to the AC127V input, passes through the F1 overcurrent protection fuse, the overvoltage protector varistor R26, the safety filter capacitor C4, and the common mode filter UM1, eliminates the common mode interference signal of the power supply, enters the 1st and 2nd pins of the AC / DC module HLK-2M05, and the 3rd pin (negative power supply) and the 4th pin (positive power supply) output DC5V, and enters the 3rd pin of the power chip U5-XC6206P332MR through the filter capacitors C6 and C8. The 2nd pin of U5 outputs 3.3V, passes through the C10 filter capacitor, and passes through the F3 overcurrent protection fuse on the DC side to supply power to the intrinsically safe side power supply. The power supply network is labeled BA3.3V. When BA3.3V supplies power, the R28 current limiting resistor lights up LED1, indicating that BA3.3V is powered on; Figure 2 The circuit below the dotted line is basically the same as the above one. It should be noted that BAGND is the ground signal on the intrinsically safe side (ground level reference terminal), and GND is the ground signal on the non-intrinsically safe side.

[0035] Figure 3The dashed boxes II and IV shown in the figure are: JU2, external CAN bus interface; resistor R2, CAN bus terminal matching resistor; D2, surge voltage ESD device; L2, common mode filter, suppressing bus common mode voltage signal; D5 / D6 / D8, surge voltage ESD device, protecting L2 and subsequent circuits; R5 / R6, CAN bus impedance matching resistor, preventing bus signal echo; U1, CAN bus chip SIT65HVD235DR, realizing the interface chip between CAN protocol controller and physical bus; R10, CAN bus mode selection resistor: strong pull-down to "0" high-speed mode, connected to CAN bus chip U1-8PIN; R11, short-circuit resistor, connected to CAN bus chip U1-5PIN automatic baud rate loopback mode input control pin for testing; C4, CAN chip U1 power decoupling capacitor; C2, optocoupler chip U4 power decoupling capacitor; U4, 4-channel high-speed optocoupler isolation chip ACSL-6420-00TE, to achieve input and output signal isolation; R16 / R17 / R20 / R22, U4 chip diode optocoupler transmitter current limiting resistor, R21 / R23 / R24 / R25, signal pull-up resistor.

[0036] Figure 4 As shown, R61 and LED3 form a CPU operation indication circuit. Every 1 second, LED3 lights up once, with a delay of 1 second. Figure 4 As shown, X1, C58, and C59 form a clock circuit, which provides a 32.768KHz reference clock for CPU timing; Figure 4 As shown, K1, R51 and C60 form a power-on reset and button reset circuit. When the system is powered on or the button is pressed, it is charged through R51 and C60 to form a low-level pulse with a charging time of ≥10mS to reset the CPU. C62 and C63 are CPU power filter capacitors to filter out power supply interference. The CN2 socket is connected to the CPU RXD / TXD to form a CPU program download and debugging interface. USART1_RX, USART1_TX and 485TR1 are 485 control signal lines, which are connected to the same-name signal ports of the optoelectronic isolator to control the data transmission and reception of the 485 chip. CAN_RX and CAN_TX are CAN bus data signal lines, which are connected to the same-name signal ports of the optoelectronic isolator to control the data transmission and reception of the CAN chip.

[0037] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0038] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A mine-used differential signal intrinsically safe isolation data processing system, characterized by: The system includes a power circuit unit, a photoelectric isolation unit, a communication interface unit and a CPU data processing unit; The power circuit unit provides two types of output power, intrinsically safe and non-intrinsically safe, with overvoltage, overcurrent and short-circuit protection, and can suppress common-mode voltage; the photoelectric isolation unit uses a photoelectric isolation chip to achieve physical isolation of data signals on the intrinsically safe side and the non-intrinsically safe side, ensuring that energy is not transferred and that the signals on both sides are not grounded; the communication interface unit converts logic signals into differential signals and communicates with external devices through 485 and CAN bus chips; the CPU data processing unit is responsible for data processing, and controls the photoelectric isolation and communication interface units to achieve data transmission and reception.

2. A method for processing data of differential signal intrinsically safe isolation for mining according to claim 1, characterized in that: The specific steps of the data processing method are as follows: S1: Power supply circuit unit design: dual isolated power supply, physical isolation between intrinsically safe and non-intrinsically safe sides, all designed according to intrinsically safe standards, AC127V to DC5V / 3.3V power supply; S2: Design of differential bus photoelectric isolation circuit: Use the optical coupler TLP521 and ACSL-6420 to isolate intrinsically safe and non-intrinsically safe signals, design 485 / CAN differential circuit, and protect against interference; S3: 485 bus data reception: CPU sets 485TR1 low level, 485 chip receives, A / B differential is converted to logic level, and is isolated and transmitted to CPU through optocoupler U4; S4: 485 bus data transmission: CPU sets 485TR1 high level, 485 chip sends, data is isolated by optocoupler U4, and differential signal is output; S5: CAN bus data transmission and reception: CAN bus data transmission and reception is automatically controlled by SIT65HVD235DR, and the signal is isolated from the intrinsically safe side and the non-intrinsically safe side through the photoelectric isolator; S6: CPU data processing: STC8H8K64U processes data, controls optoelectronic isolation and communication interface, clock, reset, and filter to ensure stable operation; S7: System indication and debugging: Design CPU operation indication circuit, LED status display, and program download debugging interface to facilitate system debugging and maintenance.

3. A method for processing data of differential signal intrinsically safe isolation for mining according to claim 2, characterized in that: The specific steps of designing the power circuit unit in S1 are as follows: Step 1: Power supply isolation and input: First, use two completely isolated power supplies, one for the intrinsically safe side and the other for the non-intrinsically safe side; Step 2: Input voltage processing: Take AC127V as input voltage, first pass through the protection circuit for overcurrent and overvoltage protection, and then filter out clutter and interference through the filter; Step 3: Voltage conversion and output: The processed AC voltage will be converted into DC 5V and 3.3V. The two DC voltages are specifically used to power the intrinsically safe circuit. During the conversion process, it is necessary to ensure that the output voltage is stable and meets the intrinsically safe circuit design standards to improve the reliability and safety of the entire circuit.

4. A method for processing data of differential signal intrinsically safe isolation for mining according to claim 2, characterized in that: The specific steps of designing the differential bus photoelectric isolation circuit in S2 are as follows: Step 1: Photoelectric signal isolation: Use the optocoupler TLP521 and the high-speed logic optocoupler ACSL-6420-00TE to photoelectrically isolate the data signals on the intrinsically safe side from those on the non-intrinsically safe side, ensuring that the circuits on both sides are physically completely disconnected, thereby preventing energy transfer and interference; Step 2: Differential signal conversion circuit design: Design a differential signal conversion circuit for the 485 bus and CAN bus. This circuit converts the logic signal into a differential signal and transmits it to external devices through the bus. At the same time, the common-mode filter and surge voltage ESD device in the circuit can effectively suppress common-mode interference and surge voltage, protecting the circuit from interference and damage. Step 3: Circuit testing and optimization: After completing the design of the optoelectronic signal isolation and differential signal conversion circuits, conduct circuit testing; Through testing, it is verified whether the function and performance of the circuit meet the design requirements. If problems or deficiencies are found, necessary optimization and improvement are carried out to ensure the reliability and stability of the circuit.

5. A mining differential signal intrinsically safe isolation data processing method according to claim 2, characterized in that: The 485 bus data reception in S3 means that when the CPU control signal 485TR1 is set to a low level, the 485 communication chip immediately enters the receiving state. At this time, the chip will monitor the differential signal on buses A and B, and convert it into a corresponding logic level according to the level relationship between the two signals to ensure signal isolation and transmission safety. The converted logic level will be isolated by the optocoupler U4 and then sent to the CPU for processing.

6. A method for processing data of differential signal intrinsically safe isolation for mining according to claim 2, characterized in that: The 485 bus data transmission in S4 means that when the CPU control signal 485TR1 is set to a high level, the 485 communication chip will immediately enter the sending state. At this time, the data that the CPU is ready to send will first be isolated by the optocoupler U4 to ensure the data transmission security and circuit stability. The isolated data will be received by the 485 chip, and according to the logical state of the data, the chip will output the corresponding differential signal to the bus.

7. A method for processing data of differential signal intrinsically safe isolation for mining according to claim 2, characterized in that: The specific steps of CAN bus data transmission and reception in S5 are as follows: Step 1: Automatic control of data direction: The data receiving and sending process of the CAN bus is automatically controlled by the chip SIT65HVD235DR, without the need for external CPU intervention, which simplifies the circuit design; Step 2: Photoelectric isolation of data signals: In order to ensure electrical isolation between the intrinsically safe side and the non-intrinsically safe side, the CAN bus signal will be isolated and transmitted through a photoelectric isolator to prevent energy transfer and interference; Step 3: Data transmission and reception execution: When sending data, the SIT65HVD235DR chip will automatically convert the data output by the CPU into CAN differential signals and send them to the bus; when receiving data, the chip will monitor the differential signals on the bus, convert them into logic levels, and send them to the CPU for processing.

8. A method for processing data of differential signal intrinsically safe isolation for mining according to claim 2, characterized in that: The specific steps of CPU data processing in S6 are as follows: Step 1: Logical operations and data processing: STC8H8K64U, as the core processor, is responsible for performing logical operations and data processing tasks, receiving data from input devices or communication interfaces, performing necessary calculations and processing, and then outputting the results to output devices or communication interfaces; Step 2: Control photoelectric isolation and communication interface: STC8H8K64U realizes electrical isolation between the intrinsically safe side and the non-intrinsically safe side by controlling the photoelectric isolation circuit unit to ensure the security of data transmission. At the same time, it also controls the communication interface unit to realize the data receiving and sending function and exchange data with external devices. Step 3: Ensure stable operation: To ensure the stable operation of the STC8H8K64U, the system is equipped with a clock circuit to provide an accurate clock signal, a reset circuit to restart the CPU when necessary, and a power filter capacitor to smooth the power supply voltage and reduce the impact of voltage fluctuations on the CPU.

9. A mining differential signal intrinsically safe isolation data processing method according to claim 2, characterized in that: The system indication and debugging in the S7 refers to real-time monitoring of the CPU's operating status. A CPU operation indication circuit is designed, which visually displays whether the CPU is in normal working condition by turning on and off the LED indicator. In addition, in order to facilitate the debugging and maintenance of the system, a CPU program download and debugging interface is specially provided. Through this interface, users can easily download the program to the CPU and perform real-time debugging and modification, which greatly improves the maintainability and flexibility of the system.

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