Improved serial cancellation list flipping decoding method and device, medium and product

Abstract

The invention discloses an improved serial cancellation list flipping decoding method and device, a medium and a product, and relates to the technical field of coding, the method comprises the following steps: in a continuous iteration process, generating a candidate path list based on an index of a current decoding bit and a flipping set in a flipping set list; performing circulation to obtain candidate paths passing through cyclic redundancy check bits and candidate paths passing through all parity check bits in the candidate path list; and storing the candidate path with the minimum path metric value into the bit sequence, updating the flip set list, and storing the candidate path which has the minimum path metric value and passes cyclic redundancy check bits into the bit sequence. And taking the bit sequence in which the candidate path is stored as a decoded bit sequence, and ending decoding. According to the method and the device, the balance between DECC and complexity performance can be realized, so that the performance of the polarization code is further improved, and the competitiveness of the polarization code in a future high-reliability and low-energy-consumption communication scene is enhanced.

Description

Technical Field

[0001] The present application relates to the field of coding technology, and in particular to an improved serial offset list flip decoding method, device, medium and product. Background Art

[0002] Polar codes, as the first coding technology that has been theoretically proven to be able to reach channel capacity, have received widespread attention. In particular, the CRC-Aided Successive Cancellation List (CA-SCL) decoding method assisted by the cyclic redundancy check (CRC) enables polar codes to have better error correction performance than LDPC (Low Density Parity Check Code) and Turbo codes in medium and short code length scenarios. This performance advantage has prompted polar codes to be selected by 3GPP (3rd Generation Partnership Project) as the control channel coding scheme in the 5G (5th-Generation Mobile Communication Technology) enhanced mobile broadband (enhanced Mobile Broadband, eMBB) scenario. In addition, polar codes are still one of the most competitive coding technologies to meet the future needs of high-reliability and low-power communications. For example, in recent years, polar codes have been deeply studied in the future Internet of Things (IoT) with high noise and limited energy, and in backscattering networks under extremely harsh channel conditions.

[0003] The key factor to improve the performance of polar codes has always been the improvement of decoding methods. For example, the introduction of the CA-SCL decoding method has enabled polar codes to achieve superior performance than other channel coding techniques in medium and short code length scenarios. In recent years, the list-flip decoding method has further improved the error correction performance of polar codes by introducing additional decoding attempts. In particular, the introduction of the dynamic SCL-Flip (D-SCLF) decoding method has further improved the previous list-flip decoding method. The core of this decoding method is to propose a new flip metric (FM). The FM is continuously updated as additional decoding attempts are made, thereby realizing dynamic error correction capability (DECC). DECC allows the decoding method to flexibly switch between low-order and high-order error correction, while the previous list-flip decoding method could only perform high-order error correction after completing all low-order corrections. This DECC makes the D-SCLF decoding method have superior error correction performance compared to other list-flip decoding methods. However, the continuous updating of FM in the D-SCLF decoding method introduces more nonlinear operations, and these additional decoding attempts cause its complexity performance to be more unstable than that of the CA-SCL decoding method.

[0004] In the subsequent study of D-SCLF decoding methods, researchers proposed a variety of improved list flip decoding methods. In order to improve the accuracy of error bit prediction, the known list flip decoding methods can perform multiple voting mechanisms for probability estimation and long short-term memory (LSTM) networks containing specific feature stacking. In order to reduce complexity, the known list flip decoding methods also use relative partial path metrics to eliminate redundant decoding attempts. In order to reduce the nonlinear operations introduced by FM in D-SCLF, although the known list flip decoding methods have also made different simplifications, these known list flip decoding methods have not been able to balance DECC and complexity performance, or often reduce complexity at the expense of DECC. Among them, this imbalance is reflected in: the known list flip decoding methods with DECC have unstable complexity performance, especially in a noisy environment, the complexity performance is very poor. Existing list flip decoding methods with excellent complexity performance often ignore DECC, which limits their error correction performance. The imbalance between DECC and complexity performance limits the improvement of polar code performance by known list flip decoding methods. Summary of the invention

[0005] The purpose of this application is to provide an improved serial cancellation list flip decoding method, device, medium and product, which can achieve a balance between DECC and complexity performance, so as to further improve the performance of polar codes, thereby enhancing the competitiveness of polar codes in future high-reliability and low-energy communication scenarios.

[0006] To achieve the above objectives, this application provides the following solutions:

[0007] In a first aspect, the present application provides an improved serial offset list flip decoding method, comprising:

[0008] Acquire a bit sequence and known parameters in a channel; the known parameters include: a maximum number of additional decoding attempts and a frame bit sequence length;

[0009] Determining an index set of cyclic redundancy check bits, an index set of parity check bits, and an index set of specific information bits;

[0010] placing cyclic redundancy check bits, parity check bits, and specific information bits in a bit sequence in a channel based on an index set of cyclic redundancy check bits, an index set of parity check bits, and an index set of specific information bits;

[0011] Generating the check bit index set based on the index set of parity check bits and the index set of specific information bits;

[0012] Determine whether the number of decoding attempts is less than or equal to the maximum number of additional decoding attempts, and obtain a first determination result;

[0013] When the first judgment result is yes, the first variable and the second variable are both set to 0, and the index of the current decoding bit is set to 1;

[0014] Determine whether the index of the current decoded bit is less than or equal to the length of a frame bit sequence, and obtain a second determination result;

[0015] When the second judgment result is yes, obtain a flip set list, and generate a candidate path list based on the index of the current decoding bit and the flip set in the flip set list; the candidate path list stores multiple candidate paths with path metric values; the length of each candidate path is equal to the index of the current decoding bit;

[0016] Determine whether the index of the current decoded bit is equal to the length of the one-frame bit sequence, and obtain a third determination result;

[0017] When the third judgment result is yes, determine whether there is a candidate path in the candidate path list that passes the cyclic redundancy check bit, and obtain a fourth judgment result;

[0018] When the fourth judgment result is yes, the second variable is set to 0; when the fourth judgment result is no, the second variable is set to 1, the index of the current decoded bit is increased by 1, and the process returns to the step of determining whether the index of the current decoded bit is less than or equal to the length of a frame bit sequence;

[0019] When the third judgment result is no, determining whether the index of the current decoding bit belongs to the check bit index set, to obtain a fifth judgment result;

[0020] When the fifth judgment result is yes, determine whether there is a candidate path passing through all parity check bits in the candidate path list to obtain a fifth judgment result;

[0021] When the fifth judgment result is yes, the first variable is set to 0, the index of the current decoded bit is incremented by 1, and the process returns to the step of determining whether the index of the current decoded bit is less than or equal to the length of a frame bit sequence;

[0022] When the fifth judgment result is no, the first variable is set to 1;

[0023] When the fifth judgment result is no or the second judgment result is no, judging whether the value of the first variable or the value of the second variable is 1, and obtaining a sixth judgment result;

[0024] When the sixth judgment result is yes, the candidate path with the minimum path metric value is stored in the bit sequence, the flip set list is updated, the number of decoding attempts is updated, and the step of determining whether the number of decoding attempts is less than or equal to the maximum number of additional decoding attempts is returned to be executed;

[0025] When the sixth judgment result is no, storing the candidate path having the minimum path metric value and passing the cyclic redundancy check bit into the bit sequence;

[0026] When the first judgment result is no, the bit sequence storing the candidate path is used as the decoded bit sequence, and the decoding is terminated.

[0027] Optionally, when the second judgment result is yes, obtaining a flip set list, and generating a candidate path list based on the index of the current decoded bit and the flip set in the flip set list, including:

[0028] Determine whether the index of the current decoding bit belongs to the flip set list, and obtain a seventh determination result;

[0029] When the seventh judgment result is yes, the current decoding attempt performs a list flipping operation at the bit position corresponding to the index of the current decoding bit, and the obtained candidate path list stores multiple candidate paths with maximum path metric values;

[0030] When the seventh judgment result is no, the obtained candidate path list stores a plurality of candidate paths with minimum path metric values.

[0031] Optionally, the formula for determining the path metric value is expressed as:

[0032]

[0033] in, represents the path metric value of the lth candidate path in the candidate path list at the i-th bit, δ(x) is the estimation function, is the estimated value corresponding to the i-th bit in the l-th candidate path, is the log-likelihood ratio corresponding to the i-th bit in the l-th candidate path, Indicates the path metric value of the lth candidate path in the candidate path list at the i-1th bit.

[0034] Optionally, updating the rollover set list includes:

[0035] Determine whether the number of decoding attempts is 0;

[0036] When the number of decoding attempts is 0, the formula is used Determine the extended flipping metric set; where, is the extended flipping metric set, β is the empirical value, m β (j) represents the flip metric value corresponding to the j-th bit; is the index set of the bit sequence of the non-frozen bits in the channel, is the index set of the bit sequence of the first log2L non-frozen bits in the channel, L is the number of paths, N0=i, i is the index of the current decoded bit, indicates that j is An element in , and j cannot be Elements in

[0037] Select T smallest flip metric values ​​from the extended flip metric set, and arrange the selected T smallest flip metric values ​​in ascending order to form a flip metric set;

[0038] Forming a new flip set list based on the flip sets corresponding to the elements in the flip metric set to update the flip set list;

[0039] When the number of decoding attempts is not 0, the formula is used Expand the set of flipping metrics; where, is the set of flip metrics retained by the (t-1)th additional decoding attempt; is the set of temporary flip metrics retained for the tth additional decoding attempt.

[0040] Optionally, placing cyclic redundancy check bits, parity check bits, and specific information bits in a bit sequence in a channel based on an index set of cyclic redundancy check bits, an index set of parity check bits, and an index set of specific information bits includes:

[0041] placing cyclic redundancy check bits and parity check bits in a non-frozen bit sequence of a channel bit sequence according to an index set of cyclic redundancy check bits and an index set of parity check bits; the non-frozen bit sequence belongs to a bit sequence in a channel;

[0042] The specific information bits are placed at other positions in the non-frozen bit sequence except for the cyclic redundancy check bits and the parity check bits.

[0043] Optionally, the index set of the cyclic redundancy check bits is expressed as:

[0044]

[0045] The index set of the parity check bits is expressed as:

[0046]

[0047] The index set of the specific information bits is expressed as:

[0048]

[0049] in, is the index set of cyclic redundancy check bits, i CRC is the index of the cyclic redundancy check bit, n CRC is the total number of cyclic redundancy check bits, is a set of positive integers, M is the set of flip metrics retained for the (t-1)th additional decoding attempt, is the index set of parity bits, i PC is the index of the parity bit, d2 is a transition parameter, n PC is the total number of parity bits, is the index set of specific information bits, i SIB is the index of a specific information bit, d3 is a transition parameter, n SIB is the total number of specific information bits.

[0050] Optionally, the check bit index set is expressed as:

[0051] I C ={i C |i C ∈A[j],j∈I PC ∪ISIB};

[0052] Among them, I C is the parity bit index set, i C is the check bit index, A[j] is the jth element of the index set of the non-frozen bit in the channel bit sequence, and I PC is the index set of parity bits, I SIB is an index set of specific information bits.

[0053] In a second aspect, the present application provides a computer device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of any one of the improved serial cancellation list flip decoding methods described above.

[0054] In a third aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of any one of the above-mentioned improved serial cancellation list flip decoding methods.

[0055] In a fourth aspect, the present application provides a computer program product, including a computer program, which, when executed by a processor, implements the steps of any one of the improved serial cancellation list flip decoding methods described above.

[0056] According to the specific embodiments provided in this application, this application has the following technical effects:

[0057] The present application provides an improved serial cancellation list flip decoding method, device, medium and product, which can achieve a balance between DECC and complexity performance by generating a candidate path list based on the index of the current decoding bit and the flip set in the flip set list and updating the flip set list, so as to further improve the performance of the polar code, thereby enhancing the competitiveness of the polar code in future high-reliability and low-energy communication scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0059] Figure 1 A flowchart of an improved serial cancellation list flip decoding method provided by an embodiment of the present application;

[0060] Figure 2A schematic diagram of a communication system based on an improved serial cancellation list flip decoding method provided in an embodiment of the present application;

[0061] Figure 3 A performance comparison diagram of D-SCLF2 and a serial cancellation list flip decoding method under PC (512, 256+24) provided in another embodiment of the present application;

[0062] Figure 4 A performance comparison diagram of D-SCLF2 and a serial cancellation list flip decoding method provided in an embodiment of the present application under PC (512, 128+24);

[0063] Figure 5 A performance comparison diagram of D-SCLF2 and a serial cancellation list flip decoding method provided in an embodiment of the present application under PC (512, 384+24);

[0064] Figure 6 Performance comparison diagram of D-SCLF2 and serial cancellation list flip decoding method under PC (256, 128 + 24) provided in an embodiment of the present application

[0065] Figure 7 A performance comparison diagram of D-SCLF2 and a serial cancellation list flip decoding method provided in an embodiment of the present application under PC (256, 64+24);

[0066] Figure 8 A performance comparison diagram of D-SCLF2 and a serial cancellation list flip decoding method provided in an embodiment of the present application under PC (256, 192+24);

[0067] Fig. 9 Array diagram showing the complexity comparison of D-SCLF2 and serial cancellation list flip decoding method at relatively large ρ2 provided in one embodiment of the present application;

[0068] Fig.10 A schematic diagram of the structure of a computer device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0069] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0070] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0071] The improved serial offset list flip decoding method provided by the present application is an enhanced early temination mechanism aided D-SCLF (EETM-DSCLF2) decoding method, which aims to more accurately estimate the original information bit sequence. Figure 2 As shown, when applied to a communication system, the decoding method provided by the present application mainly includes three parts:

[0072] (1) Setting the parity check (PC) bit and CRC bit to trigger the PC and CRC in the decoding process of the EETM-DSCLF2 decoding method.

[0073] (2) Setting a specific information bit (SIB) to trigger the PC in the decoding process of the EETM-DSCLF2 decoding method.

[0074] (3)EETM-DSCLF2 decoding method.

[0075] Based on the above, the pre-basic description of the EETM-DSCLF2 decoding method is as follows:

[0076] In this application document, both uppercase and lowercase letters represent scalars, bold lowercase letters represent vectors, and cursive uppercase letters represent sets. For example, y and Y represent scalars, y represents vectors, and represents a set. In particular, Representing a collection The i-th element in Represents a special type of vector.

[0077] Assume that Figure 2 In the channel shown, the length of an input bit sequence is N, and the bit sequence is expressed as The frame bit sequence consists of two parts: the non-frozen bit sequence and frozen bit sequence in, Indicates that the non-frozen bits are The index set of Indicates that the frozen bit is The index set of frozen bit sequence The bits in the default are 0, not the frozen bit sequence. Determined by the originator. In this application, the non-frozen bit sequence It consists of two parts, namely Figure 2The information bit sequence and check bit sequence are shown in FIG. The check bit sequence includes PC bits and CRC bits. In other words, assuming that the length of a frame of non-frozen sequence is K, then it satisfies:

[0078] K=M+n C =M+n PC +n CRC (1)

[0079] Where M represents the length of the information bit sequence, n C Indicates the total number of check bits, n PC represents the total number of PC bits, and n CRC Indicates the total number of CRC bits.

[0080] (1) Set the PC bits and CRC bits.

[0081] The first step is to use a non-frozen bit sequence The CRC bits are set in this application. The index set in is The CRC bits are placed according to the index. And the index set satisfies:

[0082]

[0083] In the second step, in the non-frozen bit sequence Set the PC bit in the application. The index set in is The PC bits are placed according to the index. And the index set satisfies:

[0084]

[0085] Among them, i PC is the index of the parity bit. d2 is a transition parameter with:

[0086]

[0087] And, the value of the PC bit satisfies the following equation:

[0088]

[0089] in,

[0090]

[0091] Where γ is an arbitrary scalar.

[0092] And there are:

[0093]

[0094] In the formula, is any set, u j are elements belonging to the non-frozen bit sequence.

[0095] The third step is to The remaining positions are used to place information bits.

[0096] (2) Set specific information bits.

[0097] The first step is to place the PC bits and CPC bits in the non-frozen bit sequence. The present application sets the SIB in a non-frozen bit sequence. The index set in is The SIB is set according to the index. And the index set satisfies:

[0098]

[0099] Among them, i SIB is the index of a specific information bit; d3 is a transition parameter, and d3 satisfies:

[0100]

[0101] The second step is to calculate the check bit index set I that can trigger PC based on the first step. C . Among them I C Satisfies the following equation:

[0102]

[0103] In the formula, i C is the index of the parity bit, is the jth element in the index set of the channel bit sequence of the non-frozen bit.

[0104] Based on this, in an exemplary embodiment, Figure 1 As shown, an improved serial offset list flip decoding method is provided, comprising:

[0105] The first step is to input the sequence received by the decoding method from the channel (i.e., the bit sequence in the channel), input the known parameters, and set the initial values ​​of the variables. The known parameters are: check bit index set I C , the maximum number of additional decoding attempts T and the length of a frame bit sequence N. The initial value of the number of decoding attempts t is set to 0.

[0106] The second step is to determine whether the number of decoding attempts is less than or equal to the maximum number of additional decoding attempts (ie, t≤T), and obtain a first determination result;

[0107] When the first judgment result is yes, the first variable e is assigned PC and the second variable e CRC is 0, the index i of the current decoded bit is assigned to 1, and the third step is executed. If there is a path that passes the CRC, then e CRC is considered to be 0, otherwise it is considered to be 1. However, e CRC 0 does not necessarily mean that a path passes the CRC. If a path passes the PC, then e PC is considered to be 0, otherwise it is considered to be 1. However, e PC A value of 0 does not necessarily mean that there is a path through the PC.

[0108] When the first judgment result is no, execute step fourteen.

[0109] The third step is to determine whether the index of the current decoded bit is less than or equal to the length of a frame bit sequence (i.e., i≤N), and obtain a second determination result;

[0110] When the second judgment result is yes, execute the fourth step, otherwise execute the tenth step.

[0111] Step 4: Execute SCL (S t ) submethod to generate a list of candidate paths The list of candidate paths Store L candidate paths and the length of these candidate paths is i. Execute step 5.

[0112] The fifth step is to determine whether the index of the current decoded bit is equal to the length of the one-frame bit sequence (ie, i=N), and obtain a third determination result.

[0113] When the third judgment result is yes, execute step 6, otherwise execute step 7.

[0114] Step 6: Determine the candidate path list Whether there is a candidate path that passes the cyclic redundancy check bit in the , a fourth judgment result is obtained.

[0115] When the fourth judgment result is yes, then e CRC =0; otherwise e CRC = 1. Go to step 9.

[0116] Step 7: Determine whether the index of the current decoded bit belongs to the check bit index set, and obtain the fifth judgment result; (i.e. ).

[0117] When the fifth judgment result is yes, execute step 8, otherwise execute step 9.

[0118] Step 8: Determine whether there is a candidate path that passes all parity check bits in the candidate path list, and obtain the sixth determination result, that is, determine whether the candidate path list Is there a path passing through all the previous PCs?

[0119] When the sixth judgment result is no, then e PC = 0, and execute step 9; otherwise e PC =1, and execute step 10.

[0120] In step 9, the index of the current decoded bit is increased by 1 (ie, i'=i+1), and the process returns to step 3. i' is the updated index of the current decoded bit.

[0121] Step 10: Determine whether the value of the first variable or the value of the second variable is 1, and obtain the seventh determination result, that is, determine whether the first variable e is 1. PC and the first variable e CRC Is there a value of 1 in .

[0122] When the seventh judgment result is yes, execute step 11, otherwise execute step 12.

[0123] Step 11. storage The candidate path with the minimum PM value in . And perform the flip set list Update the method. Go to step 13.

[0124] Step 12. storage The candidate path with the minimum PM value and passing the CRC check is selected. Execute step 14.

[0125] Step 13, update the number of decoding attempts (ie, t′=t+1), and return to step 2, where t′ is the updated number of decoding attempts.

[0126] Step 14: Output And end the decoding.

[0127] in, Refers to the candidate path list in the decoding process, which stores L candidate paths. Refers to the candidate path list when decoding to the i-th bit during the decoding process. The list stores L candidate paths and the length of each path is i. Similarly, Refers to the candidate path list when decoding to the Nth bit during the decoding process. The list stores L candidate paths and the length of each path is N. and Both special case.

[0128] In another exemplary embodiment of the present application, The implementation steps of the sub-method are as follows:

[0129] (1) Input parameters i and It refers to the flip set corresponding to the tth additional decoding attempt, and the maximum value of t is T.

[0130] (2) Determine whether the index of the current decoded bit belongs to the flip set list When the eighth judgment result is yes, the current decoding attempt will perform a list flip operation at this position. Store L candidate paths with the largest path metric (PM). Otherwise, the list flipping operation is not performed. Store L candidate paths with minimum PM.

[0131] The PM value is calculated as follows:

[0132]

[0133] in, represents the path metric value of the lth candidate path in the candidate path list at the i-th bit, δ(x) is the estimation function, is the estimated value corresponding to the i-th bit in the l-th candidate path, is the log-likelihood ratio corresponding to the i-th bit in the l-th candidate path, Indicates the path metric value of the lth candidate path in the candidate path list at the i-1th bit.

[0134] (3) Output candidate path list and end Submethod.

[0135] In another exemplary embodiment of the present application, the flip set list The implementation steps of the update method are as follows:

[0136] (1) Input parameters i, t.

[0137] (2) Determine whether the number of decoding attempts t is 0. If t=0, then execute the following step (3), otherwise execute the following step (4).

[0138] (3) Assign N0 = i. Calculate the extended flip metric set The flip metric set satisfy:

[0139]

[0140] Among them, β is an empirical value, and its value is 0.4. is the index set of the bit sequence of the non-frozen bits in the channel, is the index set of the bit sequence of the first log2L non-frozen bits in the channel, N0 = i, i is the index of the current decoded bit, indicates that j is An element in , and j cannot be Elements in m β (j) represents the flip metric value corresponding to the jth bit, which satisfies:

[0141]

[0142] In the formula, e is the natural logarithm.

[0143] is the logarithm of the posterior probability ratio, which satisfies the following formula:

[0144]

[0145] In the formula, is the path metric value of the lth candidate path in the candidate path list at the kth bit, is the path metric value of the l+Lth candidate path in the candidate path list at the kth bit,

[0146] Flipping the metric set from extension Select T smallest m β The values ​​are arranged in ascending order and these values ​​constitute the flip metric set And the flip metric set The flip sets corresponding to the elements in the list constitute the flip set list That is, flip the list of sets satisfy:

[0147]

[0148] Perform the following step (5).

[0149] (4) Assign N t =i. Calculate the extended flipping metric set The extended flip metric set satisfy:

[0150]

[0151] in, It is essentially the set of flip metrics retained by the (t-1)th additional decoding attempt. is the set of temporary flip metrics retained for the tth additional decoding attempt, satisfy:

[0152]

[0153] In the formula, is the flip set corresponding to the tth additional decoding attempt, N t =i,i t It is a flip set The last element in Is a flip set The flip metric corresponding to the element of the bit sequence, and satisfy:

[0154]

[0155] Next, according to the steps similar to step (3), based on the expanded flip metric set To update the flip set list

[0156] (5) Output the updated flip set list And end the update.

[0157] In another exemplary embodiment of the present application, in order to prove the versatility of the decoding method provided by the present application under short code conditions, the performance of the EETM-DSCLF2 decoding method and the D-SCLF decoding method proposed in the present application under different code rates and code lengths are compared. The parameters used in these charts are binary phase shift keying (BPSK) modulation, additive white Gaussian noise (AWGN) channel model and Gaussian approximation (GA) construction algorithm. The D-SCLF decoding method uses a 24-bit CRC code, and its generating polynomial is g(x)=x 24 +x 23 +x 6 +x 5 +x+1, and the EETM-DSCLF2 decoding method also uses 24 check bits, which are composed of 8 PC bits and 16 CRC bits, and the corresponding CRC generating polynomial is g(x)=x 16 +x 15 +x 2 +1. Where g(x) is the CRC generator polynomial, and x is any variable that can take the value 1 or 0.

[0158] At the same time, in order to facilitate the analysis of complexity, this application provides a simplified expression of complexity and six complexity distribution intervals. Among them, complexity C is defined as:

[0159]

[0160] Where D is the complexity of the decoder, which is approximately equal to the product of the average number of decoded paths and the average number of decoded non-frozen bits. SC =1·K=1·(M+n C ). Similarly, D CA-SCL is approximately equal to L·K, where L is the number of paths. It is worth noting that the complexity C of the same decoding method can only be compared when the values ​​of K and N are consistent.

[0161] The six complexity distribution intervals (R1, R2, R3, R4, R5 and R6) are defined as:

[0162]

[0163] in:

[0164]

[0165] And C D-SCLF is the complexity of the D-SCLF decoding method. D-SCLF The maximum value of and minimum value satisfy:

[0166]

[0167] It is worth mentioning that R2 and R6 are special distribution intervals, both of which contain only one point.

[0168] Figures 3 to 5 The performance of D-SCLF2 and EETM-DSCLF2 decoding methods are compared when the code length is 512 and the code rate is different. Figures 3 to 5 Part (a) of the paper compares the performance of the frame error rate (FER), while Figures 3 to 5 Part (b) of the paper compares the complexity performance. Table 1 lists the Figures 3 to 5 Here, ρ2 represents the complexity reduction achieved by the EETM-DSCLF2 decoding method and is defined as:

[0169]

[0170] Table 1. Comparison of the complexity of D-SCLF2 and EETM-DSCLF2 decoding methods when the code length is 512

[0171]

[0172] based on Figures 3 to 5As shown in Table 1, for a code length of 512, the D-SCLF2 and EETM-DSCLF2 decoding methods show similar error correction performance at different code rates. This indicates that under these conditions, the proposed EETM-DSCLF2 maintains the dynamic error correction capability of the original D-SCLF2 decoding method. In addition, the EETM-DSCLF2 decoding method significantly reduces the complexity of the original D-SCLF2 decoding method, especially at lower E b / N0 value. Within a given practical FER range, the EETM-DSCLF2 decoding method reduces the complexity of the original D-SCLF2 decoding method by up to 61.4% without affecting the DECC performance.

[0173] Similarly, Figures 6 to 8 The decoding performance of the methods at different code rates is compared when the code length is 256. Table 2 lists the corresponding complexity values. Figures 6 to 8 As shown in Table 2, the EETM-DSCLF2 decoding method proposed in this application significantly reduces the complexity without affecting the error correction performance of the original D-SCLF2 decoding method. b As / N0 decreases, the complexity reduction effect becomes more significant.

[0174] Table 2 Comparison of the complexity of D-SCLF2 and EETM-DSCLF2 decoding methods when the code length is 256

[0175]

[0176] Fig. 9 The complexity distribution of the D-SCLF2 and EETM-DSCLF2 decoding methods for larger ρ2 is shown. Here, Fig. 9 Part (a) of - Fig. 9 The larger ρ2 in part (f) refers to Figures 3 to 8 The lowest E b / N0 values, they are all greater than 50%. Fig. 9 It shows that the EETM-DSCLF2 decoding method proposed in this application significantly reduces the frequencies associated with intervals R5 and R6, while increasing the frequencies of intervals R1 to R4. This shows that the EETM-DSCLF2 decoding method has stronger anti-interference ability and avoids the situation where the complexity of the D-SCLF2 decoding method increases sharply when the noise reaches a certain level. Fig. 9 In the expression, frequency represents frequency, and intervals or points represents intervals or points.

[0177] Based on the above simulation results and analysis, it can be obtained that the decoding method proposed in this application significantly reduces the complexity of the D-SCLF decoding method without affecting its DECC performance. As the noise level increases, this complexity reduction becomes more obvious. Therefore, the decoding method proposed in this application can further enhance the competitiveness of polar codes in future high-reliability, low-power communication scenarios.

[0178] In an exemplary embodiment, a computer device is provided. The computer device may be a server or a terminal. The internal structure diagram thereof may be as follows: Fig.10 As shown. The computer device includes a processor, a memory, an input / output interface (Input / Output, referred to as I / O) and a communication interface. The processor, the memory and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store serial cancellation list flip decoding data. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, an improved serial cancellation list flip decoding method is implemented.

[0179] Those skilled in the art will understand that Fig.10 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components. In an exemplary embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the steps in the above-mentioned method embodiments when executing the computer program.

[0180] In an exemplary embodiment, a computer-readable storage medium is provided, storing a computer program, and when the computer program is executed by a processor, the steps in the above method embodiments are implemented.

[0181] In an exemplary embodiment, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the steps in the above method embodiments are implemented.

[0182] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant regulations.

[0183] Those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM may be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM).

[0184] The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. The non-relational database may include a distributed database based on blockchain, etc., but is not limited thereto. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but is not limited thereto.

[0185] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0186] The present application uses specific examples to illustrate the principles and implementation methods of the present application. The above examples are only used to help understand the method and core ideas of the present application. At the same time, for those skilled in the art, according to the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present application.

Claims

1. An improved serial cancellation list flip decoding method, characterized in that: The improved serial offset list flip decoding method comprises: Acquire a bit sequence and known parameters in a channel; the known parameters include: a maximum number of additional decoding attempts and a frame bit sequence length; Determining an index set of cyclic redundancy check bits, an index set of parity check bits, and an index set of specific information bits; placing cyclic redundancy check bits, parity check bits, and specific information bits in a bit sequence in a channel based on an index set of cyclic redundancy check bits, an index set of parity check bits, and an index set of specific information bits; Generating the check bit index set based on the index set of parity check bits and the index set of specific information bits; Determine whether the number of decoding attempts is less than or equal to the maximum number of additional decoding attempts, and obtain a first determination result; When the first judgment result is yes, the first variable and the second variable are both set to 0, and the index of the current decoding bit is set to 1; Determine whether the index of the current decoded bit is less than or equal to the length of a frame bit sequence, and obtain a second determination result; When the second judgment result is yes, obtain a flip set list, and generate a candidate path list based on the index of the current decoding bit and the flip set in the flip set list; the candidate path list stores multiple candidate paths with path metric values; the length of each candidate path is equal to the index of the current decoding bit; Determine whether the index of the current decoded bit is equal to the length of the one-frame bit sequence, and obtain a third determination result; When the third judgment result is yes, determine whether there is a candidate path in the candidate path list that passes the cyclic redundancy check bit, and obtain a fourth judgment result; When the fourth judgment result is yes, the second variable is set to 0; when the fourth judgment result is no, the second variable is set to 1, the index of the current decoded bit is increased by 1, and the process returns to the step of determining whether the index of the current decoded bit is less than or equal to the length of a frame bit sequence; When the third judgment result is no, determining whether the index of the current decoding bit belongs to the check bit index set, to obtain a fifth judgment result; When the fifth judgment result is yes, determine whether there is a candidate path passing through all parity check bits in the candidate path list to obtain a sixth judgment result; When the sixth judgment result is yes, the first variable is set to 0, the index of the current decoded bit is incremented by 1, and the process returns to the step of determining whether the index of the current decoded bit is less than or equal to the length of a frame bit sequence; When the sixth judgment result is no, the first variable is set to 1; When the fifth judgment result is no or the second judgment result is no, judging whether the value of the first variable or the value of the second variable is 1, to obtain a seventh judgment result; When the seventh judgment result is yes, the candidate path with the minimum path metric value is stored in the bit sequence, the flip set list is updated, the number of decoding attempts is updated, and the step of determining whether the number of decoding attempts is less than or equal to the maximum number of additional decoding attempts is returned to be executed; When the seventh judgment result is no, storing the candidate path having the minimum path metric value and passing the cyclic redundancy check bit into the bit sequence; When the first judgment result is no, the bit sequence storing the candidate path is used as the decoded bit sequence, and the decoding is terminated.

2. The improved serial cancellation list flip decoding method according to claim 1, characterized in that: When the second judgment result is yes, obtaining a flip set list, and generating a candidate path list based on the index of the current decoded bit and the flip set in the flip set list, including: Determine whether the index of the current decoding bit belongs to the flip set list, and obtain an eighth determination result; When the eighth judgment result is yes, the current decoding attempt performs a list flipping operation at the bit position corresponding to the index of the current decoding bit, and the obtained candidate path list stores multiple candidate paths with maximum path metric values; When the eighth judgment result is no, the obtained candidate path list stores a plurality of candidate paths with minimum path metric values.

3. The improved serial cancellation list flip decoding method according to claim 2, characterized in that: The formula for determining the path metric value is expressed as: in, represents the path metric value of the lth candidate path in the candidate path list at the i-th bit, δ(x) is the estimation function, is the estimated value corresponding to the i-th bit in the l-th candidate path, is the log-likelihood ratio corresponding to the i-th bit in the l-th candidate path, Indicates the path metric value of the lth candidate path in the candidate path list at the i-1th bit.

4. The improved serial cancellation list flip decoding method according to claim 1, characterized in that: Update the rollover set list, including: Determine whether the number of decoding attempts is 0; When the number of decoding attempts is 0, the formula is used Determine the extended flipping metric set; where, is the extended flipping metric set, β is the empirical value, m β (j) represents the flip metric value corresponding to the j-th bit; is the index set of the bit sequence of the non-frozen bits in the channel, is the index set of the bit sequence of the first log2L non-frozen bits in the channel, L is the number of paths, N0=i, i is the index of the current decoded bit, indicates that j is An element in , and j cannot be Elements in Select T smallest flip metric values ​​from the extended flip metric set, and arrange the selected T smallest flip metric values ​​in ascending order to form a flip metric set; Forming a new flip set list based on the flip sets corresponding to the elements in the flip metric set to update the flip set list; When the number of decoding attempts is not 0, the formula is used Determine the extended flipping metric set; where, is the set of flip metrics retained by the (t-1)th additional decoding attempt; is the set of temporary flip metrics retained for the tth additional decoding attempt.

5. The improved serial cancellation list flip decoding method according to claim 1, characterized in that: Placing cyclic redundancy check bits, parity check bits, and specific information bits in a bit sequence in a channel based on an index set of cyclic redundancy check bits, an index set of parity check bits, and an index set of specific information bits, including: placing cyclic redundancy check bits and parity check bits in a non-frozen bit sequence of a channel bit sequence according to an index set of cyclic redundancy check bits and an index set of parity check bits; the non-frozen bit sequence belongs to a bit sequence in a channel; The specific information bits are placed at other positions in the non-frozen bit sequence except for the cyclic redundancy check bits and the parity check bits.

6. The improved serial cancellation list flip decoding method according to claim 1, characterized in that: The index set of the cyclic redundancy check bits is expressed as: The index set of the parity check bits is expressed as: The index set of the specific information bits is expressed as: in, is the index set of cyclic redundancy check bits, i CRC is the index of the cyclic redundancy check bit, n CRC is the total number of cyclic redundancy check bits, is a set of positive integers, M is the set of flip metrics retained for the (t-1)th additional decoding attempt, is the index set of parity bits, i PC is the index of the parity bit, d2 is a transition parameter, n PC is the total number of parity bits, is the index set of specific information bits, i SIB is the index of a specific information bit, d3 is a transition parameter, n SIB is the total number of specific information bits.

7. The improved serial cancellation list flip decoding method according to claim 1, characterized in that: The check bit index set is expressed as: Among them, I C is the parity bit index set, i C is the parity bit index, is the jth element of the index set of the non-frozen bit in the channel bit sequence, is the index set of parity bits, is an index set of specific information bits.

8. A computer device comprising: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the improved serial cancellation list flip decoding method according to any one of claims 1 to 7.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the improved serial cancellation list flip decoding method described in any one of claims 1 to 7 is implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the improved serial cancellation list flip decoding method described in any one of claims 1 to 7 is implemented.

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