Digital receiver circuit and control method thereof

Abstract

The invention provides a digital receiver circuit and a control method thereof. The digital receiver circuit comprises a frame synchronization detection module, a symbol synchronization detection module and a symbol decoding module, the frame synchronization detection module comprises a first matched filter and a first peak detection module; the first matched filter is used for performing convolution operation on a guide code sequence in the received synchronization signal to obtain a convolution operation result; the first peak value detection module is used for determining the position of a convolution peak value according to the convolution operation result; determining the end position of the guide code sequence according to the position of the convolution peak value; the symbol synchronization detection module is used for detecting positioning information of an end position of each symbol in effective data connected with the guide code sequence; according to the positioning information, determining a pulse sequence corresponding to a judgment moment of symbol decoding of the effective data; and the symbol decoding module is used for performing symbol decoding on the effective data according to the judgment time and the pulse sequence. The technology can improve the accuracy of signal detection and decoding.

Description

Technical Field

[0001] The present invention relates to the technical field of digital circuits, and in particular to a digital receiver circuit and a control method thereof. Background Art

[0002] Currently, the mature passive IoT representative technology RFID has limitations in communication distance and networking mode. The communication distance is limited by the energy supply mode and energy conversion efficiency. RFID needs to obtain energy from the radio frequency field. Due to the energy conversion efficiency, it is impossible to obtain enough energy from the radio frequency field of the reader at a long distance. The communication distance is generally more than 20 meters.

[0003] Furthermore, RFID tags need to be designed with low power consumption, so the digital demodulation and decoding algorithm of the receiver is relatively simple. If glitches appear in the demodulated signal output by the envelope detector, the decoding will be abnormal and the anti-interference ability will be weak. The tag receiving sensitivity is generally between -22dBm and -24dBm. However, tags usually use envelope detection as an analog demodulation circuit because of its simple circuit and low complexity. However, since the envelope detector is a nonlinear device, it has weak anti-aliasing and anti-interference capabilities. When there is strong interference in the communication environment or the channel is poor and the signal-to-noise ratio is low, the signal output by the detection circuit may have glitches or distortion, and the symbol period and duty cycle may also change.

[0004] Therefore, there is an urgent need to provide a digital receiver circuit that improves the anti-interference capability of downlink reception, so as to counteract the distortion or distortion of the output signal of the detection circuit caused by interference or noise in the communication environment. Summary of the invention

[0005] The purpose of the present invention is to provide a digital receiver circuit and a control method thereof, so as to alleviate the technical problem that when there is strong interference or the channel is poor and the signal-to-noise ratio is low in the communication environment, the signal output by the detection circuit may have burrs or distortion, and the symbol period and duty cycle may also change. By performing convolution correlation operations on the synchronization signal of the downlink signaling and detecting the change of the convolution peak, the judgment threshold of the frame synchronization and symbol decoding in the receiver can be adjusted, and the dynamic adjustment of the decoding threshold can be realized to combat the distortion or distortion of the output signal of the detection circuit caused by interference or noise in the communication environment.

[0006] In the first aspect, an embodiment of the present invention provides a digital receiver circuit, comprising: a connected frame synchronization detection module, a symbol synchronization detection module and a symbol decoding module; the frame synchronization detection module comprises: a first matched filter and a first peak detection module; the first matched filter is used to perform a convolution operation on a guide code sequence in a received synchronization signal to obtain a convolution operation result; the first peak detection module is used to determine the position of a convolution peak according to the convolution operation result; the end position of the guide code sequence is determined according to the position of the convolution peak; the symbol synchronization detection module is used to detect the positioning information of the end position of each symbol in the valid data connected to the guide code sequence; according to the positioning information, a pulse sequence corresponding to the decision moment of symbol decoding of the valid data is determined; the symbol decoding module is used to perform symbol decoding on the valid data according to the decision moment and the pulse sequence.

[0007] In a preferred embodiment of the present invention, the symbol synchronization detection module includes: two groups of matched filters, a second peak detection module and a peak sorting module; the characteristic sequence of the second matched filter in the two groups of matched filters is symbol 0; the characteristic sequence of the third matched filter in the two groups of matched filters is symbol 1; the second matched filter is used to process the first valid data corresponding to the symbol 0 in the valid data to obtain a first waveform sequence; the third matched filter is used to process the second valid data corresponding to the symbol 1 in the valid data to obtain a second waveform sequence; the second peak detection module is used to detect the convolution peak of the first waveform sequence and the second waveform sequence; the peak sorting module is used to determine the effective peak of the convolution peak according to the starting position of the valid data and the symbol period; and according to the effective peak, determine the pulse sequence corresponding to the decision moment of the symbol decoding of the valid data.

[0008] In a preferred embodiment of the present invention, the above-mentioned second peak detection module includes: a first sub-symbol peak detection circuit and a second sub-symbol peak detection circuit; the above-mentioned first sub-symbol peak detection circuit is connected to the output end of the above-mentioned second matched filter; the above-mentioned second sub-symbol peak detection circuit is connected to the output end of the above-mentioned third matched filter; the above-mentioned first sub-symbol peak detection circuit is used to detect the first convolution peak of the above-mentioned first waveform sequence; the above-mentioned second sub-symbol peak detection circuit is used to detect the second convolution peak of the above-mentioned second waveform sequence; the above-mentioned peak sorting module is used to judge the above-mentioned effective peaks of the above-mentioned first convolution peak and the above-mentioned second convolution peak according to the starting position of the above-mentioned valid data and the symbol period.

[0009] In a preferred embodiment of the present invention, the above-mentioned circuit also includes: a peak detection threshold adjustment module connected to the input end of the above-mentioned second peak detection module and the output end of the above-mentioned first peak detection module; the above-mentioned peak detection threshold adjustment module is used to adjust the judgment lower limit of the position of the above-mentioned convolution peak based on the relationship between the preset SINR and the position change of the convolution peak of the above-mentioned first matched filter.

[0010] In a preferred embodiment of the present invention, the peak sorting module further includes: a clock data recovery module; the clock data recovery module is used to recover the symbol rate of the valid data so as to generate a pulse sequence corresponding to the decision moment of symbol decoding of the valid data at the end moment of each symbol in the valid data.

[0011] In a preferred embodiment of the present invention, the first peak detection module is used to determine the position of the convolution peak according to the monotonic inflection point of the convolution operation result.

[0012] In a preferred embodiment of the present invention, the first peak detection module is further used to derive the convolution operation result to obtain a derivative value; and determine the monotonic inflection point based on the derivative value.

[0013] In a preferred embodiment of the present invention, the above-mentioned first peak detection module includes: a register and an edge detection circuit; the above-mentioned register is used to delay the output of the above-mentioned convolution operation result by one clock cycle, and subtract the convolution operation results before and after the delay to obtain the difference; the above-mentioned edge detection circuit is used to determine the position of the convolution peak according to the above-mentioned difference.

[0014] In a preferred embodiment of the present invention, the above-mentioned guide code sequence includes a preamble code sequence and a postamble code sequence; the above-mentioned preamble code sequence is inverted to obtain the above-mentioned postamble code sequence.

[0015] In a second aspect, an embodiment of the present invention provides a control method for a digital receiver circuit, which is applied to the above-mentioned digital receiver circuit; the above-mentioned method includes: performing a convolution operation on a guide code sequence in a received synchronization signal through the above-mentioned first matched filter to obtain a convolution operation result; determining the position of the convolution peak according to the above-mentioned convolution operation result through the above-mentioned first peak detection module; determining the end position of the above-mentioned guide code sequence according to the position of the above-mentioned convolution peak; detecting the positioning information of the end position of each symbol in the valid data connected to the above-mentioned guide code sequence through the above-mentioned symbol synchronization detection module; determining the pulse sequence corresponding to the decision moment of symbol decoding of the above-mentioned valid data according to the above-mentioned positioning information; and performing symbol decoding on the above-mentioned valid data according to the above-mentioned decision moment and the above-mentioned pulse sequence through the above-mentioned symbol decoding module.

[0016] The embodiments of the present invention have the following beneficial technical effects:

[0017] The embodiment of the present invention provides a digital receiver circuit and a control method thereof, comprising: a connected frame synchronization detection module, a symbol synchronization detection module and a symbol decoding module; the frame synchronization detection module comprises: a first matched filter and a first peak detection module; the first matched filter is used to perform a convolution operation on a guide code sequence in a received synchronization signal to obtain a convolution operation result; the first peak detection module is used to determine the position of the convolution peak according to the convolution operation result; the end position of the guide code sequence is determined according to the position of the convolution peak; the symbol synchronization detection module is used to detect the positioning information of the end position of each symbol in the valid data connected to the guide code sequence; according to the positioning information, the pulse sequence corresponding to the decision moment of the symbol decoding of the valid data is determined; the symbol decoding module is used to perform symbol decoding on the valid data according to the decision moment and the pulse sequence. This technology uses a matched filter and a peak detection module to accurately detect the synchronization signal and the symbol position, thereby effectively suppressing noise and interference and improving the accuracy of signal detection and decoding. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 A schematic diagram of the structure of a digital receiver circuit provided by an embodiment of the present invention;

[0020] Figure 2 A schematic diagram of the structure of another digital receiver circuit provided by an embodiment of the present invention;

[0021] Figure 3 A schematic diagram of the structure of a conventional correlation receiver circuit provided by an embodiment of the present invention;

[0022] Figure 4 A schematic diagram of an improved correlation receiver circuit structure provided by an embodiment of the present invention;

[0023] Figure 5 A schematic flow chart of a control method for a digital receiver circuit provided by an embodiment of the present invention.

[0024] Icon: 10-Demod signal; 11-frame synchronization detection module; 12-symbol synchronization detection module; 13-symbol decoding module; 111-first matching filter; 112-first peak detection module; 122-second matching filter; 123-third matching filter; 21-first sub-symbol peak detection circuit; 22-second sub-symbol peak detection circuit; 23-peak sorting module; 24-peak detection threshold adjustment module. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0026] RFID tags need to be designed with low power consumption, so the digital demodulation and decoding algorithm of the receiver is relatively simple. If glitches appear in the demodulated signal output by the envelope detector, the decoding will be abnormal and the anti-interference ability will be weak. The tag receiving sensitivity is generally between -22dBm and -24dBm. However, tags usually use envelope detection as an analog demodulation circuit because of its simple circuit and low complexity. However, since the envelope detector is a nonlinear device, its anti-aliasing and anti-interference capabilities are weak. When there is strong interference in the communication environment or the channel is poor and the signal-to-noise ratio is low, the signal output by the detection circuit may have glitches or distortion, and the symbol period and duty cycle may also change. Therefore, it is urgent to provide a digital receiver circuit that improves the anti-interference capability of downlink reception to counteract the distortion or distortion of the output signal of the detection circuit caused by interference or noise in the communication environment.

[0027] Based on this, an embodiment of the present invention provides a digital receiver circuit and a control method thereof, which uses a matched filter and a peak detection module to accurately detect synchronization signals and symbol positions, thereby effectively suppressing noise and interference and improving the accuracy of signal detection and decoding. In order to facilitate understanding of the embodiment of the present invention, a digital receiver circuit is first introduced in detail.

[0028] Example 1

[0029] In an embodiment of the present invention, Figure 1 A schematic structural diagram of a digital receiver circuit provided by an embodiment of the present invention.

[0030] Depend on Figure 1As can be seen, the digital receiver circuit includes: a connected frame synchronization detection module 11, a symbol synchronization detection module 12 and a symbol decoding module 13; the frame synchronization detection module 11 includes: a first matched filter 111 and a first peak detection module 112; the first matched filter 111 is used to perform a convolution operation on the lead code sequence in the received synchronization signal to obtain a convolution operation result; the first peak detection module 112 is used to determine the position of the convolution peak according to the convolution operation result; determine the end position of the lead code sequence according to the position of the convolution peak; the symbol synchronization detection module 12 is used to detect the positioning information of the end position of each symbol in the valid data connected to the lead code sequence; determine the pulse sequence corresponding to the decision moment of the symbol decoding of the valid data according to the positioning information; the symbol decoding module 13 is used to perform symbol decoding on the valid data according to the decision moment and the pulse sequence.

[0031] Here, the first matched filter 111 is used to receive the Demod signal 10 .

[0032] In this embodiment, the amble sequence includes a preamble sequence and a postamble sequence; the preamble sequence is inverted to obtain the postamble sequence.

[0033] The embodiment of the present invention provides a digital receiver circuit, including: a connected frame synchronization detection module, a symbol synchronization detection module and a symbol decoding module; the frame synchronization detection module includes: a first matched filter and a first peak detection module; the first matched filter is used to perform a convolution operation on the lead code sequence in the received synchronization signal to obtain a convolution operation result; the first peak detection module is used to determine the position of the convolution peak according to the convolution operation result; the end position of the lead code sequence is determined according to the position of the convolution peak; the symbol synchronization detection module is used to detect the positioning information of the end position of each symbol in the valid data connected to the lead code sequence; according to the positioning information, the pulse sequence corresponding to the decision moment of the symbol decoding of the valid data is determined; the symbol decoding module is used to perform symbol decoding on the valid data according to the decision moment and the pulse sequence. This technology uses a matched filter and a peak detection module to accurately detect the synchronization signal and the symbol position, thereby effectively suppressing noise and interference and improving the accuracy of signal detection and decoding.

[0034] Example 2

[0035] Based on the above embodiments, Figure 2 A schematic structural diagram of another digital receiver circuit provided by an embodiment of the present invention.

[0036] Depend on Figure 2As can be seen, the digital receiver circuit includes: a connected frame synchronization detection module 11, a symbol synchronization detection module 12 and a symbol decoding module 13; the frame synchronization detection module 11 includes: a first matched filter 111 and a first peak detection module 112; the first matched filter 111 is used to perform a convolution operation on the lead code sequence in the received synchronization signal to obtain a convolution operation result; the first peak detection module 112 is used to determine the position of the convolution peak according to the convolution operation result; determine the end position of the lead code sequence according to the position of the convolution peak; the symbol synchronization detection module 12 is used to detect the positioning information of the end position of each symbol in the valid data connected to the lead code sequence; determine the pulse sequence corresponding to the decision moment of the symbol decoding of the valid data according to the positioning information; the symbol decoding module 13 is used to perform symbol decoding on the valid data according to the decision moment and the pulse sequence.

[0037] Among them, the above-mentioned symbol synchronization detection module 12 includes: two groups of matched filters, a second peak detection module and a peak sorting module 23; the characteristic sequence of the second matched filter 122 in the above-mentioned two groups of matched filters is symbol 0; the characteristic sequence of the third matched filter 123 in the above-mentioned two groups of matched filters is symbol 1; the above-mentioned second matched filter 122 is used to process the first valid data corresponding to the above-mentioned symbol 0 in the above-mentioned valid data to obtain a first waveform sequence; the above-mentioned third matched filter 123 is used to process the second valid data corresponding to the above-mentioned symbol 1 in the above-mentioned valid data to obtain a second waveform sequence; the above-mentioned second peak detection module is used to detect the convolution peak of the above-mentioned first waveform sequence and the above-mentioned second waveform sequence; the above-mentioned peak sorting module 23 is used to judge the effective peak of the above-mentioned convolution peak according to the starting position of the above-mentioned valid data and the symbol period; according to the above-mentioned effective peak, determine the pulse sequence corresponding to the decision moment of the symbol decoding of the above-mentioned valid data.

[0038] Furthermore, the above-mentioned second peak detection module includes: a first sub-symbol peak detection circuit 21 and a second sub-symbol peak detection circuit 22; the above-mentioned first sub-symbol peak detection circuit 21 is connected to the output end of the above-mentioned second matched filter 122; the above-mentioned second sub-symbol peak detection circuit 22 is connected to the output end of the above-mentioned third matched filter 123; the above-mentioned first sub-symbol peak detection circuit 21 is used to detect the first convolution peak of the above-mentioned first waveform sequence; the above-mentioned second sub-symbol peak detection circuit 22 is used to detect the second convolution peak of the above-mentioned second waveform sequence; the above-mentioned peak sorting module 23 is used to judge the above-mentioned effective peaks of the above-mentioned first convolution peak and the above-mentioned second convolution peak according to the starting position and symbol period of the above-mentioned valid data.

[0039] In actual operation, the above-mentioned circuit also includes: a peak detection threshold adjustment module 24 connected to the input end of the above-mentioned second peak detection module and the output end of the above-mentioned first peak detection module 112; the above-mentioned peak detection threshold adjustment module 24 is used to adjust the judgment lower limit of the position of the above-mentioned convolution peak based on the relationship between the preset SINR and the position change of the convolution peak of the above-mentioned first matching filter.

[0040] Furthermore, the peak sorting module 23 also includes: a clock data recovery module; the clock data recovery module is used to recover the symbol rate of the valid data, so as to generate a pulse sequence corresponding to the decision moment of the symbol decoding of the valid data at the end moment of each symbol in the valid data.

[0041] Furthermore, the first peak detection module 112 is used to determine the position of the convolution peak according to the monotonic inflection point of the convolution operation result.

[0042] Furthermore, the first peak detection module 112 is further configured to derive the convolution operation result to obtain a derivative value; and determine the monotonic inflection point according to the derivative value.

[0043] Among them, the above-mentioned first peak detection module 112 includes: a register and an edge detection circuit; the above-mentioned register is used to delay the output of the above-mentioned convolution operation result by one clock cycle, and subtract the convolution operation results before and after the delay to obtain the difference; the above-mentioned edge detection circuit is used to determine the position of the convolution peak according to the above-mentioned difference.

[0044] In actual operation, the first peak detection module 112 is used for frame synchronization detection. The output waveform of the first matched filter 111 is approximately a parabola. The vertex of the parabola represents the end position of the guide code in the downlink signaling. The end position of the guide code in the downlink signaling is found by locating the monotonic inflection point of the parabola.

[0045] Further, the above-mentioned second peak detection module is used for symbol synchronization detection, and the detection logic is the same as above. The end position of each symbol in the downlink signaling is found by locating the monotonic inflection point of the parabolic waveform output by the matched filter. The implementation method of the monotonic inflection point detection is to derive the output result of the matched filter. A positive derivative indicates monotonic increase, and a negative derivative indicates monotonic decrease. The monotonic inflection point is found according to the positive and negative transformation of the derivative. The implementation method of the derivation in the circuit is that after the data passes through the register, the value is stored and output after one clock cycle, and the value before and after the delay is made different. A positive value indicates monotonic increase, and a negative value indicates monotonic decrease. Then a monotonic indication signal is generated through combinational logic. When the monotonicity is positive, the signal is high level, and when the monotonicity is negative, the signal is low level. Then, through an edge detection circuit, the position of the falling edge of the signal is located. The falling edge position indicates the monotonic inflection point of the output waveform of the matched filter, that is, the peak position of the output waveform.

[0046] Furthermore, the peak detection threshold adjustment module 24 is used to adjust the judgment lower limit of the first peak detection module 112. Because the actual communication environment may deteriorate, the demod signal received by the DBB module may have burrs, signal distortion or distortion, which will cause the peak value of the output result of the matched filter to be lower than the ideal situation. At the same time, the output waveform of the first matched filter 111 may not be an approximate parabola, and multiple monotonic inflection points may appear. If the judgment threshold of the peak detection is not set, misjudgment or missed judgment may occur. The present application preliminarily simulates the peak change of the first matched filter 111 under different SINR conditions, and designs the dynamic adjustment logic of the peak detection threshold to ensure that after the communication environment deteriorates, the digital receiver can dynamically adjust the anti-interference performance of frame synchronization and symbol synchronization. The peak point of the first matched filter 111 and the peak points of the above two groups of matched filters have a linear relationship with the SINR change. Therefore, in the specific circuit implementation, a mapping table is used to map and search the peak point of the first peak detection module 112 and the judgment threshold of the second peak detection module to ensure that under different SINR conditions, the judgment threshold of the peak detection of the second peak detection module can be adjusted according to the value of the peak point of the first peak detection module 112.

[0047] Furthermore, the clock data recovery module is used to recover the clock, and what is recovered here is the symbol rate, that is, a valid pulse signal is generated at the end time of each symbol in the valid data. The valid pulse signal comes from the peak sequence collection of the output waveforms of the two-way symbol matching filter, which contains the valid peak at the end time of the corresponding symbol. The above algorithm is converted into a circuit implementation, and the valid peak in the peak sequence sum is identified, which is used as the symbol optimal decision time for symbol decoding. In the circuit, the start and end positions of the data payload are found through frame synchronization, and an indication signal is used to indicate the valid start and end positions of the payload, called the en signal. When the en signal is high, it indicates that the payload signal is valid, and when the en signal is low, it indicates that the payload signal is invalid. In addition, a symbol length counter is defined, and the counter is turned on at the rising edge of the en signal. The counting length is the symbol period length. Whenever the counter counts a full symbol period, an indication signal (temporarily called cnt_done) is started. In theory, there should be a valid peak point of the matched filter output signal near this indication signal (several sampling periods before and after). By combining logic and timing circuits, a valid symbol peak detection enable signal (temporarily called symbol_valid_interval) is generated, which is set to high level in the clock cycles before and after the cnt_done signal, and low level at other times. The signal and the peak sequence collection are logically ANDed, and a truly valid symbol optimal decision time can be screened out through an AND gate circuit.

[0048] In actual operation, the anti-interference capability is mainly achieved by the first matched filter 111, the second matched filter 122, the third matched filter 123, the first peak detection module 112, the second peak detection module and the peak detection threshold adjustment module 24. The matched filter and the peak detection ensure that the maximum signal-to-noise ratio or the minimum bit error rate is achieved at the sampling moment, and the peak detection threshold adjustment module 24 ensures that when the communication environment changes and the channel quality fluctuates, when the convolution peak fluctuates, the change of the maximum signal-to-noise ratio is tracked, and the decoding threshold is dynamically adjusted accordingly.

[0049] Furthermore, the decoding module 13 is connected to a correlation receiver, which makes a decision on the output results of the two matched filters at the best decision time, when the sampling time has the maximum signal-to-noise ratio or the minimum bit error rate. The algorithm and circuit implementation of the correlation receiver are optimized. The conventional structure of the correlation receiver is a FIR filter, which convolves the input data and the local correlation sequence based on a tapped delay line, and the circuit includes a shift register, a multiplier and an adder. For ease of understanding, Figure 3 A schematic structural diagram of a conventional correlation receiver circuit provided by an embodiment of the present invention.

[0050] This application optimizes the circuit structure of the above-mentioned receiver, and the multiplier of the above-mentioned receiver is replaced by an XOR gate. For ease of understanding, Figure 4 A schematic diagram of an improved correlation receiver circuit structure provided by an embodiment of the present invention.

[0051] The embodiment of the present invention provides a digital receiver circuit, comprising: a frame synchronization detection module, a symbol synchronization detection module and a symbol decoding module connected to each other; the frame synchronization detection module comprises: a first matched filter and a first peak detection module; the first matched filter is used to perform a convolution operation on a guide code sequence in a received synchronization signal to obtain a convolution operation result; the first peak detection module is used to determine the position of a convolution peak according to the convolution operation result; the end position of the guide code sequence is determined according to the position of the convolution peak; the symbol synchronization detection module is used to detect the positioning information of the end position of each symbol in the valid data connected to the guide code sequence; according to the positioning information, a pulse sequence corresponding to the decision moment of symbol decoding of the valid data is determined; the symbol decoding module is used to perform symbol decoding on the valid data according to the decision moment and the pulse sequence; In the invention, the symbol synchronization detection module includes: two groups of matched filters, a second peak detection module and a peak sorting module; the characteristic sequence of the second matched filter in the two groups of matched filters is symbol 0; the characteristic sequence of the third matched filter in the two groups of matched filters is symbol 1; the second matched filter is used to process the first valid data corresponding to the symbol 0 in the valid data to obtain the first waveform sequence; the third matched filter is used to process the second valid data corresponding to the symbol 1 in the valid data to obtain the second waveform sequence; the second peak detection module is used to detect the convolution peak of the first waveform sequence and the second waveform sequence; the peak sorting module is used to determine the effective peak of the convolution peak according to the starting position and symbol period of the valid data; according to the effective peak, determine the pulse sequence corresponding to the decision moment of the symbol decoding of the valid data. This technology uses multi-stage matched filters and peak detection modules to more accurately detect synchronization signals and symbol positions, thereby effectively suppressing noise and interference, and further improving the accuracy of signal detection and decoding.

[0052] Example 3

[0053] Based on the above embodiments, Figure 5 A schematic flow chart of a control method for a digital receiver circuit provided by an embodiment of the present invention.

[0054] The method is applied to the digital receiver circuit of the above embodiment.

[0055] Depend on Figure 5 As can be seen, the method includes:

[0056] Step S101: performing a convolution operation on the guide code sequence in the received synchronization signal through the first matched filter to obtain a convolution operation result.

[0057] Step S102: determining the position of the convolution peak according to the convolution operation result through the first peak detection module; and determining the end position of the guide code sequence according to the position of the convolution peak.

[0058] Step S103: Detect the positioning information of the end position of each symbol in the valid data connected to the above-mentioned guide code sequence through the above-mentioned symbol synchronization detection module; determine the pulse sequence corresponding to the decision time of symbol decoding of the above-mentioned valid data according to the above-mentioned positioning information.

[0059] Step S104: the symbol decoding module performs symbol decoding on the valid data according to the decision time and the pulse sequence.

[0060] An embodiment of the present invention provides a control method for a digital receiver circuit, and its implementation principle and technical effects are the same as those of the aforementioned digital receiver circuit embodiment. For the sake of brief description, for parts not mentioned in the embodiment of the control method for the aforementioned digital receiver circuit, reference may be made to the corresponding contents in the aforementioned digital receiver circuit embodiment.

[0061] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0062] In addition, in the description of the embodiments of the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0063] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0064] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present invention, which are used to illustrate the technical solutions of the present invention rather than to limit them. The protection scope of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the aforementioned embodiments, those of ordinary skill in the art should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the aforementioned embodiments within the technical scope disclosed by the present invention, or can easily conceive of changes, or make equivalent replacements for some of the technical features therein. Such modifications, changes or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered within the protection scope of the present invention.

Claims

1. A digital receiver circuit, characterized in that: include: A connected frame synchronization detection module, a symbol synchronization detection module and a symbol decoding module; The frame synchronization detection module includes: a first matched filter and a first peak detection module; The first matched filter is used to perform a convolution operation on the guide code sequence in the received synchronization signal to obtain a convolution operation result; The first peak detection module is used to determine the position of the convolution peak according to the convolution operation result; and determine the end position of the guide code sequence according to the position of the convolution peak; The symbol synchronization detection module is used to detect the positioning information of the end position of each symbol in the valid data connected to the guide code sequence; according to the positioning information, determine the pulse sequence corresponding to the decision time of the symbol decoding of the valid data; The symbol decoding module is used to perform symbol decoding on the valid data according to the decision time and the pulse sequence.

2. The digital receiver circuit according to claim 1, characterized in that The symbol synchronization detection module includes: two groups of matched filters, a second peak detection module and a peak sorting module; the characteristic sequence of the second matched filter in the two groups of matched filters is symbol 0; the characteristic sequence of the third matched filter in the two groups of matched filters is symbol 1; The second matched filter is used to process the first valid data corresponding to the symbol 0 in the valid data to obtain a first waveform sequence; The third matched filter is used to process the second valid data corresponding to the symbol 1 in the valid data to obtain a second waveform sequence; The second peak detection module is used to detect the convolution peaks of the first waveform sequence and the second waveform sequence; The peak sorting module is used to determine the effective peak value of the convolution peak according to the starting position of the effective data and the symbol period; and determine the pulse sequence corresponding to the decision moment of the symbol decoding of the effective data according to the effective peak value.

3. The digital receiver circuit according to claim 2, characterized in that: The second peak detection module includes: a first sub-symbol peak detection circuit and a second sub-symbol peak detection circuit; the first sub-symbol peak detection circuit is connected to the output end of the second matched filter; the second sub-symbol peak detection circuit is connected to the output end of the third matched filter; The first sub-symbol peak detection circuit is used to detect a first convolution peak of the first waveform sequence; The second sub-symbol peak detection circuit is used to detect a second convolution peak of the second waveform sequence; The peak sorting module is used to determine the effective peak values ​​of the first convolution peak value and the second convolution peak value according to the starting position and symbol period of the effective data.

4. The digital receiver circuit according to claim 2, characterized in that The circuit further comprises: a peak detection threshold adjustment module connected to both the input end of the second peak detection module and the output end of the first peak detection module; The peak detection threshold adjustment module is used to adjust the lower limit of the position of the convolution peak based on the relationship between the preset SINR and the position change of the convolution peak of the first matched filter.

5. The digital receiver circuit according to claim 2, characterized in that: The peak sorting module also includes: a clock data recovery module; The clock data recovery module is used to recover the symbol rate of the valid data, so as to generate a pulse sequence corresponding to the decision time of symbol decoding of the valid data at the end time of each symbol in the valid data.

6. The digital receiver circuit according to claim 1, characterized in that The first peak detection module is used to determine the position of the convolution peak according to the monotonic inflection point of the convolution operation result.

7. The digital receiver circuit according to claim 6, characterized in that The first peak detection module is further used to derive the convolution operation result to obtain a derivative value; and determine the monotonic inflection point according to the derivative value.

8. The digital receiver circuit according to claim 7, characterized in that: The first peak detection module includes: a register and an edge detection circuit; The register is used to delay the output of the convolution operation result by one clock cycle, and to obtain the difference by subtracting the convolution operation results before and after the delay; The edge detection circuit is used to determine the position of the convolution peak according to the difference.

9. The digital receiver circuit according to claim 1, characterized in that: The guide code sequence includes a preamble code sequence and a postamble code sequence; the preamble code sequence is inverted to obtain the postamble code sequence.

10. A control method for a digital receiver circuit, characterized in that: The digital receiver circuit as claimed in any one of claims 1 to 9; the method comprising: Performing a convolution operation on the guide code sequence in the received synchronization signal through the first matched filter to obtain a convolution operation result; Determine the position of the convolution peak according to the convolution operation result through the first peak detection module; determine the end position of the guide code sequence according to the position of the convolution peak; Detecting the positioning information of the end position of each symbol in the valid data connected to the guide code sequence through the symbol synchronization detection module; determining the pulse sequence corresponding to the decision time of symbol decoding of the valid data according to the positioning information; The symbol decoding module performs symbol decoding on the valid data according to the decision time and the pulse sequence.

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