A device and method for realizing wireless high-precision time synchronization based on FPGA

Abstract

The application discloses a device for realizing wireless high-precision time synchronization based on FPGA, and discloses a method for realizing wireless high-precision time synchronization based on FPGA. The method for recording time stamp by hardware at the FPGA end can strictly control the time sequence and eliminate the sending time delay. In addition, by making the position for recording the sending time stamp close to the radio frequency end, the accumulated time delay caused by the sending processing time delay and the delay uncertainty caused by processing data across the clock domain can be reduced. Finally, by adopting the sequence detection method after the matching filter module, the time when the time stamp of the receiving end arrives can be determined for the first time, so that the uncertainty time delay caused by the algorithm existing in the receiving processing can be reduced.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of time synchronization, and particularly relates to a device for realizing wireless high-precision time synchronization based on FPGA, and a method for realizing wireless high-precision time synchronization based on FPGA. BACKGROUND

[0002] The process of unifying clocks in different places to standard time through the transmission of standard time information is called time service. With the increasing demand for time, the time measurement method has developed from astronomical time measurement to atomic time, and the time service precision has developed from the order of seconds and milliseconds to the order of nanoseconds, sub-nanoseconds and even higher. High-precision time reference is crucial to the aerospace, navigation, guidance and other cutting-edge industries, and also plays a key role in modern warfare. At present, the high-precision wireless time synchronization scheme mainly relies on satellite time service, but the satellite reconstruction and maintenance cost is high, and the satellite signal cannot work normally in the satellite denial environment. These limitations have prompted researchers to explore more flexible and economical solutions, among which wireless time synchronization technology has gradually become an important research direction.

[0003] Software radio has the advantages of flexible radio frequency end, among which AD9361 is a high-performance radio frequency transceiver chip launched by ADI Company in the United States. It is mainly used to provide a good application scheme for 3G and 4G communication base stations and device terminals, and has the advantages of high integration, low power consumption, good programmability, and support for large bandwidth. AD9361 integrates the frequency synthesizer, low-noise amplifier, analog filter, mixer, digital-to-analog and analog-to-digital converter of the radio frequency transceiver channel into a small chip, which contains most of the processing modules required for the conversion from digital baseband signal to radio frequency analog signal.

[0004] Among them, the timestamp is used to mark the key moment of the node in processing related frame data, and the timestamp can be marked at the network layer, the MAC layer and the physical layer. The influence of the corresponding precision of the timestamp marking at different levels is also different. Therefore, when marking the timestamp at the physical layer, the closer the position of the timestamp to the radio frequency front end of the sending end and the receiving end, the less the delay and uncertainty caused by other intermediate modules in the transmission link, and the more accurately the actual sending or receiving time is reflected. In addition, the method of bit synchronization and sequence detection can also improve the accuracy of the received timestamp, thereby improving the master-slave time synchronization precision of wireless time synchronization to a certain extent. SUMMARY

[0005] The application aims at the above-mentioned problems existing in the prior art, and provides a device for realizing wireless high-precision time synchronization based on FPGA, and a method for realizing wireless high-precision time synchronization based on FPGA.

[0006] The above object of the present application is achieved by the following technical means:

[0007] A device for realizing wireless high-precision time synchronization based on FPGA, comprising a master end and a slave end, wherein the master end and the slave end each comprise a sending link, a receiving link and a radio frequency transceiver;

[0008] The sending link comprises a real-time clock module, a QPSK baseband modulation module, a first sequence detection module and a first intermediate frequency module; the real-time clock module generates a message carrying timestamp data; the message carrying timestamp data passes through the QPSK baseband modulation module to obtain I branch baseband transmission data and Q branch baseband transmission data; the I branch baseband transmission data and the Q branch baseband transmission data pass through the first intermediate frequency module to obtain I branch intermediate frequency transmission data and Q branch intermediate frequency transmission data; the I branch intermediate frequency transmission data and the Q branch intermediate frequency transmission data pass through the radio frequency transceiver to obtain I branch radio frequency transmission signals and Q branch radio frequency transmission signals respectively and are then transmitted respectively;

[0009] The first sequence detection module detects and records the arrival time of the I branch baseband transmission data or the Q branch baseband transmission data in the sending link as the arrival time of the message in the sending link;

[0010] The receiving link comprises a second intermediate frequency module, a matched filter module, a QPSK baseband demodulation module and a second sequence detection module; the radio frequency transceiver receives I branch radio frequency receiving signals and Q branch radio frequency receiving signals and then performs frequency conversion to obtain I branch intermediate frequency receiving signals and Q branch intermediate frequency receiving signals; the I branch intermediate frequency receiving signals and the Q branch intermediate frequency receiving signals pass through the second intermediate frequency module and the matched filter module in sequence to obtain I branch baseband receiving data and Q branch baseband receiving data; the I branch baseband receiving data and the Q branch baseband receiving data pass through the QPSK baseband demodulation module to obtain a timestamp;

[0011] The second sequence detection module detects and records the arrival time of the I branch baseband receiving data or the Q branch baseband receiving data in the receiving link as the arrival time of the message in the receiving link.

[0012] The QPSK baseband modulation module comprises a differential encoding module, a serial-to-parallel conversion module and a shaping filter module; the message carrying timestamp data passes through the differential encoding module, the serial-to-parallel conversion module and the shaping filter module in sequence to obtain I branch baseband data and Q branch baseband data.

[0013] The QPSK baseband demodulation module comprises a carrier synchronization module, a bit synchronization module, a data merging module and a data decision module; the I branch baseband receiving data and the Q branch baseband receiving data pass through the carrier synchronization module, the bit synchronization module, the data merging module and the data decision module in sequence to obtain a timestamp.

[0014] The receiving link of the slave end also comprises a difference calculation module which calculates the delay of the transmitting link and the receiving link.

[0015] A method for realizing wireless high-precision time synchronization based on FPGA, using a device for realizing wireless high-precision time synchronization based on FPGA as described above, comprising the following steps:

[0016] Step 1: setting the format of the message carrying timestamp data generated by the real-time clock module of the master end and the slave end, and setting the first bit of the frame header of the message to 1;

[0017] Step 2: the transmitting link of the master end generates and transmits the first frame message, and detects and records the arrival time t1 of the first frame message;

[0018] Step 3: the transmitting link of the master end generates the second frame message carrying the arrival time t1, and transmits the second frame message after a set delay time;

[0019] Step 4: the receiving link of the slave end detects and records the arrival time t2 of the first frame message; the receiving link of the slave end receives the second frame message and decodes the arrival time t1 carried in the second frame message;

[0020] Step 5: the transmitting link of the slave end generates and transmits the third frame message carrying the arrival time t2, and detects and records the arrival time t3 of the third frame message;

[0021] Step 6: the receiving link of the master end detects and records the arrival time t4 of the third frame message, and then the transmitting link of the master end generates and transmits the fourth frame message carrying the arrival time t4;

[0022] Step 7: the receiving link of the slave end receives the fourth frame message and decodes the arrival time t1 carried in the fourth frame message, and finally the slave end calculates the clock offset according to the recorded arrival times t1, t2, t3 and t4, and finally calibrates the clock of the slave end according to the calculated clock offset;

[0023] The clock offset is calculated based on the following formula:

[0024] offset=[(t1-t2)+(t4-t3)] / 2

[0025] In the formula, offset is the clock offset, and / is the division sign;

[0026] Step 8: the master end and the slave end start the 1s counter at the same time, and repeat steps 1-7 every second, with 1s as the period, to calibrate the clock of the slave end every second.

[0027] The format of the message in step 1 includes frame header, type, synchronization period number, synchronization message, synchronization message check, timestamp data, timestamp data check 1, and timestamp data check 2.

[0028] The sending link of the master end in step 2 or the sending link of the slave end in step 5 detects the arrival time of the message by the following method:

[0029] First, the real-time clock module of the sending link sets a flag data_flag, then generates and sends the first frame message, and pulls up the level of the flag data_flag;

[0030] Secondly, the first sequence detection module of the sending link sets a flag mod_flag, the first sequence detection module of the sending link detects and records the arrival time of the first falling edge after the level of data_flag is pulled up, obtains the current timestamp as the arrival time corresponding to the message, and then pulls up the level of the flag mod_flag of the first sequence detection module of the sending link.

[0031] The receiving link of the slave end in step 4 and the receiving link of the slave end in step 6 detect and record the arrival time of the message by the following method:

[0032] First, the matched filter module of the receiving link obtains the best decision point sync_flag through the garden ring bit synchronization, and detects the valid data of the message by using the best decision point sync_flag, when the valid data of the message is detected, each bit of the message is sent to the second sequence detection module;

[0033] Secondly, the second sequence detection module of the receiving link sets a flag demod_flag, the second sequence detection module of the receiving link detects the entire data sequence of the frame header of the message through a state machine, when the frame header of the message is detected, the level of the flag demod_flag is pulled up, and the current timestamp is recorded as the arrival time corresponding to the message;

[0034] Finally, the data decision module of the receiving link detects that the frame header, the timestamp data check 1 and the timestamp data check 2 are all correct, so that the arrival time recorded by the second sequence detection module of the receiving link is valid.

[0035] Compared with the prior art, the present application has the following beneficial effects:

[0036] The application can strictly control time sequence, eliminate sending delay by using the method of recording time stamp by hardware, in addition, by making the position of recording sending time stamp close to radio frequency end, the accumulated delay caused by sending processing delay and the delay uncertainty caused by processing data cross clock domain can be reduced. Finally, by using sequence detection method after matching filter module, the time when the time stamp of receiving link arrives can be determined for the first time, which can reduce the uncertainty delay caused by algorithm in receiving processing. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1 Structure diagram of the device of the application;

[0038] Figure 2 Structure diagram of the packet format of embodiment 2 of the application;

[0039] Figure 3 Corresponding relationship diagram of I branch transmitting data and I branch base frequency transmitting data I_filtered after the shaping filter module of the application;

[0040] Figure 4 Detection diagram of the time t1 in embodiment 2 of the application;

[0041] Figure 5 Detection diagram of the time t2 in embodiment 3 of the application (state is the state bit of state machine);

[0042] Figure 6 Principle diagram of calculating clock deviation of the application;

[0043] Figure 7 State transition diagram of state machine when the first frame packet is detected by the second sequence detection module of the end in embodiment 3 of the application;

[0044] Reference signs and corresponding component names:

[0045] 1-real time clock module; 2-differential encoding module; 3-serial to parallel conversion module; 4-shaping filter module; 5-first sequence detection module; 6-first intermediate frequency module; 7-radio frequency transceiver; 8-second intermediate frequency module; 9-matching filter module; 11-second sequence detection module; 10-carrier synchronization module; 12-bit synchronization module; 13-data merging module; 14-data decision module; 15-difference calculation module. DETAILED DESCRIPTION

[0046] In order to facilitate those skilled in the art to understand and implement the application, the application is further described in detail below in combination with embodiments, and the embodiments described herein are only used to illustrate and explain the application, and are not a limitation on the application.

[0047] Embodiment 1

[0048] The device for realizing wireless high-precision time synchronization based on FPGA comprises a master end (Master) and a slave end (Slave), and the master end and the slave end each comprise an AD9361 sending link, an AD9361 receiving link, and a radio frequency transceiver 7;

[0049] In this embodiment, the radio frequency transceiver 7 of the master end and the slave end each adopts an AD9361 chip;

[0050] The sending link comprises a real-time clock module 1, a QPSK base frequency modulation module, a first sequence detection module 5, and a first intermediate frequency module 6; the real-time clock module 1 generates a message para_Tx carrying timestamp data, the message para_Tx carrying timestamp data passes through the QPSK base frequency modulation module to obtain I branch base frequency transmission data I_filtered and Q branch base frequency transmission data Q_filtered, the I branch base frequency transmission data I_filtered and the Q branch base frequency transmission data Q_filtered pass through the first intermediate frequency module 6 respectively to obtain I branch intermediate frequency transmission data qpsk_i and Q branch intermediate frequency transmission data qpsk_q (specifically, the first intermediate frequency module 6 multiplies the I branch intermediate frequency transmission data I_filtered by a cos carrier signal to obtain the I branch intermediate frequency transmission data qpsk_i, and multiplies the I branch base frequency transmission data Q_filtered by a sin carrier signal to obtain the Q branch intermediate frequency transmission data qpsk_q), the I branch intermediate frequency transmission data and the Q branch intermediate frequency transmission data pass through the radio frequency transceiver 7 respectively to be up-converted to obtain I branch radio frequency transmission signals and Q branch radio frequency transmission signals, and then are respectively transmitted;

[0051] The QPSK baseband modulation module includes a differential encoding module 2, a serial-to-parallel conversion module 3, and a shaping filter module 4. The real-time clock module 1 generates a message para_Tx carrying timestamp data and outputs it to the differential encoding module 2. The differential encoding module 2 obtains a data frame para_in by differentially encoding the input data stream, and inputs the data frame para_in to the serial-to-parallel conversion module 3. The serial-to-parallel conversion module 3 converts the parallel data into serial data, and divides the serial data into orthogonal and codirectional data according to the parity position in the converted serial data, and performs bipolar conversion respectively to obtain I branch transmission data and Q branch transmission data. The serial-to-parallel conversion module 3 inputs the I branch transmission data and the Q branch transmission data into the shaping filter module 4 respectively, and the shaping filter module 4 filters the I branch transmission data and the Q branch transmission data respectively, wherein the shaping filter module 4 filters the I branch transmission data to obtain the I branch baseband transmission data I_filtered, and the shaping filter module 4 filters the Q branch data to obtain the Q branch baseband transmission data Q_filtered. The shaping filter module 4 inputs the I branch baseband transmission data I_filtered and the Q branch baseband transmission data Q_filtered into the first intermediate frequency module 6 respectively.

[0052] The first sequence detection module 5 detects and records the arrival time of the I-branch baseband transmission data I_filtered or the Q-branch baseband transmission data Q_filtered in the transmission link as the arrival time of the message in the transmission link;

[0053] The receiving chain includes a second intermediate frequency module 8, a matched filter module 9, a QPSK baseband demodulation module, and a second sequence detection module 11. The RF transceiver 7 receives the I branch RF receiving signal and the Q branch RF receiving signal and performs down-conversion respectively to obtain the I branch intermediate frequency receiving signal qpsk_i′ and the Q branch intermediate frequency receiving signal qpsk_q′. The I branch intermediate frequency receiving signal qpsk_i′ and the Q branch intermediate frequency receiving signal qpsk_q′ respectively pass through the second intermediate frequency module 8 and the matched filter module 9 to obtain the I branch baseband receiving data I′_filtered and the Q branch baseband receiving data Q′_fi ltered (specifically: the second intermediate frequency module 8 multiplies the I branch intermediate frequency receiving signal qpsk_i′ by the cos carrier signal and then inputs the signal obtained by filtering into the matched filter module 9 to obtain the I branch baseband receiving data I′_filtered, and multiplies the Q branch intermediate frequency receiving signal qpsk_q′ by the sin carrier signal and then inputs the signal obtained by multiplying the Q branch intermediate frequency receiving signal qpsk_q′ by the sin carrier signal into the matched filter module 9 to obtain the Q branch baseband receiving data Q′_filtered), the I branch baseband receiving data I′_filtered and the Q branch baseband receiving data Q′_filtered are timestamped by the QPSK baseband demodulation module;

[0054] The QPSK base frequency demodulation module comprises a carrier synchronization module 10, a bit synchronization module 12, a data merging module 13, and a data decision module 14, and the I branch base frequency received data and the Q branch base frequency received data sequentially pass through the carrier synchronization module 10, the bit synchronization module 12, the data merging module 13, and the data decision module 14 to obtain a timestamp;

[0055] Due to the boot-up time of the sending link or the receiving link, or the crystal oscillator offset, or the environmental influence in actual communication, it is necessary to perform phase discrimination and loop filtering processing on the I branch base frequency received data I'_filtered and the Q branch base frequency received data Q'_filtered, so the matching filter module 9 inputs the I branch base frequency received data I'_filtered and the Q branch base frequency received data Q'_filtered into the carrier synchronization module 10 to obtain I branch demodulation signals and Q branch demodulation signals, and then inputs the I branch demodulation signals and the Q branch demodulation signals into the bit synchronization module 12 to obtain accurate I branch single-bit data and Q branch single-bit data, and inputs the I branch single-bit data and the Q branch single-bit data into the data merging module 13 to merge them into a data frame, and inputs the merged data frame into the data decision module 14, and the data decision module 14 resolves the arrival time carried in the merged data frame, and judges the frame header, the timestamp data check 1, the timestamp data check 2, and the timestamp data check of the merged data frame.

[0056] The second sequence detection module 11 detects and records the arrival time of the I branch base frequency received data I'_filtered or the Q branch base frequency received data I'_filtered in the receiving link as the arrival time of the message in the receiving link.

[0057] The receiving link of the slave end further comprises a difference calculation module 15, the input end of the difference calculation module 15 is connected with the output ends of the first sequence detection module 5 of the slave end and the second sequence detection module 11 of the slave end, and the difference calculation module 15 calculates the delay of the sending link and the receiving link.

[0058] The first sequence detection module 5 is added in the QPSK base frequency modulation, the I branch base frequency transmitted data I_filtered (or the Q branch base frequency transmitted data Q_filtered) is detected through the first sequence detection module 5, when the I branch base frequency transmitted data I_filtered (or the Q branch base frequency transmitted data Q_filtered) is detected, the arrival time of the I branch base frequency transmitted data I_filtered (or the Q branch base frequency transmitted data Q_filtered) is recorded;

[0059] The first sequence detection module 5 of the application only needs to detect one of the I branch base frequency transmission data I_filtered and the Q branch base frequency transmission data Q_filtered, so as to obtain the data frame position at this time, because the timing of the I branch base frequency transmission data I_filtered and the Q branch base frequency transmission data Q_filtered is aligned, thus they are arrived at the same time, and the frame header of the two signals of the I branch base frequency transmission data I_filtered and the Q branch base frequency transmission data Q_filtered is also the same, thus only one of them needs to be detected.

[0060] Embodiment 2

[0061] A method for realizing wireless high-precision time synchronization based on FPGA, using the device for realizing wireless high-precision time synchronization based on FPGA in the above embodiment 1, comprising the following steps:

[0062] Step 1, setting the format of the message carrying timestamp data generated by the real-time clock module 1 of the master and slave, and setting the first bit data of the frame header of the message as 1;

[0063] The message in this embodiment is 180 bits (bits), and the message includes a 16-bit frame header, a 2-bit type, a 10-bit synchronization period number, a 64-bit synchronization message, an 8-bit synchronization message check, a 64-bit timestamp data, an 8-bit timestamp data check 1, and an 8-bit timestamp data check 2. The 2-bit type is used to indicate which frame message it is, wherein 00 represents the first frame message (First frame), 01 represents the second frame message (Second frame), 10 represents the third frame message (Third Frame), and 11 represents the fourth frame message (Fourth frame).

[0064] The application sends invalid data 0 when no message is sent.

[0065] Step 2, the sending link of the master generates and sends the first frame message, and detects and records the arrival time t1 of the first frame message, which specifically comprises the following steps:

[0066] The arrival time t1 is the time when the first frame message arrives at the first sequence detection module 5 of the sending link of the master;

[0067] Step 2.1, the real-time clock module 1 of the sending link of the master sets a flag data_flag, then generates and sends the first frame message, and pulls up the level of the flag data_flag of the real-time clock module 1 of the sending link of the master;

[0068] Step 2.2, the first sequence detection module 5 of the sending link of the master end sets a flag mod_flag, the first sequence detection module 5 of the sending link of the master end detects and records the arrival time of the first falling edge of the level pull-up of the flag data_flag of the real-time clock module 1 of the sending link of the master end, and acquires the current time stamp as the arrival time t1 of the first frame packet, and then pulls up the level of the flag mod_flag of the first sequence detection module 5 of the sending link of the master end.

[0069] Step 3, the sending link of the master end generates a second frame packet carrying the arrival time t1, and sends the second frame packet after a set delay time;

[0070] Step 4, the receiving link of the slave end detects and records the arrival time t2 of the first frame packet; the receiving link of the slave end receives the second frame packet, and decodes the arrival time t1 carried in the second frame packet, which specifically includes the following steps:

[0071] The arrival time t2 is the time when the first frame packet arrives the second sequence detection module 11 of the receiving link of the slave end;

[0072] Step 4.1, the matching filter module 9 of the receiving link of the slave end obtains the best decision point sync_flag through the garden ring bit synchronization, and detects the valid data of the first frame packet by using the best decision point sync_flag, and when the valid data of the first frame packet is detected, sends each bit of data of the first frame packet to the second sequence detection module 11 of the receiving link of the slave end;

[0073] Step 4.2, the second sequence detection module 11 of the receiving link of the slave end sets a flag demod_flag, and the second sequence detection module 11 of the receiving link of the slave end detects the entire data sequence of the frame header of the first frame packet through a state machine, and when the frame header of the first frame packet is detected, pulls up the level of the flag demod_flag of the second sequence detection module 11 of the receiving link of the slave end, and records the current time stamp as the arrival time t2 of the first frame packet;

[0074] Step 4.3, the data decision module 14 of the receiving link of the slave end detects that the frame header, the timestamp data check 1 and the timestamp data check 2 of the first frame packet are all correct, so that the arrival time t2 of the first frame packet recorded by the second sequence detection module 11 of the receiving link of the slave end is valid;

[0075] Step 4.4, the data decision module 14 of the receiving link of the slave end decodes the arrival time t1 carried in the second frame packet.

[0076] Step 5, the sending link of the slave end generates and sends the third frame message carrying the arrival time t2, and detects and records the arrival time t3 of the third frame message, specifically including the following steps:

[0077] The arrival time t3 is the time when the third frame message arrives the first sequence detection module 5 of the sending link of the slave end;

[0078] Step 5.1, the real-time clock module 1 of the sending link of the slave end sets a flag data_flag, then generates and sends the third frame message, and pulls up the level of the flag data_flag of the real-time clock module 1 of the sending link of the slave end;

[0079] Step 5.2, the first sequence detection module 5 of the sending link of the slave end sets a flag mod_flag, the first sequence detection module 5 of the sending link of the slave end detects and records the arrival time of the first falling edge after the level of the flag data_flag of the real-time clock module 1 of the sending link of the slave end is pulled up, obtains the current time stamp as the arrival time t3 of the third frame message, and then pulls up the level of the flag mod_flag of the first sequence detection module 5 of the sending link of the slave end.

[0080] Step 6, the receiving link of the master end detects and records the arrival time t4 of the third frame message, then the sending link of the master end generates and sends the fourth frame message carrying the arrival time t4, specifically including the following steps:

[0081] The arrival time t4 is the time when the third frame message arrives the second sequence detection module 11 of the receiving link of the master end;

[0082] Step 6.1, the matched filter module 9 of the receiving link of the master end obtains the best decision point sync_flag through the garden ring bit synchronization, and detects the valid data of the third frame message by using the best decision point sync_flag, when the valid data of the third frame message is detected, sends each bit of data of the third frame message to the second sequence detection module 11 of the receiving link of the master end;

[0083] Step 6.2, the second sequence detection module 11 of the receiving link of the master end sets a flag demod_flag, and the second sequence detection module 11 of the receiving link of the master end detects the entire data sequence of the frame header of the third frame message through a state machine, when the frame header of the third frame message is detected, pulls up the level of the flag demod_flag of the second sequence detection module 11 of the receiving link of the master end, and records the current time stamp as the arrival time t4 of the third frame message;

[0084] Step 6.3, the data decision module 14 of the receiving link of the master end detects that the frame header, the time stamp data check 1 and the time stamp data check 2 of the third frame packet are all correct, and then the second sequence detection module 11 of the receiving link of the master end records the arrival time t4 of the third frame packet;

[0085] Step 6.4, the sending link of the master end generates and sends the fourth frame packet carrying the arrival time t4.

[0086] Step 7, the receiving link of the slave end receives the fourth frame packet and decodes the arrival time t1 carried in the fourth frame packet, and finally the slave end calculates the clock offset according to the recorded arrival times t1, t2, t3 and t4, and finally calibrates the clock of the slave end according to the calculated clock offset;

[0087] The clock offset is calculated based on the following formula:

[0088] offset = [(t1-t2)+(t4-t3)] / 2 Formula (1)

[0089] In the formula, offset is the clock offset, and / is the division sign.

[0090] Step 8, the master end and the slave end start the 1s counter at the same time, and repeat steps 1-7 every 1s, so as to ensure the time synchronization between the master end and the slave end.

[0091] Wherein, when the third frame packet carrying the arrival time is generated, the time stamp of the arrival time is attached to the time stamp data of the corresponding packet, and the corresponding CRC check 1 (cyclic redundancy check) and CRC check 2 are calculated and attached to the time stamp data check 1 and the time stamp data check 2 of the corresponding packet respectively.

[0092] The application is critical to how to detect the arrival time of the first message in the detection of t1, t3 arrival time by the shaping filter module 4 of the sending link. Since the process of the data of the message through the shaping filter module 4 can be regarded as the convolution process of the signal spectrum and the spectrum of the shaping filter module 4 in the frequency domain, and can be regarded as the multiplication process of the signal and the waveform of the shaping filter module 4 in the time domain. Therefore, after the bipolar transformation of the data of the original message through the serial-parallel conversion module 3, 0 becomes 11 and 1 becomes 01, and after the multiplication with the shaping filter module 4, the sign bits 1 and 0 of the I branch base frequency transmission data I_filtered and the Q branch base frequency transmission data Q_filtered represent 0 and 1 of the corresponding data of the original message. Therefore, only the sign bits of the I branch base frequency transmission data I_filtered or the Q branch base frequency transmission data Q_filtered after the shaping filter module 4 are detected, and the data sequence is judged, the arrival time of the frame header of the message can be judged. Therefore, when no valid message is sent, the data sent by the sending end is 0, and the data frame sequence obtained after the shaping filter module 4 is all 1. The first data of the frame header of each valid message is set to 1, and the data frame obtained after the shaping filter module 4 is 0. Therefore, in the step, only the position of the first falling edge after the sending signal of the sending link is judged at the first sequence detection module 5, and the time stamp of the current time is recorded, the arrival time can be obtained.

[0093] In the detection of the arrival time t2, t4 of the matched filter module 9 of the receiving link, the key is how to ensure that the receiving end is correctly synchronized to the data stream of the sending end, and the method of the garden ring position synchronization is used to replace the peak value with the peak value to calculate the timing error value, the timing error is adjusted to the loop filter, so that the position of the optimal decision point sync_flag is obtained, and the signal after the matched filter module 9 of any one branch of the co-directional and quadrature is judged by using the optimal decision point sync_flag. When the optimal decision point sync_flag valid signal arrives, it can represent that a valid data is detected, since the received data is serial data, each bit of data obtained is sent to the second sequence detection module 11, and the data sequence of the entire frame header is detected through the state machine, when the frame header is detected, the level of the flag bit demod_flag of the second sequence detection module 11 is pulled up, and the time stamp at this time is recorded as the arrival time. Then the data is sent to the subsequent decoding process, if the decoded data is detected by the data decision module 14 to have a correct frame header and check, it can be considered that a correct message is received. Then the previous recorded time stamp is a valid time stamp, otherwise, it is considered that the receiving time stamp is invalid due to the error code. This time stamping method can make the positions of the sending and receiving time stamps as close to the radio frequency front end as possible, so that the higher the time stamp accuracy is, the higher the time synchronization accuracy will be. In addition, the transmission delay and processing delay caused by data processing, as well as the jitter and delay uncertainty introduced by the cross clock can be reduced, so that the accuracy of the time stamp is improved.

[0094] In wireless time synchronization, the factors affecting the accuracy of the time stamp include the sending delay, the sending processing delay, and the receiving processing delay. The sending delay is the time required for the synchronization information to reach the access layer from the network layer, which may have randomness due to the influence of operating system calls, sending data queuing, etc. The sending processing delay is the time for the sending node to transmit the synchronization information, including the cumulative delay caused by data processing such as data packaging, modulation and shaping filtering. The receiving processing delay is the time required for the receiving node to receive the entire synchronization information. This part of the delay may have randomness due to the influence of the algorithm.

[0095] By using the method of recording the time stamp by hardware at the FPGA end, the timing can be strictly controlled, and the sending delay can be eliminated. In addition, by making the position of the sending time stamp close to the radio frequency end, the cumulative delay caused by the sending processing delay and the delay uncertainty caused by processing data across the clock domain can be reduced. Finally, by using the sequence detection method at the matched filter end, the arrival time of the receiving end time stamp is judged for the first time, which can reduce the uncertain delay caused by the algorithm in the receiving processing.

[0096] Embodiment 3

[0097] A method for realizing wireless high-precision time synchronization based on FPGA, comprising the following steps:

[0098] Execute step 1 of embodiment 2. In this embodiment, the frame header of the first frame message is C3FC, the frame header of the second frame message is F3C0, and the frame headers of the third frame message and the fourth frame message are both F300.

[0099] In this embodiment, the working clocks of the real-time clock module 1, the first sequence detection module 5, the second sequence detection module 11, and the difference calculation module 15 are The frequency is 100MHz, and the working clock C of the differential encoding module 2, the serial-to-parallel conversion module 3, the shaping filter module 4, the first intermediate frequency module 6, the second intermediate frequency module 8, the matching filter module 9, the carrier synchronization module 10, the bit synchronization module 12, the data merging module 13, and the data judgment module 14 is ′ 10M The frequency is 10MHz;

[0100] Execute step 2 of Example 2, the real-time clock module 1 of the sending link of the master end sets the flag bit data_flag, the master end generates and sends the first frame message, and pulls up the level of the flag bit data_flag of the real-time clock module 1 of the sending link of the master end for 180 us. At this time, the timestamp number, timestamp data check 1, and timestamp data check 2 in the first frame message are all 0. The first sequence detection module 5 of the sending link of the master end detects and records the arrival time of the first falling edge of the flag bit data_flag of the real-time clock module 1 of the sending link of the master end after the level is pulled high, and obtains the current timestamp as the arrival time t1 of the first frame message;

[0101] Among them, the frame header of the first frame message becomes FCCF after differential encoding, and then the serial-to-parallel conversion is divided into two paths, IQ. At this time, the frame headers of the I branch and the Q branch are both 1110_1011. Then, they pass through the shaping filter module 4 respectively, and the sign bits of the frame headers of the I branch baseband transmission data I_filtered and the Q branch baseband transmission data Q_filtered output by the shaping filter module 4 are both 0001_0100. When the valid data of the message does not arrive, 0 is sent, and the sign bit output of the shaping filter module 4 is all 1. In the transmission link, it is only necessary to find the moment when the first falling edge arrives during the high level of the flag bit data_flag of the real-time clock module 1 of the transmission link of the master end. Therefore, by tapping the sign bit of one of the signals, finding the falling edge, and recording the current timestamp as the arrival time t1.

[0102] Execute step 3 of Example 2: the real-time clock module 1 of the master end writes the arrival time t1 into the second frame message, delays by 2 ms, and sends the second frame message;

[0103] The receiving link of the slave end detects and records the arrival time t2 of the first frame packet, and receives the second frame packet from the receiving link of the slave end, and extracts the arrival time t1 carried in the second frame packet;

[0104] The second sequence detection module 11 of the slave end uses a state machine to detect the data sequence of the entire frame header of the first frame packet, and records the arrival time t2 of the first frame packet when the complete data sequence of the frame header of the first frame packet is detected; the slave end receives the second frame packet sent by the master end, and extracts the timestamp data of the arrival time t1 carried in the second frame packet through the data decision module 14 of the slave end.

[0105] Wherein, after the matching filter module 9 of the slave end, whether the symbol bit of the I branch base frequency transmission data I_filtered (or the Q branch base frequency transmission data Q_filtered) after the matching filter module 9 is 1111_0001_0100 is detected by the second sequence detection module 11 of the receiving link of the slave end, since the AD9361 data transmission is serial transmission, the sequence detection mode is adopted, wherein the front 1111 represents the valid data future temporary, and 0001_0100 represents the frame header of the first frame packet, and the second sequence detection module 11 in this embodiment adopts the state machine mode, as shown in the following figure: Figure 7 When the state s12 is detected, it is considered that the slave end receives the first frame packet, and the current timestamp is recorded as the arrival time t2, and the data is sent to the subsequent decoding process, if the subsequent data stream is determined to be valid data by the decision module, it is considered that the correct data frame is received, and the recorded timestamp is valid, otherwise, it is considered that there is an error code leading to the invalidity of the received timestamp. Continue to receive the second frame data, since the frame header is different from the first frame, the second frame data will not be detected after the matching filter module 9, but directly sent to the subsequent demodulation module, if the demodulation is correct, the data frame [79:16] thereof is extracted as the timestamp t1.

[0106] Then, steps 5 and 6 of embodiment 1 are sequentially executed to obtain the arrival time t3 and the arrival time t4;

[0107] Step 7 of embodiment 1 is executed, t1, t2, t3, t4 obtained by the slave end are sent to the difference calculation module 15 for calculation difference to obtain the clock deviation, wherein the entire difference calculation module 15 is realized by FPGA. The clock deviation is sent back to the real-time clock module 1 of the slave end to calibrate the clock of the slave end, and realize the clock synchronization of the master end and the slave end;

[0108] The step 8 of the embodiment 1 is executed, the master and the slave start a 1s counter, and the steps 1-7 are repeated every 1s, the clock calibration of the slave is performed every second, so as to ensure the time synchronization between the master and the slave.

[0109] It should be noted that the embodiments described in the present application are only examples to illustrate the spirit of the present application. Those skilled in the art to which the present application belongs can make various modifications or supplements to the described embodiments or replace them with similar ways, but will not deviate from the spirit of the present application or exceed the scope defined by the appended claims.

Claims

1. A device for wireless high-precision time synchronization based on FPGA, comprising a master end and a slave end, characterized in that: Both the master end and the slave end include a transmitting link, a receiving link, and a radio frequency transceiver (7); The transmission link includes a real-time clock module (1), a QPSK baseband modulation module, a first sequence detection module (5), and a first intermediate frequency module (6); The real-time clock module (1) generates a message carrying timestamp data, the message carrying timestamp data passes through a QPSK baseband modulation module to obtain I-branch baseband transmission data and Q-branch baseband transmission data, the I-branch baseband transmission data and the Q-branch baseband transmission data pass through a first intermediate frequency module (6) to obtain I-branch intermediate frequency transmission data and Q-branch intermediate frequency transmission data, the I-branch intermediate frequency transmission data and the Q-branch intermediate frequency transmission data are respectively up-converted by a radio frequency transceiver (7) to obtain an I-branch radio frequency transmission signal and a Q-branch radio frequency transmission signal, and then are respectively transmitted; The first sequence detection module (5) detects and records the arrival time of the I-branch baseband transmission data or the Q-branch baseband transmission data in the transmission link as the arrival time of the message in the transmission link; The receiving link comprises a second intermediate frequency module (8), a matching filter module (9), a QPSK baseband demodulation module, and a second sequence detection module (11); the radio frequency transceiver (7) receives an I-branch radio frequency receiving signal and a Q-branch radio frequency receiving signal and performs down-conversion respectively to obtain an I-branch intermediate frequency receiving signal and a Q-branch intermediate frequency receiving signal; the I-branch intermediate frequency receiving signal and the Q-branch intermediate frequency receiving signal respectively pass through the second intermediate frequency module (8) and the matching filter module (9) in sequence to obtain I-branch baseband receiving data and Q-branch baseband receiving data; the I-branch baseband receiving data and the Q-branch baseband receiving data pass through the QPSK baseband demodulation module to obtain a timestamp; The second sequence detection module (11) detects and records the arrival time of the I-branch baseband receiving data or the Q-branch baseband receiving data in the receiving link as the arrival time of the message in the receiving link.

2. The device for realizing wireless high-precision time synchronization based on FPGA according to claim 1, characterized in that: The QPSK baseband modulation module comprises a differential encoding module (2), a serial-to-parallel conversion module (3), and a shaping filter module (4); a message carrying timestamp data passes through the differential encoding module (2), the serial-to-parallel conversion module (3), and the shaping filter module (4) in sequence to obtain I-branch baseband data and Q-branch baseband data.

3. The device for realizing wireless high-precision time synchronization based on FPGA according to claim 2, characterized in that: The QPSK baseband demodulation module comprises a carrier synchronization module (10), a bit synchronization module (12), a data merging module (13), and a data judgment module (14); the I-branch baseband received data and the Q-branch baseband received data sequentially pass through the carrier synchronization module (10), the bit synchronization module (12), the data merging module (13), and the data judgment module (14) to obtain a time stamp.

4. The device for realizing wireless high-precision time synchronization based on FPGA according to claim 3, characterized in that: The receiving link of the slave end further comprises a difference calculation module (15), and the difference calculation module (15) calculates the delay of the sending link and the receiving link.

5. A method for realizing wireless high-precision time synchronization based on FPGA, using the device for realizing wireless high-precision time synchronization based on FPGA according to claim 4, characterized in that: The following steps are involved: Step 1: setting the format of the message carrying the timestamp data generated by the real-time clock module (1) of the master end and the slave end, and setting the first data bit of the frame header of the message to 1; Step 2: The sending link of the master end generates and sends the first frame message, and detects and records the arrival time t1 of the first frame message; Step 3: The sending link of the master end generates a second frame message carrying the arrival time t1, and sends the second frame message after the set delay time; Step 4: The receiving link of the slave end detects and records the arrival time t2 of the first frame message; the receiving link of the slave end receives the second frame message and decodes the arrival time t1 carried in the second frame message; Step 5: The sending link of the slave generates and sends a third frame message carrying the arrival time t2, and detects and records the arrival time t3 of the third frame message; Step 6: The receiving link of the master end detects and records the arrival time t4 of the third frame message, and then the sending link of the master end generates and sends the fourth frame message carrying the arrival time t4; Step 7: The slave's receiving link receives the fourth message frame and extracts the arrival time t1 carried in the fourth message frame. Finally, the slave calculates the clock offset based on the recorded arrival times t1, t2, t3, and t4, and finally calibrates the slave's clock based on the calculated clock offset. The clock skew is calculated based on the following formula: offset=[(t1-t2)+(t4-t3)] / 2 Where offset is the clock deviation and / is the division sign; Step 8: The master and slave start a 1s counter at the same time, repeat steps 1-7 with a 1s period, and perform clock calibration on the slave once per second.

6. The method for realizing wireless high-precision time synchronization based on FPGA according to claim 5, characterized in that: The format of the message in step 1 includes a frame header, a type, a synchronization cycle number, a synchronization message, a synchronization message check, timestamp data, timestamp data check 1, and timestamp data check 2.

7. The method for realizing wireless high-precision time synchronization based on FPGA according to claim 6, characterized in that: The sending link of the master end in step 2 or the sending link of the slave end in step 5 detects the arrival time of the message in the following manner: First, the real-time clock module (1) of the sending link sets the flag bit data_flag, then generates and sends the first frame message, and pulls the level of the flag bit data_flag high; Secondly, the first sequence detection module (5) of the sending link sets the flag bit mod_flag, detects and records the arrival time of the first falling edge after the level data_flag is pulled high, obtains the current timestamp as the arrival time corresponding to the message, and then pulls the level of the flag bit mod_flag of the sending link first sequence detection module (5) high.

8. The method for realizing wireless high-precision time synchronization based on FPGA according to claim 7, characterized in that: The receiving link of the slave end in step 4 and the receiving link of the slave end in step 6 detect and record the arrival time of the message in the following manner: First, the matched filter module (9) of the receiving link obtains the optimal decision point sync_flag through garden ring synchronization, and uses the optimal decision point sync_flag to detect valid data of the message. After the valid data of the message is detected, each bit of the message data is sent to the second sequence detection module (11); Secondly, the second sequence detection module (11) of the receiving link sets the flag bit demod_flag. The second sequence detection module (11) of the receiving link detects the entire data sequence of the frame header of the message through the state machine. When the frame header of the message is detected, the level of the flag bit demod_flag is pulled high, and the current timestamp is recorded as the arrival time corresponding to the message; Finally, if the data judgment module (14) of the receiving link detects that the frame header, timestamp data check 1 and timestamp data check 2 are all correct, the arrival time recorded by the second sequence detection module (11) of the receiving link is valid.

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