Semiconductor device structure and preparation method thereof

Abstract

The invention relates to a semiconductor device structure and a preparation method thereof. The semiconductor device structure comprises a substrate, a stacking structure of interlayer dielectric layers and conductive layers which are alternately stacked on the substrate, and at least one through hole penetrating through the stacking structure, wherein a first word line, a first channel layer, a second word line, a second channel layer and a conductive connecting layer are arranged in the through hole; wherein the first word lines and the second word lines extend in the second direction perpendicular to the substrate and are arranged at intervals in the first direction parallel to the substrate; the first channel layer surrounds the side wall of the first word line and is disconnected between the adjacent conductive layers; the second channel layer surrounds the side wall of the second word line and is disconnected between the adjacent conductive layers; the conductive connecting layers are located between the adjacent conductive layers and are integrally connected with the first word lines and the second word lines in the first direction. By adopting the semiconductor device structure, the driving current can be increased.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device structure and a preparation method thereof. Background Art

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and numbers of devices contained in a single chip are increasing accordingly, so that any slight difference in process production may affect device performance.

[0003] In order to reduce the cost of products as much as possible, people hope to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's needs for current products. Summary of the invention

[0004] Based on this, the present invention provides a semiconductor device structure and a method for preparing the same.

[0005] In a first aspect, the present invention provides a semiconductor device structure, comprising: a substrate and a stack structure of interlayer dielectric layers and conductive layers alternately stacked on the substrate, at least one through hole penetrating the stack structure, and a first word line, a first channel layer, a second word line, a second channel layer and a conductive connection layer are arranged in the through hole; wherein:

[0006] The first word line and the second word line both extend along a second direction perpendicular to the substrate and are spaced apart along a first direction parallel to the substrate;

[0007] The first channel layer surrounds the sidewall of the first word line and is disconnected between adjacent conductive layers;

[0008] The second channel layer surrounds the sidewall of the second word line and is disconnected between adjacent conductive layers;

[0009] The conductive connection layer is located between adjacent conductive layers and is integrally connected to the first word line and the second word line along the first direction.

[0010] The semiconductor device structure comprises: a substrate and a stack structure of interlayer dielectric layers and conductive layers alternately stacked on the substrate, at least one through hole penetrating the stack structure, and a first word line, a first channel layer, a second word line, a second channel layer and a conductive connection layer are arranged in the through hole; wherein the first word line and the second word line are both extended along a second direction perpendicular to the substrate and are arranged at intervals along a first direction parallel to the substrate; the first channel layer surrounds the side wall of the first word line and is disconnected between adjacent conductive layers; the second channel layer surrounds the side wall of the second word line and is disconnected between adjacent conductive layers; the conductive connection layer is located between adjacent conductive layers and is integrally connected to the first word line and the second word line along the first direction. Since the first word line and the second word line are arranged in the through hole, and the first channel layer is arranged around the side wall of the first word line, and the second channel layer is arranged around the side wall of the second word line, multiple channels can be formed in the first channel layer and the second channel layer, and the arrangement of multiple channels can increase the driving current.

[0011] In one of the embodiments, the semiconductor device structure further includes: a first gate dielectric layer and a second gate dielectric layer;

[0012] The first gate dielectric layer is at least located between the first channel layer and the first word line;

[0013] The second gate dielectric layer is at least located between the second channel layer and the second word line.

[0014] In one embodiment, the semiconductor device structure further includes a plurality of conductive layers arranged in parallel and spaced apart along the second direction; each of the conductive layers includes:

[0015] A first extension portion extending along the first direction, the first extension portion serving as a bit line;

[0016] A plurality of second extension portions, located on two opposite sides of the first extension portion and integrally connected to the first extension portion; each of the second extension portions extends along a third direction parallel to the substrate, and a plurality of the second extension portions located on the same side of the first extension portion are arranged in parallel and spaced apart along the first direction;

[0017] There are multiple through holes, and the multiple through holes are respectively located at one end of the multiple second extension parts close to the first extension part.

[0018] In one embodiment, the semiconductor device structure further includes a capacitor region, and the capacitor region is located at an end of the second extension portion away from the first extension portion.

[0019] In one of the embodiments, the semiconductor device structure further includes a frame, wherein the frame is located on a side of the capacitor region away from the first extension portion and in contact with the capacitor region.

[0020] In one embodiment, the semiconductor device structure further includes a plurality of isolation structures, wherein the isolation structures are located between the first word line and the second word line, between adjacent conductive connection layers, and on the conductive connection layer at the top layer.

[0021] In a second aspect, the present invention further provides a method for preparing a semiconductor device structure, comprising:

[0022] providing a substrate;

[0023] A stacking structure is formed on the substrate, wherein the stacking structure includes conductive layers and interlayer dielectric layers alternately stacked from bottom to top.

[0024] forming at least one through hole penetrating the stacked structure;

[0025] A first word line, a second word line, a first channel layer, a second channel layer and a plurality of conductive connection layers are formed in the through hole; wherein the first word line and the second word line both extend along a second direction perpendicular to the substrate and are spaced apart along a first direction parallel to the substrate; the first channel layer surrounds the side wall of the first word line and is disconnected between adjacent conductive layers; the second channel layer surrounds the side wall of the second word line and is disconnected between adjacent conductive layers; the conductive connection layer is located between adjacent conductive layers and is integrally connected to the first word line and the second word line along the first direction.

[0026] The method for preparing the semiconductor device structure is as follows: a stacking structure is formed on the substrate, wherein the stacking structure includes conductive layers and interlayer dielectric layers alternately stacked from bottom to top; at least one through hole is formed to penetrate the stacking structure; a first word line, a second word line, a first channel layer, a second channel layer and a plurality of conductive connection layers are formed in the through hole; wherein the first word line and the second word line are both extended in a second direction perpendicular to the substrate and are arranged at intervals in a first direction parallel to the substrate; the first channel layer surrounds the side wall of the first word line and is disconnected between adjacent conductive layers; the second channel layer surrounds the side wall of the second word line and is disconnected between adjacent conductive layers; the conductive connection layer is located between adjacent conductive layers and is integrally connected to the first word line and the second word line along the first direction. Since the first word line and the second word line are arranged in the through hole, and the first channel layer is arranged to surround the side wall of the first word line and the second channel layer is arranged to surround the side wall of the second word line, a plurality of channels can be formed in the first channel layer and the second channel layer, and the arrangement of multiple channels can increase the driving current.

[0027] In one embodiment, forming a stacked structure on the substrate includes:

[0028] forming a plurality of interlayer dielectric layers on the substrate and arranged at intervals along the second direction;

[0029] A plurality of conductive layers arranged at intervals along the second direction are correspondingly formed between each layer of the interlayer dielectric layer, and each layer of the interlayer dielectric layer and each layer of the conductive layer are stacked in sequence from bottom to top to form a stacked structure; each layer of the conductive layer includes: a first extension portion extending along the first direction and a plurality of second extension portions extending along the third direction, wherein each of the second extension portions is located on two opposite sides of the first extension portion and is integrally connected to the first extension portion, and a plurality of the second extension portions located on the same side of the first extension portion are arranged in parallel and at intervals along the first direction; an end of each of the second extension portions close to the first extension portion serves as a channel region, and an isolation structure is provided in the channel region.

[0030] In one embodiment, forming a plurality of interlayer dielectric layers on the substrate and arranged at intervals along the second direction includes:

[0031] An initial stacking structure is formed on the substrate, the initial stacking structure comprising an interlayer dielectric layer and a sacrificial layer stacked in sequence from bottom to top; each interlayer dielectric layer comprises: a third extension portion extending along the first direction and a plurality of fourth extension portions extending along the third direction; wherein each of the fourth extension portions is located on two opposite sides of the third extension portion and is integrally connected to the third extension portion, and the plurality of fourth extension portions located on the same side of the third extension portion are arranged in parallel and spaced apart along the first direction; an end of each of the fourth extension portions close to the third extension portion is used as a preset channel region;

[0032] Forming a first groove and a second groove penetrating through the preset channel regions of each layer along the second direction in the initial stack structure, wherein the first groove and the second groove are arranged at intervals along the first direction;

[0033] Filling a dielectric layer in the first trench and the second trench;

[0034] The sacrificial layers are removed to form multiple interlayer dielectric layers arranged in parallel and spaced apart along the second direction, and the sacrificial layers between the sacrificial layers in the preset channel area are retained as the isolation structure, so that the isolation structures are arranged in the preset channel area along the second direction and spaced apart.

[0035] In one embodiment, after forming the first word line, the second word line, the first channel layer, the second channel layer and the multi-layer conductive connection layer in the through hole, the method further includes:

[0036] A capacitor is formed at an end of the stacked structure away from the through hole along a third direction parallel to the substrate, wherein the third direction intersects with the first direction.

[0037] In one embodiment, before forming a plurality of interlayer dielectric layers spaced apart along the second direction on the substrate, the method further comprises:

[0038] Frames are formed on opposite sides of the stacking structure.

[0039] In one embodiment, forming at least one through hole penetrating the stacked structure comprises:

[0040] forming a dielectric layer in the gap region of the stacked structure;

[0041] removing the dielectric layer in the first trench and the second trench;

[0042] Lateral etching is performed based on the first trench and the second trench to remove the dielectric layer between adjacent isolation structures and a portion of the interlayer dielectric layer between each conductive layer to obtain the through hole.

[0043] In one embodiment, forming a first word line, a second word line, a first channel layer, a second channel layer, and a multi-layer conductive connection layer in the through hole includes:

[0044] Depositing a continuously distributed channel material layer and a word line conductive layer in sequence on the inner wall of the through hole; wherein the word line conductive layer filled in the first trench serves as the first word line, the word line conductive layer filled in the second trench serves as the second word line, and the word line conductive layer filled in the through hole between adjacent conductive layers serves as the conductive connection layer;

[0045] A third trench penetrating the dielectric layer is formed in the gap region of the stacked structure, wherein the third trench exposes the sidewalls of the channel material layers arranged at intervals along the second direction on the dielectric layers, wherein the exposed sidewalls of the channel material layers correspond to the interlayer dielectric layers one by one;

[0046] Based on the third groove, the exposed layers of the channel material layer are removed to obtain channel layers corresponding to the conductive layers one by one; wherein the channel layer located in the first groove is used as the first channel layer, and the channel layer located in the second groove is used as the second channel layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0048] Figure 1 is a flow chart of a method for preparing a semiconductor device structure provided in an embodiment;

[0049] Figure 2 is a flowchart of step S20 in a method for preparing a semiconductor device structure provided in an embodiment;

[0050] Figure 3 is a flowchart of step S201 in a method for preparing a semiconductor device structure provided in an embodiment;

[0051] Figure 4 A schematic diagram of a 3D structure of a structure obtained in step S2011 in a method for preparing a semiconductor device structure provided in an embodiment;

[0052] Figure 5 A schematic diagram of a top view of a structure obtained in step S2011 in a method for preparing a semiconductor device structure provided in an embodiment;

[0053] Figure 6 The schematic diagram of the cross-sectional structure of the structure obtained in step S2011 provided in one embodiment, wherein (a) is a ... Figure 5 Schematic diagram of AA' direction shown in (b), along Figure 5 Schematic diagram of BB' direction shown;

[0054] Figure 7 A schematic diagram of a 3D structure of a structure obtained in step S2012 in a method for preparing a semiconductor device structure provided in an embodiment;

[0055] Figure 8 A schematic diagram of a top view of a structure obtained in step S2012 in a method for preparing a semiconductor device structure provided in an embodiment;

[0056] Fig. 9 The schematic diagram of the cross-sectional structure of the structure obtained in step S2012 provided in one embodiment, wherein (a) is a ... Figure 8 Schematic diagram of AA' direction shown in (b), along Figure 8 Schematic diagram of BB' direction shown;

[0057] Fig.10A schematic diagram of a 3D structure of a structure obtained in step S2013 in a method for preparing a semiconductor device structure provided in an embodiment;

[0058] Fig.11 A schematic diagram of a top view of a structure obtained in step S2013 in a method for preparing a semiconductor device structure provided in an embodiment;

[0059] Fig.12 The schematic diagram of the cross-sectional structure of the structure obtained in step S2013 provided in one embodiment, wherein (a) is a ... Fig.11 Schematic diagram of AA' direction shown in (b), along Fig.11 Schematic diagram of BB' direction shown;

[0060] Fig.13 A schematic diagram of a 3D structure of a structure obtained in step S2014 in a method for preparing a semiconductor device structure provided in an embodiment;

[0061] Fig.14 A schematic diagram of a top view of a structure obtained in step S2014 in a method for preparing a semiconductor device structure provided in an embodiment;

[0062] Fig.15 The schematic diagram of the cross-sectional structure of the structure obtained in step S2014 provided in one embodiment, wherein (a) is a ... Fig.14 Schematic diagram of AA' direction shown in (b), along Fig.14 Schematic diagram of BB' direction shown;

[0063] Fig.16 A schematic diagram of a 3D structure of a structure obtained in step S202 in a method for preparing a semiconductor device structure provided in an embodiment;

[0064] Fig.17 A schematic diagram of a top view of a structure obtained in step S202 of a method for preparing a semiconductor device structure provided in an embodiment;

[0065] Fig.18 is a schematic diagram of a cross-sectional structure of a structure obtained in step S202 provided in an embodiment, wherein (a) is ... Fig.17 Schematic diagram of AA' direction shown in (b), along Fig.17 Schematic diagram of BB' direction shown;

[0066] Fig.19 is a flowchart of step S30 in a method for preparing a semiconductor device structure provided in an embodiment;

[0067] Fig. 20 A schematic diagram of a 3D structure of a structure obtained in step S301 in a method for preparing a semiconductor device structure provided in an embodiment;

[0068] Fig.21 A schematic diagram of a top view of a structure obtained in step S301 of a method for preparing a semiconductor device structure provided in an embodiment;

[0069] Fig. 22 is a schematic diagram of a cross-sectional structure of a structure obtained in step S301 provided in an embodiment, wherein (a) is ... Fig.21 Schematic diagram of AA' direction shown in (b), along Fig.21 Schematic diagram of BB' direction shown;

[0070] Fig.23 A 3D structural schematic diagram of a structure obtained in step S302 in a method for preparing a semiconductor device structure provided in an embodiment;

[0071] Fig.24 A schematic diagram of a top view of a structure obtained in step S302 in a method for preparing a semiconductor device structure provided in an embodiment;

[0072] Fig.25 The schematic diagram of the cross-sectional structure of the structure obtained in step S302 provided in one embodiment, wherein (a) is a ... Fig.24 Schematic diagram of AA' direction shown in (b), along Fig.24 Schematic diagram of BB' direction shown;

[0073] Fig.26 A schematic diagram of a 3D structure of a structure obtained in step S303 in a method for preparing a semiconductor device structure provided in an embodiment;

[0074] Fig. 27 A schematic diagram of a top view of a structure obtained in step S303 in a method for preparing a semiconductor device structure provided in an embodiment;

[0075] Fig.28 is a schematic diagram of a cross-sectional structure of a structure obtained in step S303 provided in an embodiment, wherein (a) is ... Fig. 27 Schematic diagram of AA' direction shown in (b), along Fig. 27 Schematic diagram of BB' direction shown;

[0076] Fig.29 is a flowchart of step S40 in a method for preparing a semiconductor device structure provided in an embodiment;

[0077] Fig.30 A schematic diagram of a 3D structure of a structure obtained in step S401 in a method for preparing a semiconductor device structure provided in an embodiment;

[0078] Fig.31A schematic diagram of a top view of a structure obtained in step S401 in a method for preparing a semiconductor device structure provided in an embodiment;

[0079] Fig.32 Schematic diagram of the cross-sectional structure of the structure obtained in step S401 provided in an embodiment, wherein (a) is a ... Fig.31 Schematic diagram of AA' direction shown in (b), along Fig.31 Schematic diagram of BB' direction shown;

[0080] Fig.33 A schematic diagram of a 3D structure of a structure obtained in step S402 in a method for preparing a semiconductor device structure provided in an embodiment;

[0081] Fig.34 A schematic diagram of a top view of a structure obtained in step S402 in a method for preparing a semiconductor device structure provided in an embodiment;

[0082] Fig.35 The schematic diagram of the cross-sectional structure of the structure obtained in step S402 provided in one embodiment, wherein (a) is a ... Fig.34 Schematic diagram of AA' direction shown in (b), along Fig.34 Schematic diagram of BB' direction shown;

[0083] Fig.36 A schematic diagram of a 3D structure of a structure obtained in step S403 in a method for preparing a semiconductor device structure provided in an embodiment;

[0084] Fig.37 A schematic diagram of a top view of a structure obtained in step S403 in a method for preparing a semiconductor device structure provided in an embodiment;

[0085] Fig.38 The schematic diagram of the cross-sectional structure of the structure obtained in step S403 provided in one embodiment, wherein (a) is a ... Fig.37 Schematic diagram of AA' direction shown in (b), along Fig.37 Schematic diagram of BB' direction shown;

[0086] Fig.39 is a schematic diagram of a 3D structure of a semiconductor device structure provided in an embodiment;

[0087] Fig.40 is a schematic top view of a semiconductor device structure provided in an embodiment;

[0088] Fig.41 is a schematic diagram of a cross-sectional structure of a semiconductor device structure provided in an embodiment, wherein (a) is a schematic diagram of a cross-sectional structure of a semiconductor device structure provided in an embodiment, Fig.40 Schematic diagram of AA' direction shown in (b), along Fig.40Schematic diagram of the BB' direction is shown.

[0089] Explanation of the reference numerals: 10 - substrate, 101 - first groove, 102 - second groove, 103 - third groove, 11 - through hole, 20 - interlayer dielectric layer, 201 - dielectric layer, 30 - sacrificial layer, 301 - third extension portion, 302 - fourth extension portion, 303 - preset channel region, 304 - isolation structure, 40 - conductive layer, 401 - first extension portion, 402 - second extension portion, 403 - channel region, 50 - filling layer, 601 - channel material layer, 602 - gate dielectric layer, 603 - word line conductive layer, 604 - channel layer, 61 - first word line, 62 - second word line, 63 - conductive connection layer, 70 - capacitor region, 80 - frame. DETAILED DESCRIPTION

[0090] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Embodiments of the present invention are given in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0091] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0092] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish an element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0093] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0094] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0095] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic diagrams of preferred embodiments of the invention (and intermediate structures), so that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the invention.

[0096] See also Figure 1 The present invention provides a method for preparing a semiconductor device structure, comprising the following steps:

[0097] S10: providing a substrate;

[0098] S20: forming a stacked structure on the substrate, the stacked structure comprising conductive layers and interlayer dielectric layers alternately stacked from bottom to top;

[0099] S30: forming at least one through hole penetrating the stacked structure;

[0100] S40: forming a first word line, a second word line, a first channel layer, a second channel layer and a plurality of conductive connection layers in the through hole; wherein the first word line and the second word line both extend along a second direction perpendicular to the substrate and are spaced apart along a first direction parallel to the substrate; the first channel layer surrounds the side wall of the first word line and is disconnected between adjacent conductive layers; the second channel layer surrounds the side wall of the second word line and is disconnected between adjacent conductive layers; the conductive connection layer is located between adjacent conductive layers and is integrally connected to the first word line and the second word line along the first direction.

[0101] Among them, Figure 36-Figure 38 FIG. 1 is a schematic diagram of a semiconductor device structure prepared through steps S10 to S40 in one embodiment, wherein: Fig.36 It is a 3D structural diagram of the semiconductor device structure. Fig.37 It is a schematic diagram of the top view of the semiconductor device structure. Fig.38 Figure (a) shows the Fig.37 Schematic diagram of the cross-sectional structure in the AA' direction, Fig.38 Figure (b) shows the Fig.37 Schematic diagram of the cross-sectional structure in the BB' direction. Of course, Figure 36-Figure 38 What is given is an example of a semiconductor structure prepared by the method for preparing a semiconductor device structure of the present invention. There may be other suitable examples of semiconductor structures prepared by the method for preparing a semiconductor structure of the present invention, and the present invention is not limited here.

[0102] In addition, to facilitate understanding of the present solution, the first direction involved in the present invention may be the X direction in the drawings provided by the present invention, the second direction may be the Y direction in the drawings provided by the present invention, and the third direction may be the Z direction in the drawings provided by the present invention. Of course, in other suitable application scenarios, the first direction, the second direction, and the third direction may also have other definitions, which are not limited here.

[0103] The method for preparing the semiconductor device structure is as follows: a stacking structure is formed on a substrate, wherein the stacking structure includes conductive layers and interlayer dielectric layers alternately stacked from bottom to top; at least one through hole is formed to penetrate the stacking structure; a first word line, a second word line, a first channel layer, a second channel layer and a plurality of conductive connection layers are formed in the through hole; wherein the first word line and the second word line extend in a second direction perpendicular to the substrate and are arranged at intervals in a first direction parallel to the substrate; the first channel layer surrounds the side wall of the first word line and is disconnected between adjacent conductive layers; the second channel layer surrounds the side wall of the second word line and is disconnected between adjacent conductive layers; the conductive connection layer is located between adjacent conductive layers and is integrally connected to the first word line and the second word line along the first direction. Since the first word line and the second word line are arranged in the through hole, and the first channel layer is arranged to surround the side wall of the first word line and the second channel layer is arranged to surround the side wall of the second word line, a plurality of channels can be formed in the first channel layer and the second channel layer, and the arrangement of the plurality of channels can increase the driving current compared with the double channel in the related art.

[0104] like Figure 3-Figure 5 As shown, in step S10, a substrate 10 is provided.

[0105] The material of the substrate 10 may be any suitable substrate material known in the art, for example, at least one of the following materials: silicon (Si), germanium (Ge), red phosphorus, silicon germanium (SiGe), silicon carbide (SiC), carbon germanium silicon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), or double-sided polished silicon wafers (Double Side Polished Wafers, DSP), or ceramic substrates such as alumina, quartz or glass substrates, etc., which are not limited in this embodiment.

[0106] like Figure 3-Figure 18 As shown, in step S20 , a stacked structure is formed on the substrate 10 , and the stacked structure includes conductive layers 40 and interlayer dielectric layers 20 that are alternately stacked from bottom to top.

[0107] In one embodiment, Figure 2 As shown, the above step S20 includes:

[0108] S201: forming a plurality of interlayer dielectric layers on a substrate and arranged at intervals along a second direction.

[0109] S202: forming a plurality of conductive layers spaced apart along the second direction between the interlayer dielectric layers, and stacking the interlayer dielectric layers and the conductive layers in sequence from bottom to top to form a stacked structure.

[0110] In one embodiment, Figure 3 As shown, the above step S201 includes:

[0111] S2011: forming an initial stacking structure on the substrate 10, wherein the initial stacking structure includes an interlayer dielectric layer 20 and a sacrificial layer 30 stacked sequentially from bottom to top.

[0112] like Figure 4-Figure 6 As shown, each interlayer dielectric layer 20 includes: a third extension portion 301 extending along a first direction and a plurality of fourth extension portions 302 extending along a third direction; wherein each fourth extension portion 302 is located on two opposite sides of the third extension portion 301 and is integrally connected to the third extension portion 301, and a plurality of fourth extension portions 302 located on the same side of the third extension portion 301 are arranged in parallel and spaced apart along the first direction; an end of each fourth extension portion 302 close to the third extension portion 301 serves as a preset channel region 303.

[0113] By accurately defining the photolithography pattern to manufacture the relevant mask, and then going through processes such as deposition, photolithography and grinding, the final product can be formed. Figure 4 The structure shown in the figure has a relatively mature process, which will not be described in detail here.

[0114] The material of the interlayer dielectric layer 20 may include a suitable dielectric material, such as an oxide material or a nitride material; the material of the sacrificial layer 30 may include a suitable insulating material, such as an oxide material or a nitride material. However, it should be noted that the material of the interlayer dielectric layer 20 is different from the material of the sacrificial layer 30. For example, the material of the interlayer dielectric layer 20 may be silicon oxide, and the material of the sacrificial layer 30 may be silicon nitride, or the material of the interlayer dielectric layer 20 may be silicon nitride, and the material of the sacrificial layer 30 may be silicon oxide.

[0115] S2012: forming a first trench 101 and a second trench 102 penetrating through each layer of the preset channel region 303 along the second direction in the initial stacking structure, wherein the first trench 101 and the second trench 102 are arranged at intervals along the first direction, such as Figure 7-Figure 9 shown.

[0116] S2013: Fill the dielectric layer 201 in the first trench 101 and the second trench 102, such as Figure 10-12 shown.

[0117] The material of the dielectric layer 201 may include an oxide material or a nitride material. Optionally, the material of the dielectric layer 201 may be the same as that of the interlayer dielectric layer 20, for example, the materials of the dielectric layer 201 and the interlayer dielectric layer 20 may both be silicon oxide or silicon nitride.

[0118] S2014: removing each sacrificial layer 30 to form a plurality of interlayer dielectric layers 20 arranged in parallel and spaced apart along the second direction, and retaining the sacrificial layer 30 between the first trench 101 and the second trench 102 as an isolation structure 304, so that each isolation structure 304 is arranged in a predetermined channel region 303 along the second direction and spaced apart, such as Figure 13-Figure 15 shown.

[0119] The sacrificial layers 30 can be removed by selective etching to retain the interlayer dielectric layers 20. Due to the support of the dielectric layer 201, the structure of the interlayer dielectric layers 20 can be completely retained to form the following structure: Figure 13-Figure 15 In addition, the sacrificial layer 30 located in the preset channel region 303 of each layer will not be removed due to the protection of the dielectric layer 201, and thus will be retained to form an isolation structure 304.

[0120] In this embodiment, the purpose of forming the initial stacking structure in steps S2011 to S2014 is to form an isolation structure 304 located in the preset channel region 303 of each layer, and to remove each sacrificial layer 30 by selective removal to retain each interlayer dielectric layer 20. At the same time, after the selective removal, since part of the sacrificial layer 30 is sandwiched between the dielectric layers 201, an isolation structure 304 is formed, and the support function of the dielectric layer 201 is used to form the isolation structure 304. Figure 13-Figure 15 The interlayer dielectric layers 20 shown are provided to meet the requirements of subsequent processes.

[0121] Of course, further, the Figure 13-Figure 15 The interlayer dielectric layers 20 shown can also be formed by other suitable preparation processes. The above steps S2011-S2014 are only provided as an example. In other suitable application scenarios, other suitable preparation processes can also be used to prepare the morphology of the structure in step S201. This embodiment is not limited here.

[0122] In step S202, refer to Figure 16-Figure 18 A plurality of conductive layers 40 arranged in a spaced relationship along the second direction are correspondingly formed between each interlayer dielectric layer 20 , and each interlayer dielectric layer 20 and each conductive layer 40 are stacked in sequence from bottom to top to form a stacked structure.

[0123] Among them, each layer of the conductive layer 40 includes: a first extension portion 401 extending along a first direction and multiple second extension portions 402 extending along a third direction, wherein each second extension portion 402 is located on two opposite sides of the first extension portion 401 and is integrally connected to the first extension portion 401, and multiple second extension portions 402 located on the same side of the first extension portion 401 are arranged in parallel and spaced apart along the first direction; one end of each second extension portion 402 close to the first extension portion 401 serves as a channel region 403, and an isolation structure 304 is provided in the channel region 403.

[0124] Among them, the material of the conductive layer 40 may include any suitable conductive material, for example, it may include metals such as tungsten, copper, gold, titanium, silver, aluminum, etc., it may also include a multilayer metal composed of metals of the above materials, it may also include metal alloys, etc., and this embodiment is not limited here.

[0125] contrast Fig.17 and Fig.11 It can be seen that the position of the channel region 403 corresponds to the position of the preset channel region 303, or it can be said that the position of the channel region 403 is the same as the position of the preset channel region 303. Therefore, the dielectric layer 201 and the isolation structure 304 are located in the channel region 403 of each layer, and combined with Fig.18 As can be seen from FIG. 5( a ) , the isolation structure 304 and a portion of the interlayer dielectric layer 20 are alternately stacked in sequence along the second direction.

[0126] Optionally, an initial conductive material layer may be deposited in the gap region of the structure obtained in step S201 by a deposition process, and then a conductive layer may be formed by photolithography, etching and other process steps. Figure 16-Figure 18 In the structure shown, the mask in the photolithography process can continue to reuse the mask used to form the initial stacking structure to save process costs. The deposition process can include, for example, an atomic layer deposition process.

[0127] like Figure 26-Figure 28 As shown, in step S30, at least one through hole 11 penetrating the stacked structure is formed.

[0128] In one embodiment, Fig.19 As shown, the above step S30 includes:

[0129] S301: forming a filling layer 50 in the gap region of the stacked structure.

[0130] like Figure 20-22 As shown, a deposition process may be used to form the filling layer 50 by one deposition. The deposition process may include, for example, an atomic layer deposition process, a physical vapor deposition process, a chemical vapor deposition process, and the like.

[0131] The material of the filling layer 50 may include a nitride material or an oxide material, for example, may include silicon oxide. The filling layer 50 plays a role in further supporting the stacking structure.

[0132] S302: removing the dielectric layer 201 in the first trench 101 and the second trench 102, such as Figure 23-Figure 25 shown.

[0133] S303: performing lateral etching based on the first trench 101 and the second trench 102 to remove the dielectric layer 201 between adjacent isolation structures 304 and a portion of the interlayer dielectric layer 20 between each conductive layer 40 to obtain a through hole 11, such as Figure 26-Figure 28 shown.

[0134] The lateral etching may include wet etching or steam etching. After the lateral etching, both ends of each layer of isolation structure 304 are in contact with each layer of conductive layer 40. Fig.28 shown.

[0135] like Figure 30-Figure 32 As shown, in step S40, a first word line, a second word line, a first channel layer, a second channel layer and a multi-layer conductive connection layer are formed in the through hole.

[0136] Among them, the first word line and the second word line both extend along a second direction perpendicular to the substrate and are spaced apart along a first direction parallel to the substrate; the first channel layer surrounds the side wall of the first word line and is disconnected between adjacent conductive layers; the second channel layer surrounds the side wall of the second word line and is disconnected between adjacent conductive layers; the conductive connection layer is located between adjacent conductive layers and is integrally connected to the first word line and the second word line along the first direction.

[0137] In one embodiment, Fig.29 As shown, the above step S40 includes:

[0138] S401: Depositing continuously distributed channel material layers and word line conductive layers on the inner wall of the through hole in sequence; wherein the word line conductive layer filled in the first trench serves as the first word line, the word line conductive layer filled in the second trench serves as the second word line, and the word line conductive layer filled in the through hole between adjacent conductive layers serves as a conductive connection layer.

[0139] like Figure 30-Figure 32 As shown, a continuously distributed channel material layer 601 and a word line conductive layer may be sequentially deposited by a deposition process, wherein the deposition process may include an atomic layer deposition process, a physical vapor deposition process, a chemical vapor deposition process, and the like.

[0140] The material of the channel material layer 601 may include a metal oxide semiconductor material, such as indium gallium zinc oxide (IGZO). When the metal oxide semiconductor material is IGZO, the leakage current of the transistor is small (the leakage current is not greater than or equal to 10-15A), thereby ensuring a low refresh rate of the dynamic memory. It should be noted that the material of the metal oxide semiconductor material can also be ITO, IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO, IAZO, IGO, IZO (indium-zinc-oxide), IZOx and the like, as long as the leakage current of the transistor can meet the requirements, and the specific adjustment can be made according to the actual situation.

[0141] The material of the word line conductive layer 603 may include ITO, polysilicon, metal material or other suitable conductive materials.

[0142] In addition, if Fig.32 As shown in FIGS. (a) and (b) , the word line conductive layers 603 extending along the first direction and filled between the conductive layers 40 serve as the conductive connection layers 63 .

[0143] Optional, such as Figure 30-Figure 32 As shown, while forming the channel material layer and the word line conductive layer, a gate dielectric layer 602 may also be formed.

[0144] The material of the gate dielectric layer 602 may include a suitable dielectric material, for example, a high-K dielectric material.

[0145] Furthermore, the gate dielectric layer 602 includes a first gate dielectric layer and a second gate dielectric layer, wherein the first gate dielectric layer is located between the first channel layer and the first word line, and the second gate dielectric layer is located at least between the second channel layer and the second word line.

[0146] In addition, it should be noted that the channel material layer 601 and the gate dielectric layer 602 are substantially continuously distributed on the inner wall of the through hole 11. Fig.32 It can be seen clearly in Figure (a) and Figure (b).

[0147] S402: forming a third trench penetrating the dielectric layer in the gap region of the stacked structure, wherein the third trench exposes the sidewalls of the channel material layers arranged at intervals along the second direction on the dielectric layers, wherein the exposed sidewalls of the channel material layers correspond to the interlayer dielectric layers one by one.

[0148] like Figure 33-Figure 35 As shown, the morphology of the third groove 103 can be determined by designing the mask, and the purpose of forming the third groove 103 is to utilize the side wall of the third groove 103 to expose the surface of the channel material layer 601 of the interlayer dielectric layer 20 surrounding each layer of the channel region 403, and the channel material layer 601 located in each layer of the channel region 403 will not be exposed by the side wall of the third groove 103.

[0149] In addition, the third trench 103 can be formed by selectively removing the filling layer 50 and the interlayer dielectric layer 20, and the filling layer 50 and the interlayer dielectric layer 20 can be made of the same material, for example, both can be silicon oxide, and the conductive layers 40 can be left unremoved during the formation of the third trench 103. Fig.35 The third grooves 103 shown in FIG. (b) may be arranged at intervals along the second direction.

[0150] S403: removing the exposed channel material layers based on the third trench to obtain channel layers corresponding to the conductive layers one by one; wherein the channel layer located in the first trench is used as the first channel layer, and the channel layer located in the second trench is used as the second channel layer.

[0151] like Figure 36-Figure 38 As shown, in step S402, the positions of the channel material layers 601 exposed by the side walls of the third trench 103 correspond to the positions of the interlayer dielectric layers 20, and the positions of the filling layers 50 correspond to the positions of the conductive layers 40. Therefore, a selective etching process can be used to remove the channel material layers 601 exposed by the side walls of the third trench 103, and the retained channel material layers 601 corresponding to the conductive layers 40 can be used as the channel layers 604.

[0152] In addition, in the above embodiment, since the channel material layer 601 is continuously distributed, it is also partially distributed on the side walls of each interlayer dielectric layer 20. From the perspective of device design, this embodiment only needs to form the channel material layer 601 on the side walls of each conductive layer 40. The channel material layer 601 located on the side walls of each interlayer dielectric layer 20 will bring about the problem of parasitic MOS. Therefore, this embodiment can also remove the channel material layer 601 exposed on the side wall of the third trench 103, thereby achieving the purpose of removing parasitic MOS.

[0153] Optionally, in other suitable application scenarios, a method similar to any embodiment provided by the present invention can be adopted to achieve that the word line structure corresponding to each layer of the channel region 403 has multiple word lines arranged at intervals along the first direction, and is not limited to having only two word lines. For example, in the above step S2012, multiple grooves arranged at intervals along the first direction can be formed in the initial stacking structure, and the multiple grooves all penetrate the preset channel region 303 of each layer along the first direction, and then more word lines are formed in a through hole in combination with other embodiments of the present invention, and more channels are formed accordingly, so that the driving current of the semiconductor device structure can be further improved.

[0154] In one embodiment, Figure 39-41 As shown, after step S40, the method for preparing the semiconductor device structure further includes:

[0155] A capacitor is formed at an end of the stacked structure away from the through hole 11 along a third direction parallel to the substrate 10 , wherein the third direction intersects with the first direction.

[0156] In one embodiment, Figure 39-41 As shown, before step S201, the method for preparing the semiconductor device structure further includes:

[0157] A frame 80 is formed on a side of the capacitor region 70 away from the first extension portion 401 , and the frame 80 is in contact with the capacitor region 70 .

[0158] Optionally, the frame 80 may be formed after step S2011 and before step S2012, and the frame 80 may be formed in all subsequent drawings. Optionally, all other drawings in the present invention may be formed with Figure 39-Figure 41 In the framework 80, combined Figure 39-Figure 41 Other figures forming the frame 80 can be obtained, which will not be described in detail here.

[0159] The present invention also provides a semiconductor device structure, such as Figure 36-Figure 38 As shown, the semiconductor device structure includes: a substrate 10 and a stack structure of interlayer dielectric layers 20 and conductive layers 40 alternately stacked on the substrate 10, at least one through hole 11 penetrating the stack structure, and a first word line 61, a first channel layer, a second word line 62, a second channel layer and a conductive connection layer 63 are arranged in the through hole 11; wherein the first word line 61 and the second word line 62 both extend along a second direction perpendicular to the substrate 10 and are spaced apart along a first direction parallel to the substrate 10; the first channel layer surrounds the side wall of the first word line 61 and is disconnected between adjacent conductive layers 40; the second channel layer surrounds the side wall of the second word line 62 and is disconnected between adjacent conductive layers 40; the conductive connection layer 63 is located between adjacent conductive layers 40 and is integrally connected to the first word line and the second word line along the first direction.

[0160] The semiconductor device structure includes a substrate 10 and a stack structure of interlayer dielectric layers 20 and conductive layers 40 alternately stacked on the substrate 10, at least one through hole 11 penetrating the stack structure, and a first word line 61, a first channel layer, a second word line 62, a second channel layer and a conductive connection layer 63 are arranged in the through hole 11; wherein the first word line 61 and the second word line 62 both extend along a second direction perpendicular to the substrate 10 and are arranged at intervals along a first direction parallel to the substrate 10; the first channel layer surrounds the side wall of the first word line 61 and is disconnected between adjacent conductive layers 40; the second channel layer surrounds the side wall of the second word line 62 and is disconnected between adjacent conductive layers 40; the conductive connection layer 63 is located between adjacent conductive layers 40 and is integrally connected to the first word line and the second word line along the first direction. Since the first word line 61 and the second word line 62 are arranged in the through hole 11, and the first channel layer is arranged around the side wall of the first word line 61, and the second channel layer is arranged around the side wall of the second word line 62, multiple channels can be formed in the first channel layer and the second channel layer. Compared with the double channel in the related technology, the multi-channel setting can increase the driving current.

[0161] In one embodiment, Figure 36-Figure 38 As shown, the semiconductor device structure further includes: a first gate dielectric layer and a second gate dielectric layer; the first gate dielectric layer is at least located between the first channel layer and the first word line 61 ; the second gate dielectric layer is at least located between the second channel layer and the second word line 62 .

[0162] In one embodiment, Figure 36-Figure 38 As shown, each conductive layer 40 includes: a first extension portion 401 extending along a first direction, the first extension portion 401 serving as a bit line; a plurality of second extension portions 402 located on two opposite sides of the first extension portion 401 and integrally connected to the first extension portion 401; each second extension portion 402 extends along a third direction parallel to the substrate 10, and the plurality of second extension portions 402 located on the same side of the first extension portion 401 are arranged in parallel and spaced apart along the first direction;

[0163] There are multiple through holes 11 , and the multiple through holes 11 are respectively located at one end of the multiple second extension portions 402 close to the first extension portion 401 .

[0164] In one embodiment, Figure 39-41 As shown, the semiconductor device structure further includes a capacitor region 70 , and the capacitor region 70 is located at one end of the second extension portion 402 away from the first extension portion 401 .

[0165] In one embodiment, Figure 39-Figure 41 As shown, the semiconductor device structure further includes a frame 80 . The frame 80 is located on a side of the capacitor region 70 away from the first extension portion 401 and is in contact with the capacitor region 70 .

[0166] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0167] The above embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for those of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A semiconductor device structure, characterized in that: include: A substrate and a stack structure of interlayer dielectric layers and conductive layers alternately stacked on the substrate, at least one through hole penetrating the stack structure, and a first word line, a first channel layer, a second word line, a second channel layer and a conductive connection layer are arranged in the through hole; wherein, The first word line and the second word line both extend along a second direction perpendicular to the substrate and are spaced apart along a first direction parallel to the substrate; The first channel layer surrounds the sidewall of the first word line and is disconnected between adjacent conductive layers; The second channel layer surrounds the sidewall of the second word line and is disconnected between adjacent conductive layers; The conductive connection layer is located between adjacent conductive layers and is integrally connected to the first word line and the second word line along the first direction.

2. The semiconductor device structure according to claim 1, characterized in that: The semiconductor device structure further includes: a first gate dielectric layer and a second gate dielectric layer; The first gate dielectric layer is at least located between the first channel layer and the first word line; The second gate dielectric layer is at least located between the second channel layer and the second word line.

3. The semiconductor device structure according to claim 1, characterized in that: Each conductive layer comprises: A first extension portion extending along the first direction, the first extension portion serving as a bit line; A plurality of second extension portions, located on two opposite sides of the first extension portion and integrally connected to the first extension portion; each of the second extension portions extends along a third direction parallel to the substrate, and a plurality of the second extension portions located on the same side of the first extension portion are arranged in parallel and spaced apart along the first direction; There are multiple through holes, and the multiple through holes are respectively located at one end of the multiple second extension parts close to the first extension part.

4. The semiconductor device structure according to claim 3, characterized in that: The semiconductor device structure further includes a capacitor region, and the capacitor region is located at an end of the second extension portion away from the first extension portion.

5. The semiconductor device structure according to claim 4, characterized in that: The semiconductor device structure further includes a frame, which is located at a side of the capacitor region away from the first extension portion and in contact with the capacitor region.

6. The semiconductor device structure according to any one of claims 1 to 5, characterized in that: The semiconductor device structure further includes a plurality of isolation structures, wherein the isolation structures are located between the first word line and the second word line, between adjacent conductive connection layers, and on the conductive connection layer at the top layer.

7. A method for preparing a semiconductor device structure, characterized in that: include: providing a substrate; forming a stacking structure on the substrate, wherein the stacking structure comprises conductive layers and interlayer dielectric layers alternately stacked from bottom to top; forming at least one through hole penetrating the stacked structure; A first word line, a second word line, a first channel layer, a second channel layer and a plurality of conductive connection layers are formed in the through hole; wherein the first word line and the second word line both extend along a second direction perpendicular to the substrate and are spaced apart along a first direction parallel to the substrate; the first channel layer surrounds the side wall of the first word line and is disconnected between adjacent conductive layers; the second channel layer surrounds the side wall of the second word line and is disconnected between adjacent conductive layers; the conductive connection layer is located between adjacent conductive layers and is integrally connected to the first word line and the second word line along the first direction.

8. The method for preparing a semiconductor device structure according to claim 7, characterized in that: The forming of a stacked structure on the substrate comprises: forming a plurality of interlayer dielectric layers on the substrate and arranged at intervals along the second direction; A plurality of conductive layers arranged at intervals along the second direction are correspondingly formed between each layer of the interlayer dielectric layer, and each layer of the interlayer dielectric layer and each layer of the conductive layer are stacked in sequence from bottom to top to form a stacked structure; each layer of the conductive layer includes: a first extension portion extending along the first direction and a plurality of second extension portions extending along the third direction, wherein each of the second extension portions is located on two opposite sides of the first extension portion and is integrally connected to the first extension portion, and a plurality of the second extension portions located on the same side of the first extension portion are arranged in parallel and at intervals along the first direction; an end of each of the second extension portions close to the first extension portion serves as a channel region, and an isolation structure is provided in the channel region.

9. The method for preparing a semiconductor device structure according to claim 8, characterized in that: The method of forming a plurality of interlayer dielectric layers on the substrate and arranged in intervals along the second direction comprises: An initial stacking structure is formed on the substrate, the initial stacking structure comprising an interlayer dielectric layer and a sacrificial layer stacked in sequence from bottom to top; each interlayer dielectric layer comprises: a third extension portion extending along the first direction and a plurality of fourth extension portions extending along the third direction; wherein each of the fourth extension portions is located on two opposite sides of the third extension portion and is integrally connected to the third extension portion, and the plurality of fourth extension portions located on the same side of the third extension portion are arranged in parallel and spaced apart along the first direction; an end of each of the fourth extension portions close to the third extension portion is used as a preset channel region; Forming a first groove and a second groove penetrating through the preset channel regions of each layer along the second direction in the initial stack structure, wherein the first groove and the second groove are arranged at intervals along the first direction; Filling a dielectric layer in the first trench and the second trench; The sacrificial layers are removed to form multiple interlayer dielectric layers arranged in parallel and spaced apart along the second direction, and the sacrificial layers between the first trench and the second trench are retained as the isolation structure, so that each isolation structure is arranged in the preset channel area at intervals along the second direction.

10. The method for preparing a semiconductor device structure according to claim 7, characterized in that: After forming a first word line, a second word line, a first channel layer, a second channel layer, and a multi-layer conductive connection layer in the through hole, the method further includes: A capacitor is formed at an end of the stacked structure away from the through hole along a third direction parallel to the substrate, wherein the third direction intersects with the first direction.

11. The method for preparing a semiconductor device structure according to claim 8, characterized in that: Before forming a plurality of interlayer dielectric layers spaced apart along the second direction on the substrate, the method further comprises: Frames are formed on opposite sides of the stacking structure.

12. The method for preparing a semiconductor device structure according to claim 9, characterized in that: The forming of at least one through hole penetrating the stacked structure comprises: forming a filling layer in the gap region of the stacked structure; removing the dielectric layer in the first trench and the second trench; Lateral etching is performed based on the first trench and the second trench to remove the dielectric layer between adjacent isolation structures and a portion of the interlayer dielectric layer between each conductive layer to obtain the through hole.

13. The method for preparing a semiconductor device structure according to claim 12, characterized in that: The forming of the first word line, the second word line, the first channel layer, the second channel layer and the multi-layer conductive connection layer in the through hole includes: Depositing a continuously distributed channel material layer and a word line conductive layer in sequence on the inner wall of the through hole; wherein the word line conductive layer filled in the first trench serves as the first word line, the word line conductive layer filled in the second trench serves as the second word line, and the word line conductive layer filled in the through hole between adjacent conductive layers serves as the conductive connection layer; A third trench penetrating the dielectric layer is formed in the gap region of the stacked structure, wherein the third trench exposes the sidewalls of the channel material layers arranged at intervals along the second direction on the dielectric layers, wherein the exposed sidewalls of the channel material layers correspond to the interlayer dielectric layers one by one; Based on the third groove, the exposed layers of the channel material layer are removed to obtain channel layers corresponding to the conductive layers one by one; wherein the channel layer located in the first groove is used as the first channel layer, and the channel layer located in the second groove is used as the second channel layer.

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