Semiconductor device and method of manufacturing semiconductor device

Abstract

A semiconductor device and a method of manufacturing the semiconductor device are provided. The semiconductor device may include a peripheral circuit structure on a substrate; an interlayer insulating layer on the peripheral circuit structure; a bit line extending in a first direction in the interlayer insulating layer; a semiconductor pattern on the bit line and including a first vertical portion and a second vertical portion facing each other in the first direction and a horizontal portion connecting the first vertical portion and the second vertical portion to each other; first and second word lines on the horizontal portion and adjacent to the first and second vertical portions, respectively; and a gate insulating pattern interposed between the first vertical portion and the first word line and between the second vertical portion and the second word line. An upper surface of the interlayer insulating layer and an upper surface of the bit line are coplanar with each other.

Description

Technical Field

[0001] Various example embodiments relate to a semiconductor device, and more particularly, to a semiconductor device including a vertical channel transistor and / or a method of manufacturing the same. Background Art

[0002] As the design rule of semiconductor devices decreases, a manufacturing technology has been developed to increase the integration of semiconductor devices and / or increase the operation speed and / or yield. Therefore, a transistor with a vertical channel has been proposed to expand the integration, resistance and / or current driving capability of the transistor. Summary of the invention

[0003] Various example embodiments may provide a semiconductor device having improved electrical characteristics and reliability and a method of manufacturing the same.

[0004] Problems to be solved or improved by the exemplary embodiments are not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those of ordinary skill in the art from the following description.

[0005] A semiconductor device according to some example embodiments may include: a peripheral circuit structure on a substrate; an interlayer insulating layer on the peripheral circuit structure; a bit line in the interlayer insulating layer and extending in a first direction; a semiconductor pattern on the bit line and including first and second vertical portions facing each other in the first direction and a horizontal portion connecting the first and second vertical portions to each other; first and second word lines on the horizontal portion and adjacent to the first and second vertical portions, respectively; and a gate insulating pattern interposed between the first vertical portion and the first word line and between the second vertical portion and the second word line. An upper surface of the interlayer insulating layer and an upper surface of the bit line may be coplanar with each other.

[0006] Alternatively or additionally, a semiconductor device according to some example embodiments may include: a peripheral circuit structure on a substrate; an interlayer insulating layer on the peripheral circuit structure; a bit line in the interlayer insulating layer and extending in a first direction; a semiconductor pattern on the bit line and including first and second vertical portions facing each other and spaced apart from each other in the first direction; first and second word lines, respectively disposed on inner surfaces of the first and second vertical portions; and a gate insulating pattern interposed between the first vertical portion and the first word line and between the second vertical portion and the second word line. An upper surface of the interlayer insulating layer and an upper surface of the bit line are coplanar with each other.

[0007] Alternatively or additionally, a method for manufacturing a semiconductor device according to some example embodiments may include: forming a peripheral circuit structure on a substrate, forming an interlayer insulating layer on the peripheral circuit structure, forming a bit line in the interlayer insulating layer, sequentially stacking a first insulating layer and a sacrificial layer on the interlayer insulating layer and the bit line, patterning the first insulating layer and the sacrificial layer to form a first insulating pattern and a sacrificial pattern intersecting the bit line, forming a mold layer covering the first insulating pattern and the sacrificial pattern, patterning the mold layer to form a mold pattern intersecting the first insulating pattern and the sacrificial pattern, and performing a surface treatment process on the mold pattern so that a surface of the mold pattern has hydrophobicity. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Various example embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings, which represent non-limiting example embodiments described herein.

[0009] Figure 1 is a block diagram of a semiconductor memory device including a semiconductor device according to some example embodiments.

[0010] Figure 2 is a schematic perspective view of a semiconductor device according to some example embodiments.

[0011] Figure 3 is a plan view of a semiconductor device according to some example embodiments.

[0012] Figure 4 is corresponding to Figure 3 Cross-sectional view along line AA'.

[0013] Figure 5A is corresponding to Figure 3 Cross-sectional view along line BB'. Figure 5B yes Figure 5A An enlarged view of portion "A".

[0014] Figure 6 is corresponding to Figure 3 Cross-sectional view along line CC'.

[0015] FIG. 7A to FIG. 7D is corresponding to Figure 3 Cross-sectional view along line D-D'.

[0016] Figure 8 is corresponding to Figure 3 Cross-sectional view along line EE'.

[0017] 9A to 15D and Fig.16 It shows the manufacturing Fig. 7A A cross-sectional view of a method for a semiconductor device.

[0018] Fig.17It shows the manufacturing Figure 7C and Fig.7D A cross-sectional view of a semiconductor device process. DETAILED DESCRIPTION

[0019] Hereinafter, a semiconductor memory device and a method of manufacturing the same according to various example embodiments will be described in detail with reference to the accompanying drawings.

[0020] Figure 1 is a block diagram of a semiconductor memory device including a semiconductor device according to some example embodiments.

[0021] Reference Figure 1 , a semiconductor memory device may include a memory cell array 1 , a row decoder 2 , a sense amplifier 3 , a column decoder 4 , and a control logic 5 .

[0022] The memory cell array 1 may include a plurality of memory cells MC arranged two-dimensionally and / or three-dimensionally. Each memory cell MC may be provided between and connected to a word line WL (eg, a row line) and a bit line BL (eg, a column line) crossing each other.

[0023] Each memory cell MC may include, for example, a selection element TR and a data storage element DS electrically connected in series. The selection element TR may be provided between the data storage element DS and the word line WL and connected to them, and the data storage element DS may be connected to the bit line BL through the selection element TR. The selection element TR may be or may include a field effect transistor (FET), and the data storage element DS may be implemented using at least one of a capacitor, a memristor, a magnetic tunnel junction pattern, or a variable resistor. As an example, the selection element TR may include a transistor such as an NMOS transistor, the gate electrode of the transistor may be connected to the word line WL, and the drain / source terminal of the transistor may be connected to the bit line BL and the data storage element DS, respectively. In some example embodiments, at least some memory cells MC may be or may include dummy cells, which are not electrically activated during the operation of the semiconductor device. Alternatively or additionally, at least some memory cells MC may be or may include redundant cells.

[0024] The row decoder 2 may be configured to decode address information and select one of the word lines WL of the memory cell array 1 based on the decoded address information, and in some example embodiments, the address information is input from the outside. The address information decoded by the row decoder 2 may be provided to a row driver (not shown), and in this case, the row driver may provide corresponding voltages to a selected one of the word lines WL and an unselected one of the word lines WL in response to the control of the control circuit.

[0025] The sense amplifier 3 may be configured to sense, amplify, and output a voltage difference between one of the bit lines BL (which is selected based on address information decoded by the column decoder 4 ) and a reference bit line (such as but not limited to a complementary bit line) or a value corresponding to the voltage difference.

[0026] The column decoder 4 may provide a data transmission path between the sense amplifier 3 and an external device (eg, a memory controller). The column decoder 4 may be configured to decode address information that may be input from the outside and select one of the bit lines BL based on the decoded address information.

[0027] The control logic 5 may be configured to generate a control signal for controlling a data write or read operation on the memory cell array 1 .

[0028] Figure 2 is a schematic perspective view of a semiconductor device according to some example embodiments.

[0029] Reference Figure 2 , a semiconductor device according to some example embodiments may include a peripheral circuit structure PS on a semiconductor substrate 100 and a cell array structure CS on the peripheral circuit structure PS.

[0030] The peripheral circuit structure PS may include a core and peripheral circuit PERI formed on the semiconductor substrate 100. The core and peripheral circuit PERI may include reference Figure 1 The row decoder 2 and column decoder 4, sense amplifier 3 and control logic 5 described. The core may include a sense amplifier S / A and a sub-word driver SWD. The sense amplifier S / A may play a role in amplifying the signal. The sub-word driver SWD may be used to supply and control power to the word line. The peripheral circuit structure PS may be provided between the substrate 100 and the cell array structure CS in a third direction D3 perpendicular to the upper surface of the substrate 100.

[0031] The cell array structure CS may include bit lines BL, word lines WL and memory cells MC therebetween (see Figure 1 ). Storage cell MC (see Figure 1 ) may be arranged two-dimensionally and / or three-dimensionally on a plane extending in a first direction D1 and a second direction D2 intersecting each other. As described above, each memory cell MC (see Figure 1 ) may include a selection element TR and a data storage element DS.

[0032] According to some embodiments, a vertical channel transistor (VCT) may be provided as each memory cell MC (see Figure 1) selection element TR. The vertical channel transistor may represent or may correspond to a transistor whose channel region extends in a direction perpendicular to the upper surface of the semiconductor substrate 100 (eg, in the third direction D3). In some example embodiments, a capacitor and / or a memristor may be provided as each memory cell MC (see Figure 1 )'s data storage element DS.

[0033] Figure 3 is a plan view of a semiconductor device according to some example embodiments. Figure 4 is corresponding to Figure 3 Cross-sectional view along line AA'. Figure 5A is corresponding to Figure 3 Cross-sectional view along line BB'. Figure 5B yes Figure 5A An enlarged view of portion "A". Figure 6 is corresponding to Figure 3 Cross-sectional view along line CC'. FIG. 7A to FIG. 7D is corresponding to Figure 3 Cross-sectional view along line D-D'. Figure 8 is corresponding to Figure 3 Cross-sectional view along line EE'.

[0034] Reference Figure 3 , Figure 4 , Figure 5A , Figure 5B , Figure 6 , Fig. 7A and Figure 8 , a semiconductor device according to some example embodiments may include a substrate 100 , a peripheral circuit structure PS on the substrate 100 , and a cell array structure CS on the peripheral circuit structure PS.

[0035] The substrate 100 may be or include a semiconductor substrate. The substrate 100 may be or include, for example, one or more of a silicon substrate, a germanium substrate, or a silicon germanium substrate.

[0036] The peripheral circuit structure PS may include a peripheral gate structure PC integrated on the substrate 100, a peripheral contact pad CP, a peripheral contact plug CPLG1, and a first interlayer insulating layer 102 covering the peripheral contact plug CPLG1. The peripheral gate structure PC may include Figure 1 of the sense amplifier 3.

[0037] The cell array structure CS may include a memory cell including a vertical channel transistor. The cell array structure CS may include a plurality of cell contact plugs CPLG2, a plurality of bit lines BL, a plurality of shielding structures SM, a second interlayer insulating layer 104, a plurality of semiconductor patterns SP, a plurality of word lines WL, a plurality of gate insulating patterns Gox, and a data storage pattern DSP. The second interlayer insulating layer 104 may cover the cell contact plugs CPLG2 and the shielding structure SM.

[0038] As an example, the peripheral gate structure PC of the peripheral circuit structure PS may be electrically connected to the bit line BL through the peripheral contact plug CPLG1, the peripheral contact pad CP, and the cell contact plug CPLG2. Each of the first interlayer insulating layer 102 and the second interlayer insulating layer 104 may include a plurality of insulating layers, and may include, for example, independently or simultaneously at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric material. Although the peripheral gate structure PC is shown as extending in the first direction D1, example embodiments are not limited thereto.

[0039] The bit line BL may be provided in the second interlayer insulating layer 104 on the substrate 100 and may extend in the first direction D1. A plurality of bit lines BL may be provided and the bit lines BL may be spaced apart from each other in the second direction D2. The bit line BL may be electrically connected to the peripheral contact pad CP through the cell contact plug CPLG2.

[0040] The bit line BL may include at least one of the following: for example, doped polysilicon, a metal (for example, one or more of Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co), a conductive metal nitride (for example, one or more of TiN, TaN, WN, NbN, TiAlN, TiSiN, TaSiN, RuTiN), a conductive metal silicide, and / or a conductive metal oxide (for example, PtO, RuO 2 、IrO 2 、SrRuO 3 (SRO), (Ba,Sr)RuO 3 (BSRO), CaRuO 3 (CRO), LSCo, or one or more thereof), but is not limited thereto. The bit line BL may include a single layer or multiple layers of the above materials. In some example embodiments, the bit line BL may include a two-dimensional semiconductor material, for example, the two-dimensional material may include graphene, carbon nanotubes, or a combination thereof.

[0041] Shielding structures SM may be provided between the bit lines BL, respectively, and the shielding structures SM may extend in the first direction D1. The shielding structures SM may include, for example, a conductive material such as metal. The shielding structures SM may be provided in the second interlayer insulating layer 104, and the upper surface of the shielding structures SM may be located at a height lower than the uppermost surface BLa of the bit lines BL.

[0042] As an example, the shielding structure SM may be formed of a conductive material and may include or define an air gap or void therein. As another example, although not shown, an air gap may be provided in the second interlayer insulating layer 104 instead of or in addition to the shielding structure SM.

[0043] The semiconductor pattern SP may be disposed on the bit line BL. A plurality of semiconductor patterns SP may be provided. The semiconductor patterns SP may be spaced apart from each other in the first direction D1 and the second direction D2.

[0044] The semiconductor pattern SP may include a first vertical portion V1, a second vertical portion V2 facing each other, and a horizontal portion H connecting the first and second vertical portions V1 and V2. The horizontal portion H may be adjacent to lower portions of the first and second vertical portions V1 and V2 to connect the first and second vertical portions V1 and V2.

[0045] like Figure 5B As shown, the horizontal portion H of the semiconductor pattern SP may include a first region R1 and a second region R2. The second region R2 may be disposed at both ends of the first region R1 in the second direction D2. The second region R2 may protrude from the first region R1 in the third direction D3 and may extend in the first direction D1. The thickness SPT of the first region R1 of the horizontal portion H of the semiconductor pattern SP in the third direction D3 may be 1.5 nm to 10 nm; example embodiments are not limited thereto.

[0046] like Figure 5A As shown, the horizontal portion H of the semiconductor pattern SP may have a first width W1 in the second direction D2. Figure 8 As shown, the first vertical portion V1 and the second vertical portion V2 of the semiconductor pattern SP may have a second width W2 in the second direction D2. The first width W1 and the second width W2 may be equal to each other.

[0047] The upper surface of the bit line BL may extend in a straight line in the first direction D1. The height of the upper surface of the bit line BL may remain substantially the same in the first direction D1. Therefore, the upper surface of the bit line BL may be the uppermost surface BLa of the bit line BL, which will be described later. The upper surface of the bit line BL may be substantially coplanar with the uppermost surface 104a of the second interlayer insulating layer 104.

[0048] The horizontal portion H of the semiconductor pattern SP may be provided on an upper surface of the bit line BL. A lower surface Hb of the horizontal portion H may make contact with the uppermost surface BLa of the bit line BL and may be located at substantially the same height as the uppermost surface BLa of the bit line BL.

[0049] The horizontal portion H may include a common source / drain region, and the upper portions of the first vertical portion V1 and the second vertical portion V2 may include first and second source / drain regions, respectively. The first vertical portion V1 may include a first channel region between the common source / drain region and the first source / drain region, and the second vertical portion V2 may include a second channel region between the common source / drain region and the second source / drain region. Each of the first vertical portion V1 and the second vertical portion V2 may be electrically connected to a bit line BL. That is, the semiconductor device according to the present invention may have a structure in which a pair of vertical channel transistors share one bit line BL.

[0050] The semiconductor pattern SP may include at least one of oxide semiconductors, such as one or more of InxGayZnzO, InxGaySizO, InxSnyZnzO, InxZnyO, ZnxO, ZnxSnyO, ZnxOyN, ZrxZnySnzO, SnxO, HfxInyZnzO, GaxZnySnzO, AlxZnySnzO, YbxGayZnzO, and InxGayO, but is not limited thereto. In some cases, x+y+z may be equal to 1; however, example embodiments are not limited thereto. As an example, the semiconductor pattern SP may include indium gallium zinc oxide (IGZO). The semiconductor pattern SP may include a single layer or multiple layers of an oxide semiconductor. The semiconductor pattern SP may include an amorphous, crystalline, or polycrystalline oxide semiconductor. In some embodiments, the semiconductor pattern SP may have a band gap energy greater than the band gap energy of silicon. For example, the semiconductor pattern SP may have a band gap energy of approximately 1.5 eV to 5.6 eV. For example, when the semiconductor pattern SP has a band gap energy of about 2.0 eV to 4.0 eV, the semiconductor pattern SP may have the best channel performance. For example, the semiconductor pattern SP may be or include a polycrystalline phase and / or an amorphous phase, but is not limited thereto. In some embodiments, the semiconductor pattern SP may include a two-dimensional semiconductor material, such as graphene, carbon nanotubes, or a combination thereof. The semiconductor pattern SP may be doped, or may be undoped; example embodiments are not limited thereto.

[0051] The word line WL may be disposed between the first vertical portion V1 and the second vertical portion V2. A plurality of word lines WL may be provided. The word lines WL may extend in the second direction D2 and be spaced apart from each other in the first direction D1.

[0052] Each word line WL may include a first word line WL1 and a second word line WL2, which may face each other in the first direction D1. The first word line WL1 may cover an inner surface of the first vertical portion V1, which may be a side of the first vertical portion V1 facing the second vertical portion V2.

[0053] The first word line WL1 may be adjacent to the first channel region of the first vertical portion V1 and may control the first channel region. The second word line WL2 may cover an inner surface of the second vertical portion V2, and the inner surface of the second vertical portion V2 may be a side of the second vertical portion V2 facing the first vertical portion V1. The second word line WL2 may be adjacent to the second channel region of the second vertical portion V2 and may control the second channel region.

[0054] According to some example embodiments, lower portions of the first word line WL1 and the second word line WL2 may protrude toward each other. In this case, the width of the lower portions of the first word line WL1 and the second word line WL2 in the first direction D1 may be greater than the width of the upper portions of the first word line WL1 and the second word line WL2. However, example embodiments are not limited thereto, and for example, although not shown, the widths of the upper and lower portions of the first word line WL1 and the second word line WL2 may be substantially the same.

[0055] The word line WL may include at least one of the following: for example, doped polysilicon, a metal (for example, one or more of Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co), a conductive metal nitride (for example, one or more of TiN, TaN, WN, NbN, TiAlN, TiSiN, TaSiN, RuTiN), a conductive metal silicide, or a conductive metal oxide (for example, PtO, RuO 2 、IrO 2 、SrRuO 3 (SRO), (Ba,Sr)RuO 3 (BSRO), CaRuO 3 (CRO), LSCo, or one or more thereof), but is not limited thereto. The word line WL may include a single layer or multiple layers of the above materials. In some example embodiments, the word line WL may include a two-dimensional semiconductor material, for example, graphene, carbon nanotubes, or a combination thereof.

[0056] The gate insulating pattern Gox may be interposed between the semiconductor pattern SP and the word line WL. In detail, the gate insulating pattern Gox may be interposed between the inner surface of the first vertical portion V1 and the first word line WL1 and between the inner surface of the second vertical portion V2 and the second word line WL2. The gate insulating pattern Gox may further extend between the horizontal portion H of the semiconductor pattern SP and the word line WL. The word line WL may be separated from the semiconductor pattern SP by the gate insulating pattern Gox. The gate insulating pattern Gox may cover the semiconductor pattern SP with a uniform thickness.

[0057] For example, Fig. 7A As shown, a plurality of gate insulation patterns Gox may be respectively interposed between the first vertical portion V1 and the first word line WL1 and between the second vertical portion V2 and the second word line WL2, and may be separated from each other rather than connected on the horizontal portion H. In some example embodiments, the gate insulation patterns Gox may be spaced apart from each other on the horizontal portion H.

[0058] As another example, although not shown, the gate insulating pattern Gox may be interposed between the first vertical portion V1 and the first word line WL1 and between the second vertical portion V2 and the second word line WL2 , and may extend and connect on the horizontal portion H.

[0059] The gate insulating pattern Gox may include at least one of silicon oxide, silicon oxynitride, and a high dielectric material having a dielectric constant higher than that of silicon oxide. The high dielectric material may include metal oxide and / or metal oxynitride. For example, the high dielectric material capable of being used as the gate insulating pattern Gox may include HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO 2 and Al 2 O 3 At least one of, but not limited to.

[0060] The first insulating pattern 120 may be interposed between adjacent semiconductor patterns SP in the first direction D1. A plurality of first insulating patterns 120 may be provided. The first insulating patterns 120 may extend in the second direction D2 across the bit line BL and may be spaced apart from each other in the first direction D1. The first insulating pattern 120 may cover at least a portion of the outer surface of the first vertical portion V1 and the second vertical portion V2. As an example, the first insulating pattern 120 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric material. As an example, the first insulating pattern 120 may be formed of a single layer or multiple layers.

[0061] For example, Fig. 7AAs shown, the first insulating pattern 120 may contact the uppermost surface BLa of the bit line BL. The first insulating pattern 120 may cover the outer surfaces of the first vertical portion V1 and the second vertical portion V2 of the semiconductor pattern SP. The lower surface Hb of the horizontal portion H may be located at substantially the same height as the lowermost surface of the first insulating pattern 120.

[0062] The second insulating pattern 130 may be disposed between the first word line WL1 and the second word line WL2 in the word line WL. A plurality of second insulating patterns 130 may be provided. The second insulating patterns 130 may extend in the second direction D2 across the bit line BL and may be spaced apart from each other in the first direction D1. The first insulating pattern 120 and the second insulating pattern 130 may be alternately arranged in the first direction D1. The second insulating pattern 130 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric material.

[0063] The protection pattern 110 may be interposed between the word line WL and the second insulating pattern 130. The protection pattern 110 may cover the inner surface of the word line WL and may extend onto the horizontal portion H of the semiconductor pattern SP. As an example, the protection pattern 110 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0064] A capping pattern 220 may be provided on an upper surface of the word line WL. The capping pattern 220 may cover an upper surface of the protection pattern 110 and an upper surface of the second insulating pattern 130. The capping pattern 220 may extend in the second direction D2. For example, the capping pattern 220 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0065] The landing pads LP may be disposed on the first vertical portion V1 and the second vertical portion V2 of the semiconductor pattern SP, respectively. The landing pads LP may be in direct contact with and electrically connected to the first vertical portion V1 and the second vertical portion V2. When viewed in a plan view, the landing pads LP may be spaced apart from each other in the first direction D1 and the second direction D2, and may be arranged in various shapes, such as a matrix shape, a zigzag shape, or a honeycomb shape. When viewed in a two-dimensional plan view, each landing pad LP may have various shapes, such as one or more of a circle, an ellipse, a rectangle, a square, a diamond, or a hexagon.

[0066] The landing pad LP may be formed of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx or a combination thereof, or may include doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx or a combination thereof, but is not limited thereto.

[0067] The third interlayer insulating layer 240 may fill the space between the landing pads LP on the first and second insulating patterns 120 and 130. For example, the third interlayer insulating layer 240 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride, and may include a single layer or multiple layers.

[0068] The data storage patterns DSP may be disposed on the landing pads LP, respectively. The data storage patterns DSP may be electrically connected to the first and second vertical portions V1 and V2 of the semiconductor pattern SP through the landing pads LP, respectively.

[0069] According to some example embodiments, the data storage pattern DSP may be or include a capacitor and may include a lower electrode and an upper electrode and a capacitor dielectric layer interposed therebetween. In this case, when viewed in a plan view, the lower electrode may contact the landing pad LP, and the lower electrode may have various shapes such as a circle, an ellipse, a rectangle, a square, a rhombus, or a hexagon.

[0070] Alternatively or additionally, the data storage pattern DSP may be or may include a variable resistance pattern that may be switched between two resistance states by an electric pulse applied to the storage element. For example, the data storage pattern DSP may include one or more of a phase change material, a perovskite compound, a transition metal oxide, and a magnetic material, a ferromagnetic material, or an antiferromagnetic material whose crystal state changes according to the amount of current.

[0071] Figure 7B is a method according to various example embodiments corresponding to Figure 3 In order to simplify the explanation, the description of the contents overlapping with the above contents is omitted.

[0072] Reference Figure 7B, the semiconductor pattern SP may include a first vertical portion V1 and a second vertical portion V2 facing each other, and the first vertical portion V1 and the second vertical portion V2 may be separated. The word line WL may be disposed on each of the first vertical portion V1 and the second vertical portion V2. The word line WL may include a first word line WL1 on an inner surface of the first vertical portion V1 and a second word line WL2 on an inner surface of the second vertical portion V2. The gate insulating pattern Gox may be interposed between the first vertical portion V1 and the first word line WL1 and between the second vertical portion V2 and the second word line WL2. The second insulating pattern 130 may fill the space between the first word line WL1 and the second word line WL2. The lower surface Vb of the first vertical portion V1 and the second vertical portion V2 may be located at substantially the same height as the lower surface Goxb of the gate insulating pattern Gox.

[0073] The upper surface of the bit line BL may extend in a straight line in the first direction D1. The height of the upper surface of the bit line BL may remain substantially the same in the first direction D1. Therefore, the upper surface of the bit line BL may be the uppermost surface BLa of the bit line BL.

[0074] The first and second vertical portions V1 and V2 of the semiconductor pattern SP may be provided on the upper surface of the bit line BL. The lower surfaces Vb of the first and second vertical portions V1 and V2 and the lower surface Goxb of the gate insulating pattern Gox may contact the uppermost surface BLa of the bit line BL and may be located at substantially the same height as the uppermost surface BLa of the bit line BL.

[0075] For example, Figure 7B As shown, the first insulating pattern 120 may be in contact with the uppermost surface BLa of the bit line BL. The first insulating pattern 120 may cover the outer surfaces of the first vertical portion V1 and the second vertical portion V2 of the semiconductor pattern SP. The lower surface Vb of the first vertical portion V1 and the second vertical portion V2 and the lower surface Goxb of the gate insulating pattern Gox may be located at substantially the same height as the lowermost surface of the first insulating pattern 120.

[0076] Figure 7C is a method according to an embodiment of the present invention corresponding to Figure 3 In order to simplify the explanation, the description of the contents overlapping with the above contents is omitted.

[0077] Reference Figure 7C , the upper surface of the bit line BL may have a concavo-convex structure. The upper surface of the bit line BL below the semiconductor pattern SP may be located at a height lower than the uppermost surface BLa of the bit line BL. The uppermost surface BLa of the bit line BL may be or may correspond to an upper surface located at the highest height among the upper surfaces of the bit line BL, and may be provided in a region that does not vertically overlap with the semiconductor pattern SP.

[0078] The lower surface Hb of the horizontal portion H of the semiconductor pattern SP may be located at a lower height than the uppermost surface BLa of the bit line BL. For example, the lower surface Hb of the horizontal portion H may be a portion located at the lowest height among the lower surfaces of the horizontal portion H, but is not limited thereto. At least a portion of the horizontal portion H may be buried in the upper portion of the bit line BL. For example, Figure 7C As shown, the upper surface of the horizontal portion H may be located at a lower height than the uppermost surface BLa of the bit line BL, but is not limited thereto. As another example, although not shown, the upper surface of the horizontal portion H may be located at a higher height than the uppermost surface BLa of the bit line BL or at the same level as the uppermost surface BLa of the bit line BL.

[0079] The lower portions of the first vertical portion V1 and the second vertical portion V2 may be buried in the upper portion of the bit line BL. The lower surface Vb of the first vertical portion V1 and the second vertical portion V2 may be substantially coplanar with the lower surface Hb of the horizontal portion H, and may be located at a height lower than the uppermost surface BLa of the bit line BL. For example, each lower surface Vb of the first vertical portion V1 and the second vertical portion V2 may be a portion located at the lowest height among the lower surfaces Vb of the first vertical portion V1 and the second vertical portion V2, but is not limited thereto. The outer surface of the lower portion of the first vertical portion V1 and the second vertical portion V2 may be surrounded by the bit line BL.

[0080] The bit line BL has a concavo-convex structure, and a portion of the word line WL may be buried in the upper portion of the bit line BL. Therefore, the buried portion of the word line WL may horizontally overlap the bit line BL. Therefore, the word line WL may be effectively controlled or may be more effectively controlled until the lower portion of each of the first and second channel regions (for example, until the lower portion of each of the first and second channel regions provided at a height lower than the uppermost surface BLa of the bit line BL), and as a result, the electrical characteristics and reliability of the semiconductor device may be improved.

[0081] The first insulating pattern 120 may be in contact with the uppermost surface BLa of the bit line BL. The first insulating pattern 120 may cover portions of outer surfaces of the first vertical portion V1 and the second vertical portion V2 that are not buried by the bit line BL. The lower surface Hb of the horizontal portion H of the semiconductor pattern SP may be located at a height lower than the lowermost surface of the first insulating pattern 120.

[0082] Although not shown, the gate insulating pattern Gox may be interposed between the first vertical portion V1 and the first word line WL1 and between the second vertical portion V2 and the second word line WL2 , and may extend and connect on the horizontal portion H. As shown in FIG.

[0083] Fig.7D is a method according to an embodiment of the present invention corresponding to Figure 3In order to simplify the explanation, the description of the contents overlapping with the above contents is omitted.

[0084] Reference Fig.7D , the semiconductor pattern SP may include a first vertical portion V1 and a second vertical portion V2 facing each other, and the first vertical portion V1 and the second vertical portion V2 may be separated. The word line WL may be disposed on each of the first vertical portion V1 and the second vertical portion V2. The word line WL may include a first word line WL1 on an inner surface of the first vertical portion V1 and a second word line WL2 on an inner surface of the second vertical portion V2. The gate insulating pattern Gox may be interposed between the first vertical portion V1 and the first word line WL1 and between the second vertical portion V2 and the second word line WL2. The second insulating pattern 130 may fill the space between the first word line WL1 and the second word line WL2. The lower surface Vb of the first vertical portion V1 and the second vertical portion V2 may be located at substantially the same height as the lower surface Goxb of the gate insulating pattern Gox. For example, the lower surface Goxb of the gate insulating pattern Gox may be a portion located at the lowest height among the lower surface of the gate insulating pattern Gox, but is not limited thereto.

[0085] The upper surface of the bit line BL may have a concavo-convex structure. The upper surface of the bit line BL may be recessed below a region from an outer surface of the first vertical portion V1 to an outer surface of the second vertical portion V2. The bit line BL may have an uppermost surface BLa below a region between the semiconductor patterns SP adjacent in the first direction D1.

[0086] The lower portions of the first vertical portion V1 and the second vertical portion V2 and the lower portion of the gate insulation pattern Gox may be buried in the upper portion of the bit line BL. The lower surface Vb of the first vertical portion V1 and the second vertical portion V2 and the lower surface Goxb of the gate insulation pattern Gox may be located at a height lower than the uppermost surface BLa of the bit line BL. The lower portions of the first vertical portion V1 and the second vertical portion V2 may contact the bit line BL. As an example, a portion of the word line WL may be buried in the upper portion of the bit line BL. The buried portion of the word line WL may horizontally overlap the bit line BL. The lower surfaces of the first word line WL1 and the second word line WL2 may be located at a height lower than the uppermost surface BLa of the bit line BL.

[0087] The first insulating pattern 120 may be in contact with the uppermost surface BLa of the bit line BL. The first insulating pattern 120 may cover outer surfaces of the first vertical portion V1 and the second vertical portion V2 of the semiconductor pattern SP. The lower surface Vb of the first vertical portion V1 and the second vertical portion V2 and the lower surface Goxb of the gate insulating pattern Gox may be located at a height lower than the lowermost surface of the first insulating pattern 120.

[0088] 9A to 15Dand Fig.16 It shows the manufacturing Fig. 7A Hereinafter, reference will be made to Figure 3 , 9A to 15D and Fig.16 Description of manufacturing Fig. 7A In order to simplify the explanation, the description of the contents overlapping with the above contents is omitted.

[0089] Reference Figure 3 and 9A to 9D , a peripheral circuit structure PS may be formed on the substrate 100. Forming the peripheral circuit structure PS may include forming a peripheral gate structure PC, a peripheral contact pad CP, a peripheral contact plug CPLG1, and a first interlayer insulating layer 102 covering them. A second interlayer insulating layer 104 may be formed on the peripheral circuit structure PS. A bit line BL may be formed in the second interlayer insulating layer 104. A plurality of bit lines BL may be provided. The bit lines BL may extend in a first direction D1 and be spaced apart from each other in a second direction D2. The bit lines BL may be formed to be electrically connected to the lower wiring and the wiring in the peripheral circuit structure PS. Forming the bit lines BL may include depositing a bit line layer (not shown) and patterning the bit line layer to form the bit lines BL. The process of forming the peripheral circuit structure PS may include one or more of the following: a deposition process (such as, but not limited to, a chemical vapor deposition process), an etching process (such as, but not limited to, a wet etching and / or a dry etching process), a chemical mechanical planarization process, a photolithography process, an ion implantation process, and a heat treatment; example embodiments are not limited thereto.

[0090] The first insulating layer 120L and the sacrificial layer 121L may be sequentially formed on the second interlayer insulating layer 104 and the bit line BL. In some cases, the first insulating layer 120L and the sacrificial layer 121L may be formed in an in-situ process; example embodiments are not limited thereto. The first insulating layer 120L and the sacrificial layer 121L may completely cover the second interlayer insulating layer 104 and the bit line BL. The first insulating layer 120L may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric material. The sacrificial layer 121L may include, for example, silicon nitride.

[0091] Reference Figure 3 and FIG. 10A to FIG. 10D, a first insulating pattern 120 and a sacrificial pattern 121 may be formed. Forming the first insulating pattern 120 and the sacrificial pattern 121 may include forming a mask pattern (not shown) on the sacrificial layer 121L, sequentially etching the sacrificial layer 121L and the first insulating layer 120L using the mask pattern as an etching mask, and removing the mask pattern. In the etching process, the bit line BL may not be etched. The etching process may include a wet etching process and / or a dry etching process. The first insulating pattern 120 and the sacrificial pattern 121 may be formed in plurality. The first insulating pattern 120 and the sacrificial pattern 121 may extend in the second direction D2 and be spaced apart from each other in the first direction D1.

[0092] The first insulating pattern 120 and the sacrificial pattern 121 may have a first trench region TR1. The first trench region TR1 may be provided in plurality and may extend in the second direction D2. The first trench region TR1 may expose a side surface of the first insulating pattern 120, an upper surface and a side surface of the sacrificial pattern 121, a portion of the second interlayer insulating layer 104, and a portion of the bit line BL.

[0093] Reference Figure 3 and FIG. 11A to FIG. 11D , a mold layer 122L covering the first insulating pattern 120 and the sacrificial pattern 121 may be formed. Forming the mold layer 122L may be performed using one or more layer formation techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), etc. The mold layer 122L may also cover the second interlayer insulating layer 104 and the bit line BL. The mold layer 122L may completely cover the first insulating pattern 120, the sacrificial pattern 121, the second interlayer insulating layer 104, and the bit line BL.

[0094] The mold layer 122L may include a carbon-containing material. For example, the mold layer 122L may include a spin-on hard mask (SOH) and / or an amorphous carbon layer (ACL).

[0095] Reference Figure 3 and FIG. 12A to FIG. 12D , a mold pattern 122 may be formed. Forming the mold pattern 122 may include forming a mask pattern (not shown) on the mold layer 122L, etching the mold layer 122L using the mask pattern as an etching mask, and removing the mask pattern. In the etching process, the bit line BL, the second interlayer insulating layer 104, the first insulating pattern 120, and the sacrificial pattern 121 may not be etched. The mold pattern 122 may be formed in plurality. The mold pattern 122 may extend in the first direction D1 and be spaced apart from each other in the second direction D2. When viewed in a plan view, the mold pattern 122 may not be formed in a portion vertically overlapping the bit line BL.

[0096] The mold pattern 122 may have a second trench region TR2. The second trench region TR2 may be provided in plurality and may extend in the first direction D1. When viewed in a plan view, the second trench region TR2 may be formed in a portion vertically overlapping the bit line BL. A portion of the second interlayer insulating layer 104, a portion of the bit line BL, a side surface of the first insulating pattern 120, and an upper surface and a side surface of the sacrificial pattern 121 may be exposed by the second trench region TR2.

[0097] After forming the mold pattern 122, a surface treatment process (H2 treatment) may be performed by providing hydrogen plasma. Hydrophobic CH bonds may be formed on the surface of the mold pattern 122 through the surface treatment process.

[0098] Reference Figure 3 and FIG. 13A to FIG. 13D , a semiconductor layer SL may be formed. The semiconductor layer SL may be formed using a layer formation technique having excellent step coverage characteristics, such as one or more of chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). The semiconductor layer SL may fill a portion of the second trench region TR2. In detail, the semiconductor layer SL may conformally cover a portion of the second interlayer insulating layer 104 exposed by the second trench region TR2, a portion of the bit line BL, a side surface of the first insulating pattern 120, and an upper surface and a side surface of the sacrificial pattern 121. Therefore, as described above with reference to Figure 5A and Figure 8 As described above, the widths of the semiconductor patterns SP in the second direction D2 may be formed to be the same.

[0099] In the process of forming the semiconductor layer SL, the semiconductor layer SL may not be formed on the mold pattern 122. The semiconductor layer SL is suppressed from being formed in the mold pattern 122 by the surface treatment process using hydrogen plasma. Fig.13A and Fig. 13B As shown, a portion of the semiconductor layer SL may be formed in a lower portion adjacent to the lower surface of the mold pattern 122. For example, the semiconductor layer SL may include a portion protruding in the third direction D3 from a portion adjacent to the mold pattern 122. Figure 5A and Figure 5B As described above, the horizontal portion H of the semiconductor pattern SP may include a first region R1 and a second region R2, and the second region R2 may be disposed on both ends of the first region R1 in the second direction D2. The second region R2 may protrude in the third direction D3 and may extend in the first direction D1.

[0100] Reference Figure 3 and FIG. 14A to FIG. 14D , the mold pattern 122 may be removed. Removing the mold pattern 122 may be performed by a wet etching process.

[0101] Reference Figure 3 and FIG. 15A to FIG. 15D , the sacrificial pattern 121 and a portion of the semiconductor layer SL may be removed. Removing a portion of the semiconductor layer SL may include removing the semiconductor layer SL on a region provided between the bit lines BL adjacent to each other in the second direction D2 and extending in the first direction D1. By removing the semiconductor layer SL, the semiconductor layer SL may be divided into a plurality of semiconductor patterns SP. Each semiconductor pattern SP may include a first vertical portion V1 and a second vertical portion V2 facing each other, and a horizontal portion H connecting the first vertical portion V1 and the second vertical portion V2.

[0102] Although not shown, in the process of removing the semiconductor layer SL, the horizontal portion H of the semiconductor pattern SP may also be removed. Figure 7B As shown, the semiconductor pattern SP may include a first vertical portion V1 and a second vertical portion V2 , and the first vertical portion V1 and the second vertical portion V2 may be spaced apart from each other.

[0103] Reference Figure 3 and Fig.16 , the gate insulating layer GIL, the conductive layer CL, and the protective layer 112 may be formed to completely cover the upper surfaces of the first insulating pattern 120, the semiconductor pattern SP, and the second interlayer insulating layer 104. The gate insulating layer GIL, the conductive layer CL, and the protective layer 112 may conformally cover the inner surfaces of the first vertical portion V1 and the second vertical portion V2, the upper surface of the horizontal portion H, and the upper surface of the first insulating pattern 120. The formation of the gate insulating layer GIL, the conductive layer CL, and the protective layer 112 may be performed using a layer formation technique having excellent step coverage characteristics, such as one or more of chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

[0104] Refer again Figure 3 and Fig. 7A , a word line WL and a gate insulating pattern Gox may be formed. The word line WL may be formed to include a first word line WL1 on the first vertical portion V1 and a second word line WL2 on the second vertical portion V2. Forming the word line WL may include, for example, removing the conductive layer CL on the first insulating pattern 120 and the horizontal portion H to divide the conductive layer CL into a plurality of word lines WL.

[0105] When forming the word line WL, the first insulating pattern 120 and the gate insulating layer GIL on the horizontal portion H may be removed and separated into a plurality of gate insulating patterns Gox. As another example, although not shown, when forming the word line WL, the gate insulating layer GIL on the first insulating pattern 120 may be removed to be separated into a plurality of gate insulating patterns Gox, and the gate insulating layer GIL on the horizontal portion H may remain without being removed to form a portion of the gate insulating pattern Gox. In this case, the gate insulating pattern GIL may have a U-shape connected on the horizontal portion H.

[0106] As an example, although not shown, a portion of the horizontal portion H of the semiconductor pattern SP may be further removed when forming the word line WL and the gate insulating pattern Gox. In this case, the horizontal portion H may be divided into a first sub-horizontal portion and a second sub-horizontal portion (not shown) connected to the first vertical portion V1 and the second vertical portion V2, respectively, and the first sub-horizontal portion and the second sub-horizontal portion may be separated from each other. The first vertical portion V1 and the first sub-horizontal portion may be connected to each other to have an "L" shape, and the second vertical portion V2 and the second sub-horizontal portion may be connected to each other to have an "L" shape.

[0107] As an example, the upper surface of the word line WL may be formed to be located at a height lower than the upper surfaces of the gate insulating pattern Gox and the first insulating pattern 120 .

[0108] A portion of the protective layer 112 may be removed in the removal process. After the removal process, an additional protective layer (not shown) may be formed on the remaining portion of the protective layer 112 , and the remaining portion of the protective layer 112 and the additional protective layer may form the protective pattern 110 .

[0109] Thereafter, a second insulating pattern 130 may be formed between the first word line WL1 and the second word line WL2. Forming the second insulating pattern 130 may include forming a second insulating layer (not shown) covering the semiconductor pattern SP, the gate insulating pattern Gox, and the word line WL, and removing an upper portion of the second insulating layer to separate the second insulating layer into a plurality of second insulating patterns 130. An upper surface of the second insulating pattern 130 may be located at a height lower than an upper surface of the gate insulating pattern Gox and an upper surface of the first insulating pattern 120, and may be formed at a height adjacent to an upper surface of the word line WL.

[0110] The capping pattern 220 may be formed on upper surfaces of the word lines WL, the protection pattern 110, and the second insulating pattern 130. When the capping pattern 220 is formed, upper surfaces of the first insulating pattern 120 and the first and second vertical portions V1 and V2 may be exposed to the outside.

[0111] The landing pads LP may be formed on the first vertical portion V1 and the second vertical portion V2 of the semiconductor pattern SP, respectively. Forming the landing pads LP may include forming a recessed area by removing upper portions of the first vertical portion V1 and the second vertical portion V2, forming a landing pad layer filling the recessed area and covering the cover pattern 220, and separating a portion of the landing pad layer into a plurality of landing pads.

[0112] The third interlayer insulating layer 240 may be formed to fill the space between the landing pads LP on the first and second insulating patterns 120 and 130. The data storage pattern DSP may be formed on each of the landing pads LP. The data storage pattern DSP may be electrically connected to the first and second vertical portions V1 and V2 of the semiconductor pattern SP through the landing pads LP, respectively.

[0113] An oxide semiconductor having a vertical channel structure is formed by depositing a channel material during channel formation and separating the channel by an etching process using an etching mask. However, there may be a problem of interface byproducts due to deposition of an etching mask on the channel material, and the etching process for the vertical structure is very difficult. Therefore, dispersion of the channel may occur due to process difficulties, and the electrical characteristics and reliability of the semiconductor device may deteriorate.

[0114] According to various example embodiments, as described above with reference to 9A to 15D and Fig.16 As described above, after forming the mold pattern 122, the semiconductor layer SL may be deposited in the second trench region TR2. Due to the hydrogen plasma surface treatment process (H2 treatment), the deposition of the semiconductor layer SL on the mold pattern 122 may be suppressed, and the semiconductor layer SL may be selectively deposited in a desired region. For example, there is no process for depositing an etching mask on the channel material, so no interface byproducts may occur. Alternatively or additionally, the etching process (which has a high process difficulty) is not performed on the vertical structure, thereby improving the distribution of the channel. Alternatively or additionally, since the etching process is not performed on the vertical structure, the upper surface 104a of the second interlayer insulating layer 104 between the bit lines BL may not be recessed. Therefore, the upper surface 104a of the second interlayer insulating layer 104 and the uppermost surface BLa of the bit line BL may be coplanar with each other.

[0115] Fig.17 It shows the manufacturing Figure 7C and Fig.7D In order to simplify the explanation, the description of the contents overlapping with the above contents is omitted.

[0116] Reference Fig.17, a first insulating pattern 120 and a sacrificial pattern 121 may be formed. Forming the first insulating pattern 120 and the sacrificial pattern 121 may include forming a mask pattern (not shown) on the sacrificial layer 121L, and sequentially etching the sacrificial layer 121L and the first insulating layer 120L using the mask pattern as an etching mask, and removing the mask pattern. In the etching process, a portion of the upper portion of the bit line BL may be recessed. Therefore, the upper surface of the bit line BL may have a concave-convex structure.

[0117] In the subsequent process, by referring to the above FIG. 11A to FIG. 15D The semiconductor pattern SP may include a first vertical portion V1 and a second vertical portion V2 facing each other and a horizontal portion H connecting the first vertical portion V1 and the second vertical portion V2. When forming the semiconductor pattern SP, the lower portions of the first vertical portion V1 and the second vertical portion V2 and at least a portion of the horizontal portion H may be buried in the upper portion of the bit line BL. Therefore, the semiconductor pattern SP may be manufactured by the above-mentioned subsequent processes. Figure 7C The semiconductor device shown in .

[0118] Although not shown, the horizontal portion H may be removed when the semiconductor pattern SP is formed. Fig.7D As shown, the semiconductor pattern SP may include a first vertical portion V1 and a second vertical portion V2, and the first vertical portion V1 and the second vertical portion V2 are spaced apart from each other. FIG. 11A to FIG. 15D The same process as described is used to manufacture Fig.7D The semiconductor device shown.

[0119] According to various example embodiments, interface byproducts may not be present in a channel material, thereby improving electrical characteristics and / or reliability of a semiconductor device.

[0120] Additionally or alternatively, according to various example embodiments, an etching process may not be performed on a vertical structure having a high processing difficulty to improve distribution of channels, thereby improving electrical characteristics and / or reliability of a semiconductor device.

[0121] When the term "approximately" or "substantially" is used in conjunction with a numerical value in this specification, it is intended that the relevant numerical value includes a manufacturing or operating tolerance (e.g., ±10%) around the numerical value. In addition, when the words "substantially" and "substantially" are used in conjunction with a geometric shape, it is intended that the accuracy of the geometric shape is not required, but the tolerance of the shape is within the scope of the present disclosure. In addition, when the words "substantially" and "substantially" are used in conjunction with a material composition, it is intended that the accuracy of the material is not required, but the tolerance of the material is within the scope of the present disclosure.

[0122] In addition, regardless of whether a value or shape is modified as "about" or "substantially", it should be understood that these values ​​and shapes should be interpreted as including manufacturing or operating tolerances (e.g., ±10%) around the value or shape. Therefore, although the terms "same", "equivalent" or "equal" are used in the description of example embodiments, it should be understood that some imprecision may exist. Therefore, when an element or a value is referred to as being the same as or equal to another value as another element, it should be understood that the element or value is the same as the other element or another value within the desired manufacturing or operating tolerance range (e.g., ±10%).

[0123] Although various example embodiments have been described in detail, it will be appreciated by those skilled in the art that many modifications and changes may be made without departing from the spirit and scope of the appended claims. Therefore, the example embodiments of the inventive concept should be considered in all respects to be illustrative and not restrictive, and the spirit and scope of the invention are indicated by the appended claims. In addition, the example embodiments are not necessarily mutually exclusive. For example, some example embodiments may include one or more features described with reference to one or more figures, and may also include one or more other features described with reference to one or more other figures.

[0124] This application claims the priority of Korean Patent Application No. 10-2023-0136775 filed on October 13, 2023 in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor device, comprising: Peripheral circuit structures on a substrate; an interlayer insulating layer on the peripheral circuit structure; a bit line in the interlayer insulating layer and extending in a first direction; a semiconductor pattern on the bit line and including a first vertical portion and a second vertical portion facing each other in the first direction and a horizontal portion connecting the first vertical portion and the second vertical portion to each other; a first word line and a second word line, on the horizontal portion, adjacent to the first vertical portion and the second vertical portion, respectively; as well as a gate insulating pattern interposed between the first vertical portion and the first word line and between the second vertical portion and the second word line, An upper surface of the interlayer insulating layer and an upper surface of the bit line are coplanar with each other.

2. The semiconductor device according to claim 1, wherein The horizontal portion includes a first region and a second region, and The second region is located on a first end and a second end of the first region in a second direction, the second direction is parallel to the upper surface of the substrate and intersects the first direction, the second region protrudes from the first region in a third direction perpendicular to the upper surface of the substrate, and The second region extends in the first direction. 3 . The semiconductor device according to claim 2 , wherein a thickness of the first region in the third direction is 1.5 nm to 10 nm.

4. The semiconductor device according to claim 1, wherein The horizontal portion has a first width in a second direction parallel to the upper surface of the substrate and intersecting the first direction, The first vertical portion and the second vertical portion have a second width in the second direction, and The first width and the second width are identical to each other.

5. The semiconductor device according to claim 4, wherein The horizontal portion includes a first area and a second area, The second region is located on a first end and a second end of the first region in the second direction, protrudes from the first region in a third direction perpendicular to the upper surface of the substrate, and extends in the first direction. 6 . The semiconductor device according to claim 1 , wherein at least a portion of the horizontal portion is buried in an upper portion of the bit line. 7 . The semiconductor device according to claim 1 , wherein a lower surface of the horizontal portion is at the same height as an uppermost surface of the bit line. 8 . The semiconductor device according to claim 1 , wherein the semiconductor pattern comprises an oxide semiconductor.

9. The semiconductor device according to claim 1, further comprising: landing pads on the first vertical portion and the second vertical portion of the semiconductor pattern; as well as Data storage patterns are respectively arranged on the landing pads.

10. A semiconductor device comprising: A peripheral circuit structure on a substrate; an interlayer insulating layer on the peripheral circuit structure; a bit line in the interlayer insulating layer and extending in a first direction; a semiconductor pattern on the bit line and including a first vertical portion and a second vertical portion facing each other and spaced apart from each other in the first direction; A first word line and a second word line are arranged on an inner surface of the first vertical portion and an inner surface of the second vertical portion, respectively; as well as a gate insulating pattern interposed between the first vertical portion and the first word line and between the second vertical portion and the second word line, An upper surface of the interlayer insulating layer and an upper surface of the bit line are coplanar with each other. 11 . The semiconductor device according to claim 10 , wherein a lower portion of the first vertical portion and a lower portion of the second vertical portion are buried in an upper portion of the bit line. 12 . The semiconductor device according to claim 10 , wherein a lower surface of the first vertical portion and a lower surface of the second vertical portion are at the same height as an uppermost surface of the bit line. 13 . The semiconductor device according to claim 10 , wherein the semiconductor pattern comprises an oxide semiconductor.

14. A method for manufacturing a semiconductor device, the method comprising: forming a peripheral circuit structure on the substrate; forming an interlayer insulating layer on the peripheral circuit structure; forming a bit line in the interlayer insulating layer; stacking a first insulating layer and a sacrificial layer in sequence on the interlayer insulating layer and the bit line; patterning the first insulating layer and the sacrificial layer to form a first insulating pattern and a sacrificial pattern crossing the bit line; forming a mold layer covering the first insulating pattern and the sacrificial pattern; patterning the mold layer to form a mold pattern intersecting the first insulating pattern and the sacrificial pattern; as well as A surface treatment process is performed on the mold pattern so that a surface of the mold pattern has hydrophobicity. The method of claim 14 , wherein the mold pattern comprises carbon. The method of claim 15 , wherein the surface treatment process uses hydrogen plasma.

17. The method according to claim 16, further comprising: A semiconductor layer is formed on an upper surface of the bit line, a side surface of the first insulating pattern, and a side surface and an upper surface of the sacrificial pattern. The method of claim 17 , wherein the semiconductor layer is not formed on the mold pattern. 19 . The method of claim 17 , wherein the semiconductor layer includes a portion adjacent to the mold pattern and protruding in a direction perpendicular to the upper surface of the substrate.

20. The method of claim 17, further comprising: patterning the semiconductor layer to form semiconductor patterns spaced apart from each other on the bit lines, Wherein patterning the semiconductor layer includes removing the sacrificial pattern and portions of the semiconductor layer formed on the side surface and the upper surface of the sacrificial pattern.

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