Semiconductor device and preparation method thereof

Abstract

The invention discloses a semiconductor device and a preparation method thereof, and the preparation method comprises the steps: providing a semiconductor layer, forming a gate cap layer on a barrier layer of the semiconductor layer, forming a gate dielectric layer, forming a first field plate on the gate dielectric layer, enabling the first field plate to correspondingly cover the gate cap layer and extend along the edge of one side of the gate cap layer, a field plate hole is formed in the area, corresponding to the gate cap layer, of the first field plate. Source metal and drain metal are formed, in the horizontal direction, the first field plate is located between the source metal and the drain metal, and the first field plate extends towards the drain metal and covers the upper portion of the edge, close to the drain metal, of the gate cap layer. And forming a gate contact hole, the opening size of the gate contact hole being smaller than the opening size of the field plate hole so as to form a nested hole structure. Therefore, the breakdown phenomenon caused by large electric field intensity between the grid electrode and the drain electrode can be avoided, meanwhile, the preparation technology is simplified, the preparation process is shortened, and the reliability and the yield of the device are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a semiconductor device and a method for preparing the same. Background Art

[0002] High electron mobility transistor (HEMT) is a field effect transistor based on the high mobility characteristics of two-dimensional electron gas in heterojunction. It has high electron mobility at low temperature and low electric field, and can achieve high-speed and low-noise operation. At present, gallium nitride high electron mobility transistor (GaN HEMT) has been widely used in power conversion circuits of consumer electronics due to its advantages such as fast switching speed, low on-resistance and low loss. With the development of science and technology, the application end has put forward higher requirements for power devices such as higher efficiency, higher frequency, miniaturization and lightness. In order to improve the different performances of HEMT devices, the methods adopted are endless. There are also great differences in the structure and preparation methods of HEMT devices. Usually, in order to improve the performance of the device, it will more or less affect the reliability of the HEMT device, increase the difficulty of manufacturing or reduce the production efficiency, so that the application prospects of HEMT devices are limited. Therefore, how to maintain its reliability and improve production efficiency while improving the performance of the device has become a technical problem that gallium nitride HEMT needs to solve urgently. Summary of the invention

[0003] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a semiconductor device and a method for manufacturing the same, so as to improve the device performance and reliability of HEMT and improve the production efficiency.

[0004] In order to achieve the above-mentioned object and other related objects, the present invention provides a method for preparing a semiconductor device, comprising:

[0005] Providing a semiconductor layer, the semiconductor layer comprising a channel layer and a barrier layer;

[0006] forming a gate cap layer on the barrier layer, wherein the gate cap layer covers a portion of the barrier layer;

[0007] forming a gate dielectric layer on the gate cap layer and the barrier layer;

[0008] A first field plate is formed on the gate dielectric layer, the first field plate correspondingly covers the gate cap layer and extends along an edge of one side of the gate cap layer; a field plate hole is formed on a region of the first field plate corresponding to the gate cap layer;

[0009] A source metal and a drain metal are formed, and both the source metal and the drain metal penetrate the gate dielectric layer and are connected to the barrier layer; in the horizontal direction, the first field plate is located between the source metal and the drain metal, and the first field plate extends toward the drain metal and covers the top of the edge of the gate cap layer close to the drain metal;

[0010] Forming a gate contact hole, extending downward from the corresponding field plate hole above the first field plate to expose the gate cap layer, the opening size of the gate contact hole is smaller than the opening size of the field plate hole, and the boundary of the gate contact hole does not overlap with the boundary of the field plate hole to form a nested hole structure;

[0011] A gate metal is formed in the gate contact hole, and the gate metal is connected to the gate cap layer through the gate contact hole.

[0012] Optionally, the step of forming a first field plate on the gate dielectric layer includes:

[0013] forming a field plate metal layer on the gate dielectric layer;

[0014] The field plate metal layer is patterned based on an etching process to form a first field plate having a field plate hole.

[0015] Optionally, the step of forming a first field plate on the gate dielectric layer includes:

[0016] forming a field plate metal layer on the gate dielectric layer;

[0017] Patterning the field plate metal layer to retain a portion of the field plate metal layer covering the gate cap layer and an edge of the gate cap layer close to the drain metal side;

[0018] A hole is opened in a part of the field plate metal layer corresponding to the area covering the gate cap layer to form a field plate hole.

[0019] Optionally, the step of forming the source metal and the drain metal further includes:

[0020] forming a first dielectric layer on the first field plate and the gate dielectric layer, wherein the first dielectric layer fills the field plate hole;

[0021] Forming a source contact hole and a drain contact hole in the first dielectric layer and the gate dielectric layer, wherein the source contact hole and the drain contact hole expose the barrier layer;

[0022] forming a first electrode metal layer on the first dielectric layer, in the source contact hole and in the gate contact hole;

[0023] The first electrode metal layer is patterned, and the first electrode metal layer in the source contact hole and the drain contact hole is retained to obtain the source metal and the drain metal; a portion of the first electrode metal layer located on the first dielectric layer is retained to form a second field plate; in the horizontal direction, the second field plate is between the first field plate and the drain metal, and the second field plate and the first field plate overlap in the vertical direction.

[0024] Optionally, the step of forming a gate contact hole includes:

[0025] The gate contact hole is formed by adopting a photolithography self-alignment process and an etching process.

[0026] Optionally, the step of forming a gate contact hole includes:

[0027] forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer covers the patterned first electrode metal layer;

[0028] A gate contact hole is formed in the second dielectric layer. The gate contact hole penetrates the first dielectric layer and the gate dielectric layer downward from the second dielectric layer to expose the gate cap layer.

[0029] Optionally, the step of forming a gate metal in the gate contact hole includes:

[0030] forming a second electrode metal layer above the second dielectric layer and in the gate contact hole;

[0031] The second electrode metal layer is patterned, at least the second electrode metal layer in the gate contact hole is retained to form a gate metal, and part of the second electrode metal layer on the second dielectric layer is retained to form a third field plate; in the horizontal direction, the third field plate is between the second field plate and the drain metal, and the projections of the third field plate and the second field plate in the vertical direction partially overlap.

[0032] Optionally, a plurality of field plate holes are provided, and the plurality of field plate holes are arranged at intervals in a region of the first field plate corresponding to the gate cap layer, and the gate contact holes are arranged in one-to-one correspondence with the field plate holes.

[0033] According to one aspect of the present invention, there is also provided a semiconductor device, comprising:

[0034] A semiconductor layer, the semiconductor layer comprising a channel layer and a barrier layer;

[0035] a gate cap layer, partially covering the barrier layer;

[0036] A gate dielectric layer covering the gate cap layer and the barrier layer;

[0037] A first field plate is formed on the gate dielectric layer and covers the gate cap layer correspondingly, the first field plate at least covers an edge of one side of the gate cap layer, and a field plate hole is provided in the area of ​​the first field plate corresponding to the gate cap layer;

[0038] The source metal and the drain metal are located above the semiconductor layer. Both the source metal and the drain metal penetrate the gate dielectric layer and are connected to the barrier layer. In the horizontal direction, the first field plate is located between the source metal and the drain metal. The first field plate extends toward the drain metal and covers the edge of the gate cap layer close to the drain metal.

[0039] A gate contact hole extends downward from the corresponding field plate hole above the first field plate to expose the gate cap layer, the gate contact hole has an opening size smaller than the opening size of the field plate hole, and the boundary of the gate contact hole does not overlap with the boundary of the field plate hole, so as to form a nested hole structure with the field plate hole;

[0040] The gate metal is at least located in the gate contact hole, and the gate metal is connected to the gate cap layer through the gate contact hole.

[0041] Optionally, a plurality of field plate holes are provided, and the plurality of field plate holes are arranged at intervals in a region of the first field plate corresponding to the gate cap layer, and the gate contact holes are arranged in one-to-one correspondence with the field plate holes.

[0042] Compared with the prior art, the semiconductor device and the method for manufacturing the same of the present invention have at least the following beneficial effects:

[0043] The method for preparing a semiconductor device of the present invention includes forming a first field plate on a gate dielectric layer, the first field plate correspondingly covers a gate cap layer and extends along the edge of the gate cap layer close to the drain metal direction, and a field plate hole is formed on the region of the first field plate corresponding to the gate cap layer. Thus, the first field plate can completely cover the edge of the gate cap layer close to the drain metal direction, and when the device is turned off, the field plate structure ensures the continuity of the low potential region, making the channel electric field more uniform, thereby avoiding protecting the gate edge from being broken down and improving the reliability of the device. In addition, a field plate hole is formed on the first field plate, and a gate contact hole can be formed subsequently by photolithography alignment, reducing a mask and photolithography process, simplifying the preparation process, and shortening the preparation process. In the process of forming the gate contact hole, the opening size of the gate contact hole is controlled to be smaller than the opening size of the field plate hole, and the boundary of the gate contact hole does not overlap with the boundary of the field plate hole to form a nested hole structure, so that etching to the first field plate when forming the gate contact hole can be avoided, resulting in etching difficulties, and at the same time, the electrical contact between the gate metal formed in the gate contact hole and the first field plate is avoided, thereby improving the reliability and yield of the device. In addition, the present invention does not increase the gate length and the gate-source / gate-drain spacing, that is, the device withstand voltage is improved without increasing the device size.

[0044] The first field plate in the semiconductor device of the present invention includes a portion covering the edge of the gate cap layer close to the drain metal side, which can protect the position of the gate close to the drain side where the electric field strength is large to avoid breakdown. Furthermore, the semiconductor device of the present invention is formed by the above-mentioned semiconductor device preparation method, which also has the technical effect of simplifying the preparation process, shortening the preparation process, and improving the reliability and yield of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1a A schematic diagram of the structure of a semiconductor device in an embodiment of the present invention;

[0046] Figure 1b is a flow chart of steps of a method for preparing a semiconductor device in an embodiment of the present invention;

[0047] Figure 2To provide a schematic structural diagram of a semiconductor layer;

[0048] Figure 3 For Figure 2 A schematic diagram of a structure after a gate cap layer is formed on the semiconductor layer;

[0049] Figure 4 For Figure 3 A schematic diagram of a structure after a gate dielectric layer is formed on the semiconductor layer and the gate cap layer;

[0050] Figure 5 For Figure 4 A schematic diagram of a structure after a first field plate is formed on the gate dielectric layer;

[0051] Figure 6 For Figure 5 A schematic structural diagram after a first dielectric layer is formed on the first field plate and the gate dielectric layer;

[0052] Figure 7 For Figure 6 A schematic diagram of a structure after a source metal, a gate metal and a second field plate are formed on the structure in FIG.

[0053] Figure 8 For Figure 7 A schematic diagram of a structure after a second dielectric layer is formed on the structure in FIG.

[0054] Fig. 9 For Figure 8 A schematic diagram of a structure after a gate contact hole is formed on the structure in FIG.

[0055] Fig.10 For Fig. 9 A schematic diagram of a structure after a gate metal and a third field plate are formed on the structure in FIG.

[0056] Fig.11 For Fig.10 A schematic diagram of a structure after an interlayer dielectric layer is formed on the structure in FIG.

[0057] Fig.12 for Fig.11 A projection view of the structure in the top (vertical) direction;

[0058] Fig.13 is a schematic diagram of the three-dimensional structure of the first field plate;

[0059] Fig.14 For Fig.13 Schematic diagram of the three-dimensional structure after gate metal is formed on the first field plate in FIG.

[0060] List of reference numerals:

[0061] 100 Semiconductor layer

[0062] 101 substrate layer

[0063] 102 Channel layer

[0064] 103 Barrier layer

[0065] 110 Gate cap layer

[0066] 120 gate dielectric layer

[0067] 130 First Board

[0068] 131 Field plate hole

[0069] 140 Isolation Structure

[0070] 150 First dielectric layer

[0071] 161 Source Metal

[0072] 162 Drain Metal

[0073] 163 Second Board

[0074] 170 Second dielectric layer

[0075] 180 Gate contact hole

[0076] 191 Gate Metal

[0077] 192 Third Board

[0078] 200 Interlayer dielectric layer DETAILED DESCRIPTION

[0079] The following specific embodiments illustrate the embodiments of the present invention, and those familiar with the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0080] It should be noted that the diagrams provided in the embodiments of the present invention are only used to illustrate the basic concept of the present invention in a schematic manner. Although the diagrams only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of each component can be changed at will during actual implementation, and the layout of the components may also be more complex. The structures, proportions, sizes, etc. illustrated in the drawings of the specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the limiting conditions that can be implemented in this application, so they have no technical substantive significance. Any structural modification, change in proportional relationship or adjustment of size should still fall within the scope of the technical content disclosed in this application without affecting the effects and purposes that can be achieved by the present invention.

[0081] During the operation of HEMT devices, the drain side is subjected to high voltage, the source / gate side is at low voltage, and the electric field is depleted along the channel direction. The electric field strength is the largest at the edge of the gate near the drain side, and it is also the most likely location for breakdown. Usually, several layers of metal field plates are arranged near the gate position toward the drain to make the electric field distribution in the channel uniform, thereby avoiding premature breakdown of the gate edge and improving the voltage resistance of the device. Figure 1a As shown, in order to avoid the dielectric opening process of the gate contact hole 180 from being engraved on the first field plate 130 when preparing the HEMT device, the inventors leave a certain distance D between the first field plate 130 and the gate cap layer 110. This results in that although the field plate plays a certain role, the edge of the gate cap layer 110 is not completely protected and there is still a high risk of breakdown.

[0082] In order to solve the background technology and the above-mentioned technical problems, the present embodiment provides a semiconductor device and a preparation method thereof, so as to protect the edge of the gate cap layer close to the drain metal direction to prevent the gate edge from being broken down, and at the same time prevent the gate contact hole from being etched onto the field plate, thereby reducing the manufacturing difficulty and simplifying the manufacturing cost.

[0083] The present invention is described in detail below with reference to specific embodiments.

[0084] Example 1

[0085] This embodiment provides a method for preparing a semiconductor device. Figure 1b , the method for preparing the semiconductor device comprises:

[0086] S1: providing a semiconductor layer, wherein the semiconductor layer comprises a channel layer and a barrier layer;

[0087] S2: forming a gate cap layer on the barrier layer, wherein the gate cap layer covers a portion of the barrier layer;

[0088] S3: forming a gate dielectric layer on the gate cap layer and the barrier layer;

[0089] S4: forming a first field plate on the gate dielectric layer, the first field plate correspondingly covering the gate cap layer and extending along an edge of one side of the gate cap layer; a field plate hole is formed on a region of the first field plate corresponding to the gate cap layer;

[0090] S5: forming a source metal and a drain metal, wherein the source metal and the drain metal both penetrate the gate dielectric layer and are connected to the barrier layer; in the horizontal direction, the first field plate is located between the source metal and the drain metal, and the first field plate extends toward the drain metal and covers the top of the edge of the gate cap layer close to the drain metal;

[0091] S6: forming a gate contact hole, extending downward from the corresponding field plate hole above the first field plate to expose the gate cap layer, wherein the opening size of the gate contact hole is smaller than the opening size of the field plate hole, and the boundary of the gate contact hole does not overlap with the boundary of the field plate hole to form a nested hole structure;

[0092] S7: forming a gate metal in the gate contact hole, and connecting the gate metal to the gate cap layer through the gate contact hole.

[0093] Specifically, please refer to Figure 2 , perform step S1 to provide a semiconductor layer 100 , where the semiconductor layer 100 includes a channel layer 102 and a barrier layer 103 .

[0094] As an example, the semiconductor layer 100 is stacked from bottom to top in a substrate layer 101, a channel layer 102, and a barrier layer 103. The material of the substrate layer 101 includes conventional semiconductor substrate materials such as silicon and aluminum oxide. The band gap of the barrier layer 103 is greater than the band gap of the channel layer 102 to form a potential well for accommodating a two-dimensional electron gas (2DEG) at a heterogeneous interface between the channel layer 102 and the barrier layer 103. In this embodiment, the material of the channel layer 102 is gallium nitride, and the material of the barrier layer 103 is gallium aluminum nitride. That is, the semiconductor device manufactured in this embodiment is a gallium nitride HEMT device.

[0095] Please refer to Figure 3 , executing step S2 , forming a gate cap layer 110 on the barrier layer 103 , wherein the gate cap layer 110 covers a portion of the barrier layer 103 .

[0096] As an example, the gate cap layer 110 may be a P-type doped material layer or a metal material layer. When the gate cap layer 110 is a P-type doped material layer, it may be a P-type gallium nitride layer doped with magnesium. When the gate cap layer 110 is a metal material layer, it may be gold, titanium, aluminum, tungsten, etc.

[0097] Furthermore, when the gate cap layer 110 is a P-type doped material layer, a P-type gallium nitride layer can be deposited on the barrier layer 103 by chemical vapor deposition, and then a portion of the region is removed by etching to form the gate cap layer 110 at the gate region.

[0098] Please refer to Figure 4 , perform step S3 to form a gate dielectric layer 120 on the gate cap layer 110 and the barrier layer 103. Specifically, the gate dielectric layer 120 may be formed by chemical vapor deposition, such as low pressure chemical vapor deposition (LPCVD). Optionally, the material of the gate dielectric layer 120 includes silicon nitride. Optionally, as Figure 4 As shown, before forming the gate dielectric layer 120 , a step of forming an isolation structure 140 is also included. The isolation structure 140 vertically penetrates the barrier layer 103 and contacts the channel layer 102 to achieve electrical isolation of the device from other regions in the semiconductor layer 100 .

[0099] Reference Figure 5 Combination Fig.12 , Fig.13 , step S4 is performed to form a first field plate 130 on the gate dielectric layer 120, the first field plate 130 correspondingly covers the gate cap layer 110 and extends along the edge of one side of the gate cap layer 110, and a field plate hole 131 is formed on the region of the first field plate 130 corresponding to the gate cap layer 110. The projection of the first field plate 130 manufactured in this embodiment in the vertical direction completely covers the lower gate cap layer 110, and the first field plate 130 also extends in the direction close to the drain metal 162 formed subsequently in the projection direction in the vertical direction, covering the edge of the gate cap layer 110 close to the drain metal 162, so that the vertical projections between the first field plate 130 and the gate cap layer 110 can overlap each other ("vertical projection" or "projection in the vertical direction" refers to the projection falling on the horizontal plane or the surface of the substrate layer 101), so as to protect the edge position of the gate end close to the drain side and prevent the breakdown phenomenon at the position with large electric field intensity. In addition, in this embodiment, a field plate hole 131 is formed on the area of ​​the first field plate 130 corresponding to the gate cap layer 110. The field plate hole 131 is used for photolithography alignment of the subsequent gate contact hole 180 to avoid etching difficulties caused by the dielectric opening process etching onto the first field plate 130.

[0100] As an example, in the step of forming the first field plate 130 on the gate dielectric layer 120, the step includes: forming a field plate metal layer on the gate dielectric layer 120. Patterning the field plate metal layer based on an etching process to form the first field plate 130 having the field plate hole 131. In the process of forming the first field plate 130 having the field plate hole 131 based on the etching process, a mask having a field plate hole pattern can be used to perform etching to form the first field plate 130, thereby forming the first field plate 130 having the field plate hole 131 based on only one etching process, thereby simplifying the manufacturing process and improving production efficiency.

[0101] As an example, in the step of forming the first field plate 130 on the gate dielectric layer 120, it includes: forming a field plate metal layer on the gate dielectric layer 120, patterning the field plate metal layer to retain a portion of the field plate metal layer covering the gate cap layer 110 and an edge of the gate cap layer 110 on one side close to the drain metal 162, and opening a hole in the portion of the field plate metal layer corresponding to the area covering the gate cap layer 110 to form a field plate hole 131.

[0102] Optionally, the number of the field plate hole 131 is at least 1, and may also be 2 or more. Fig.12 Or 13, when there are multiple field plate holes 131, the multiple field plate holes 131 are arranged at intervals in the region of the first field plate 130 corresponding to the gate cap layer 110.

[0103] Please continue to refer to Figure 7 , execute step S5 to form a source metal 161 and a drain metal 162. The source metal 161 and the drain metal 162 both penetrate the gate dielectric layer 120 and are connected to the barrier layer 103. In the horizontal direction, the first field plate 130 is located between the source metal 161 and the drain metal 162. The first field plate 130 extends toward the drain metal 162 and covers the gate cap layer 110 above the edge of the drain metal 162.

[0104] As an example, before forming the source metal 161 and the drain metal 162, refer to Figure 6 First, a first dielectric layer 150 is formed on the first field plate 130 and the gate dielectric layer 120, and the first dielectric layer 150 fills the field plate hole 131. A source contact hole and a drain contact hole are formed in the first dielectric layer 150 and the gate dielectric layer 120, and the source contact hole and the drain contact hole expose the barrier layer 103. A first electrode metal layer is formed on the first dielectric layer 150, in the source contact hole and in the gate contact hole 180. Figure 7, patterning the first electrode metal layer, retaining the first electrode metal layer in the source contact hole and the drain contact hole to obtain the source metal 161 and the drain metal 162. Retaining part of the first electrode metal layer located on the first dielectric layer 150 to form the second field plate 163. In the horizontal direction, the second field plate 163 is between the first field plate 130 and the drain metal 162, and the second field plate 163 partially overlaps with the projection of the first field plate 130 in the vertical direction. The formed second field plate 163 overlaps with the first field plate 130, and the regional electric field between the gate and the drain can be regulated to achieve uniform electric field distribution. Of course, the second field plate 163 can be prepared separately, or it can be prepared simultaneously with the source metal 161 and the drain metal 162. In this embodiment, the second field plate 163 is prepared simultaneously with the source metal 161 and the drain metal 162, which can reduce the number of times the mask is used and the number of times the photolithography is performed, and shorten the manufacturing cycle.

[0105] Please continue to refer to Fig. 9 , step S5 is performed to form a gate contact hole 180. The gate contact hole 180 extends downward from the corresponding field plate hole 131 above the first field plate 130 to expose the gate cap layer 110, referring to Fig.12 or Fig.14 , the opening size of the gate contact hole 180 is smaller than the opening size of the field plate hole 131, and the boundary of the gate contact hole 180 does not overlap with the boundary of the field plate hole 131 to form a nested hole structure. In order to avoid the electrical contact between the gate metal 191 formed in the gate contact hole 180 and the first field plate 130 or to avoid etching the first field plate 130 during etching of the gate contact hole 180, the opening size of the formed gate contact hole 180 needs to be smaller than the opening size of the field plate hole 131, so that there is a dielectric layer of a certain thickness between the two. Since the field plate hole 131 is formed first in this embodiment, the gate contact hole 180 can be formed based on the window of the field plate hole 131 by using a photolithography self-alignment process and an etching process, thereby reducing the number of times the mask is used and the number of photolithography times, shortening the manufacturing cycle.

[0106] As an example, before forming the gate contact hole 180, refer to Figure 8 , forming a second dielectric layer 170 on the first dielectric layer 150, and the second dielectric layer 170 covers the patterned first electrode metal layer. Fig. 9 A gate contact hole 180 is formed in the second dielectric layer 170 . The gate contact hole 180 penetrates downward from the second dielectric layer 170 through the first dielectric layer 150 and the gate dielectric layer 120 to expose the gate cap layer 110 .

[0107] Please continue to refer to Fig.10 , executing step S5 to form a gate metal 191 in the gate contact hole 180 , and the gate metal 191 is connected to the gate cap layer 110 through the gate contact hole 180 .

[0108] As an example, before forming the gate metal 191, a second electrode metal layer is first formed on the second dielectric layer 170 and in the gate contact hole 180. Fig.10 , patterning the second electrode metal layer, at least retaining the second electrode metal layer in the gate contact hole 180 to form the gate metal 191, retaining part of the second electrode metal layer on the second dielectric layer 170 to form the third field plate 192, in the horizontal direction, the third field plate 192 is between the second field plate 163 and the drain metal 162, and the third field plate 192 partially overlaps with the projection of the second field plate 163 in the vertical direction. Similarly, the formed third field plate 192 overlaps with the second field plate 163, and the regional electric field between the gate and the drain can be regulated to achieve a uniform electric field distribution. Of course, the third field plate 192 can be prepared separately or simultaneously with the gate metal 191. In this embodiment, the third field plate 192 and the gate metal 191 are prepared simultaneously, which can reduce the number of times the mask is used and the number of times the photolithography is performed, thereby shortening the manufacturing cycle.

[0109] After forming the gate metal 191, refer to Fig.11 , further comprising forming an interlayer dielectric layer 200 above the gate metal 191, the third field plate 192 and the second dielectric layer 170, and forming a metal interconnection layer in the interlayer dielectric layer 200. The metal interconnection layer is used to realize the electrical connection and electrical lead-out of the internal structure in the device, and the interlayer dielectric layer 200 is used for electrical isolation between some structures in the metal interconnection layer. A passivation layer is also formed above the interlayer dielectric layer 200 and the metal interconnection layer, and the passivation layer is used to realize insulation protection. The above-mentioned interlayer dielectric layer 200, metal interconnection layer and passivation layer are all conventional settings in the art, and their structures, materials and formation methods are not repeated here.

[0110] The method for preparing the semiconductor device of this embodiment includes forming a first field plate on the gate dielectric layer, the first field plate correspondingly covers the gate cap layer and extends along the edge of the gate cap layer close to the drain metal direction, and a field plate hole is formed on the region of the first field plate corresponding to the gate cap layer. Thus, the first field plate can completely cover the edge of the gate cap layer close to the drain metal direction, and when the device is turned off, the field plate structure ensures the continuity of the low potential area, making the channel electric field more uniform, thereby avoiding protecting the gate edge from being broken down and improving the reliability of the device. In addition, a field plate hole is formed on the first field plate, and a gate contact hole can be formed by photolithography alignment in the subsequent process, reducing a mask and photolithography process, simplifying the preparation process, and shortening the preparation process. In the process of forming the gate contact hole, the opening size of the gate contact hole is controlled to be smaller than the opening size of the field plate hole, and the boundary of the gate contact hole does not overlap with the boundary of the field plate hole to form a nested hole structure, so that etching to the first field plate when forming the gate contact hole can be avoided, resulting in etching difficulties, and at the same time, the electrical contact between the gate metal formed in the gate contact hole and the first field plate is avoided, thereby improving the reliability and yield of the device. In addition, this embodiment does not increase the gate length and the gate-source / gate-drain spacing, that is, the device withstand voltage is improved without increasing the device size.

[0111] Example 2

[0112] This embodiment provides a semiconductor device, which is prepared by any method of the semiconductor device in the above embodiment 1 or other suitable methods. Fig.11 The semiconductor device includes a semiconductor layer 100 , a gate cap layer 110 , a gate dielectric layer 120 , a first field plate 130 , a source metal 161 , a drain metal 162 , a gate contact hole 180 and a gate metal 191 .

[0113] The semiconductor layer 100 includes a channel layer 102 and a barrier layer 103, and the gate cap layer 110 partially covers the barrier layer 103. The gate dielectric layer 120 covers the gate cap layer 110 and the barrier layer 103. The first field plate 130 is formed on the gate dielectric layer 120 and covers the gate cap layer 110. The first field plate 130 at least covers the edge of one side of the gate cap layer 110, and the first field plate 130 is provided with a field plate hole 131 in the region corresponding to the gate cap layer 110. The source metal 161 and the drain metal 162 are located above the semiconductor layer 100. The source metal 161 and the drain metal 162 both penetrate the gate dielectric layer 120 and are connected to the barrier layer 103. In the horizontal direction, the first field plate 130 is located between the source metal 161 and the drain metal 162. The first field plate 130 extends toward the drain metal 162 and covers the edge of the gate cap layer 110 close to the drain metal 162. The gate contact hole 180 extends downward from the corresponding field plate hole 131 above the first field plate 130 to expose the gate cap layer 110. The opening size of the gate contact hole 180 is smaller than the opening size of the field plate hole 131. The boundary of the gate contact hole 180 does not overlap with the boundary of the field plate hole 131, so as to form a nested hole structure with the field plate hole 131. The gate metal 191 is at least located in the gate contact hole 180, and the gate metal 191 is connected to the gate cap layer 110 through the gate contact hole 180.

[0114] Optionally, refer to Fig.11 Combination Fig.12 or Fig.13 The number of the field plate holes 131 is at least one, and may be two or more. When the number of the field plate holes 131 is multiple, the multiple field plate holes 131 are arranged at intervals in the region of the first field plate 130 corresponding to the gate cap layer 110. The gate contact hole 180 extends downward from the corresponding field plate hole 131 above the first field plate 130 to expose the gate cap layer 110, referring to Fig.14 The opening size of the gate contact hole 180 is smaller than the opening size of the field plate hole 131, and the boundary of the gate contact hole 180 does not overlap with the boundary of the field plate hole 131 to form a nested hole structure. In order to avoid electrical contact between the gate metal 191 formed in the gate contact hole 180 and the first field plate 130 or to avoid etching the first field plate 130 during etching of the gate contact hole 180, the opening size of the formed gate contact hole 180 needs to be smaller than the opening size of the field plate hole 131, so that a dielectric layer of a certain thickness exists between the two.

[0115] The first field plate in the semiconductor device of the present invention includes a portion covering the edge of the gate cap layer close to the drain metal side, which can protect the position of the gate close to the drain side where the electric field strength is large to avoid breakdown. The opening size of the gate contact hole is smaller than the opening size of the field plate hole, and the boundary of the gate contact hole does not overlap with the boundary of the field plate hole to form a nested hole structure, thereby avoiding electrical contact between the gate metal subsequently formed in the gate contact hole and the first field plate, and also avoiding the etching difficulty caused by etching the first field plate during etching of the gate contact hole, thereby reducing the manufacturing difficulty and improving the device reliability. Furthermore, the semiconductor device of the present invention is formed by the above-mentioned semiconductor device preparation method, which also has the effect of simplifying the preparation process, shortening the preparation process, and improving the device reliability and yield.

[0116] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: Providing a semiconductor layer, the semiconductor layer comprising a channel layer and a barrier layer; forming a gate cap layer on the barrier layer, wherein the gate cap layer covers a partial area of ​​the barrier layer; forming a gate dielectric layer on the gate cap layer and the barrier layer; forming a first field plate on the gate dielectric layer, the first field plate correspondingly covering the gate cap layer and extending along an edge of one side of the gate cap layer, and a field plate hole being formed on a region of the first field plate corresponding to the gate cap layer; forming a source metal and a drain metal, wherein the source metal and the drain metal both penetrate the gate dielectric layer and are connected to the barrier layer; In the horizontal direction, the first field plate is located between the source metal and the drain metal, and the first field plate extends toward the drain metal and covers the top of the edge of the gate cap layer close to the drain metal; forming a gate contact hole, wherein the gate contact hole extends downward from above the first field plate corresponding to the field plate hole to expose the gate cap layer, the opening size of the gate contact hole is smaller than the opening size of the field plate hole, and the boundary of the gate contact hole does not overlap with the boundary of the field plate hole to form a nested hole structure; A gate metal is formed in the gate contact hole, and the gate metal is connected to the gate cap layer through the gate contact hole.

2. The method for preparing a semiconductor device according to claim 1, wherein: The step of forming a first field plate on the gate dielectric layer includes: forming a field plate metal layer on the gate dielectric layer; The field plate metal layer is patterned based on an etching process to form the first field plate having the field plate hole.

3. The method for preparing a semiconductor device according to claim 1, characterized in that: The step of forming a first field plate on the gate dielectric layer includes: forming a field plate metal layer on the gate dielectric layer; Patterning the field plate metal layer to retain a portion of the field plate metal layer covering the gate cap layer and an edge of the gate cap layer close to the drain metal side; A hole is opened in the area of ​​the partial field plate metal layer corresponding to the area covering the gate cap layer to form the field plate hole.

4. The method for preparing a semiconductor device according to claim 1, wherein: The step of forming the source metal and the drain metal further includes: forming a first dielectric layer on the first field plate and the gate dielectric layer, wherein the first dielectric layer fills the field plate hole; forming a source contact hole and a drain contact hole in the first dielectric layer and the gate dielectric layer, wherein the source contact hole and the drain contact hole expose the barrier layer; forming a first electrode metal layer on the first dielectric layer, in the source contact hole and in the gate contact hole; The first electrode metal layer is patterned, and the first electrode metal layer in the source contact hole and the drain contact hole is retained to obtain the source metal and the drain metal; a portion of the first electrode metal layer located on the first dielectric layer is retained to form a second field plate; in the horizontal direction, the second field plate is between the first field plate and the drain metal, and the second field plate partially overlaps with the projection of the first field plate in the vertical direction.

5. The method for preparing a semiconductor device according to claim 1, characterized in that: The step of forming a gate contact hole includes: The gate contact hole is formed by adopting a photolithography self-alignment process and an etching process.

6. The method for preparing a semiconductor device according to claim 4, characterized in that: The step of forming a gate contact hole includes: forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer covers the patterned first electrode metal layer; A gate contact hole is formed in the second dielectric layer, and the gate contact hole penetrates the first dielectric layer and the gate dielectric layer from the second dielectric layer downward to expose the gate cap layer.

7. The method for preparing a semiconductor device according to claim 6, characterized in that: The step of forming a gate metal in the gate contact hole includes: forming a second electrode metal layer above the second dielectric layer and in the gate contact hole; The second electrode metal layer is patterned, at least the second electrode metal layer in the gate contact hole is retained to form the gate metal, and part of the second electrode metal layer on the second dielectric layer is retained to form a third field plate; in the horizontal direction, the third field plate is between the second field plate and the drain metal, and the third field plate partially overlaps with the projection of the second field plate in the vertical direction.

8. The method for preparing a semiconductor device according to claim 1, characterized in that: The field plate holes are arranged in plurality, and the plurality of field plate holes are arranged at intervals in a region of the first field plate corresponding to the gate cap layer, and the gate contact holes are arranged in one-to-one correspondence with the field plate holes.

9. A semiconductor device, characterized in that: include: A semiconductor layer, wherein the semiconductor layer includes a channel layer and a barrier layer; A gate cap layer partially covering the barrier layer; A gate dielectric layer covering the gate cap layer and the barrier layer; A first field plate is formed on the gate dielectric layer and covers the gate cap layer, the first field plate at least covers an edge of one side of the gate cap layer, and a field plate hole is provided in a region of the first field plate corresponding to the gate cap layer; A source metal and a drain metal are located above the semiconductor layer, the source metal and the drain metal both penetrate the gate dielectric layer and are connected to the barrier layer, in the horizontal direction, the first field plate is located between the source metal and the drain metal, the first field plate extends toward the drain metal and covers the gate cap layer above the edge of the drain metal; A gate contact hole extending downward from above the first field plate corresponding to the field plate hole to expose the gate cap layer, wherein the opening size of the gate contact hole is smaller than the opening size of the field plate hole, and the boundary of the gate contact hole does not overlap with the boundary of the field plate hole, so as to form a nested hole structure with the field plate hole; The gate metal is at least located in the gate contact hole, and the gate metal is connected to the gate cap layer through the gate contact hole.

10. The semiconductor device according to claim 9, characterized in that The field plate holes are arranged in plurality, and the plurality of field plate holes are arranged at intervals in a region of the first field plate corresponding to the gate cap layer, and the gate contact holes are arranged in one-to-one correspondence with the field plate holes.

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