Semiconductor device and electronic device including the same

Abstract

The invention provides a semiconductor device and an electronic apparatus including the same. Comprising a channel layer comprising a semiconductor material, a ferroelectric layer disposed on the channel layer and comprising a ferroelectric material, a gate electrode disposed on the ferroelectric layer, a first insertion layer disposed between the ferroelectric layer and the gate electrode and comprising a first paraelectric material, and a second insertion layer disposed between the channel layer and the ferroelectric layer and including a second paraelectric material having a dielectric constant higher than that of the first paraelectric material.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and an electronic apparatus including the semiconductor device. Background Art

[0002] Ferroelectrics are materials with ferroelectric properties in which the internal electric dipole moment is arranged so as to maintain spontaneous polarization even when an electric field is no longer applied to it from the outside. For example, even if a certain voltage is applied to the ferroelectric and the voltage returns to 0V, the polarization is semi-permanently maintained in the ferroelectric. Research continues to apply these ferroelectric properties to logic devices or memory devices. For example, in the case of a ferroelectric field effect transistor using a ferroelectric, the threshold voltage of the field effect transistor can vary depending on the polarization direction in the ferroelectric. Logic devices or memory devices can be realized by using the threshold voltage variation characteristics of the ferroelectric field effect transistor. Summary of the invention

[0003] Provided are a semiconductor device and an electronic apparatus including the semiconductor device.

[0004] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented embodiments of the disclosure.

[0005] According to one aspect of an embodiment, a semiconductor device includes a channel layer including a semiconductor material, a ferroelectric layer on the channel layer, a gate electrode on the ferroelectric layer, a first insertion layer between the ferroelectric layer and the gate electrode and including a first paraelectric material, and a second insertion layer arranged between the channel layer and the ferroelectric layer, the ferroelectric layer including a ferroelectric material, and the second insertion layer including a second paraelectric material having a dielectric constant higher than the dielectric constant of the first paraelectric material.

[0006] The second paraelectric material may be a high-k material.

[0007] The first paraelectric material may have a band gap energy greater than a band gap energy of a ferroelectric material included in the ferroelectric layer.

[0008] The second paraelectric material may include SiON, GeON, SiGeO x N y 、Al 2 O 3 , Y 2 O 3 、SrTa 2 O 7 , HfO 2 、ZrO 2 、 2 O 5 、SrTiO 3 ,La 2 O3 、SrHfO 3 、BaZrO 3 、BaHfO 3 、 2 Ti 2 O x 、TiO 2 or BaHf 0.5 Ti 0.5 O 3 At least one of .

[0009] The dielectric constant of the first paraelectric material may be less than 4.

[0010] The first paraelectric material may include at least one or more of silicon oxide, silicon nitride, silicon oxynitride, or boron nitride.

[0011] The dielectric constant of the second paraelectric material may be equal to or greater than 4 and equal to or less than 60.

[0012] The thickness of the second insertion layer may be smaller than the thickness of the first insertion layer.

[0013] The thickness of the second insertion layer may be equal to or less than 70% of the thickness of the first insertion layer.

[0014] A ratio of a dielectric constant of the second paraelectric material to a dielectric constant of the first paraelectric material is greater than or equal to 1.2.

[0015] The second paraelectric material may include Al 2 O 3 、 2 O 5 or La 2 O 3 At least one of .

[0016] The semiconductor device may further include an interface layer between the channel layer and the second insertion layer, and the interface layer may include an oxide.

[0017] The semiconductor device may further include a charge trap layer between the ferroelectric layer and the first insertion layer, the charge trap layer contacting the ferroelectric layer.

[0018] The trap energy level of the charge trap layer may be lower than the conduction band of the charge trap layer by 1 eV or more.

[0019] The charge trap layer may include at least one of AlN, GaN, GeN, SiN, CN, InN, YN, ScN, or ZrN.

[0020] The dielectric constant of the paraelectric material included in the charge trap layer may be smaller than the dielectric constant of the second paraelectric material.

[0021] According to another aspect of the embodiment, a semiconductor device includes: a channel layer including a semiconductor material; a ferroelectric layer on the channel layer and including a ferroelectric material; a gate electrode on the ferroelectric layer; a first insertion layer between the ferroelectric layer and the gate electrode, the first insertion layer including at least one or more layers; and a second insertion layer between the channel layer and the ferroelectric layer, the second insertion layer including at least one or more layers, wherein a ratio of a dielectric constant presented by the entire second insertion layer to a dielectric constant presented by the entire first insertion layer is equal to or greater than 1.2.

[0022] The first insertion layer has a multilayer structure including a layer of silicon oxide and a layer of silicon nitride.

[0023] According to another aspect of the embodiment, an electronic device includes a semiconductor substrate and a plurality of memory cells stacked on the semiconductor substrate and in a first direction, wherein each of the plurality of memory cells includes a channel layer comprising a semiconductor material, a ferroelectric layer on the channel layer and comprising a ferroelectric material, a gate electrode on the ferroelectric layer, a first insertion layer between the ferroelectric layer and the gate electrode and comprising a first paraelectric material, and a second insertion layer, the second insertion layer being between the channel layer and the ferroelectric layer and comprising a second paraelectric material having a dielectric constant higher than that of the first paraelectric material, such that a ratio of the dielectric constant of the second paraelectric material to the dielectric constant of the first paraelectric material is equal to or greater than 1.2, wherein the channel layer, the second insertion layer, the ferroelectric layer, the first insertion layer and the gate electrode are sequentially arranged in a second direction perpendicular to the first direction.

[0024] The spacer may be between adjacent gate electrodes of the plurality of memory cells and may include an insulating material.

[0025] According to another aspect of the embodiment, an electronic device includes an array, which includes a plurality of synaptic elements arranged in two dimensions, wherein each of the plurality of synaptic elements includes an access transistor and a ferroelectric field effect transistor, wherein the ferroelectric field effect transistor includes a channel layer comprising a semiconductor material, a ferroelectric layer arranged on the channel layer and including a ferroelectric material, a gate electrode arranged on the ferroelectric layer, a first insertion layer arranged between the ferroelectric layer and the gate electrode and including a first paraelectric material, and a second insertion layer, the second insertion layer being arranged between the channel layer and the ferroelectric layer and including a second paraelectric material having a dielectric constant higher than the dielectric constant of the first paraelectric material, wherein a ratio of the dielectric constant of the second paraelectric material to the dielectric constant of the first paraelectric material is greater than or equal to 1.2. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent through the following description in conjunction with the accompanying drawings, in which:

[0027] Figure 1is a cross-sectional view showing a schematic structure of a semiconductor device according to at least one embodiment;

[0028] Figure 2 is a cross-sectional view conceptually illustrating charge distribution in a semiconductor device according to at least one embodiment when the semiconductor device is in a programmed state;

[0029] Figure 3 illustrates an example of charge density in a semiconductor device according to at least one embodiment when the semiconductor device is in a programmed state;

[0030] Figure 4 is a cross-sectional view conceptually illustrating charge distribution in a semiconductor device according to at least one embodiment when the semiconductor device is in an erase state;

[0031] Figure 5 illustrates an example of charge density in a semiconductor device according to at least one embodiment when the semiconductor device is in an erased state;

[0032] Fig. 6A is a graph showing an example of electric field changes in a first insertion layer and a second insertion layer according to a dielectric constant ratio when a semiconductor device according to at least one embodiment is in a programmed state;

[0033] Figure 6B is a graph showing an example of the amount of charge traps in the first insertion layer and the second insertion layer according to a dielectric constant ratio when the semiconductor device according to at least one embodiment is in a programmed state;

[0034] Figure 7 is a cross-sectional view showing a schematic structure of a semiconductor device according to at least one embodiment;

[0035] Figure 8 is a cross-sectional view showing a schematic structure of a semiconductor device according to at least one embodiment;

[0036] Fig. 9 is a cross-sectional view showing a schematic structure of a memory device according to at least one embodiment;

[0037] Fig.10 is a cross-sectional view showing a schematic structure of a memory device according to at least one embodiment;

[0038] Fig.11A is a cross-sectional view of a schematic structure of a memory device according to at least one embodiment, Fig. 11B It is along Fig.11A A cross-sectional view taken along line AA';

[0039] Fig.12is a diagram showing an equivalent circuit of a memory device according to at least one embodiment;

[0040] Fig.13 is a schematic circuit diagram of a neural network device according to at least one embodiment; and

[0041] Fig.14 is a block diagram schematically illustrating an electronic device including a neural network device according to at least one embodiment. DETAILED DESCRIPTION

[0042] Now will refer to the embodiment in detail, examples of which are shown in the accompanying drawings, wherein the same reference numerals always represent the same elements. In this respect, the present embodiment can have different forms and should not be construed as being limited to the description set forth herein. Therefore, the embodiment is described below only by reference to the accompanying drawings to explain various aspects. As used herein, the term "and / or" includes any and all combinations of one or more associated listed items. Statements such as "at least one of ... " modify the entire element list when after the element list, rather than modifying the individual elements in the list.

[0043] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings. The embodiments described below are merely exemplary, and various modifications may be made from these embodiments. In the following drawings, the same or similar reference numerals represent the same or similar components, and for the sake of clarity and convenience of description, the size of each component in the drawings may be exaggerated.

[0044] When the term "about" or "substantially" is used in conjunction with a numerical value and / or a geometric term in this specification, it is intended that the associated numerical value includes a manufacturing tolerance (e.g., ±10%) around the numerical value. In addition, regardless of whether the numerical value and / or geometric term is modified as "about" or "substantially", it should be understood that these values ​​should be interpreted as including a manufacturing or operating tolerance (e.g., ±10%) around the numerical value and / or geometric term. When referring to "C to D", this means C (including C) to D (including D) unless otherwise specified.

[0045] Hereinafter, it will also be understood that spatially relative terms (such as "above", "top", etc.) are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures, and that the device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative terms used herein are to be interpreted accordingly; and the term "upper portion" or "on..." may also include "existing above, below, left and right sides on a non-contact basis" as well as "directly in contact on the top, bottom, left and right portions".

[0046] Terms such as first, second, etc. may be used to describe various components, but are only used to distinguish one component from another. These terms do not limit the difference in materials or structures of the components.

[0047] Singular expressions include plural expressions unless they are clearly indicated differently in the context. In addition, when a part "includes" a component, it means that it can further include other components, and does not exclude other components, unless otherwise specified and / or contrary.

[0048] In addition, the terms "unit", "module", etc. refer to a unit that processes at least one function or operation, which can be implemented in a processing circuit such as hardware, software, and / or a combination of hardware and software. For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc. The processing circuit may include electrical components such as at least one of a transistor, a resistor, a capacitor, etc. and / or an electronic circuit including the components.

[0049] The use of the term "the" and similar indicative terms can correspond to both the singular and the plural.

[0050] The operations constituting the method may be performed in an appropriate order unless it is explicitly mentioned that the operations should be performed in the order described. In addition, the use of all exemplary terms (e.g., etc.) is intended only to describe the technical concept in detail, and the scope of rights is not limited by these exemplary terms unless limited by the claims.

[0051] Figure 1 is a cross-sectional view showing a schematic structure of a semiconductor device according to at least one embodiment.

[0052] Reference Figure 1 , the semiconductor device 100 includes a channel layer 111, a ferroelectric layer 140 disposed on the channel layer 111 and including a ferroelectric material, a gate electrode 170 disposed on the ferroelectric layer 140, a first insertion layer 160 disposed between the ferroelectric layer 140 and the gate electrode 170 and including a first paraelectric material, and a second insertion layer 130 disposed between the channel layer 111 and the ferroelectric layer 140 and including a second paraelectric material having a dielectric constant different from that of the first paraelectric material. In at least one embodiment, the dielectric constant of the second paraelectric material included in the second insertion layer 130 may be greater than the dielectric constant of the first paraelectric material included in the first insertion layer 160.

[0053] The first insertion layer 160 may contact the ferroelectric layer 140. For example, the first paraelectric material included in the first insertion layer 160 may contact the ferroelectric layer 140. The first insertion layer 160 may include a plurality of dielectric layers, and in these cases, the dielectric constant of the material directly contacting the ferroelectric layer 140 may be less than the dielectric constant of the second paraelectric material included in the second insertion layer 130.

[0054] The semiconductor device 100 is a field effect transistor that exhibits different threshold voltages according to a voltage applied to the gate electrode 170 .

[0055] In at least one embodiment, the channel layer 111 includes a semiconductor material. The channel layer 111 may be defined as a region of the substrate 110 between the source region 113 and the drain region 116 spaced apart from each other on the substrate 110 including the semiconductor material. For example, the channel layer 111 may be defined as a semiconductor region between the source region 113 and the drain region 116 in the substrate 110 on which the source region 113 and the drain region 116 are formed.

[0056] Source region 113 and drain region 116 may be doped with a first conductivity type, and substrate 110 may be doped with a second conductivity type electrically opposite to the first conductivity type. For example, substrate 110 may include a p-type semiconductor, source region 113 and drain region 116 may include an n-type semiconductor, or substrate 110 may include an n-type semiconductor, source region 113 and drain region 116 may include a p-type semiconductor. Substrate 110 may be doped with about 10 16 Up to 10 17 / cm 3 The source region 113 and the drain region 116 may be doped at a relatively low concentration of about 10 19 Up to 10 21 / cm 3 The source region 113 and the drain region 116 may be formed by doping both sides of the upper portion of the substrate 110, respectively. The upper region of the substrate 110 where the source region 113 and the drain region 116 are not formed becomes the channel layer 111. However, this is only an example embodiment. For example, the channel layer 111 may alternatively and / or additionally include a semiconductor material and / or layer disposed on the substrate 110.

[0057] The channel layer 111 may include a group IV semiconductor, a two-dimensional semiconductor, or an oxide semiconductor. The channel layer 111 may include, for example, silicon (Si), germanium (Ge), SiGe, molybdenum disulfide (MoS 2 ), tungsten diselenide (WSe 2), graphene, indium gallium zinc oxide (IGZO), indium tungsten oxide (IWO), zinc tin oxide (ZnSnO and / or ZTO), etc. The channel layer 111 may also include III-V compound semiconductors, II-VI compound semiconductors, etc.

[0058] The substrate 110 , the source region 113 , and the drain region 116 may also each include the material of the channel layer 111 described above.

[0059] When the substrate 110, the channel layer 111, the source region 113, and the drain region 116 include Si, Ge, SiGe, etc., the substrate 110 and the channel layer 111 may be doped with at least one dopant of B, Al, Ga, and In, and the source region 113 and the drain region 116 may be doped with at least one dopant of P, As, and Sb. In these cases, the semiconductor device 100 is referred to as an n-channel metal oxide semiconductor field effect transistor (NMOS). Alternatively, the substrate 110 and the channel layer 111 may be doped with at least one dopant of P, As, and Sb, and the source region 113 and the drain region 116 may be doped with at least one dopant of B, Al, Ga, and In. In these cases, the semiconductor device 100 may be referred to as a p-channel metal oxide semiconductor field effect transistor (PMOS).

[0060] In at least one embodiment, the ferroelectric layer 140 includes a ferroelectric material. A ferroelectric is a material having ferroelectricity that maintains spontaneous polarization by arranging an internal electric dipole moment without applying an electric field from an external electric field source. The threshold voltage of the semiconductor device 100 can be changed according to the polarization direction of the ferroelectric layer 140 (e.g., the direction from the gate electrode 170 to the channel layer 111, or vice versa).

[0061] In at least one embodiment, the ferroelectric material included in the ferroelectric layer 140 may include a hafnium oxide material and / or an aluminum nitride material. For example, the ferroelectric material may have a structure in which a dopant is inserted into a hafnium oxide-based material and / or a structure in which a dopant is inserted into an aluminum nitride-based material. When the ferroelectric material included in the ferroelectric layer 140 is a hafnium oxide-based material, the dopant may be at least one of zirconium (Zr), lanthanum (La), aluminum (Al), silicon (Si), yttrium (Y), and / or gadolinium (Gd). When the ferroelectric material included in the ferroelectric layer 140 is an aluminum nitride-based material, the dopant may be at least one of boron (B) and / or scandium (Sc).

[0062] In addition, the ferroelectric layer 140 may include, for example, a ferroelectric having at least one of a fluorite structure, a perovskite structure, and / or a wurtzite structure. The ferroelectric having a fluoride structure may include, for example, hafnium oxide (HfO 2). For example, hafnium oxide may be doped with at least one element of Zr, La, Al, Si, Y and / or Gd. In at least one embodiment, the ferroelectric layer 140 may include an antiferroelectric material. For example, the antiferroelectric material may include zirconium oxide. For example, zirconium oxide may be doped with at least one element of hafnium (Hf), lanthanum (La), aluminum (Al), silicon (Si), yttrium (Y) and / or gadolinium (Gd). In addition, a ferroelectric having a perovskite structure may include, for example, lead zirconate titanate (PZT). A ferroelectric having a wurtzite structure may include, for example, zinc oxide (ZnO) and / or aluminum nitride (AlN). Such a wurtzite structured ferroelectric may be doped with, for example, at least one element of boron (B) and scandium (Sc). In addition, the ferroelectric layer 140 may include an antiferroelectric material as well as the above-mentioned ferroelectric materials. For example, the ferroelectric layer 140 may include ZrO 2 .

[0063] In at least one embodiment, the ferroelectric layer 140 may include at least one of hafnium (Hf) and zirconium (Zr). For example, the ferroelectric layer 140 may include hafnium and zirconium (eg, Hf) in substantially the same element ratio. 0.5 Zr 0.5 O 2 ), and further includes at least one dopant in a ratio less than about 10 at %, such as an element of lanthanum (La), aluminum (Al), silicon (Si), yttrium (Y), and gadolinium (Gd).

[0064] The thickness of the ferroelectric layer 140 may be, for example, about 5 nm to about 20 nm. However, the embodiment is not limited thereto.

[0065] The gate electrode 170 may include a conductive material. For example, the gate electrode 170 may have a conductivity of about 1 Mohm / square or less. In at least one embodiment, the gate electrode 170 may include one or more selected from the group consisting of metals, metal nitrides, metal carbides, polysilicon, and / or combinations thereof. For example, the metal may include aluminum (Al), tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), etc.; the metal nitride film may include a titanium nitride (TiN) film, a tantalum nitride (TaN) film, etc.; and the metal carbide may be a metal carbide doped with aluminum and / or silicon (or containing aluminum and / or silicon), and may include, for example, TiAlC, TaAlC, TiSiC, TaSiC, etc.

[0066] In at least one embodiment, the gate electrode 170 may have a structure in which multiple materials are stacked. For example, the gate electrode may have a stacked structure of a metal nitride layer / metal layer (such as TiN / Al), and / or a stacked structure of a metal nitride layer / metal carbide layer / metal layer (such as TiN / TiAlC / W). The gate electrode 170 may include a titanium nitride (TiN) layer and / or molybdenum (Mo), and this example may be used for various modifications. In addition, the gate electrode 170 may include a conductive two-dimensional material. For example, the conductive two-dimensional material may include at least one of graphene, black phosphorus, amorphous boron nitride, two-dimensional hexagonal boron nitride (h-BN), phosphorene, etc.

[0067] A first insertion layer 160 disposed between the ferroelectric layer 140 and the gate electrode 170 and a second insertion layer 130 disposed between the ferroelectric layer 140 and the channel layer 111 may be provided to increase a memory window of the semiconductor device 100. The memory window is a difference between two different threshold voltages of the semiconductor device 100. As the memory window increases, the operational reliability of the semiconductor device 100 may be improved. For example, the memory window of the semiconductor device 100 may be about 6.5 V or greater.

[0068] Since the amount of charge traps at the interface between the first insertion layer 160 and the ferroelectric layer 140 is relatively large and the amount of charge traps at the interface between the second insertion layer 130 and the ferroelectric layer 140 is relatively small, the memory window of the semiconductor device 100 may be increased.

[0069] The first paraelectric material included in the first insertion layer 160 may be a low-k material so that more charges are captured at the interface with the ferroelectric layer 140, and the captured charges do not escape through the gate electrode 170. For example, the low-k paraelectric material may have a dielectric constant (k) less than or equal to that of silicon dioxide. The dielectric constant of the first paraelectric material included in the first insertion layer 160 may be less than about 10, about 8 or less, about 7 or less, about 6 or less, and / or about 5 or less. In at least one embodiment, the first paraelectric material may include at least one or more of silicon oxide, silicon nitride, silicon oxynitride, or boron nitride. The first paraelectric material may have a dielectric constant greater than 1 and less than about 4. The first paraelectric material may have a dielectric constant of about 1 to about 3.9. The first paraelectric material may have a dielectric constant greater than about 3 and less than about 8. The first paraelectric material may have a dielectric constant of about 3.5 to about 7.5. The first paraelectric material may have a dielectric constant greater than about 4 and less than about 7. The first paraelectric material may have a band gap energy greater than a band gap energy of a ferroelectric material included in the ferroelectric layer 140 .

[0070] The second paraelectric material included in the second insertion layer 130 may be a high-k material and may reduce (and / or minimize) the amount of charge traps at the interface between the second insertion layer 130 and the ferroelectric layer 140. For example, the high-k paraelectric material may have a higher dielectric constant (k) than silicon oxide. In at least one embodiment, the second paraelectric material may include SiON, GeON, SiGeO x N y 、Al 2 O 3 , Y 2 O 3 、SrTa 2 O 7 , HfO 2 、ZrO 2 、 2 O 5 、SrTiO 3 ,La 2 O 3 、SrHfO 3 、BaZrO 3 、BaHfO 3 、 2 Ti 2 O x 、TiO 2 and / or BaHf 0.5 Ti 0.5 O 3 The second paraelectric material may include Al 2 O 3 、 2 O 5 or La 2 O 3 At least one or more of. The dielectric constant of the second paraelectric material may be approximately equal to or greater than 3.5, equal to or greater than 4, equal to or greater than 4.5, equal to or greater than 6, equal to or greater than 8, equal to or greater than 9, or equal to or greater than 20, and equal to or less than about 60. The dielectric constant of the second paraelectric material may be about 9 to about 10. The dielectric constant of the second paraelectric material may be about 26 to about 28.

[0071] The ratio of the dielectric constant of the second paraelectric material included in the second insertion layer 130 to the dielectric constant of the first paraelectric material included in the first insertion layer 160 can be greater than 1, equal to or greater than 1.1, equal to or greater than 1.2, equal to or greater than 1.3, equal to or greater than 1.5, equal to or greater than 1.7, or equal to or greater than 2.0, and less than or equal to 20, less than or equal to 15, or less than or equal to 10, for example, greater than or equal to 1.2.

[0072] The thickness of the second insertion layer 130 may be less than the thickness of the first insertion layer 160. For example, the thickness of the first insertion layer 160 may be about 3 nm or more, and the thickness of the second insertion layer 130 may be less than about 3 nm. The thickness of the first insertion layer 160 may be greater than or equal to about 2 nm and less than or equal to about 10 nm, and the thickness of the second insertion layer 130 may be less than about 2 nm. The thickness of the second insertion layer 130 may be about 70% or less, about 50% or less, and / or about 1 / 3 or less of the thickness of the first insertion layer 160.

[0073] Figure 2 is a cross-sectional view conceptually illustrating charge distribution in a semiconductor device when the semiconductor device according to at least one embodiment is in a programmed state, and Figure 3 An example of charge density in a semiconductor device when the semiconductor device according to at least one embodiment is in a programmed state is shown.

[0074] Reference Figure 2 In the case of the NMOS type semiconductor device 100, when the positive charges in the ferroelectric layer 140 are directed toward the channel layer 111 and the negative charges are directed toward the gate electrode 170, the semiconductor device 100 may be in a programming state. In the programming state, negative charges may be collected in the second insertion layer 130, and positive charges may be collected in the first insertion layer 160. In particular, negative charges may be collected at the interface with the ferroelectric layer 140 in the second insertion layer 130. In addition, positive charges may be collected at the interface with the ferroelectric layer 140 in the first insertion layer 160. In this programming state, electrons may easily flow along the channel layer 111, and the threshold voltage of the semiconductor device 100 may be reduced.

[0075] exist Figure 3 In the graph of , the vertical axis represents the charge density, and the horizontal axis represents the positions of the gate electrode 170, the first insertion layer 160, the ferroelectric layer 140, the second insertion layer 130, and the channel layer 111 in the semiconductor device 100. Figure 3 , the charge density Q of the positive charges trapped at the interface between the first insertion layer 160 and the ferroelectric layer 140 it,I1 can be greater than the polarization value P of the ferroelectric layer 140 r In addition, the charge density Q of the negative charges trapped at the interface between the second insertion layer 130 and the ferroelectric layer 140 is it,I2 The absolute value of the polarization value of the ferroelectric layer 140 may be smaller than the polarization value -P r The absolute value of .

[0076] Figure 4 is a cross-sectional view conceptually illustrating charge distribution in a semiconductor device when the semiconductor device according to at least one embodiment is in an erase state, and Figure 5An example of charge density in a semiconductor device when the semiconductor device according to at least one embodiment is in an erase state is shown.

[0077] Reference Figure 4 In the case of the NMOS type semiconductor device 100, when the negative charges in the ferroelectric layer 140 are directed toward the channel layer 111 and the positive charges are directed toward the gate electrode 170, the semiconductor device 100 may be in an erased state. The programming state and the erased state may be selectively switched by applying a positive coercive voltage or a negative coercive voltage to the gate electrode 170 of the semiconductor device 100. In the erased state, positive charges may be collected in the second insertion layer 130, and negative charges may be collected in the first insertion layer 160. Positive charges may be collected to the interface with the ferroelectric layer 140 in the second insertion layer 130, and negative charges may be collected to the interface with the ferroelectric layer 140 in the first insertion layer 160. In this erased state, electrons may not easily flow along the channel layer 111, and the threshold voltage of the semiconductor device 100 may be increased.

[0078] Reference Figure 5 The absolute value of the charge density of negative charges trapped at the interface between the first insertion layer 160 and the ferroelectric layer 140 may be greater than the polarization value −P of the ferroelectric layer 140. r In addition, the charge density of positive charges trapped at the interface between the second insertion layer 130 and the ferroelectric layer 140 may be less than the polarization value P of the ferroelectric layer 140. r .

[0079] although Figures 2 to 5 The description shows that the semiconductor device 100 is an NMOS, but the same principle can be applied to the case where the semiconductor device 100 is a PMOS. For example, when the semiconductor device 100 is a PMOS, it should be understood that Figures 2 to 5 The polarity of the charges described in can be reversed.

[0080] like Figure 3 and Figure 5 As shown, the semiconductor device 100 can increase the memory window of the semiconductor device 100 by including a first insertion layer 160 having a large number of charge traps and a second insertion layer 130 having a small number of charge traps. In addition, the amount of charge traps in the second insertion layer 130 can be smaller than the amount of charge traps between the gate electrode 170 and the ferroelectric layer 140 (e.g., the amount of charge traps in the first insertion layer 130), and can be smaller than the polarization in the ferroelectric layer 140. Therefore, the memory window of the semiconductor device 100 can be further increased.

[0081] The memory window (MW) of the semiconductor device 100 may be expressed by Equation 1 below.

[0082] [Equation 1]

[0083]

[0084] In the above equation 1, ΔP is the polarization amount of the ferroelectric layer 140, and ΔQ it,I2 is the amount of charge trapped at the interface between the ferroelectric layer 140 and the second insertion layer 130, ΔQ it,I1 is the amount of charge trapped at the interface between the ferroelectric layer 140 and the first insertion layer 160, C Ferro is the capacitance of the ferroelectric layer 140, C I1 is the capacitance of the first insertion layer 160 .

[0085] As described above, since the semiconductor device 100 according to the embodiment has a structure in which ΔQ it,I2 can reduce and ΔQ it,I1 -ΔQ it,I2 The structure can be increased, and thus the semiconductor device 100 can have a large memory window.

[0086] Fig. 6A is a graph showing an example of electric field changes in the first insertion layer and the second insertion layer according to a dielectric constant ratio when the semiconductor device according to at least one embodiment is in a programmed state.

[0087] In the graph, k(I2) is the dielectric constant of the second paraelectric material included in the second insertion layer 130, and k(I1) is the dielectric constant of the first paraelectric material included in the first insertion layer 160. As k(I2) / k(I1) increases, the electric field intensity in the first insertion layer 160 increases, and the electric field intensity in the second insertion layer 130 decreases.

[0088] As k(I2) / k(I1) increases, the electric field intensity in the first insertion layer 160 increases with a very sharp slope, and the electric field intensity in the second insertion layer 130 decreases with a very sharp slope. When k(I2) / k(I1) is about 10 or more and / or about 15 or more, the increase in the electric field intensity in the first insertion layer 160 and the decrease in the electric field intensity in the second insertion layer 130 gradually saturate.

[0089] In view of this, the first paraelectric material of the first insertion layer 160 and the second paraelectric material of the second insertion layer 130 may be set so that k(I2) / k(I1) is greater than about 1. The first paraelectric material of the first insertion layer 160 and the second paraelectric material of the second insertion layer 130 may be determined so that k(I2) / k(I1) is about 10 or less, about 15 or less, and / or about 20 or less. The first paraelectric material of the first insertion layer 160 and the second paraelectric material of the second insertion layer 130 may be determined so that k(I2) / k(I1) is greater than 1 and equal to or less than about 20, or equal to or greater than about 1.2 and equal to or less than about 15. The first paraelectric material of the first insertion layer 160 and the second paraelectric material of the second insertion layer 130 can be determined so that k(I2) / k(I1) is greater than 1, equal to or greater than 1.1, equal to or greater than 1.2, equal to or greater than 1.3, equal to or greater than 1.5, equal to or greater than 1.7, or equal to or greater than 2.0, and equal to or less than about 20, equal to or less than about 15, or equal to or less than about 10.

[0090] Figure 6B is a graph showing an example of the amount of charge traps in the first insertion layer and the second insertion layer according to a dielectric constant ratio when the semiconductor device according to at least one embodiment is in a programmed state.

[0091] The graph shows the amount of charge ΔQ trapped at the interface between the ferroelectric layer 140 and the first insertion layer 160 according to the dielectric constant ratio. it,I1 and the amount of charge ΔQ trapped at the interface between the ferroelectric layer 140 and the second insertion layer 130 it,I2 It can be seen that as k(I2) / k(I1) increases, ΔQ it,I1 / ΔQ it,I2 Rapidly increasing. Considering this graph and considering ΔQ it,I1 / ΔQ it,I2 To contribute to the storage window, k(I2) / k(I1) can be set appropriately.

[0092] Figure 7 is a cross-sectional view showing a schematic structure of a semiconductor device according to at least one embodiment.

[0093] The semiconductor device 101 of this embodiment is Figure 1 The semiconductor device 100 is different in that an interface layer 112 is further included between the channel layer 111 and the second insertion layer 130. The rest of the configuration is the same or substantially similar.

[0094] The interface layer 112 may be formed by naturally oxidizing a portion of the semiconductor material included in the substrate 110 and / or the channel layer 111 during the process of manufacturing the semiconductor device 100. Therefore, the interface layer 112 may include an oxide of the semiconductor material. For example, when the substrate 110 and / or the channel layer 111 includes Si, the interface layer 112 may include SiO 2 When the substrate 110 and / or the channel layer 111 include Ge, the interface layer 112 may include GeO 2 When the substrate 110 and / or the channel layer 111 include SiGe, the interface layer 112 may include SiGeO 4 .

[0095] During the process of manufacturing the semiconductor device 101, the second insertion layer 130 may be nitrided to reduce the charge trapping amount of the second insertion layer 130 and increase the dielectric constant of the second insertion layer 130. In these cases, the interface layer 112 may include oxynitrides of semiconductor materials included in the substrate 110 and / or the channel layer 111. For example, the interface layer 112 may include SiON, GeON, SiGeO x N y wait.

[0096] The thickness of the interface layer 112 may be about 1 nm to about 5 nm.

[0097] Figure 8 is a cross-sectional view showing a schematic structure of a semiconductor device according to at least one embodiment.

[0098] The semiconductor device 102 of this embodiment is Figure 1 The semiconductor device 100 is different in that a charge trap layer 150 is further arranged between the first insertion layer 160 and the ferroelectric layer 140. The remaining configurations may be the same and / or substantially similar.

[0099] The charge trap layer 150 may include a material having a dielectric constant less than that of the second paraelectric material included in the second insertion layer 130. The charge trap layer 150 may be in contact with the ferroelectric layer 140. The charge trap layer 150 may be a paraelectric material. In at least one embodiment, the charge trap layer 150 may be an amorphous-based material. The charge trap layer 150 may have a large band gap energy and a deep trap energy level. The charge trap layer 150 may have a band gap energy of, for example, about 4 eV or more, and may have a deep trap energy level below the conduction band. For example, the deep trap energy level may be about 1.0 eV or more and / or about 1.5 eV or more lower than the conduction band. The charge trap layer 150 may include at least one of AlN, GaN, GeN, SiN, CN, InN, YN, ScN and / or ZrN. Alternatively, the charge trap layer 150 may also include various nitrides, polycrystalline silicon, amorphous silicon, etc.

[0100] The charge trap layer 150 may have a thickness in the same and / or similar range as the first insertion layer 160. The thickness of the charge trap layer 150 may be greater than the thickness of the second insertion layer 130. Alternatively, the thickness of the first insertion layer 160 and the thickness of the charge trap layer 150 may be determined such that the sum of the thickness of the charge trap layer 150 and the thickness of the first insertion layer 160 is greater than the thickness of the second insertion layer 130.

[0101] The charge trap layer 150 and the first insertion layer 160 can increase the memory window of the semiconductor device 102. Since the charge trap layer 150 is provided, the amount of charge captured at the interface of the ferroelectric layer 140 toward the gate electrode 170 can be further increased, and the difference with the amount of charge captured at the interface of the ferroelectric layer 140 toward the channel layer 111 can be further increased.

[0102] Although not shown, Figure 7 The interface layer 112 may be further formed between the channel layer 111 and the second insertion layer 130 .

[0103] According to another embodiment, a semiconductor device is provided, comprising: a channel layer comprising a semiconductor material; a ferroelectric layer disposed on the channel layer and comprising a ferroelectric material; a gate electrode disposed on the ferroelectric layer; a first insertion layer between the ferroelectric layer and the gate electrode; and a second insertion layer between the channel layer and the ferroelectric layer; wherein the dielectric constant of the second insertion layer is greater than the dielectric constant of the first insertion layer.

[0104] The ratio of the dielectric constant of the second insertion layer to the dielectric constant of the first insertion layer can be greater than 1.0, greater than or equal to 1.1, greater than or equal to 1.2, greater than or equal to 1.3, greater than or equal to 1.5, greater than or equal to 1.7, or greater than or equal to 2.0, and less than or equal to 20, less than or equal to 15, or less than or equal to 10.

[0105] The first insertion layer may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and boron nitride. The second insertion layer may include Al 2 O 3 、 2 O 5 and La 2 O 3 At least one of .

[0106] Each of the first insertion layer and the second insertion layer includes one or more layers. At least one of the first insertion layer and the second insertion layer may have a multilayer structure including a plurality of layers. In this case, the dielectric constant of the first insertion layer and the dielectric constant of the second insertion layer may represent the dielectric constant of the entire first insertion layer and the dielectric constant of the entire second insertion layer, respectively. That is, the dielectric constant of the first insertion layer may be determined by the dielectric constant of the dielectric material included in the plurality of layers forming the first insertion layer, and the dielectric constant of the second insertion layer may be determined by the dielectric constant of the dielectric material included in the plurality of layers forming the second insertion layer.

[0107] For example, the first insertion layer may have a multilayer structure in which Si, O, and N are combined in various ways, such as SiO 2 , SiN, SiON or SiO / SiN / SiO, etc. The first insertion layer has a multilayer structure including a layer of silicon oxide and a layer of silicon nitride. In this case, the dielectric constant of the first insertion layer may be equal to or greater than 4 and equal to or less than 7.

[0108] The semiconductor device may further include an interface layer between the channel layer and the second insertion layer. The semiconductor device may further include a charge trap layer between the first insertion layer and the ferroelectric layer.

[0109] The semiconductor devices 100, 101 and 102 described above may be applied to various electronic devices, for example, to individual memory cells in a memory device. The memory device may have a three-dimensional structure, a vertical structure, etc., and may have, for example, a vertical NAND (VNAND) structure.

[0110] Fig. 9 is a cross-sectional view showing a schematic structure of a memory device according to at least one embodiment.

[0111] The memory device 200 includes a plurality of memory cells MC. The plurality of memory cells MC may be repeatedly arranged in a first direction (Z direction). Each of the memory cells MC may have a structure similar to that of the semiconductor device 100 described above.

[0112] The memory device 200 includes a plurality of gate electrodes 270 spaced apart from each other in a first direction (Z direction). Spacers 280 including an insulating material may be disposed between adjacent gate electrodes of the gate electrodes 270. The spacers 280 may include, for example, silicon oxide (eg, SiO 2 , SiOC, SiON, etc.). However, the embodiment is not limited thereto.

[0113] One side surface of each of the plurality of gate electrodes 270 and the plurality of spacers 280 (which are alternately arranged) may be connected to align, and the first insertion layer 260 may be arranged on the connected surface, and the ferroelectric layer 240, the second insertion layer 230, and the channel layer 210 are sequentially arranged. In at least one embodiment, an insulating layer 220 may be included. However, this may be only an example, and the insulating layer 220 may be omitted. The direction in which the first insertion layer 260, the ferroelectric layer 240, the second insertion layer 230, and the channel layer 210 are sequentially arranged may be a second direction (X direction) perpendicular to the first direction (Z direction).

[0114] Each of the gate electrode 270 , the first insertion layer 260 , the ferroelectric layer 240 , the second insertion layer 230 , and the channel layer 210 may include the materials given above as the materials of the gate electrode 170 , the first insertion layer 160 , the ferroelectric layer 140 , the second insertion layer 130 , and the channel layer 111 , respectively.

[0115] Each gate electrode 270 and a region of the first insertion layer 260 , the ferroelectric layer 240 , the second insertion layer 230 , and the channel layer 210 facing the gate electrode 270 form an individual memory cell MC.

[0116] In addition, although not shown, an interface layer (eg, Figure 7 described above).

[0117] Fig.10 is a cross-sectional view showing a schematic structure of a memory device according to at least one embodiment.

[0118] The memory device 201 of this embodiment is Fig. 9 The memory device 200 is different in that the charge trap layer 250 is further disposed between the first insertion layer 260 and the ferroelectric layer 240, and the remaining configurations are substantially the same. The charge trap layer 250 may include Figure 8 The charge trap layer 150 is made of the material described above.

[0119] In addition, although not shown, an interface layer (eg, Figure 7 described above).

[0120] Fig.11A is a cross-sectional view of a schematic structure of a memory device according to at least one embodiment, Fig. 11B It is along Fig.11A A cross-sectional view taken along line AA'.

[0121] Reference Fig.11A, the memory device 300 may include a substrate 301 and a cell string CS formed on the substrate 301. One cell string CS is shown in the drawing, but this is only an example, and the memory device 300 may include a plurality of cell strings. For example, the plurality of cell strings CS may extend away from the substrate 301 along a first direction (Z direction), and may be arranged two-dimensionally in second and third directions (X and Y directions) perpendicular to the first direction. As will be described later, Fig.12 As shown in the circuit diagram of , these multiple cell strings can be provided in k*n and arranged in a matrix form, and can be referred to as CSij according to the position of each row and each column, where 1≤i≤k and 1≤j≤n.

[0122] The substrate 301 may be a semiconductor substrate. The substrate 301 may include a silicon material doped with a first type of impurity. For example, the substrate 301 may include a silicon material doped with a p-type impurity. For example, the substrate 301 may be a p-type well (e.g., a pocket p-well). However, the embodiment is not limited thereto, and the substrate 301 may include various semiconductor materials and / or dopant types.

[0123] A common source region 305 is provided on the substrate 301. The common source region 305 may be of a different type than the semiconductor material included in the substrate 301, and may be, for example, an n-type. The common source region 305 may be connected to, for example, Fig.12 The common source line CSL shown in the circuit diagram.

[0124] like Fig. 11B As shown in the cross-sectional view of , the cell string CS may have a circular cross-section. For example, the cell string CS may have a cylindrical shape with a central axis parallel to the Z direction. However, this is merely an example, and the cell string CS may be modified into the form of an elliptical column or a polygonal column.

[0125] The plurality of gate electrodes 370 are arranged to be spaced apart from each other in an axial direction (eg, in the Z direction) of the cell string CS, and a spacer 380 including an insulating material may be arranged between every two adjacent gate electrodes of the plurality of gate electrodes 370 .

[0126] The gate electrode 370 and the spacer 380 may have a cylindrical shell shape whose inner surfaces are connected to each other, and the first insertion layer 360 may be conformally formed on the inner surface. In addition, the ferroelectric layer 340 may be conformally formed on the first insertion layer 360, and then the second insertion layer 330 and the channel layer 310 may be conformally formed.

[0127] The cell string CS may be filled at a center portion thereof with a cylindrical insulating layer 320. However, this may be only an example, and the insulating layer 320 may be omitted or formed in a cylindrical shell form.

[0128] The materials of the channel layer 310, the second insertion layer 330, the ferroelectric layer 340, the first insertion layer 360 and the gate electrode 370 may include reference Figure 1 The materials shown in the channel layer 111, the second insertion layer 130, the ferroelectric layer 140, the first insertion layer 160, and the gate electrode 170 are described.

[0129] One end of the channel layer 310 (eg, a region of the channel layer 310 located at the lowermost end of the cell string CS) may be in contact with the common source region 305 .

[0130] A drain 390 may be provided on the cell string CS. The drain 390 may include, for example, a silicon material doped with an n-type. The other end of the channel layer 310 (for example, a region of the channel layer 310 located at the uppermost end of the cell string CS) may contact the drain 390. The drain 390 may be connected to a bit line through a contact plug.

[0131] The gate electrode 370 and a region of the first insertion layer 360 , the ferroelectric layer 340 , the second insertion layer 330 , and the channel layer 310 facing the gate electrode 370 form a memory cell MC.

[0132] The memory cells MC are continuously arranged in the vertical direction (Z direction) to constitute a cell string CS. In addition, the common source region 305 and the drain 390 respectively connected to both ends of the cell string CS may be respectively connected to Fig.12 The gate electrode 370 is connected to the word line WL. By applying voltages to the word line WL, the common source line CSL and the bit line BL, programming, reading and erasing processes can be performed on a plurality of memory cells MC.

[0133] As described above, the ferroelectric layer 340 is a material in which the polarization value is semi-permanently maintained in the material even if the voltage returns to 0V after a certain voltage is applied to the ferroelectric layer 340, and the polarity (direction) of the residual polarization may depend on the polarity (direction) of the voltage applied from the outside. The region of the ferroelectric layer 340 corresponding to each memory cell MC may have a residual polarization corresponding to the electric field formed in the ferroelectric layer 340 by the voltage applied to the gate electrode 370. Due to the polarization direction of the ferroelectric layer 340, a conductivity difference may occur in the region of the channel layer 310 corresponding to the memory cell MC, by which information can be written or confirmed.

[0134] In addition, the memory device 300 according to the embodiment includes the first insertion layer 360 and the second insertion layer 330 made of a paraelectric material satisfying a predetermined dielectric constant ratio, so that the memory window may be increased, and thus the reliability of the memory operation may be improved.

[0135] Fig.12is a diagram showing an equivalent circuit of a memory device according to at least one embodiment. Fig.12 , the memory device may include a plurality of memory cell strings CS11 to CSkn. The plurality of memory cell strings CS11 to CSkn may be arranged two-dimensionally in the row direction and the column direction to form rows and columns. Each cell string CSij (where 1≤i≤k and 1≤j≤n) may be connected to a bit line BL, a string selection line SSL, a word line WL, and a common source line CSL.

[0136] The cell string CSij includes a memory cell MC and a string selection transistor SST. The memory cell MC and the string selection transistor SST of each cell string CSij may be stacked in a height direction.

[0137] The rows of the plurality of cell strings CSij are respectively connected to different string selection lines SSL1 to SSLk. For example, the string selection transistors SST of the cell strings CS11 to CS1n are commonly connected to the string selection line SSL1. The string selection transistors SST of the cell strings CSk1 to CSkn are commonly connected to the string selection line SSLk.

[0138] The columns of the plurality of cell strings CSij are respectively connected to different bit lines BL1 to BLn. For example, the memory cells MC and string selection transistors SST of the cell strings CS11 to CSk1 may be commonly connected to the bit line BL1, and the memory cells MC and string selection transistors SST of the cell strings CS1n to CSkn may be commonly connected to the bit lines BL1 to BLn.

[0139] Rows of multiple cell strings CSij may be connected to different common source lines CSL1 to CSLk, respectively. For example, string selection transistors SST of cell strings CS11 to CS1n may be commonly connected to a common source line CSL1, and string selection transistors SST of cell strings CSk1 to CSkn may be commonly connected to a common source line CSLk.

[0140] Located at Fig.11A String selection transistors SST and / or memory cells MC at the same height of the substrate 301 may be commonly connected to one of the word lines WL1 to WLm, and memory cells MC located at different heights may be respectively connected to different word lines WL1 to WLm.

[0141] In this structure, write and read operations can be performed in units of rows of memory cell strings CS11 to CSkn. For example, memory cell strings CS11 to CSkn can be selected as units of a row by a common source line CSL, and memory cell strings CS11 to CSkn can be selected as units of a row by a string selection line SSL. In addition, in a selected row of memory cell strings CS11 to CSkn, write and / or read operations can be performed in units of pages. For example, a page can be a row of memory cells MC connected to one word line WL. In a selected row of memory cell strings CS11 to CSkn, memory cells MC can be selected in units of pages by word lines WL.

[0142] The circuit structure shown is only an example. For example, the number of rows of cell strings CSij (where 1≤i≤k and 1≤j≤n) can be increased or decreased. As the number of rows of cell strings CS changes, the number of string selection lines connected to the rows of cell strings CS and the number of cell strings CS connected to one bit line BL can also change. As the number of rows of cell strings CS changes, the number of common source lines connected to the rows of cell strings CS can also change.

[0143] The number of columns of cell strings CS may also increase or decrease. As the number of columns of cell strings CSij changes, the number of bit lines BL connected to the columns of cell strings CSij and the number of cell strings CSij connected to one string selection line may also change.

[0144] The height of the cell string CSij may also be increased or decreased compared to the illustration. For example, the number of memory cells MC stacked in each cell string CSij may be greater than or less than the number shown. As the number of memory cells MC stacked in each cell string CSij changes, the number of word lines WL may also change. For example, the number of string selection transistors provided in each cell string CSij may increase. As the number of string selection transistors provided to each cell string CSij changes, the number of string selection lines or common source lines may also change. When the number of string selection transistors increases, the string selection transistors may be stacked in the same form as the memory cells MC.

[0145] Fig.13 is a schematic circuit diagram of a neural network device according to at least one embodiment. Fig.13 According to at least one embodiment, a neural network device 400 may include an array of a plurality of synaptic elements 410 provided in two dimensions. Each of the plurality of synaptic elements 410 may include an access transistor 411 and a ferroelectric field effect transistor 412. The ferroelectric field effect transistor 412 may be a reference Figures 1 to 8Any one of the described semiconductor devices 100 , 101 , and 102 , or a semiconductor device according to a combination thereof or a modification thereof The access transistor 411 may be used as a selection element for turning on / off the synapse element 410 .

[0146] The neural network device 400 may also include a plurality of word lines WL, a plurality of bit lines BL, a plurality of input lines IL, and a plurality of output lines OL. The gate of the access transistor 411 may be electrically connected to any one of the plurality of word lines WL, the source thereof may be electrically connected to any one of the plurality of bit lines BL, and the drain thereof may be connected to the gate of the ferroelectric field effect transistor 412. In addition, the source of the ferroelectric field effect transistor 412 may be electrically connected to any one of the plurality of input lines IL, and the drain thereof may be electrically connected to any one of the plurality of output lines OL.

[0147] During the learning operation of the neural network device 400, the access transistor 411 is individually turned on through the individual word line WL, and a programming pulse can be applied to the gate of the ferroelectric field effect transistor 412 through the bit line BL. The signal of the training data can be applied through the input line IL. Through this process, the weight can be stored in each ferroelectric field effect transistor 412.

[0148] During the inference operation of the neural network device 400, all access transistors 411 may be turned on through the entire word line WL, and a read voltage Vread may be applied through the bit line BL. Then, the current from each synaptic element 410 connected in parallel to the output line OL is added to and flows in each output line OL. The output circuit is connected to the plurality of output lines OL to convert the current flowing through each output line OL into a digital signal.

[0149] Fig.14 is a block diagram schematically showing an example configuration of an electronic device including a neural network device. Fig.14 , the electronic device 500 can analyze input data in real time based on a neural network to extract effective information, determine a situation based on the extracted information, or control the configuration of a device equipped with the electronic device 500. For example, the electronic device 500 can be applied to robot devices such as drones, advanced driver assistance systems (ADAS), smart TVs, smart phones, medical devices, mobile devices, image display devices, measuring devices, IoT devices, etc., and can be installed on at least one of various types of devices.

[0150] The electronic device 500 may include a processor 510, a random access memory (RAM) 520, a neural network device 530, a memory 540, a sensor module 550, and a communication (transmit (Tx) / receive (Rx)) module 560. The electronic device 500 may further include an input / output module, a security module, a power control device, etc. Some of the hardware components of the electronic device 500 may be mounted on at least one semiconductor chip.

[0151] The processor 510 controls the overall operation of the electronic device 500. The processor 510 may include a single processor core or multiple processor cores (i.e., multi-core). The processor 510 may process or execute programs and / or data stored in the memory 540. In some embodiments, the processor 510 may control the functions of the neural network device 530 by executing the programs stored in the memory 540. The processor 510 may be implemented as a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP), etc.

[0152] The RAM 520 may temporarily store programs, data, or instructions. For example, the programs and / or data stored in the memory 540 may be temporarily stored in the RAM 520 according to the control or boot code of the processor 510. The RAM 520 may be implemented as a memory such as a dynamic RAM (DRAM), a static RAM (SRAM), or the like.

[0153] The neural network device 530 may perform the operation of the neural network based on the received input data, and generate an information signal based on the execution result. The neural network may include, but is not limited to, CNN, RNN, FNN, long short-term memory (LSTM), stacked neural network (SNN), state space dynamic neural network (SSDNN), deep belief network (DBN), restricted Boltzmann machine (RBM), etc. The neural network device 530 may be a hardware accelerator dedicated to the neural network itself or a device including the same. The neural network device 530 may perform read or write operations as well as operations of the neural network. The neural network device 530 may include reference Fig.13 The neural network device 400 described and / or referenced Figures 1 to 8 One of the semiconductor devices 100 , 101 , and 102 is described.

[0154] The information signal may include one of various types of recognition signals, such as a voice recognition signal, an object recognition signal, an image recognition signal, a biometric information recognition signal, etc. For example, the neural network device 530 may receive frame data included in a video stream as input data, and generate a recognition signal for an object included in an image represented by the frame data from the frame data. However, the neural network device is not limited thereto, and the neural network device 530 may receive various types of input data, and generate a recognition signal according to the input data according to the type or function of the device on which the electronic device 500 is installed.

[0155] The neural network device 530 may execute, for example, machine learning models such as linear regression, logistic regression, statistical clustering, Bayesian classification, decision trees, principal component analysis and / or expert systems, and / or machine learning models of integration techniques such as random forests, etc. The machine learning models may be used to provide various services, such as image classification services, user authentication services based on biometric information and / or biometric data, advanced driver assistance systems (ADAS), voice assistance services, automatic speech recognition (ASR) services, etc.

[0156] The memory 540 is a storage location for storing data and may store an operating system (OS), various programs, and various pieces of data. In at least one embodiment, the memory 540 may store intermediate results generated during the operation of the neural network device 530.

[0157] The memory 540 may be a DRAM, but is not limited thereto. The memory 540 may include at least one of a volatile memory and / or a non-volatile memory. The non-volatile memory includes a read-only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a flash memory, a phase change ROM (PROM), a magnetic ROM (MROM), a resistive ROM (RROM), a ferroelectric ROM (FeROM), and the like. The volatile memory includes a dynamic RAM (DRAM), a static RAM (SRAM), a synchronous DRAM (SDRAM), a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), and a ferroelectric RAM (FeRAM). In at least one embodiment, the memory 540 may include at least one of a hard disk drive (HDD), a solid state drive (SSD), a compact flash (CF), a secure digital (SD), a micro secure digital (Micro-SD), a mini secure digital (Mini-SD), a memory stick, and the like. In at least one embodiment, the memory 540 may include a reference Figures 1 to 8 and FIG. 11A to FIG. 11BOne of the semiconductor devices 100 , 101 , 102 , 300 described.

[0158] The sensor module 550 may collect information around the device on which the electronic device 500 is mounted. The sensor module 550 may sense and / or receive signals (e.g., image signals, voice signals, magnetic signals, bio-signals, touch signals, etc.) from outside the electronic device 500, and convert the sensed and / or received signals into data. To this end, the sensor module 550 may include at least one of various types of sensing devices, such as, for example, a microphone, an imaging device, an image sensor, a light detection and ranging (LIDAR) sensor, an ultrasonic sensor, an infrared sensor, a bio-sensor, and a touch sensor.

[0159] The sensor module 550 may provide the converted data as input data to the neural network device 530. For example, the sensor module 550 may include an image sensor, generate a video stream by photographing the external environment of the electronic device 500, and sequentially provide continuous data frames of the video stream to the neural network device 530 as input data. However, the embodiment is not limited thereto, and the sensor module 550 may provide various types of data to the neural network device 530.

[0160] The communication module 560 may include various wired or wireless interfaces capable of communicating with external devices. For example, the communication module 560 may include a wired local area network (LAN), a wireless local area network (WLAN) (such as wireless fidelity (Wi-Fi)), a wireless personal area network (WPAN) (such as Bluetooth), a wireless universal serial bus (USB), Zigbee, near field communication (NFC), radio frequency identification (RFID), power line communication (PLC), and a communication interface capable of connecting to a mobile cellular network (such as the third generation (3G), the fourth generation (4G), long term evolution (LTE), etc.).

[0161] The above-mentioned semiconductor device can operate as a field effect transistor with an increased memory window.

[0162] The above-described semiconductor device may have improved operational reliability and may be used as a memory cell of a memory device.

[0163] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for the purpose of limitation. The description of features or aspects within each embodiment should generally be considered to be applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the spirit and scope defined by the appended claims.

[0164] This application is based on and claims the benefit of priority of Korean Patent Application No. 10-2023-0137144 filed in the Korean Intellectual Property Office on October 13, 2023 and Korean Patent Application No. 10-2024-0137684 filed in the Korean Intellectual Property Office on October 10, 2024, the disclosures of which are incorporated herein by reference in their entirety.

Claims

1. A semiconductor device, comprising: a channel layer including a semiconductor material; a ferroelectric layer on the channel layer and comprising a ferroelectric material; a gate electrode on the ferroelectric layer; a first insertion layer between the ferroelectric layer and the gate electrode, the first insertion layer comprising a first paraelectric material; as well as A second insertion layer between the channel layer and the ferroelectric layer includes a second paraelectric material having a dielectric constant higher than a dielectric constant of the first paraelectric material. 2 . The semiconductor device according to claim 1 , wherein the second paraelectric material is a high-k material. 3 . The semiconductor device according to claim 1 , wherein the first paraelectric material has a band gap energy greater than a band gap energy of the ferroelectric material included in the ferroelectric layer.

4. The semiconductor device according to claim 1, wherein the second paraelectric material comprises SiON, GeON, SiGeO x N y , Al2O3, Y2O3, SrTa2O7, HfO2, ZrO2, Ta2O5, SrTiO3, La2O3, SrHfO3, BaZrO3, BaHfO3, Ta2Ti2O x , TiO2 or BaHf 0.5 Ti 0.5 At least one of O3. The semiconductor device of claim 1 , wherein the dielectric constant of the first paraelectric material is less than 4. 6 . The semiconductor device of claim 1 , wherein the first paraelectric material comprises at least one or more of silicon oxide, silicon nitride, silicon oxynitride, or boron nitride. 7 . The semiconductor device according to claim 1 , wherein the dielectric constant of the second paraelectric material is equal to or greater than 4 and equal to or less than 60. 8 . The semiconductor device according to claim 1 , wherein a thickness of the second insertion layer is smaller than a thickness of the first insertion layer. 9 . The semiconductor device according to claim 8 , wherein the thickness of the second insertion layer is 70% or less of the thickness of the first insertion layer. 10 . The semiconductor device according to claim 1 , wherein a ratio of the dielectric constant of the second paraelectric material to the dielectric constant of the first paraelectric material is greater than or equal to 1.

2.

11. The semiconductor device according to claim 1, wherein the second paraelectric material comprises at least one of Al2O3, Ta2O5 or La2O3.

12. The semiconductor device according to claim 1, further comprising: An interface layer between the channel layer and the second insertion layer includes an oxide.

13. The semiconductor device according to claim 1, further comprising: A charge trap layer is between the ferroelectric layer and the first insertion layer, the charge trap layer contacts the ferroelectric layer. 14 . The semiconductor device according to claim 13 , wherein a trap energy level of the charge trap layer is lower than a conduction band of the charge trap layer by 1 eV or more. 15 . The semiconductor device according to claim 13 , wherein the charge trap layer comprises at least one of AlN, GaN, GeN, SiN, CN, InN, YN, ScN, or ZrN. 16 . The semiconductor device according to claim 13 , wherein a dielectric constant of a paraelectric material included in the charge trap layer is smaller than the dielectric constant of the second paraelectric material.

17. A semiconductor device comprising: a channel layer including a semiconductor material; a ferroelectric layer on the channel layer and comprising a ferroelectric material; a gate electrode on the ferroelectric layer; a first insertion layer between the ferroelectric layer and the gate electrode, the first insertion layer comprising one or more layers; as well as a second insertion layer between the channel layer and the ferroelectric layer, the second insertion layer comprising one or more layers, wherein a ratio of a dielectric constant exhibited by the entire second insertion layer to a dielectric constant exhibited by the entire first insertion layer is greater than or equal to 1.

2. 18 . The semiconductor device according to claim 17 , wherein the first insertion layer has a multilayer structure including a layer of silicon oxide and a layer of silicon nitride.

19. An electronic device comprising: Semiconductor substrate; as well as A plurality of memory cells are stacked on the semiconductor substrate and in a first direction, Each of the plurality of storage units includes a channel layer comprising a semiconductor material, a ferroelectric layer on the channel layer and comprising a ferroelectric material, a gate electrode on the ferroelectric layer, a first insertion layer between the ferroelectric layer and the gate electrode, the first insertion layer comprising a first paraelectric material, and a second insertion layer between the channel layer and the ferroelectric layer, the second insertion layer comprising a second paraelectric material, the second paraelectric material having a dielectric constant higher than the dielectric constant of the first paraelectric material, such that a ratio of the dielectric constant of the second paraelectric material to the dielectric constant of the first paraelectric material is equal to or greater than 1.2, and The channel layer, the second insertion layer, the ferroelectric layer, the first insertion layer, and the gate electrode are sequentially disposed in a second direction perpendicular to the first direction.

20. The electronic device according to claim 19, further comprising: A spacer is provided between adjacent gate electrodes of the plurality of memory cells, wherein the spacer comprises an insulating material.

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