Semiconductor device and method of manufacturing the same

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, and the semiconductor device comprises a substrate which is provided with a first surface and a second surface; the gate electrode connecting pad and the source electrode connecting pad are laterally separated from each other and are arranged on the first surface of the substrate; a drain region disposed on the second surface of the substrate; the first groove is formed in the substrate and is positioned right below the gate electrode connecting pad; the conductive part is filled in the first groove; the dielectric lining layer is arranged in the first groove and surrounds the conductive part; the first doped region is positioned on the side edge of the first groove; the second groove is formed in the substrate and is positioned right below the source electrode connecting pad; the gate electrode is filled in the second groove; a gate dielectric layer disposed in the second trench and surrounding the gate electrode; and the source electrode region is located on the side edge of the second groove, and the first doped region and the source electrode region have the same conduction type.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device including a trench power transistor and a manufacturing method thereof. Background Art

[0002] In power electronic systems, power transistors are usually used as power elements such as power switches and converters. Power transistors refer to transistors that work under high voltage and high current conditions. The most common power transistors are, for example, power metal-oxide-semiconductor field effect transistors (power MOSFETs), which include horizontal structures, such as laterally-diffused MOS (LDMOS) field effect transistors (FETs), and vertical structures, such as planar gate MOSFETs and trench gate MOSFETs. Trench gate MOSFETs have gates disposed in trenches. Compared with planar gate MOSFETs, trench gate MOSFETs have the advantage of reducing the size of component units. However, existing trench gate MOSFETs still have many requirements for improvement, such as reducing on-resistance (Ron) and reducing various parasitic capacitances. Summary of the invention

[0003] In view of this, the present invention proposes a semiconductor device and a manufacturing method thereof, wherein a plurality of trenches are arranged directly below a gate pad, a dielectric liner and a conductive portion are arranged in these trenches, and doped regions are arranged on the sides of these trenches, thereby increasing the number of effective trench-type power transistors directly below the gate pad, thereby reducing the specific on-resistance (Ron,sp) of the semiconductor device. In addition, a thick oxide layer is provided at the bottom of these trenches, thereby reducing the gate-drain capacitance (Cgd) under the gate pad. In addition, a metal silicide layer with a self-aligned contact is used on the doped region on the side of the trench, thereby further reducing the cell pitch of the trench-type power transistor, which helps to reduce the specific on-resistance of the semiconductor device.

[0004] According to one embodiment of the present invention, a semiconductor device is provided, comprising: a substrate having a first surface and a second surface; a gate pad and a source pad, which are laterally separated from each other and are both arranged on the first surface of the substrate; a drain region, which is arranged on the second surface of the substrate; a first trench, which is arranged in the substrate and is located directly below the gate pad; a conductive portion, which is filled in the first trench; a dielectric liner, which is arranged in the first trench and surrounds the conductive portion; a first doped region, which is located on a side of the first trench; a second trench, which is arranged in the substrate and is located directly below the source pad; a gate electrode, which is filled in the second trench; a gate dielectric layer, which is arranged in the second trench and surrounds the gate electrode; and a source region, which is located on a side of the second trench, wherein the first doped region and the source region have the same conductivity type.

[0005] According to another embodiment of the present invention, a method for manufacturing a semiconductor device is provided, comprising: providing a substrate, comprising forming a drain region and forming an epitaxial layer on the drain region; performing an ion implantation process on the epitaxial layer to form a first doped region and a source region, wherein the first doped region and the source region both have a first conductivity type; forming a first trench and a second trench in the epitaxial layer, adjacent to the first doped region and the source region respectively; forming a dielectric liner and a gate dielectric layer in the first trench and the second trench respectively; forming a conductive portion and a gate electrode in the first trench and the second trench respectively, wherein the dielectric liner surrounds the conductive portion and the gate dielectric layer surrounds the gate electrode; and forming a gate pad and a source pad laterally separated from each other on the epitaxial layer, and located directly above the first trench and the second trench respectively.

[0006] In order to make the features of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to make the following easier to understand, the drawings and their detailed text descriptions can be referred to when reading the present invention. Through the specific embodiments in this article and with reference to the corresponding drawings, the specific embodiments of the present invention are explained in detail and the working principles of the specific embodiments of the present invention are explained. In addition, for the sake of clarity, the features in the drawings may not be drawn according to the actual scale, so the size of some features in some drawings may be deliberately enlarged or reduced.

[0008] Figure 1 FIG. 4 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

[0009] Figure 2FIG. 4 is a schematic top view of a gate pad and a source pad of a semiconductor device according to an embodiment of the present invention.

[0010] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 and Fig.10 2 is a cross-sectional schematic diagram illustrating some stages of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0011] Description of reference numerals:

[0012] 100...Semiconductor devices

[0013] 100G...Gate pad area

[0014] 100S...Source pad area

[0015] 101...Epitaxial layer

[0016] 101-1...First epitaxial layer

[0017] 101-2...Second epitaxial layer

[0018] 102...Sheltered Area

[0019] 103...Drain area

[0020] 105...well area

[0021] 107...N-type heavily doped region

[0022] 107-1...first doping region

[0023] 107-2...Source region

[0024] 109...P-type heavily doped region

[0025] 109-1...Second doping region

[0026] 109-2...Matrix area

[0027] 110...base

[0028] 110F...First surface

[0029] 110B...Second surface

[0030] 111...Metal silicide layer

[0031] 120-1...First groove

[0032] 120-2...Second groove

[0033] 120i...initial groove

[0034] 120iB...bottom

[0035] 120s...sub groove

[0036] 121...Conductive part

[0037] 122...Gate electrode

[0038] 123...Dielectric lining

[0039] 123S...Part 1

[0040] 123B...Part 2

[0041] 125...Gate dielectric layer

[0042] 125S...Part 3

[0043] 125B...Part 4

[0044] 131...First metal layer

[0045] 132...Second metal layer

[0046] 133...Dielectric layer

[0047] 133-1 ... a portion of the dielectric layer

[0048] 133-2... Another part of the dielectric layer

[0049] 134...Open

[0050] 135...Through hole

[0051] 137...Gate pad

[0052] 137E...Extension

[0053] 139...Source pad

[0054] 140...Hard shield

[0055] 141...Pad oxide layer

[0056] 142...First spacer material layer

[0057] 142S...Spacer

[0058] 143...Second spacer material layer

[0059] 143S...Another spacer

[0060] 145...Dielectric layer

[0061] T1, T2, T3, T4...Thickness

[0062] Steps S101, S103, S105, S107, S109, S111, S113, S115, S117, S119, S121, S123, S125, S127, S129, ... DETAILED DESCRIPTION

[0063] The present invention provides several different embodiments that can be used to implement different features of the present invention. For the sake of simplicity of description, the present invention also describes examples of specific components and arrangements. The purpose of providing these embodiments is only for illustration, not for any limitation. For example, the description below for "a first feature is formed on or above a second feature" may refer to "the first feature is in direct contact with the second feature", or it may refer to "there are other features between the first feature and the second feature", so that the first feature and the second feature are not in direct contact. In addition, various embodiments of the present invention may use repeated figure marks and / or text annotations. The use of these repeated figure marks and annotations is to make the description more concise and clear, rather than to indicate the association between different embodiments and / or configurations.

[0064] In addition, for the spatially related descriptive words mentioned in the present invention, such as "below", "low", "down", "above", "above", "up", "top", "bottom" and similar words, for the convenience of description, their usage is to describe the relative relationship between one element or feature and another (or multiple) elements or features in the drawings. In addition to the orientation shown in the drawings, these spatially related words are also used to describe the possible orientations of the semiconductor device during use and operation. As the orientation of the semiconductor device is different (rotated 90 degrees or other orientations), the spatially related descriptions used to describe its orientation should also be interpreted in a similar manner.

[0065] Although the present invention uses the terms "first", "second", "third", etc. to describe various elements, components, regions, layers and / or sections, it should be understood that these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish a certain element, component, region, layer and / or section from another element, component, region, layer and / or section, and they themselves do not represent any previous ordinal number of the element, nor do they represent the arrangement order of a certain element and another element or the order of the manufacturing method. Therefore, without departing from the scope of the specific embodiments of the present invention, the first element, component, region, layer or block discussed below can also be referred to as the second element, component, region, layer or block.

[0066] The terms "about" or "substantially" mentioned in the present invention generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, in the absence of a specific description of "about" or "substantially", the meaning of "about" or "substantially" can still be implied.

[0067] The words "coupled", "coupled", "electrically connected" and the like mentioned in the present invention include any direct and indirect electrical connection means. For example, if the text describes that a first component is coupled to a second component, it means that the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other devices or connection means.

[0068] Although the technical solution of the present invention is described below by specific embodiments, the inventive principle of the present invention can also be applied to other embodiments. In addition, in order not to obscure the spirit of the present invention, certain details will be omitted, and these omitted details belong to the knowledge scope of those skilled in the art.

[0069] The present invention discloses a semiconductor device including a trench power transistor and a manufacturing method thereof. In an embodiment of the present invention, a plurality of trenches are arranged directly below a gate pad, a dielectric liner and a conductive portion are arranged in the trenches, and a doping region is arranged on the side of the trenches, thereby increasing the number of effective trench power transistors directly below the gate pad, thereby reducing the characteristic on-resistance (Ron,sp) of the semiconductor device, and at the same time, significantly reducing the contact area between the source electrode and the drift region, thereby effectively reducing the drain-source capacitance (Cds). In addition, in an embodiment of the present invention, a thick oxide layer is provided at the bottom of each trench, which can reduce the gate-drain capacitance (Cgd) increased by arranging the trench power transistor directly below the gate pad, thereby reducing the switching loss. In addition, in the embodiment of the present invention, a metal silicide layer with a self-aligned contact is used on the doping region on the side of each trench, which can reduce the cell pitch of the trench power transistor and help reduce the characteristic on-resistance.

[0070] Figure 1 FIG. 1 is a cross-sectional view of a semiconductor device 100 according to an embodiment of the present invention. The semiconductor device 100 includes a gate pad region 100G and a source pad region 100S. Figure 2 FIG. 1 is a top view of a gate pad 137 and a source pad 139 of a semiconductor device 100 according to an embodiment of the present invention, wherein Figure 1 The gate pad area 100G is along Figure 2 The section line A-A' is drawn, Figure 1 The source pad region 100S is along Figure 2 The section line B-B' is drawn. Figure 1 The semiconductor device 100 includes a substrate 110 having a first surface 110F (e.g., a front surface) and a second surface 110B (e.g., a back surface) opposite to each other. The substrate 110 may include a drain region 103 disposed on the second surface 110B of the substrate. The drain region 103 has a first conductivity type, such as an N-type heavily doped region (N + The substrate 110 further includes an epitaxial layer 101, which is located on the drain region 103. The epitaxial layer 101 has a first conductivity type, such as an N-type epitaxial layer. In some embodiments, the drain region 103 is composed of, for example, an N-type heavily doped silicon carbide substrate (N + The epitaxial layer 101 may be composed of, for example, an N-type silicon carbide epitaxial layer (N SiC epitaxial layer), but is not limited thereto.

[0071] Still reading Figure 1 The semiconductor device 100 includes a gate pad 137 and a source pad 139, both of which are disposed on the first surface 110F of the substrate 110. Figure 2 As shown, the gate pad 137 and the source pad 139 are laterally separated from each other on the same plane (eg, XY plane). Figure 1 As shown, the semiconductor device 100 includes a plurality of first trenches 120-1 disposed in the substrate 110 and located directly below the gate pad 137, and a plurality of second trenches 120-2 disposed in the substrate 110 and located directly below the source pad 139. Figure 2 From a top-down perspective, the long axes of the first trenches 120-1 and the second trenches 120-2 extend in the same direction (eg, the Y-axis direction), and a first trench 120-1 directly below the gate pad 137 can be aligned with a second trench 120-2 directly below the source pad 139 and arranged on the same straight line.

[0072] like Figure 1 As shown, a dielectric liner 123 is disposed on the sidewall and bottom surface of the first trench 120-1 directly below the gate pad 137. The dielectric liner 123 includes a first portion 123S located on the sidewall of the first trench 120-1 and a second portion 123B on the bottom surface, and the thickness T1 of the second portion 123B in the Z-axis direction is greater than the thickness T2 of the first portion 123S in the X-axis direction. The conductive portion 121 is filled in the first trench 120-1, and the dielectric liner 123 surrounds the conductive portion 121. In addition, a gate dielectric layer 125 is disposed on the sidewall and bottom surface of the second trench 120-2 directly below the source pad 139. The gate dielectric layer 125 includes a third portion 125S located on the sidewall of the second trench 120-2 and a fourth portion 125B on the bottom surface. Similarly, the thickness T1 of the fourth portion 125B in the Z-axis direction is greater than the thickness T2 of the third portion 125S in the X-axis direction. The gate electrode 122 is filled in the second trench 120-2, and the gate dielectric layer 125 surrounds the gate electrode 122.

[0073] In addition, the semiconductor device 100 includes a well region 105 disposed in the epitaxial layer 101. The well region 105 has a second conductivity type, for example, a P-type well region (p-well), and the well region 105 extends laterally from directly below the gate pad 137 to directly below the source pad 139. In addition, a first doped region 107-1 and a second doped region 109-1 are disposed in the well region 105 directly below the gate pad 137. The first doped region 107-1 has a first conductivity type, for example, an N-type heavily doped region (N + ), the second doped region 109-1 has a second conductivity type, for example, a P-type heavily doped region (P+ ), wherein the first doped region 107-1 is adjacent to both sides of the first trench 120-1, and the second doped region 109-1 is located between the two first doped regions 107-1 and adjacent to the first doped region 107-1. In addition, a source region 107-2 and a bulk region 109-2 are provided in the well region 105 directly below the source pad 139, and the source region 107-2 has a first conductivity type, for example, an N-type heavily doped region (N + ), the body region 109-2 has a second conductivity type, for example, a P-type heavily doped region (P + ), wherein the source region 107-2 is adjacent to both sides of the second trench 120-2, and the substrate region 109-2 is located between the two source regions 107-2 and adjacent to the source region 107-2. In addition, the semiconductor device 100 further includes a metal silicide layer 111 using a self-aligned contact, which is disposed on the first doped region 107-1, the second doped region 109-1, the source region 107-2 and the substrate region 109-2, and the metal silicide layer 111 contacts the top surfaces of the above regions. The semiconductor device 100 further includes a shielding region 102 located in the epitaxial layer 101, and the shielding region 102 is correspondingly disposed directly below each first trench 120-1 and each second trench 120-2, and surrounds the bottom of each first trench 120-1 and each second trench 120-2, and the shielding region 102 has a second conductivity type, for example, a P-type heavily doped region (P + ), the shielding region 102 can provide electric field shielding, thereby increasing the breakdown voltage of the semiconductor device.

[0074] Still reading Figure 1, the semiconductor device 100 further includes a first metal layer 131 disposed directly below the source pad 139, and the first metal layer 131 directly contacts the metal silicide layer 111 located directly below the source pad 139. In addition, the vertical projection area of ​​the first metal layer 131 and the vertical projection area of ​​the gate pad 137 do not overlap, and when viewed from a top view, the first metal layer 131 and the gate pad 137 do not overlap on the XY plane. In addition, the semiconductor device 100 includes a dielectric layer 133 covering the first metal layer 131 and the metal silicide layer 111, a portion 133-1 of the dielectric layer 133 is located directly below the gate pad 137, another portion 133-2 of the dielectric layer 133 is located directly below the source pad 139, and a thickness T3 of the portion 133-1 of the dielectric layer 133 is greater than a thickness T4 of the other portion 133-2 of the dielectric layer 133. In one embodiment, the via 135 is disposed in another portion 133-2 of the dielectric layer 133, the gate pad 137 and the source pad 139 are disposed on the dielectric layer 133, the top surface of the gate pad 137 and the top surface of the source pad 139 may be on the same plane, and the gate pad 137, the source pad 139 and the via 135 may all be formed by the second metal layer 132, and the source pad 139 may be electrically connected to the first metal layer 131 through the via 135. In this embodiment, the provision of the first metal layer 131 helps the source pad 139 to be electrically connected to the source region 107-2 and the substrate region 109-2, and can reduce the height difference in the cross-sectional structure when manufacturing the source pad 139 and the via 135, so that the process of manufacturing the source pad 139 and the via 135 is easier to carry out.

[0075] In one embodiment, the gate electrode 122 and the conductive portion 121 can be electrically coupled to the gate pad 137 to have a gate potential, wherein the gate electrode 122 located directly below the source pad 139 can be electrically coupled to the source pad 139 via other via holes and wires (not shown) disposed in another portion 133-2 of the dielectric layer 133 and via holes (not shown) passing through the dielectric layer 145 located above the gate electrode 122. Figure 2133-1 and the dielectric layer 133-2 are formed on the conductive portion 121. The conductive portion 121 directly below the gate pad 137 can be electrically coupled to the gate pad 137 via other vias (not shown) passing through a portion 133-1 of the dielectric layer 133 and the dielectric layer 145 above the conductive portion 121. In addition, the first doped region 107-1 located on the side of the first trench 120-1 can be electrically coupled to the source pad 139 via the metal silicide layer 111 and the vias and wires (not shown) disposed in the portion 133-1 of the dielectric layer 133. The source region 107-2 located on the side of the second trench 120-2 can be electrically coupled to the source pad 139 via the metal silicide layer 111, the first metal layer 131 and the vias 135. In this embodiment, the conductive portion 121 and the dielectric liner 123 in the first trench 120-1 directly below the gate pad 137, and the first doped region 107-1 located on the side of the first trench 120-1 can constitute a trench-type power transistor. Therefore, the number of effective trench-type power transistors directly below the gate pad 137 can be increased, thereby reducing the characteristic on-resistance (Ron,sp) of the semiconductor device 100.

[0076] Compared to other semiconductor devices that do not have a trench power transistor directly under the gate pad 137, the characteristic on-resistance (Ron,sp) of the semiconductor device 100 of the embodiment of the present invention can be reduced by about 5% to 10%, but is not limited thereto. When the gate pad 137 occupies a larger proportion of the overall area of ​​the die, the number of effective trench power transistors that can be added directly under the gate pad 137 is greater, so that the reduction of the characteristic on-resistance (Ron,sp) of the semiconductor device 100 is greater, especially for small-sized die, because the area occupied by the gate pad is higher, so the effect of reducing the characteristic on-resistance is more significant. In addition, in other embodiments, depending on the different electrical requirements of the semiconductor device 100, the conductive portion 121 in the first trench 120-1 can be electrically coupled to other potentials other than the gate, for example, it can be electrically coupled to the source potential or the ground terminal.

[0077] In addition, compared to other semiconductor devices that do not have any trenches disposed under the gate pad 137, according to some embodiments of the present invention, the plurality of first trenches 120-1 disposed under the gate pad 137 can also effectively reduce the drain-source capacitance (Cds). In addition, according to some embodiments of the present invention, the bottom of the first trench 120-1 under the gate pad 137 has a thick oxide layer (i.e., the second portion 123B of the dielectric liner 123), thereby reducing the gate-drain capacitance (Cgd) increased by disposing a trench-type power transistor directly under the gate pad 137, thereby reducing the switching loss of the semiconductor device 100. In addition, according to some embodiments of the present invention, a metal silicide layer 111 with self-aligned contacts is used on the first doping region 107-1, the second doping region 109-1, the source region 107-2 and the body region 109-2, which can further reduce the cell pitch of the trench power transistor, which helps to reduce the characteristic on-resistance (Ron,sp) of the semiconductor device 100.

[0078] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 and Fig.10 is a cross-sectional schematic diagram of some stages of a method for manufacturing a semiconductor device 100 according to an embodiment of the present invention. Figure 3 , Figure 4 , Figure 5 and Figure 6 In the embodiment, the gate pad region 100G and the source pad region 100S of the semiconductor device 100 have the same cross-sectional structure. Figure 7 , Figure 8 , Fig. 9 and Fig.10 In the present invention, the cross-sectional structures of the gate pad region 100G and the source pad region 100S of the semiconductor device 100 begin to differ. Figure 3 First, a wafer is provided, which includes a drain region 103 and a first epitaxial layer 101-1 epitaxially grown on the drain region 103. In one embodiment, the drain region 103 is, for example, an N-type heavily doped silicon carbide substrate (N + SiC substrate, the first epitaxial layer 101-1 is, for example, an N-type silicon carbide epitaxial layer (N SiC epitaxial layer). Then, through an ion implantation process and using a patterned photoresist, a shielding region 102 is formed in the first epitaxial layer 101-1, for example, a P-type heavily doped shielding region (P +The doping concentration of the shield region 102 is, for example, 1E17 to 1E19 atoms / cm 3 , but not limited to this.

[0079] Continue reading Figure 3 In step S101, a second epitaxial layer 101-2 is epitaxially grown on the first epitaxial layer 101-1, so that the shielding area 102 is buried in the epitaxial layer 101 composed of the first epitaxial layer 101-1 and the second epitaxial layer 101-2, and the drain region 103 and the epitaxial layer 101 formed on the drain region 103 provide a substrate 110 of the semiconductor device 100. In one embodiment, the second epitaxial layer 101-2 is, for example, an N-type silicon carbide epitaxial layer, and the doping concentration of the second epitaxial layer 101-2 may be substantially equal to or higher than the doping concentration of the first epitaxial layer 101-1. In one embodiment, the doping concentration of the first epitaxial layer 101-1 may be about 1E14 to 1E16 atoms / cm 3 The doping concentration of the second epitaxial layer 101-2 may be about 1E15 to 1E17 atoms / cm 3 , but not limited to this.

[0080] Next, see Figure 3 In step S103, a well region 105, such as a P-type well region, is first formed in the second epitaxial layer 101-2 through an ion implantation process and a hard mask. Then, a P-type heavily doped region (P + ) 109, whose doping concentration is higher than that of the well region 105. The P-type heavily doped region 109 is subsequently used as the second doping region 109-1 of the gate pad region 100G and the body region 109-2 of the source pad region 100S. Then, another ion implantation process and another hard mask are used to form an N-type heavily doped region (N + ) 107, whose doping concentration is higher than that of the well region 105, and the N-type heavily doped region 107 is adjacent to the P-type heavily doped region 109, and the N-type heavily doped region 107 is subsequently used as the first doping region 107-1 of the gate pad region 100G and the source region 107-2 of the source pad region 100S. Afterwards, a high temperature activation process can be performed to activate the doped ions in the N-type heavily doped region 107 and the P-type heavily doped region 109.

[0081] Next, see Figure 4In step S105, a patterned pad oxide layer 141 and a patterned hard mask 140 are formed on the N-type heavily doped region 107 and the P-type heavily doped region 109 through deposition, photolithography and etching processes, and then an initial trench 120i is formed in the epitaxial layer 101 through the openings of the pad oxide layer 141 and the hard mask 140 using an etching process, which extends downward through the N-type heavily doped region 107 and the well region 105 but does not reach the shielding region 102. The initial trench 120i located in the gate pad region 100G can be referred to as a first initial trench, and the initial trench 120i located in the source pad region 100S can be referred to as a second initial trench. Also refer to Figure 1 and Figure 4 In the gate pad region 100G, the first doping region 107-1 is located on both sides of the initial trench 120i, and the second doping region 109-1 is located between the two first doping regions 107-1. Similarly, in the source pad region 100S, the source region 107-2 is located on both sides of the initial trench 120i, and the body region 109-2 is located between the two source regions 107-2.

[0082] Continue reading Figure 4 In step S107, a first spacer material layer 142, such as a silicon oxide layer, is conformally formed on the sidewalls and bottom surface of the initial trench 120i by a thermal oxidation process. Then, a second spacer material layer 143 is conformally formed on the sidewalls and bottom surface of the initial trench 120i by a deposition process to cover the first spacer material layer 142. The second spacer material layer 143 is, for example, a silicon nitride layer. Figure 4 In step S109, an etching process is used to remove the second spacer material layer 143 and the first spacer material layer 142 located on the bottom surface of the initial trench 120i to expose the bottom surface 120iB of the initial trench 120i, and to form a spacer 142S and another spacer 143S located on the sidewall of the initial trench 120i. In the gate pad area 100G, the spacer 142S located on the sidewall of the initial trench 120i can be referred to as a first spacer. In the source pad area 100S, the spacer 142S located on the sidewall of the initial trench 120i can be referred to as a second spacer. In addition, in the gate pad area 100G, another spacer 143S located on the sidewall of the initial trench 120i can be referred to as a third spacer, wherein the third spacer (spacer 143S) covers the first spacer (spacer 142S). In the source pad region 100S, another spacer 143S located on the sidewall of the initial trench 120 i may be referred to as a fourth spacer, wherein the fourth spacer (spacer 143S) covers the second spacer (spacer 142S).

[0083] Next, see Figure 5In step S111, the bottom surface 120iB (eg, Figure 4 ), an etching process is used to remove a portion of the epitaxial layer 101 directly below the initial trench 120i to form a sub-trench 120s. The sub-trench 120s is connected to the initial trench 120i, and the bottom surface of the sub-trench 120s is located in the shielding area 102. The sub-trench 120s located in the gate pad area 100G can be called a first sub-trench, and the sub-trench 120s located in the source pad area 100S can be called a second sub-trench.

[0084] Continue reading Figure 5 In step S113, a thermal oxidation process is used to form an oxide layer 145 in the sub-trench 120s. In the gate pad region 100G, the oxide layer 145 located in the first sub-trench can be referred to as a first oxide layer; in the source pad region 100S, the oxide layer 145 located in the second sub-trench can be referred to as a second oxide layer. During the thermal oxidation process in step S113, the spacer 142S located on the sidewall of the initial trench 120i is covered by another spacer 143S, so that the thickness T2 of the spacer 142S after the thermal oxidation process is substantially the same as the thickness T2 of the spacer 142S before the thermal oxidation process. In addition, by controlling the process parameters of the thermal oxidation process in step S113, such as controlling the amount of oxygen introduced, the heating temperature and time, the oxide layer 145 formed in the sub-trench 120s can have a thickness T1, and the thickness T1 of the oxide layer 145 is much greater than the thickness T2 of the spacer 142S. For example, the thickness T1 can be 10 to 100 times the thickness T2. Figure 5 As shown, after step S113 , the outlines of the first trench 120 - 1 of the gate pad region 100G and the second trench 120 - 2 of the source pad region 100S may be formed.

[0085] Afterwards, still refer to Figure 5 In step S115, a stripping process is used, such as a wet etching process using a phosphoric acid solution, to remove the hard mask 140 and the spacers 143S on the sidewalls of the first trench 120-1 and the second trench 120-2, leaving the spacers 142S on the sidewalls of the first trench 120-1 and the second trench 120-2, and the liner oxide layer 141 on each doped region in the well region 105. The spacers 142S (first spacers) on the sidewalls of the first trench 120-1 and the oxide layer 145 (first oxide layer) on the bottom surface constitute the dielectric liner 123 in the first trench 120-1, and the spacers 142S (second spacers) on the sidewalls of the second trench 120-2 and the oxide layer 145 (second oxide layer) on the bottom surface constitute the gate dielectric layer 125 in the second trench 120-2.

[0086] Afterwards, see Figure 6 In step S117, a conductive material layer is deposited on the pad oxide layer 141 using a deposition process, and the first trench 120-1 and the second trench 120-2 are filled. In one embodiment, the conductive material layer is composed of, for example, doped polysilicon. Then, the conductive material layer is subjected to an etch-back process to form a conductive portion 121 in the first trench 120-1, and a gate electrode 122 in the second trench 120-2. The bottom surface of the conductive portion 121 and the bottom surface of the gate electrode 122 are both lower than the bottom surface of the well region 105, and the dielectric liner 123 in the first trench 120-1 surrounds the conductive portion 121, and the gate dielectric layer 125 in the second trench 120-2 surrounds the gate electrode 122. In this embodiment, the lower portion of the conductive portion 121 and the lower portion of the gate electrode 122 that are lower than the bottom surface of the well region 105 can be used as a field plate, which has the function of dispersing the electric field, thereby increasing the breakdown voltage of the semiconductor device.

[0087] Continue reading Figure 6 In step S119, a dielectric layer 145 may be formed on the conductive portion 121 and the gate electrode 122 using a thermal oxidation process. After the dielectric layer 145 is formed, the top surfaces of the conductive portion 121 and the gate electrode 122 may be slightly lower than the top surfaces of the doped regions in the well region 105. Then, the pad oxide layer 141 located on the doped regions in the well region 105 may be removed by forming a patterned photoresist and using an etching process to expose the first doped region 107-1 and the second doped region 109-1 of the gate pad region 100G, and expose the source region 107-2 and the body region 109-2 of the source pad region 100S.

[0088] Then, still refer to Figure 6 In step S121, a metal material (not shown), such as titanium (Ti), cobalt (Co), nickel platinum (NiPt) or other suitable metal barrier materials, is first deposited on the first doping region 107-1, the second doping region 109-1, the source region 107-2 and the body region 109-2 through a deposition process, and then a rapid thermal processing (RTP) is performed to make the metal material react with silicon in the first doping region 107-1, the second doping region 109-1, the source region 107-2 and the body region 109-2 to form a metal silicide layer 111 located in the gate pad region 100G and the source pad region 100S. Afterwards, the unreacted metal material is removed.

[0089] Next, see Figure 7In step S123, a first metal layer 131 is formed on the gate pad region 100G and the source pad region 100S through a deposition process, which covers the metal silicide layer 111 and the dielectric layer 145 on the conductive portion 121 and the gate electrode 122. In one embodiment, the composition of the first metal layer 131 is, for example, aluminum silicon copper (AlSiCu), but is not limited thereto. The use of aluminum silicon copper (AlSiCu) can avoid the occurrence of a junction spike phenomenon between the first metal layer 131 and the silicon carbide substrate 110.

[0090] Then, see Figure 8 In step S125, a patterned photoresist is formed to cover the first metal layer 131 located in the source pad region 100S, and the first metal layer 131 located in the gate pad region 100G is removed by an etching process, so that the metal silicide layer 111 on the first doping region 107-1 and the second doping region 109-1 of the gate pad region 100G is exposed, and the first metal layer 131 located in the source pad region 100S is left, so that the first metal layer 131 is electrically connected to the metal silicide layer 111 located on the source region 107-2 and the body region 109-2. Removing the first metal layer 131 located in the gate pad region 100G can avoid the generation of parasitic capacitance between the first metal layer 131 and the gate pad formed subsequently.

[0091] Afterwards, see Fig. 9 In step S127, a dielectric material layer is deposited in the gate pad region 100G and the source pad region 100S to cover the metal silicide layer 111 in the gate pad region 100G and the first metal layer 131 in the source pad region 100S. Then, a chemical mechanical planarization (CMP) process is performed on the dielectric material layer to form a dielectric layer 133, wherein a thickness T3 of the dielectric layer 133 in the gate pad region 100G is greater than a thickness T4 of the dielectric layer 133 in the source pad region 100S.

[0092] Next, see Fig.10 In step S129, a patterned photoresist is formed and an etching process is used to form an opening 134 in the dielectric layer 133 of the source pad region 100S to expose the first metal layer 131. Then, a second metal layer 132 is deposited on the dielectric layer 133 and in the opening 134, wherein the second metal layer 132 filled in the opening 134 forms a via 135. In one embodiment, the composition of the second metal layer 132 is, for example, aluminum copper (AlCu), but is not limited thereto. Thereafter, another patterned photoresist is formed and another etching process is used to pattern the second metal layer 132 on the dielectric layer 133 to form a Figure 2The gate pad 137 and the source pad 139 are separated from each other laterally, and the semiconductor device 100 is completed. The gate pad 137 is located directly above the first trench 120-1, and the source pad 139 is located directly above the second trench 120-2. In addition, the top surface of the gate pad 137 and the top surface of the source pad 139 formed on the flat surface of the dielectric layer 133 are on the same plane. In this embodiment, the gate pad 137, the source pad 139 and the via 135 are all formed by the second metal layer 132.

[0093] According to some embodiments of the present invention, the structures of the gate pad region and the source pad region of a semiconductor device can be formed simultaneously in the same process steps. Therefore, there is no need to increase the number of masks and process steps. The number of effective trench power transistors can be increased directly below the gate pad, thereby achieving the purpose of improving the electrical performance of the semiconductor device and saving the manufacturing cost of the semiconductor device.

[0094] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art of the present invention, several equivalent substitutions or obvious variations can be made without departing from the concept of the present invention, and the performance or use is the same, which should be regarded as belonging to the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A substrate having a first surface and a second surface; A gate pad and a source pad, which are laterally separated from each other and are both disposed on the first surface of the substrate; a drain region disposed on the second surface of the substrate; a first trench disposed in the substrate and directly below the gate pad; a conductive portion filled in the first trench; a dielectric liner disposed in the first trench and surrounding the conductive portion; a first doped region, located on a side of the first trench; a second trench disposed in the substrate and directly below the source pad; a gate electrode filled in the second trench; a gate dielectric layer disposed in the second trench and surrounding the gate electrode; as well as A source region is located at a side of the second trench, wherein the first doped region and the source region have the same conductivity type.

2. The semiconductor device according to claim 1, wherein The dielectric liner includes a first part and a second part, which are respectively located on the side wall and the bottom surface of the first trench, and the thickness of the second part is greater than the thickness of the first part. The gate dielectric layer includes a third part and a fourth part, which are respectively located on the side wall and the bottom surface of the second trench, and the thickness of the fourth part is greater than the thickness of the third part.

3. The semiconductor device according to claim 1, wherein: The gate electrode and the conductive portion are both electrically coupled to the gate pad, and the first doped region and the source region are both electrically coupled to the source pad.

4. The semiconductor device according to claim 1, wherein: The substrate includes an epitaxial layer located on the drain region, and a well region is arranged in the epitaxial layer, the well region extends laterally from directly below the gate pad to directly below the source pad, wherein the first doped region and the source region both have a first conductivity type, the well region has a second conductivity type, the drain region and the epitaxial layer both have the first conductivity type, and the first doped region and the source region are both arranged in the well region.

5. The semiconductor device according to claim 4, wherein: It also includes a second doped region and a base region, both of which have the second conductivity type and are arranged in the well region, wherein the second doped region is adjacent to the first doped region, and the base region is adjacent to the source region.

6. The semiconductor device according to claim 5, wherein: It also includes a metal silicide layer, which directly contacts the top surfaces of the first doped region, the second doped region, the source region and the base region.

7. The semiconductor device according to claim 6, wherein: It also includes a first metal layer, which is arranged directly below the source pad and directly contacts the metal silicide layer, wherein the source pad is electrically connected to the first metal layer, and the vertical projection area of ​​the first metal layer and the vertical projection area of ​​the gate pad do not overlap.

8. The semiconductor device according to claim 7, wherein: It also includes a dielectric layer covering the first metal layer and the metal silicide layer, a portion of the dielectric layer is located directly below the gate pad, another portion of the dielectric layer is located directly below the source pad, and the thickness of the portion of the dielectric layer is greater than the thickness of the other portion of the dielectric layer.

9. The semiconductor device according to claim 8, wherein: The gate pad and the source pad are made of a second metal, and the top surface of the gate pad and the top surface of the source pad are on the same plane.

10. The semiconductor device according to claim 4, wherein: It also includes a shielding area, which is arranged directly below the first trench and the second trench and has a conductivity type opposite to that of the first doping area and the source area.

11. A method for manufacturing a semiconductor device, characterized in that: include: Providing a substrate, including forming a drain region and forming an epitaxial layer on the drain region; Performing an ion implantation process on the epitaxial layer to form a first doped region and a source region, wherein the first doped region and the source region both have a first conductivity type; forming a first trench and a second trench in the epitaxial layer, adjacent to the first doped region and the source region respectively; forming a dielectric liner and a gate dielectric layer in the first trench and the second trench respectively; forming a conductive portion and a gate electrode in the first trench and the second trench respectively, wherein the dielectric liner surrounds the conductive portion, and the gate dielectric layer surrounds the gate electrode; as well as A gate pad and a source pad are formed on the epitaxial layer and are laterally separated from each other and are located directly above the first trench and the second trench respectively.

12. The method for manufacturing a semiconductor device according to claim 11, wherein: Forming the dielectric liner and the gate dielectric layer in the first trench and the second trench respectively comprises: forming a first initial trench and a second initial trench in the epitaxial layer; Forming a first spacer and a second spacer on the sidewalls of the first initial trench and the sidewalls of the second initial trench respectively, and exposing the bottom surface of the first initial trench and the bottom surface of the second initial trench; removing a portion of the epitaxial layer directly below the first initial trench and directly below the second initial trench to form a first sub-trench and a second sub-trench connected to the first initial trench and the second initial trench, respectively; and A thermal oxidation process is performed in the first sub-trench and the second sub-trench to form a first oxide layer and a second oxide layer respectively, wherein the first spacer and the first oxide layer constitute the dielectric liner, and the second spacer and the second oxide layer constitute the gate dielectric layer.

13. The method for manufacturing a semiconductor device according to claim 12, wherein: The thickness of the first oxide layer is greater than the thickness of the first spacer, and the thickness of the second oxide layer is greater than the thickness of the second spacer.

14. The method for manufacturing a semiconductor device according to claim 12, wherein: Before forming the first sub-trench and the second sub-trench, it also includes forming a third spacer to cover the first spacer, and forming a fourth spacer to cover the second spacer, and after forming the first oxide layer and the second oxide layer, and before forming the conductive part and the gate electrode, removing the third spacer and the fourth spacer.

15. The method for manufacturing a semiconductor device according to claim 12, wherein: The method further includes forming a shielding area in the epitaxial layer, which has a second conductivity type, wherein the bottom surface of the first sub-groove and the bottom surface of the second sub-groove are both located in the shielding area.

16. The method for manufacturing a semiconductor device according to claim 11, wherein: It also includes forming a well region with a second conductivity type in the epitaxial layer, the first doped region and the source region are both formed in the well region, and the bottom surface of the conductive portion and the bottom surface of the gate electrode are both lower than the bottom surface of the well region.

17. The method for manufacturing a semiconductor device according to claim 16, wherein: It also includes forming a second doping region and a base region in the well region, wherein the second doping region and the base region both have the second conductivity type, and the second doping region is adjacent to the first doping region, and the base region is adjacent to the source region.

18. The method for manufacturing a semiconductor device according to claim 17, wherein: It also includes depositing a metal material on the first doped region, the second doped region, the source region and the base region, and the metal material reacts with silicon in the first doped region, the second doped region, the source region and the base region to form a metal silicide layer.

19. The method for manufacturing a semiconductor device according to claim 18, wherein: Also includes: Depositing a first metal layer on the metal silicide layer; removing the first metal layer located in a predetermined formation area of ​​the gate pad; forming a dielectric layer to cover the first metal layer and the predetermined formation area of ​​the gate pad; forming an opening in the dielectric layer to expose the first metal layer; depositing a second metal layer on the dielectric layer and in the opening; as well as The second metal layer is patterned to form the gate pad and the source pad.

20. The method for manufacturing a semiconductor device according to claim 19, wherein: Forming the dielectric layer includes: Depositing a dielectric material layer on the predetermined formation region of the gate pad and the first metal layer; and Performing a planarization process on the dielectric material layer to form the dielectric layer; The top surface of the gate pad and the top surface of the source pad formed on the dielectric layer are on the same plane.

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