Semiconductor device and manufacturing method thereof
By diffusion of fluorine-containing byproducts generated in the semiconductor device manufacturing process, the structural damage caused by fluorine plasma implantation in the prior art is solved, efficient passivation of fluorine doping defects is achieved, and the reliability and stability of the device are improved.
Patent Information
- Application Number
- CN202411808034.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-09
- Publication Date
- 2025-04-15
AI Technical Summary
The prior art When fluorine doping defects are passivated by fluorine plasma implantation in semiconductor devices, it is easy to cause damage to the device structure and reduce stability and reliability.
The fluorine-containing by-products generated during the manufacturing of the gate electrode are used as the fluorine source, and the fluorine element is introduced into the gate dielectric layer and the active layer through diffusion to achieve passivation of fluorine doping defects and avoid structural damage.
It improves the manufacturing efficiency and performance of semiconductor devices, reduces manufacturing costs and thermal budgets, and enhances the reliability and stability of the devices.
Smart Images
Figure CN119835985A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof. Background Art
[0002] In the development of semiconductor technology, the problem of reduced reliability of semiconductor devices caused by defects in the structure of semiconductor devices has always needed to be solved. For the gate dielectric layer, oxygen vacancies in the gate dielectric layer and the electronic defects caused by them will significantly affect the reliability of the device. For the active area, vacancies will be generated in the semiconductor structure of the active area during the manufacturing process of the active area, which will also significantly affect the reliability of the device. Doping fluorine in the structure of semiconductor devices can passivate the defects in the structure of semiconductor devices, thereby improving the stability of semiconductor devices.
[0003] In the prior art, fluorine is doped into the structure of semiconductor devices, usually by annealing after the active region is grown through fluorine plasma implantation. However, plasma implantation can damage the structure of semiconductor devices, resulting in reduced stability of semiconductor devices. Summary of the invention
[0004] The object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which are used to reduce damage to the semiconductor device while passivating fluorine-doped defects in the semiconductor device, thereby improving the reliability of the semiconductor device.
[0005] In order to achieve the above-mentioned object, in a first aspect, the present invention provides a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device comprises: first, forming a gate electrode on a substrate. The gate electrode and / or the surface of the gate electrode contain fluorine-containing byproducts. Next, forming a gate dielectric layer and an active layer on the gate electrode in sequence along the thickness direction of the substrate; and diffusing the fluorine element in the fluorine-containing byproducts into the gate dielectric layer and the active layer.
[0006] In the case of adopting the above technical scheme, the fluorine source for fluorine-doped defect passivation in the manufacturing method provided by the present invention is a fluorine-containing byproduct from the process of manufacturing the gate electrode. Compared with the method of using fluorine plasma injection in the prior art, the fluorine source of the manufacturing method provided by the present invention does not need to be formed additionally, which not only improves the manufacturing efficiency of semiconductor devices, but also helps to control the manufacturing cost of semiconductor devices, and is more compatible with existing processes; and the byproducts remaining in the manufacturing process are used as a useful fluorine source, thereby improving the performance of semiconductor devices. In addition, compared with the prior art, the fluorine plasma injection method is used to passivate the fluorine-doped defects of the gate dielectric layer and the active layer, which will cause structural damage to the gate dielectric layer and the active layer. In the manufacturing method provided by the present invention, the fluorine element in the fluorine-containing byproduct is diffused into the gate dielectric layer and the active layer to realize fluorine-doped defect passivation, which will not cause structural damage to the gate dielectric layer and the active layer, and ensures the structural integrity of the gate dielectric layer and the active layer, which is conducive to improving the reliability of the semiconductor device manufactured by the manufacturing method provided by the present invention.
[0007] As a possible implementation, the material of the gate electrode includes at least one of tungsten, titanium and titanium nitride.
[0008] In the case of adopting the above technical solution, the process of forming a gate electrode whose material includes at least one of tungsten, titanium and titanium nitride will form more fluorine-containing byproducts in the gate electrode or on the surface of the gate electrode, which is beneficial to improve the effect of subsequent fluorine-doped defect passivation by diffusion, and is beneficial to improve the reliability of the semiconductor device manufactured by the manufacturing method provided by the present invention. For example, when the gate electrode whose material includes tungsten is grown by atomic layer deposition, tungsten hexafluoride and silane are usually reacted to generate metallic tungsten, and fluorine-containing byproducts such as silicon fluoride and hydrogen fluoride are generated. These fluorine-containing byproducts can be attached to the gate electrode and / or the surface of the gate electrode, and diffuse into the gate dielectric layer and the active layer when forming the gate dielectric layer and the active layer, so as to passivate the fluorine-doped defects in the gate dielectric layer and the active layer.
[0009] As a possible implementation, an atomic layer deposition process is used to form a gate electrode on a substrate.
[0010] When the above technical solution is adopted, a chemical reaction will occur in the process of forming a gate electrode by the atomic layer deposition process, and fluorine-containing byproducts will be produced; and the temperature of the atomic layer deposition process is relatively low, which can reduce the dissipation of fluorine-containing byproducts in the process of forming the gate electrode, and can increase the total amount of fluorine-containing byproducts in the gate electrode and / or on the surface of the gate electrode, thereby facilitating the subsequent passivation of fluorine-doped defects by diffusion. In addition, the gate electrode formed by the atomic layer deposition process has high uniformity and low defect density, so that the gate electrode has high quality, which is conducive to improving the performance of the semiconductor device manufactured by the present invention.
[0011] As a possible embodiment, the fluorine-containing byproduct includes at least one of hydrogen fluoride, boron fluoride, ammonium fluoride, fluorosilicic acid, fluorosilicates, fluorocarbons, ammonium bifluoride and metal fluorides.
[0012] When the above technical solution is adopted, the process of forming the gate electrode can effectively form a fluorine-containing byproduct having a relatively high concentration and including at least one of the above types, which is beneficial to improving the effect of subsequent fluorine-doping defect passivation by diffusion. In addition, the fluorine-containing byproduct includes at least one of the above substances, and the fluorine-containing byproduct has a good passivation effect on the fluorine-doping defects of the gate dielectric layer and the active layer, which is beneficial to improving the fluorine-doping defect passivation effect of the manufacturing method provided by the present invention.
[0013] As a possible implementation, after forming a gate dielectric layer on the gate electrode, the method for manufacturing a semiconductor device further includes: at least performing an annealing process on the gate dielectric layer.
[0014] In the case of adopting the above technical solution, after forming a gate dielectric layer on the gate electrode, at least the gate dielectric layer is annealed, which can eliminate the internal stress of the gate dielectric layer, repair the structural damage that may exist in the gate dielectric layer, and improve the structural quality of the gate dielectric layer; and help the fluorine-containing byproducts in the gate electrode and / or on the surface of the gate electrode to diffuse into the gate dielectric layer, thereby improving the fluorine-doping defect passivation effect of the manufacturing method provided by the present invention. In addition, when annealing the gate dielectric layer, the gate electrode can also be annealed at the same time, thereby improving the structural quality of the gate electrode, and helping the fluorine-containing byproducts in the gate electrode and / or on the surface of the gate electrode to diffuse into the gate dielectric layer, thereby improving the fluorine-doping defect passivation effect of the manufacturing method provided by the present invention.
[0015] As a possible implementation, after forming the active layer on the gate dielectric layer, the method for manufacturing the semiconductor device further includes: at least performing annealing treatment on the active layer.
[0016] In the case of adopting the above technical solution, after the active layer is formed on the gate dielectric layer, at least the active layer is annealed, which can eliminate the internal stress of the active layer, repair the structural damage that may exist in the active layer, and improve the quality of the structure of the active layer; and help the fluorine-containing byproducts in the gate electrode and / or on the surface of the gate electrode to diffuse into the active layer, thereby improving the fluorine-doping defect passivation effect of the manufacturing method provided by the present invention. In addition, when annealing the active layer, the gate electrode and the gate dielectric layer can also be annealed at the same time, thereby improving the quality of the structure of the gate electrode, and helping the fluorine-containing byproducts in the gate electrode and / or on the surface of the gate electrode to diffuse into the gate dielectric layer and the active layer, thereby improving the fluorine-doping defect passivation effect of the manufacturing method provided by the present invention.
[0017] As a possible implementation, the annealing temperature of the annealing treatment is greater than or equal to 100°C and less than or equal to 600°C.
[0018] When the above technical solution is adopted, the annealing temperature of at least the gate dielectric layer and at least the active layer is within the above range, which can avoid the low structural quality of the gate dielectric layer and the active layer due to the annealing temperature being too low, thereby ensuring the quality of the gate dielectric layer and the active layer; it can also avoid the significant increase in the thermal budget due to the annealing temperature being too high, thereby ensuring the structural integrity of the semiconductor device. In addition, the annealing temperature of the gate electrode when the gate dielectric layer is annealed, and the annealing temperature of the gate electrode and the gate dielectric layer when the active layer is annealed are also within the above range. Please refer to the above paragraph for its beneficial effects, which will not be repeated here.
[0019] As a possible implementation scheme, the annealing treatment time is greater than or equal to 10 minutes and less than or equal to 120 minutes.
[0020] When the above technical solution is adopted, the annealing time of at least the gate dielectric layer and at least the active layer is within the above range, which can avoid the low structural quality of the gate dielectric layer and the active layer due to too short annealing time, thereby ensuring the quality of the gate dielectric layer and the active layer; it can also avoid the significant increase in thermal budget due to too long annealing time, thereby ensuring the structural integrity of the semiconductor device. In addition, the annealing time of the gate electrode when annealing the gate dielectric layer, and the annealing time of the gate electrode and the gate dielectric layer when annealing the active layer are also within the above range. Please refer to the above paragraph for its beneficial effects, which will not be repeated here.
[0021] As a possible implementation scheme, the diffusion temperature of diffusing the fluorine element in the fluorine-containing byproduct into the gate dielectric layer and the active layer is greater than or equal to 100° C. and less than or equal to 600° C., and the diffusion time is greater than or equal to 10 minutes and less than or equal to 120 minutes.
[0022] When the above technical solution is adopted, the process temperature and process time for diffusing the fluorine element in the fluorine-containing by-products into the gate dielectric layer and the active layer are within the above range, which can avoid insufficient diffusion of the fluorine-containing by-products due to low diffusion temperature and short diffusion time, thereby reducing the fluorine-doping defect passivation effect of the manufacturing method provided by the present invention, thereby ensuring the fluorine-doping defect passivation effect of the manufacturing method provided by the present invention; it can also avoid a significant increase in the thermal budget due to high diffusion treatment temperature and long time, thereby ensuring the structural integrity of the semiconductor device.
[0023] As a possible implementation, while forming a gate dielectric layer on the gate electrode, fluorine elements in the fluorine-containing byproducts are diffused into the gate dielectric layer.
[0024] When the above technical solution is adopted, the diffusion of fluorine elements in fluorine-containing by-products is promoted by means of an annealing process for forming a gate dielectric layer on the gate electrode, thereby avoiding a significant increase in the thermal budget caused by fluorine elements in fluorine-containing by-products due to a separate annealing treatment, which is beneficial to reducing the thermal budget of the manufacturing method provided by the present invention, thereby ensuring the structural integrity of the semiconductor device manufactured by the manufacturing method provided by the present invention.
[0025] As a possible implementation, while forming an active layer on the gate dielectric layer, fluorine elements in the fluorine-containing byproducts are diffused into the active layer.
[0026] When the above technical solution is adopted, the diffusion of fluorine elements in fluorine-containing by-products is promoted by means of an annealing process for forming an active layer on the gate dielectric layer, thereby avoiding a significant increase in the thermal budget caused by fluorine elements in fluorine-containing by-products due to a separate annealing treatment, which is beneficial to reducing the thermal budget of the manufacturing method provided by the present invention, thereby ensuring the structural integrity of the semiconductor device manufactured by the manufacturing method provided by the present invention.
[0027] As a possible implementation, the material of the gate dielectric layer includes silicon oxide, aluminum oxide or hafnium oxide.
[0028] When the above technical solution is adopted, the material of the gate dielectric layer is silicon oxide, which has high compatibility with the prior art. The material of the gate dielectric layer is aluminum oxide and hafnium oxide. Since aluminum oxide and hafnium oxide have high dielectric constants, they can reduce the leakage of the gate electrode to the active layer, which is beneficial to improving the performance of the semiconductor device manufactured by the manufacturing method provided by the present invention; and the material of the gate dielectric layer is selected from them, which can speed up the opening and closing speed of the semiconductor device manufactured by the manufacturing method provided by the present invention, reduce the power consumption of the semiconductor device, strengthen the control ability of the gate electrode to the active layer, and is beneficial to improving the performance of the semiconductor device manufactured by the manufacturing method provided by the present invention.
[0029] As a possible implementation, the material of the active layer includes silicon, silicon germanium, germanium or oxide semiconductor.
[0030] When the above technical solution is adopted, the material of the active layer includes silicon, silicon germanium, germanium or oxide semiconductor, including common active layer materials, which can expand the application scope of the manufacturing method provided by the present invention.
[0031] As a possible implementation scheme, the active layer includes a source region, a drain region, and a channel region located between the source region and the drain region, and both ends of the channel region along the length direction are respectively in contact with the source region and the drain region; after the active layer is formed on the gate dielectric layer, the manufacturing method of the semiconductor device also includes: forming a source electrode on the source region, and forming a drain electrode on the drain region.
[0032] When the above technical solution is adopted, the semiconductor device manufactured by the manufacturing method provided by the present invention includes a common transistor structure, which can expand the application scope of the manufacturing method provided by the present invention.
[0033] In a second aspect, the present invention provides a semiconductor device, which is manufactured using the method for manufacturing the semiconductor device provided in the first aspect.
[0034] Compared with the prior art, the beneficial effects of the semiconductor device provided by the present invention are the same as the beneficial effects of the method for manufacturing the semiconductor device provided by the first aspect, and are not elaborated herein. BRIEF DESCRIPTION OF THE DRAWINGS
[0035] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:
[0036] Figure 1 A flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention;
[0037] Figure 2 is a schematic diagram of forming a gate electrode on a substrate in an embodiment of the present invention;
[0038] Figure 3 is a schematic diagram of forming a gate dielectric layer on a gate electrode in an embodiment of the present invention;
[0039] Figure 4 It is a schematic diagram of forming an active layer on a gate electrode in an embodiment of the present invention.
[0040] Reference numerals:
[0041] 100-substrate, 200-gate electrode,
[0042] 300-gate dielectric layer, 400-active layer. DETAILED DESCRIPTION
[0043] In order to make the technical problems, technical solutions and beneficial effects to be solved by the embodiments of the present invention more clearly understood, the embodiments of the present invention are further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the embodiments of the present invention and are not used to limit the embodiments of the present invention.
[0044] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.
[0045] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present invention, "multiple" means two or more, unless otherwise clearly and specifically defined. "Several" means one or more, unless otherwise clearly and specifically defined.
[0046] In the description of the embodiments of the present invention, it should be understood that the directions or positional relationships indicated by the terms "up", "down", "front", "back", "left", "right", etc. are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the embodiments of the present invention.
[0047] In the description of the embodiments of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the embodiments of the present invention can be understood according to specific circumstances.
[0048] In the development of semiconductor technology, the problem of reduced reliability of semiconductor devices caused by defects in the structure of semiconductor devices has always needed to be solved. For the gate dielectric layer, oxygen vacancies in the gate dielectric layer and the electronic defects caused by them will significantly affect the reliability of the device. For the active area, vacancies will be generated in the semiconductor structure of the active area during the manufacturing process of the active area, which will also significantly affect the reliability of the device. Doping fluorine in the structure of semiconductor devices can passivate the defects in the structure of semiconductor devices, thereby improving the stability of semiconductor devices.
[0049] In the prior art, fluorine is doped into the structure of semiconductor devices, usually by annealing after the active region is grown through fluorine plasma implantation. However, plasma implantation can damage the structure of semiconductor devices, and the increase in thermal budget caused by annealing can also damage the structure of semiconductor devices, resulting in reduced stability of semiconductor devices.
[0050] An object of an embodiment of the present invention is to provide a semiconductor device and a method for manufacturing the same, which are used to reduce damage to the semiconductor device while passivating fluorine-doped defects in the semiconductor device, thereby improving the reliability of the semiconductor device.
[0051] In order to achieve the above-mentioned object, in a first aspect, an embodiment of the present invention provides a method for manufacturing a semiconductor device. Figure 1 The manufacturing method of the semiconductor device comprises: first, forming a gate electrode on a substrate. The gate electrode and / or the surface of the gate electrode have fluorine-containing byproducts. Next, forming a gate dielectric layer and an active layer on the gate electrode in sequence along the thickness direction of the substrate; and diffusing the fluorine element in the fluorine-containing byproducts into the gate dielectric layer and the active layer.
[0052] In the case of adopting the above technical solution, the fluorine source for fluorine-doped defect passivation in the manufacturing method provided by the embodiment of the present invention is a fluorine-containing byproduct from the process of manufacturing the gate electrode. Compared with the method of using fluorine plasma injection in the prior art, the fluorine source of the manufacturing method provided by the embodiment of the present invention does not need to be additionally formed, which not only improves the manufacturing efficiency of semiconductor devices, but also helps to control the manufacturing cost of semiconductor devices, and is more compatible with existing processes; it also uses the residual byproducts in the manufacturing process as a useful fluorine source, thereby improving the performance of semiconductor devices. Moreover, compared with the prior art in which the fluorine source is a high-temperature plasma, the thermal budget caused by the introduction of the fluorine source in the manufacturing method provided by the embodiment of the present invention is greatly reduced, which is conducive to improving the reliability of semiconductor devices manufactured by the manufacturing method provided by the embodiment of the present invention. In addition, compared with the prior art that uses fluorine plasma injection to achieve fluorine-doping defect passivation of the gate dielectric layer and the active layer, which will cause structural damage to the gate dielectric layer and the active layer, the manufacturing method provided in the embodiment of the present invention diffuses the fluorine element in the fluorine-containing by-product into the gate dielectric layer and the active layer to achieve fluorine-doping defect passivation without causing structural damage to the gate dielectric layer and the active layer, thereby ensuring the structural integrity of the gate dielectric layer and the active layer, which is beneficial to improving the reliability of the semiconductor device manufactured by the manufacturing method provided in the embodiment of the present invention.
[0053] First, please refer to Figure 2 , a gate electrode 200 is formed on the substrate 100. The gate electrode 200 has fluorine-containing byproducts in the gate electrode 200 and / or on the surface of the gate electrode.
[0054] Regarding the above-mentioned substrate, the embodiment of the present invention does not specifically limit the material and structure of the substrate. Exemplarily, the above-mentioned substrate can be a single-layer structure or a stacked structure stacked along the thickness direction of the substrate. If the above-mentioned substrate is a single-layer structure, the material of the substrate includes silicon, germanium, germanium silicon, glass or diamond. If the above-mentioned substrate is a stacked structure, the material of a layer of the substrate close to the gate electrode includes insulating materials such as silicon oxide and aluminum oxide to reduce the leakage of the gate electrode to the substrate, and the material of a layer of the substrate away from the gate electrode includes silicon, germanium, germanium silicon, glass or diamond.
[0055] As for the material of the above-mentioned gate electrode, the embodiment of the present invention does not make any specific limitation thereto. The material of the gate electrode needs to enable the process of forming the gate electrode to form fluorine-containing byproducts in the gate electrode and / or on the surface of the gate electrode, thereby making it possible to achieve fluorine doping defect passivation through subsequent diffusion.
[0056] Exemplarily, the material of the gate electrode includes at least one of tungsten, titanium and titanium nitride. In this case, the process of forming a gate electrode whose material includes at least one of tungsten, titanium and titanium nitride will form more fluorine-containing byproducts in the gate electrode or on the surface of the gate electrode, which is beneficial to improve the subsequent fluorine-doped defect passivation effect achieved by diffusion, and is beneficial to improve the reliability of the semiconductor device manufactured by the manufacturing method provided in the embodiment of the present invention. For example, when a gate electrode whose material is tungsten is grown by atomic layer deposition, tungsten hexafluoride and silane are usually reacted to generate metallic tungsten, and fluorine-containing byproducts such as silicon fluoride and hydrogen fluoride are generated. These fluorine-containing byproducts can be attached to the gate electrode and / or the surface of the gate electrode due to their low concentration, and diffuse into the gate dielectric layer and the active layer when forming the gate dielectric layer and the active layer, so as to passivate the fluorine-doped defects in the gate dielectric layer and the active layer.
[0057] As for the process of forming the gate electrode, the embodiment of the present invention does not specifically limit it, as long as the process of forming the gate electrode can form a fluorine-containing byproduct in the gate electrode and / or on the surface of the gate electrode. For example, the gate electrode can be formed on the substrate by using an atomic layer deposition process and / or a chemical vapor deposition process.
[0058] It is worth noting that the process of forming the gate electrode by the atomic layer deposition process will produce a chemical reaction and generate fluorine-containing byproducts; and the temperature of the atomic layer deposition process is relatively low, which can reduce the dissipation of fluorine-containing byproducts in the process of forming the gate electrode, and can increase the total amount of fluorine-containing byproducts in the gate electrode and / or on the surface of the gate electrode, thereby facilitating the subsequent passivation of fluorine doping defects through diffusion. In addition, the gate electrode formed by the atomic layer deposition process has high uniformity and low defect density, so that the gate electrode has high quality, which is conducive to improving the performance of the semiconductor device manufactured by the embodiment of the present invention.
[0059] As for the types of materials included in the above-mentioned fluorine-containing by-products, they can be determined according to the material of the gate electrode and the process for forming the gate electrode, and the embodiment of the present invention does not make any specific limitation thereto.
[0060] Exemplarily, the fluorine-containing byproducts include at least one of hydrogen fluoride, boron fluoride, ammonium fluoride, fluorosilicic acid, fluorosilicates, fluorocarbons, ammonium bifluoride and metal fluorides. In this case, the process of forming the gate electrode can effectively form a fluorine-containing byproduct with a relatively high concentration and including at least one of the above types, which is beneficial to improving the effect of subsequent fluorine-doping defect passivation by diffusion. In addition, the fluorine-containing byproducts include at least one of the above substances, and the fluorine-containing byproducts have a good passivation effect on the fluorine-doping defects of the gate dielectric layer and the active layer, which is beneficial to improving the fluorine-doping defect passivation effect of the manufacturing method provided in the embodiment of the present invention.
[0061] Next, please refer to Figure 3 , a gate dielectric layer 300 is formed on the gate electrode 200 along the thickness direction of the substrate.
[0062] As for the material of the gate dielectric layer, the embodiment of the present invention does not make any specific limitation thereto and can be determined according to the requirements in the actual application process.
[0063] Exemplarily, the material of the gate dielectric layer includes silicon oxide, aluminum oxide or hafnium oxide. In this case, the material of the gate dielectric layer is silicon oxide, which has high compatibility with the prior art. The material of the gate dielectric layer is aluminum oxide and hafnium oxide. Since aluminum oxide and hafnium oxide have high dielectric constants, they can reduce the leakage of the gate electrode to the active layer, which is beneficial to improving the performance of the semiconductor device manufactured by the manufacturing method provided by the embodiment of the present invention; and, the material of the gate dielectric layer is selected from them, which can speed up the opening and closing speed of the semiconductor device manufactured by the manufacturing method provided by the embodiment of the present invention, reduce the power consumption of the semiconductor device, and enhance the control ability of the gate electrode to the active layer, which is beneficial to improving the performance of the semiconductor device manufactured by the manufacturing method provided by the embodiment of the present invention.
[0064] In addition, after forming a gate dielectric layer on the gate electrode, the method for manufacturing a semiconductor device may further include the step of: at least annealing the gate dielectric layer. In this case, after forming the gate dielectric layer on the gate electrode, at least annealing the gate dielectric layer can eliminate the internal stress of the gate dielectric layer, repair the structural damage that may exist in the gate dielectric layer, and improve the structural quality of the gate dielectric layer; and help the fluorine-containing byproducts in the gate electrode and / or on the surface of the gate electrode to diffuse into the gate dielectric layer, thereby improving the fluorine-doping defect passivation effect of the manufacturing method provided by the embodiment of the present invention. In addition, when annealing the gate dielectric layer, the gate electrode can also be annealed at the same time, thereby improving the structural quality of the gate electrode, and helping the fluorine-containing byproducts in the gate electrode and / or on the surface of the gate electrode to diffuse into the gate dielectric layer, thereby improving the fluorine-doping defect passivation effect of the manufacturing method provided by the embodiment of the present invention.
[0065] As for the annealing temperature of the annealing treatment performed after forming the gate dielectric layer, the embodiment of the present invention does not make any specific limitation thereto, and it can be determined according to the thermal budget of the manufacturing method provided by the embodiment of the present invention.
[0066] Exemplarily, the annealing temperature of the above annealing treatment is greater than or equal to 100°C and less than or equal to 600°C. For example: the annealing temperature of the annealing treatment is 100°C, 150°C, 200°C, 250°C, 300°C, 350°C, 400°C, 450°C, 500°C, 550°C or 600°C. In this case, the annealing temperature of at least the gate dielectric layer for annealing is within the above range, which can avoid the low structural quality of the gate dielectric layer due to the annealing temperature being too low, thereby ensuring the quality of the gate dielectric layer; it can also avoid the significant increase in the thermal budget due to the annealing temperature being too high, thereby ensuring the structural integrity of the semiconductor device. In addition, when the gate dielectric layer is annealed, the annealing temperature of the gate electrode is still within the above range. Please refer to the above paragraph for its beneficial effects, which will not be repeated here.
[0067] As for the processing time of the annealing treatment after forming the gate dielectric layer and after forming the active layer, the embodiment of the present invention does not make any specific limitation thereto, and it can be determined according to the thermal budget of the manufacturing method provided by the embodiment of the present invention.
[0068] Exemplarily, the processing time of the above-mentioned annealing treatment is greater than or equal to 10 minutes and less than or equal to 120 minutes. For example: the processing time of the annealing treatment is 10 minutes, 20 minutes, 30 minutes, 40 minutes, 50 minutes, 60 minutes, 70 minutes, 80 minutes, 90 minutes, 100 minutes, 110 minutes or 120 minutes. In this case, the annealing time of at least the gate dielectric layer for annealing is within the above-mentioned range, which can avoid the low structural quality of the gate dielectric layer due to the annealing time being too short, thereby ensuring the quality of the gate dielectric layer; it can also avoid the significant increase in the thermal budget due to the annealing time being too long, thereby ensuring the structural integrity of the semiconductor device. In addition, when the gate dielectric layer is annealed, the annealing time for annealing the gate electrode is still within the above-mentioned range. Please refer to the above paragraph for its beneficial effects, which will not be repeated here.
[0069] It should be noted that, in some embodiments, if the quality requirements for the semiconductor device are not high, after forming the gate dielectric layer on the gate electrode, the gate dielectric layer may not be annealed to further reduce the thermal budget. In other embodiments, the quality of the gate dielectric layer may be improved by other possible methods besides annealing.
[0070] Regarding the specific process of diffusing the fluorine element in the fluorine-containing byproduct into the gate dielectric layer, the fluorine element in the fluorine-containing byproduct may be diffused into the gate dielectric layer while forming the gate dielectric layer on the gate electrode.
[0071] Specifically, while forming a gate dielectric layer on the gate electrode, diffusing the fluorine element in the fluorine-containing byproduct into the gate dielectric layer may include diffusing the fluorine element in the fluorine-containing byproduct when depositing the gate dielectric layer, and / or diffusing the fluorine element in the fluorine-containing byproduct when at least the gate dielectric layer is annealed after the gate dielectric layer is formed on the gate electrode. In this case, the diffusion of the fluorine element in the fluorine-containing byproduct is promoted by means of the heat in the process of forming the gate dielectric layer on the gate electrode, thereby avoiding the significant increase in the thermal budget caused by the fluorine element in the fluorine-containing byproduct by adopting a separate annealing treatment, which is conducive to reducing the thermal budget of the manufacturing method provided by the embodiment of the present invention, thereby ensuring the structural integrity of the semiconductor device manufactured by the manufacturing method provided by the embodiment of the present invention.
[0072] Alternatively, after forming the gate dielectric layer, other processes may be additionally used to diffuse the fluorine element in the fluorine-containing byproduct into the gate dielectric layer. For example, after forming the gate dielectric layer, the gate dielectric layer and the gate electrode may be additionally annealed.
[0073] As for the diffusion temperature and diffusion time of the above-mentioned fluorine element diffusion, the embodiment of the present invention does not make any specific limitation thereto, and they can be determined according to the thermal budget of the manufacturing method provided by the embodiment of the present invention.
[0074] Exemplarily, the diffusion temperature of diffusing the fluorine element in the fluorine-containing byproduct into the gate dielectric layer and the active layer is greater than or equal to 100° C. and less than or equal to 600° C., and the diffusion time is greater than or equal to 10 min and less than or equal to 120 min. For example, the diffusion temperature is 100° C., 150° C., 200° C., 250° C., 300° C., 350° C., 400° C., 450° C., 500° C., 550° C. or 600° C., and the diffusion time is 10 min., 20 min., 30 min., 40 min., 50 min., 60 min., 70 min., 80 min., 90 min., 100 min., 110 min. or 120 min. In this case, the process temperature and process time for diffusing the fluorine element in the fluorine-containing by-products into the gate dielectric layer and the active layer are within the above range, which can avoid insufficient diffusion of the fluorine-containing by-products due to low diffusion temperature and short diffusion time, thereby reducing the fluorine-doping defect passivation effect of the manufacturing method provided by the embodiment of the present invention, thereby ensuring the fluorine-doping defect passivation effect of the manufacturing method provided by the embodiment of the present invention; it can also avoid a significant increase in the thermal budget due to high diffusion treatment temperature and long time, thereby ensuring the structural integrity of the semiconductor device.
[0075] Next, please refer to Figure 4 , an active layer 400 is formed on the gate dielectric layer 300 .
[0076] As for the material of the active layer, the embodiment of the present invention does not make any specific limitation thereto and can be determined according to the requirements in the actual application process.
[0077] Exemplarily, the material of the active layer includes silicon, silicon germanium, germanium or an oxide semiconductor. If the material of the active layer is an oxide semiconductor, the material of the active layer may include indium gallium zinc oxide or indium tin zinc oxide. In this case, the material of the active layer includes common active layer materials, which can expand the application scope of the manufacturing method provided by the embodiment of the present invention.
[0078] In addition, regarding the specific structure of the active layer, illustratively, it may include a source region, a drain region, and a channel region located between the source region and the drain region, and both ends of the channel region along the length direction are in contact with the source region and the drain region respectively.
[0079] The specific process of forming the active layer is not specifically limited in the embodiment of the present invention and can be determined according to actual needs. For example, the active layer can be formed by a chemical vapor deposition process.
[0080] In addition, after the active layer is formed on the gate dielectric layer, the method for manufacturing the semiconductor device may further include the step of: at least annealing the active layer. In this case, after the active layer is formed on the gate dielectric layer, at least annealing the active layer can eliminate the internal stress of the active layer, repair the structural damage that may exist in the active layer, and improve the quality of the structure of the active layer; and help the fluorine-containing byproducts in the gate electrode and / or on the surface of the gate electrode to diffuse into the active layer, thereby improving the fluorine-doping defect passivation effect of the manufacturing method provided by the embodiment of the present invention. In addition, when annealing the active layer, the gate electrode and the gate dielectric layer can also be annealed at the same time, thereby improving the quality of the structure of the gate electrode, and helping the fluorine-containing byproducts in the gate electrode and / or on the surface of the gate electrode to diffuse into the gate dielectric layer and the active layer, thereby improving the fluorine-doping defect passivation effect of the manufacturing method provided by the embodiment of the present invention.
[0081] As for the annealing temperature and processing time of the annealing treatment performed after the active layer is formed, reference may be made to the relevant description of the annealing temperature and processing time of the annealing treatment performed after the gate dielectric layer is formed, and no further details will be given here.
[0082] It should be noted that in some embodiments, if the quality requirements for the semiconductor device are not high, after the active layer is formed on the gate dielectric layer, the active layer may not be annealed to further reduce the thermal budget. In other embodiments, the quality of the active layer may be improved by other possible methods besides annealing.
[0083] Regarding the specific process of diffusing the fluorine element in the fluorine-containing byproduct into the active layer, the fluorine element in the fluorine-containing byproduct may be diffused into the active layer while the active layer is formed on the gate dielectric layer.
[0084] Specifically, while forming an active layer on the gate dielectric layer, diffusing the fluorine element in the fluorine-containing byproduct into the active layer may include diffusing the fluorine element in the fluorine-containing byproduct when depositing the active layer, and / or diffusing the fluorine element in the fluorine-containing byproduct when at least annealing the active layer after forming the active layer on the gate dielectric layer. In this case, the diffusion of the fluorine element in the fluorine-containing byproduct is promoted by means of the heat in the process of forming the active layer on the gate dielectric layer, thereby avoiding the significant increase in the thermal budget caused by the fluorine element in the fluorine-containing byproduct by adopting a separate annealing treatment, which is conducive to reducing the thermal budget of the manufacturing method provided by the embodiment of the present invention, thereby ensuring the structural integrity of the semiconductor device manufactured by the manufacturing method provided by the embodiment of the present invention.
[0085] Alternatively, after forming the active layer, other processes may be additionally used to diffuse the fluorine element in the fluorine-containing byproduct into the gate dielectric layer. For example, after forming the active layer, the gate electrode, the gate dielectric layer and the active layer are additionally annealed.
[0086] As for the diffusion temperature and diffusion time of the above-mentioned fluorine element diffusion, the embodiment of the present invention does not make any specific limitation thereto, and they can be determined according to the thermal budget of the manufacturing method provided by the embodiment of the present invention.
[0087] Exemplarily, the diffusion temperature of diffusing the fluorine element in the fluorine-containing byproduct into the gate dielectric layer and the active layer is greater than or equal to 100° C. and less than or equal to 600° C., and the diffusion time is greater than or equal to 10 min and less than or equal to 120 min. For example, the diffusion temperature is 100° C., 150° C., 200° C., 250° C., 300° C., 350° C., 400° C., 450° C., 500° C., 550° C. or 600° C., and the diffusion time is 10 min., 20 min., 30 min., 40 min., 50 min., 60 min., 70 min., 80 min., 90 min., 100 min., 110 min. or 120 min. In this case, the process temperature and process time for diffusing the fluorine element in the fluorine-containing by-product into the active layer are within the above-mentioned range, which can avoid insufficient diffusion of the fluorine-containing by-products due to low diffusion temperature and short diffusion time, thereby reducing the fluorine-doping defect passivation effect of the manufacturing method provided by the embodiment of the present invention, thereby ensuring the fluorine-doping defect passivation effect of the manufacturing method provided by the embodiment of the present invention; it can also avoid a significant increase in the thermal budget due to high diffusion treatment temperature and long time, thereby ensuring the structural integrity of the semiconductor device.
[0088] Next, after forming an active layer on the gate dielectric layer, the method for manufacturing a semiconductor device further includes: forming a source electrode on the source region, and forming a drain electrode on the drain region.
[0089] The embodiment of the present invention does not specifically limit the materials of the source electrode and the drain electrode, and can be determined according to actual needs. For example, the materials of the source electrode and the drain electrode can be copper, aluminum, chromium or silver.
[0090] The embodiment of the present invention does not specifically limit the materials of the source electrode and the drain electrode, which can be determined according to actual needs. Exemplarily, the source electrode and the drain electrode can be a single-layer structure or a stacked structure stacked along the thickness direction of the substrate.
[0091] The specific process of forming the source electrode on the source region and the drain electrode on the drain region is not specifically limited in the embodiment of the present invention and can be determined according to actual needs. For example, a process combining thin film deposition, photolithography and etching can be used to form the source electrode on the source region and the drain electrode on the drain region.
[0092] When the above technical solution is adopted, the semiconductor device manufactured by the manufacturing method provided by the embodiment of the present invention includes a common transistor structure, which can expand the application scope of the manufacturing method provided by the embodiment of the present invention.
[0093] In a second aspect, an embodiment of the present invention provides a semiconductor device, which is manufactured using the semiconductor device manufacturing method provided in the first aspect.
[0094] Compared with the prior art, the beneficial effects of the semiconductor device provided by the embodiment of the present invention are the same as the beneficial effects of the method for manufacturing the semiconductor device provided by the first aspect, and are not elaborated herein.
[0095] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.
[0096] The above is only a specific implementation of the embodiment of the present invention, but the protection scope of the embodiment of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the embodiment of the present invention, which should be included in the protection scope of the embodiment of the present invention. Therefore, the protection scope of the embodiment of the present invention should be based on the protection scope of the claims.
Claims
1. A method for manufacturing a semiconductor device, characterized in that: include: Forming a gate electrode on a substrate; wherein the gate electrode and / or the surface of the gate electrode has fluorine-containing byproducts; forming a gate dielectric layer and an active layer in sequence on the gate electrode along the thickness direction of the substrate; The fluorine element in the fluorine-containing byproduct is diffused into the gate dielectric layer and the active layer.
2. The method for manufacturing a semiconductor device according to claim 1, wherein: The material of the gate electrode includes at least one of tungsten, titanium and titanium nitride; And / or, the gate electrode is formed on the substrate by using an atomic layer deposition process.
3. The method for manufacturing a semiconductor device according to claim 1, wherein: The fluorine-containing byproduct includes at least one of hydrogen fluoride, boron fluoride, ammonium fluoride, fluorosilicic acid, fluorosilicates, fluorocarbons, ammonium bifluoride and metal fluorides.
4. The method for manufacturing a semiconductor device according to claim 1, wherein: After forming the gate dielectric layer on the gate electrode, the method for manufacturing the semiconductor device further comprises: performing at least annealing treatment on the gate dielectric layer; And / or, after forming the active layer on the gate dielectric layer, the method for manufacturing the semiconductor device further comprises: at least performing annealing treatment on the active layer.
5. The method for manufacturing a semiconductor device according to claim 4, wherein: The annealing temperature of the annealing treatment is greater than or equal to 100° C. and less than or equal to 600° C.; and / or the annealing time of the annealing treatment is greater than or equal to 10 min and less than or equal to 120 min.
6. The method for manufacturing a semiconductor device according to claim 1, wherein: The diffusion temperature of diffusing the fluorine element in the fluorine-containing byproduct into the gate dielectric layer and the active layer is greater than or equal to 100° C. and less than or equal to 600° C., and the diffusion time is greater than or equal to 10 minutes and less than or equal to 120 minutes.
7. The method for manufacturing a semiconductor device according to claim 1, wherein: While forming a gate dielectric layer on the gate electrode, diffusing fluorine elements in the fluorine-containing byproduct into the gate dielectric layer; And / or, while forming the active layer on the gate dielectric layer, the fluorine element in the fluorine-containing byproduct is diffused into the active layer.
8. The method for manufacturing a semiconductor device according to claim 1, wherein: The material of the gate dielectric layer includes silicon oxide, aluminum oxide or hafnium oxide; And / or, the material of the active layer includes silicon, silicon germanium, germanium or oxide semiconductor.
9. The method for manufacturing a semiconductor device according to claim 1, wherein: The active layer comprises a source region, a drain region, and a channel region located between the source region and the drain region, and two ends of the channel region along the length direction are in contact with the source region and the drain region respectively; After forming the active layer on the gate dielectric layer, the method for manufacturing the semiconductor device further includes: forming a source electrode on the source region, and forming a drain electrode on the drain region.
10. A semiconductor device, characterized in that: The semiconductor device is manufactured by the manufacturing method according to any one of claims 1 to 9.