Semiconductor structure, manufacturing method thereof and electronic equipment

Abstract

The invention relates to a semiconductor structure, a manufacturing method thereof and electronic equipment. The manufacturing method of the semiconductor structure comprises the steps of providing a substrate; forming a first vertical transistor on the substrate; depositing one or more interlayer insulating dielectric material layers on the first vertical transistor, and performing plasma treatment on the one or more interlayer insulating dielectric material layers to form one or more interlayer insulating dielectric layers; forming a second vertical transistor on one or more interlayer insulating dielectric layers; wherein the channel layer of the first vertical transistor and / or the second vertical transistor is made of a metal oxide semiconductor material. By adopting the manufacturing method of the semiconductor structure, the performance of the device can be improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a manufacturing method thereof, and an electronic device. Background Art

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and numbers of devices contained in a single chip are increasing accordingly, so that any slight difference in process production may affect device performance.

[0003] In order to reduce the cost of products as much as possible, people hope to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's needs for current products.

[0004] Using metal oxide semiconductor materials as channel materials of semiconductor devices can achieve relatively small leakage current. However, these metal oxide semiconductor materials are relatively sensitive to impurities, external water vapor, etc., and are easily affected by subsequent process and external environment. Summary of the invention

[0005] The present application provides a semiconductor structure and a manufacturing method thereof, and an electronic device.

[0006] The present invention provides a method for manufacturing a semiconductor structure, comprising:

[0007] providing a substrate;

[0008] forming a first vertical transistor on the substrate;

[0009] Depositing one or more interlayer insulating dielectric material layers on the first vertical transistor, and performing plasma treatment on the one or more interlayer insulating dielectric material layers to form one or more interlayer insulating dielectric layers;

[0010] forming a second vertical transistor on the one or more interlayer insulating dielectric layers;

[0011] At least one of the first channel layer of the first vertical transistor and the second channel layer of the second vertical transistor comprises a metal oxide semiconductor material.

[0012] In some embodiments, the interlayer insulating dielectric material layer before the plasma treatment is deposited at a low temperature, the temperature range of the low temperature is not higher than 300° C., and the interlayer insulating dielectric material layer contains impurity ions, and the impurity ions include at least one of carbon ions and hydrogen ions;

[0013] The plasma treatment of the one or more interlayer insulating dielectric material layers comprises:

[0014] The one or more interlayer insulating dielectric material layers are plasma-treated using at least one of nitrogen plasma, fluorine plasma, sulfur plasma, and oxygen plasma.

[0015] In some embodiments, the number of the interlayer insulating dielectric layers is two or three; the materials of the two or three interlayer insulating dielectric layers are the same or different.

[0016] In some embodiments, forming a first vertical transistor on the substrate includes:

[0017] forming a first stacked structure on the substrate, wherein the first stacked structure comprises a first dielectric layer, a first conductive layer, a second dielectric layer, a second conductive layer and a third dielectric layer stacked in sequence from bottom to top;

[0018] forming a first gate hole in the first stacked structure, wherein the first gate hole penetrates the second dielectric layer, the second conductive layer and the third dielectric layer, and extends into the first conductive layer;

[0019] A first gate structure is formed in the first gate hole.

[0020] In some embodiments, before forming the first gate structure in the first gate hole, the method further includes:

[0021] Depositing a first channel material layer on the bottom of the first gate hole, the sidewall of the first gate hole and the upper surface of the first stacked structure, and patterning the first channel material layer to form the first channel layer;

[0022] The first gate structure includes a first gate dielectric layer and a first gate conductive layer;

[0023] A first gate structure is formed in the first gate hole, including: depositing a first gate dielectric material layer on the surface of the first channel material layer, depositing a first gate conductive material layer on the surface of the first gate dielectric material layer and in the first gate hole, and patterning the first gate dielectric material layer and the first gate conductive material layer to form the first gate dielectric layer and the first gate conductive layer.

[0024] In some embodiments, forming a second vertical transistor on the one or more interlayer insulating dielectric layers includes:

[0025] forming a second stacked structure on the upper surface of the one or more interlayer insulating dielectric layers, wherein the second stacked structure comprises a third conductive layer, a fourth dielectric layer, a fourth conductive layer and a fifth dielectric layer stacked sequentially from bottom to top;

[0026] forming a second gate hole in the second stacked structure, wherein the second gate hole penetrates the fifth dielectric layer, the fourth conductive layer, the fourth dielectric layer, and extends into the third conductive layer;

[0027] A second gate structure is formed in the second gate hole.

[0028] In some embodiments, before forming the second gate structure in the second gate hole, the method further includes:

[0029] forming a second channel material layer at the bottom of the second gate hole, the sidewall of the second gate hole and the upper surface of the second stacked structure, and patterning the second channel material layer to form the second channel layer;

[0030] The second gate structure includes a second gate dielectric layer and a second gate conductive layer;

[0031] A second gate structure is formed in the second gate hole, including: forming a second gate conductive material layer on the surface of the second gate dielectric material layer and in the second gate hole, and patterning the second gate dielectric material layer and the second gate conductive material layer to form the second gate dielectric layer and the second gate conductive layer.

[0032] In some embodiments, the number of the interlayer insulating dielectric layers is multiple, and the plasma treatment of the multiple interlayer insulating dielectric material layers includes:

[0033] After the deposition of the interlayer insulating dielectric material layer of the previous layer is completed, the interlayer insulating dielectric material layer of the previous layer is subjected to plasma treatment, and then the deposition of the interlayer insulating dielectric material layer of the next layer is performed, so that the multiple interlayer insulating dielectric material layers are all subjected to plasma treatment; or

[0034] After the deposition of the multiple interlayer insulating dielectric material layers is completed, the multiple interlayer insulating dielectric material layers are simultaneously subjected to plasma treatment.

[0035] An embodiment of the present application provides a semiconductor structure, which includes a substrate, and further includes a first vertical transistor and a second vertical transistor stacked on the substrate, wherein one or more interlayer insulating dielectric layers are provided between the first vertical transistor and the second vertical transistor; the interlayer insulating dielectric layers are subjected to plasma treatment; wherein the material of at least one of the first channel layer of the first vertical transistor and the second channel layer of the second vertical transistor is a metal oxide semiconductor material.

[0036] In some embodiments, the plasma used in the plasma treatment includes at least one of nitrogen plasma, fluorine plasma, sulfur plasma and oxygen plasma.

[0037] In some embodiments, the first vertical transistor includes:

[0038] The first stacked structure includes a first dielectric layer, a first conductive layer, a second dielectric layer, a second conductive layer and a third dielectric layer stacked in sequence from bottom to top; the first conductive layer serves as a first electrode of the first vertical transistor, and the second conductive layer serves as a second electrode of the second vertical transistor;

[0039] a first gate hole, penetrating the second dielectric layer, the second conductive layer and the third dielectric layer, and extending to the first conductive layer;

[0040] The first gate structure fills the first gate hole; the first gate structure includes a first gate dielectric layer and a first gate conductive layer.

[0041] In some embodiments, the second vertical transistor includes:

[0042] The second stacked structure includes a third conductive layer, a fourth dielectric layer, a fourth conductive layer and a fifth dielectric layer stacked in sequence from bottom to top; the third conductive layer serves as a first electrode of the second vertical transistor, and the fourth conductive layer serves as a second electrode of the second vertical transistor;

[0043] a second gate hole, penetrating the fifth dielectric layer, the fourth conductive layer, the fourth dielectric layer, and extending into the third conductive layer;

[0044] The second gate structure fills up the second gate hole; the second gate structure includes a second gate dielectric layer and a second gate conductive layer.

[0045] An embodiment of the present application provides an electronic device, including the above-mentioned semiconductor structure or a semiconductor structure formed by the manufacturing method.

[0046] The present invention relates to a semiconductor structure and a manufacturing method thereof, and an electronic device. The manufacturing method of the semiconductor structure comprises: providing a substrate; forming a first vertical transistor on the substrate; depositing one or more interlayer insulating dielectric material layers on the first vertical transistor, and performing plasma treatment on the one or more interlayer insulating dielectric material layers to form one or more interlayer insulating dielectric layers; forming a second vertical transistor on the one or more interlayer insulating dielectric layers; wherein the channel layer of the first vertical transistor and / or the second vertical transistor is a metal oxide semiconductor material. The manufacturing method of the semiconductor structure of the present invention can improve device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or related technologies, the drawings required for use in the embodiments or related technical descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0048] Figure 1 is a flow chart of a method for manufacturing a semiconductor structure provided in an embodiment;

[0049] Figure 2 A schematic cross-sectional view of a structure obtained in step S10 in a method for manufacturing a semiconductor structure provided in an embodiment;

[0050] Figure 3 is a flowchart of step S20 in a method for manufacturing a semiconductor structure provided in an embodiment;

[0051] Figure 4 A schematic cross-sectional view of a structure obtained in step S201 of a method for manufacturing a semiconductor structure provided in an embodiment;

[0052] Figure 5 A schematic diagram of a cross-sectional structure of a structure obtained in step S202 in a method for manufacturing a semiconductor structure provided in an embodiment;

[0053] Figure 6 A schematic cross-sectional view of a structure obtained in step S203 of a method for manufacturing a semiconductor structure provided in an embodiment;

[0054] Figure 7 is a flowchart of step S203 in a method for manufacturing a semiconductor structure provided in an embodiment;

[0055] Figure 8 A schematic diagram of a cross-sectional structure of a structure obtained in step S2031 in a method for manufacturing a semiconductor structure provided in an embodiment;

[0056] Fig. 9 A schematic cross-sectional view of a structure obtained in step S2032 in a method for manufacturing a semiconductor structure provided in an embodiment;

[0057] Fig.10 A schematic diagram of a cross-sectional structure of a structure obtained in step S2033 in a method for manufacturing a semiconductor structure provided in an embodiment;

[0058] Fig.11 A schematic diagram of a cross-sectional structure of a structure obtained in step S2034 in a method for manufacturing a semiconductor structure provided in an embodiment;

[0059] Fig.12A schematic diagram of a cross-sectional structure of a structure obtained in step S30 in a method for manufacturing a semiconductor structure provided in an embodiment;

[0060] Fig.13 is a schematic cross-sectional structural diagram of a structure before plasma treatment in step S30 in a method for manufacturing a semiconductor structure provided in an embodiment;

[0061] Fig.14 A schematic cross-sectional view of a structure obtained in step S30 in a method for manufacturing a semiconductor structure provided in another embodiment;

[0062] Fig.15 A schematic cross-sectional view of a structure obtained in step S40 in a method for manufacturing a semiconductor structure provided in another embodiment;

[0063] Fig.16 is a flowchart of step S40 in a method for manufacturing a semiconductor structure provided in an embodiment;

[0064] Fig.17 A schematic diagram of a cross-sectional structure of a structure obtained in step S401 in a method for manufacturing a semiconductor structure provided in an embodiment;

[0065] Fig.18 A schematic cross-sectional view of a structure obtained in step S402 in a method for manufacturing a semiconductor structure provided in an embodiment;

[0066] Fig.19 A schematic cross-sectional view of a structure obtained in step S403 in a method for manufacturing a semiconductor structure provided in an embodiment;

[0067] Fig. 20 is a flowchart of step S403 in a method for manufacturing a semiconductor structure provided in an embodiment;

[0068] Fig.21 A schematic diagram of a cross-sectional structure of a structure obtained in step S4031 in a method for manufacturing a semiconductor structure provided in an embodiment;

[0069] Fig. 22 A schematic diagram of a cross-sectional structure of a structure obtained in step S4032 in a method for manufacturing a semiconductor structure provided in an embodiment;

[0070] Fig.23 A schematic diagram of a cross-sectional structure of a structure obtained in step S4033 in a method for manufacturing a semiconductor structure provided in an embodiment;

[0071] Fig.24 Schematic diagram of the cross-sectional structure of the structure obtained in step S4034 in the method for manufacturing a semiconductor structure provided in one embodiment.

[0072] Description of reference numerals: 1-substrate, 2-first vertical transistor, 20-first stacked structure, 201-first dielectric layer, 202-first conductive layer, 203-second dielectric layer, 204-second conductive layer, 205-third dielectric layer, 21-first gate structure, 211-first gate hole, 212-first channel layer, 2121-first channel material layer, 213-first gate dielectric layer, 2131-first gate dielectric material layer, 214-first gate conductive layer, 2141-first gate conductive material layer, 30-interlayer insulating dielectric material layer, 301-interlayer insulating dielectric material layer, 31-second vertical transistor, 311-second stacked structure, 3111-third conductive layer, 3112-fourth dielectric layer, 3113-fourth conductive layer, 3114-fifth dielectric layer, 312-second gate structure, 3121-second gate hole, 3122-second channel layer, 3122a-second channel material layer, 3123-second gate dielectric layer, 3123a-second gate dielectric material layer, 3124-second gate conductive layer, 3124a-second gate conductive material layer. DETAILED DESCRIPTION

[0073] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Embodiments of the present invention are given in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thoroughly and comprehensively understand the present invention.

[0074] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0075] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0076] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0077] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0078] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic diagrams of preferred embodiments of the invention (and intermediate structures), so that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the invention should not be limited to the preset shapes of the zones shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the invention.

[0079] See also Figure 1 The present invention provides a method for manufacturing a semiconductor structure, comprising the following steps:

[0080] S10: providing a substrate;

[0081] S20: forming a first vertical transistor on the substrate;

[0082] S30: depositing one or more interlayer insulating dielectric material layers on the first vertical transistor at a preset temperature, and performing plasma treatment on the one or more interlayer insulating dielectric material layers to form one or more interlayer insulating dielectric layers; the preset temperature is not greater than 300°C.

[0083] The interlayer insulating dielectric material layer deposited at a temperature not higher than 300° C. has relatively more impurities, but the deposition of the interlayer insulating dielectric material layer in the present application is not limited to 300° C. or below. The deposition temperature higher than 300° C. is also within the scope of the present application to manufacture a 2T stacked transistor using the embodiments of the present application.

[0084] S40: forming a second vertical transistor on one or more interlayer insulating dielectric layers.

[0085] Wherein, the material of the channel layer of the first vertical transistor and / or the second vertical transistor is a metal oxide semiconductor material.

[0086] In some embodiments, when the channel of the transistor located below is made of metal oxide material, one or more interlayer insulating dielectric material layers provided by the present application are used and plasma treatment is performed, and the performance of the transistor below is relatively significantly improved.

[0087] The manufacturing method of the semiconductor structure is as follows: a first vertical transistor is formed on a substrate; at a preset temperature not greater than 300°C, one or more interlayer insulating dielectric material layers are deposited on the first vertical transistor, and one or more interlayer insulating dielectric material layers are subjected to plasma treatment to form one or more interlayer insulating dielectric layers; a second vertical transistor is formed on the one or more interlayer insulating dielectric layers; wherein the channel layers of the first vertical transistor and the second vertical transistor are made of metal oxide semiconductor materials. Plasma treatment can effectively improve the impurity ions formed by the low-temperature deposited interlayer insulating dielectric material layer, thereby preventing the impurity ions from diffusing into the channel, thereby improving the device performance.

[0088] In addition, the density and hardness of the interlayer insulating dielectric layer obtained after the interlayer insulating dielectric material layer is subjected to plasma treatment will be better than those of the interlayer insulating dielectric layer not subjected to plasma treatment, thereby further improving the device performance.

[0089] In step S10, refer to Figure 1 Step S10 in Figure 2 , providing a substrate 1.

[0090] The material of the substrate 1 may be a common substrate material, such as a silicon-containing substrate, glass, a flexible substrate, etc.

[0091] For example, it may be at least one of the following materials: silicon (Si), germanium (Ge), red phosphorus, silicon germanium (SiGe), silicon carbide (SiC), carbon silicon germanium (SiGe C), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGe OI), silicon germanium on insulator (SiGe OI) and germanium on insulator (GeOI), or it may be double-sided polished silicon wafers (Double Side Polished Wafers, DSP), or it may be a ceramic substrate such as alumina, a quartz or glass substrate, etc., and this embodiment is not limited here.

[0092] In step S20, refer to Figure 1 Step S20 in Figure 6 , a first vertical transistor 2 is formed on the substrate 1.

[0093] In one embodiment, Figure 3 As shown, the above step S20 includes:

[0094] S201 : forming a first stacked structure 20 on a substrate 1 , the first stacked structure 20 comprising a first dielectric layer 201 , a first conductive layer 202 , a second dielectric layer 203 , a second conductive layer 204 and a third dielectric layer 205 stacked in sequence from bottom to top.

[0095] like Figure 4 As shown, a first stacked structure 20 may be formed on a substrate 1 by using a multi-pass deposition process, and the first stacked structure 20 includes a first dielectric layer 201, a first conductive layer 202, a second dielectric layer 203, a second conductive layer 204, and a third dielectric layer 205 stacked in sequence from bottom to top. Each deposition process may include: an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, or a low pressure chemical vapor deposition (LPCVD) process.

[0096] The first electrode of the first vertical transistor 2 may be a source, and the second electrode of the first vertical transistor 2 may be a drain, or the first electrode of the first vertical transistor 2 may be a drain, and the second electrode of the first vertical transistor 2 may be a source.

[0097] The materials of the first dielectric layer 201, the second dielectric layer 203 and the third dielectric layer 205 may include insulating materials, such as silicon oxide, silicon nitride, etc., or may be other suitable insulating materials. In order to reduce the influence of parasitic capacitance, the first dielectric layer 201, the second dielectric layer 203 and the third dielectric layer 205 may be made of insulating materials with small dielectric constants as much as possible. The materials of the first dielectric layer 201, the second dielectric layer 203 and the third dielectric layer 205 may be the same or different.

[0098] The materials of the first conductive layer 202 and the second conductive layer 204 may be conductive materials, such as titanium nitride, tungsten metal, molybdenum metal, etc., or materials that can be conductive after ion doping, etc., or other suitable conductive materials. In order to reduce the influence of parasitic capacitance, the first conductive layer 202 and the second conductive layer 204 may be made of conductive materials with low resistivity as much as possible. The materials of the first conductive layer 202 and the second conductive layer 204 may be the same or different.

[0099] S202 : forming a first gate hole 211 in the first stacked structure 20 . The first gate hole 211 penetrates the second dielectric layer 203 , the second conductive layer 204 , and the third dielectric layer 205 , and extends into the first conductive layer 202 .

[0100] like Figure 5 As shown, a process combining photolithography and etching may be used to remove a portion of the first stacked structure 20 to form a first gate hole 211 in the first stacked structure 20 .

[0101] S203 : forming a first gate structure 21 in the first gate hole 211 , wherein the first gate structure 21 also extends to the upper surface of the first stacked structure 20 .

[0102] like Figure 6 As shown, the first gate hole 211 penetrates the second dielectric layer 203, the second conductive layer 204 and the third dielectric layer 205, and extends into the first conductive layer 202. In addition, the thickness of the second dielectric layer 203 determines the length of the channel of the first vertical transistor 2.

[0103] In one embodiment, Figure 7 As shown, the above step S203 includes:

[0104] S2031 : forming a first channel material layer 2121 on the bottom of the first gate hole 211 , the sidewall of the first gate hole 211 , and the upper surface of the first stacked structure 20 .

[0105] like Figure 8As shown, a deposition process may be used to form the first channel material layer 2121. The material of the first channel material layer 2121 may include a metal oxide semiconductor material, such as indium gallium zinc oxide (IGZO). When the metal oxide semiconductor material is IGZO, the leakage current of the transistor is small (the leakage current is less than or equal to 10-15A), thereby ensuring a low refresh rate of the electronic device. It should be noted that the material of the metal oxide semiconductor material can also be ITO, IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO, IAZO, IGO, IZO (indium-zinc-oxide), IZOx and the like, as long as the leakage current of the transistor can meet the requirements, and the specific adjustment can be made according to the actual situation.

[0106] S2032 : forming a first gate dielectric material layer 2131 on a surface of the first channel material layer 2121 .

[0107] like Fig. 9 As shown, a deposition process may be used to form the first gate dielectric material layer 2131. The material of the first gate dielectric material layer 2131 may include a high dielectric material, for example, at least one of HfO2, Al2O3, HfAlO, and HfLaO.

[0108] S2033 : forming a first gate conductive material layer 2141 on the surface of the first gate dielectric material layer 2131 and in the first gate hole 211 .

[0109] like Fig.10 As shown, a deposition process may be used to form the first gate conductive material layer 2141. The first gate conductive material layer 2141 may include a conductive material, for example, at least one of ITO, W, TiN, TiAl, and TaN.

[0110] S2034: removing a portion of the first channel material layer 2121, a portion of the first gate dielectric material layer 2131 and a portion of the first gate conductive material layer 2141 located on the first stacked structure 20 and around the first gate hole 211 to form a first channel layer 212, a first gate dielectric layer 213 and a first gate conductive layer 214; wherein the first gate dielectric layer 213 and the first gate conductive layer 214 together constitute the first gate structure 21, and the first channel layer 212 serves as a channel layer of the first vertical transistor.

[0111] like Fig.11 As shown, a removal process combining photolithography and etching can be used to remove part of the first channel material layer 2121, part of the first gate dielectric material layer 2131 and part of the first gate conductive material layer 2141, so that the first channel layer 212, the first gate dielectric layer 213 and the first gate conductive layer 214 include not only the part located in the first gate hole 211, but also an extended part located at the opening of the first gate hole 211, and the extended part can prevent impurities in the external environment from directly entering the first gate hole 211.

[0112] In step S30, refer to Figure 1 Step S30 in Fig.12 , at a preset temperature, one or more interlayer insulating dielectric material layers 301 are formed on the first vertical transistor 2, and one or more interlayer insulating dielectric material layers 301 are plasma treated to form one or more interlayer insulating dielectric layers 30; the preset temperature is not greater than 300°C.

[0113] like Fig.13 As shown, a deposition process may be used to form the interlayer insulating dielectric material layer 301, and the deposition process may include PVD, CVD, PECVD or ALD process. The material of the interlayer insulating dielectric material layer 301 may include silicon oxide, silicon nitride, etc. The type of impurity ions may be determined based on the specific deposition process and the specific material of the interlayer insulating dielectric material layer, and this embodiment is not limited here.

[0114] In the related art, the interlayer insulating dielectric material layer 301 is usually formed at a temperature between 300°C and 500°C. The purpose of this is to use high temperature conditions to prevent the formation of impurity ions in the interlayer insulating dielectric material layer 301 as much as possible. However, under high temperature conditions, the channel formed by the metal oxide semiconductor material of the transistor is unstable, which makes the transistor prone to failure. For example, Fig.13 In the present invention, after forming the first vertical transistor 2 and before forming the second vertical transistor 31, if the interlayer insulating dielectric material layer 301 is formed under high temperature conditions, the first channel layer 212 in the first vertical transistor 2 is unstable, which may easily cause the entire first vertical transistor 2 to fail.

[0115] Therefore, in this embodiment, in order to keep the channel in the transistor stable, in the process of forming the interlayer insulating dielectric material layer 301 by the deposition process, the interlayer insulating dielectric material layer 301 can be formed at a preset temperature not greater than 300°C. For example, the preset temperature can be between 200°C and 300°C, more specifically, between 230°C and 280°C, such as 250°C. At such a relatively low preset temperature, the stability of the channel layer of the first vertical transistor 2 can be guaranteed, but compared with the high temperature condition, there will be relatively more impurity ions inside the interlayer insulating dielectric material layer 301 formed in the present application. Once these impurity ions diffuse into each channel layer of the stacked transistor, the performance of each device structure layer will be reduced. In addition, the interlayer insulating dielectric material layer 301 formed at a lower preset temperature has a lower density, which may cause impurities such as water vapor in the environment to enter the channel layer through the interlayer insulating dielectric material layer 301, which is also likely to cause the performance of each device to be reduced.

[0116] Generally, the impurity ions exist in the interlayer insulating dielectric material layer 301 in a free state, and are not bonded to the interlayer insulating dielectric material layer 301. For example, taking the deposition process as a PECVD process, and the material of the interlayer insulating dielectric material layer 301 as an example, the impurity ions in the interlayer insulating dielectric material layer 301 include at least one of carbon ions and hydrogen ions, and the carbon ions and / or hydrogen ions exist in the silicon oxide as the interlayer insulating dielectric material layer 301 in a free state, and are not bonded to the silicon oxide.

[0117] like Fig.13 As shown, during the process of plasma treatment of the interlayer insulating dielectric material layer 301, the plasma will reduce or eliminate the impurity ions in the interlayer insulating dielectric material layer 301 to obtain the interlayer insulating dielectric layer 30. In addition, the interlayer insulating dielectric layer 30 obtained after the plasma treatment of the interlayer insulating dielectric material layer 301 will also have better compactness and hardness than the interlayer insulating dielectric material layer 301 that has not been subjected to the plasma treatment.

[0118] Therefore, this embodiment can improve the stability of each channel layer when forming the interlayer insulating dielectric material layer 301. At the same time, the use of plasma treatment can reduce or eliminate impurity ions in the interlayer insulating dielectric material layer 301, thereby reducing or preventing impurity ions from diffusing into the channel.

[0119] Optionally, after step S30 , a step of flattening the upper surface of the interlayer insulating dielectric layer 30 by using chemical mechanical polishing (CMP) may be further included.

[0120] In one embodiment, the interlayer insulating dielectric material layer 301 before plasma treatment contains impurity ions, and the impurity ions include at least one of carbon ions and hydrogen ions. The above step S30 includes: using at least one of nitrogen plasma, fluorine plasma, sulfur plasma and oxygen plasma to perform plasma treatment on one or more interlayer insulating dielectric material layers 301. Preferably, nitrogen plasma or fluorine plasma is used to perform plasma treatment on the interlayer insulating dielectric material layer 301.

[0121] In this embodiment, when one or more interlayer insulating dielectric material layers 301 are plasma treated with at least one of nitrogen plasma, fluorine plasma, sulfur plasma and oxygen plasma, at least one of nitrogen plasma, fluorine plasma, sulfur plasma and oxygen plasma can form bonds with at least one impurity ion of carbon ions and hydrogen ions, thereby inhibiting the diffusion of impurity ions and improving device performance.

[0122] In one embodiment, the number of the interlayer insulating dielectric layers 30 is two or three; the materials of the two or three interlayer insulating dielectric layers 30 are the same or different. For example, the number of interlayer insulating dielectric layers 30 can be Fig.14 The three layers shown in .

[0123] In one embodiment, the number of the interlayer insulating dielectric layer 30 is multiple layers, and the step of performing plasma treatment on the multiple interlayer insulating dielectric material layers 301 in the above step S30 includes:

[0124] After the deposition of the previous interlayer insulating dielectric material layer 301 is completed, the previous interlayer insulating dielectric material layer 301 is subjected to plasma treatment, and then the next interlayer insulating dielectric material layer 301 is deposited, so that the multiple interlayer insulating dielectric material layers 301 are all subjected to plasma treatment; or,

[0125] After the deposition of the multi-layer interlayer insulating dielectric material layer 301 is completed, the multi-layer interlayer insulating dielectric material layer 301 is subjected to plasma treatment.

[0126] After each interlayer insulating dielectric material layer 301 is formed, it can be subjected to plasma treatment to reduce or eliminate impurity ions before the next interlayer insulating dielectric material layer 301 is grown, so as to ensure that the impurity ions in each interlayer insulating dielectric layer 30 are reduced or eliminated by plasma. Alternatively, multiple interlayer insulating dielectric material layers 301 can be formed first, and then plasma treatment can be uniformly performed to reduce or eliminate impurity ions. At the same time, the multiple interlayer insulating dielectric layers 30 treated with plasma have good density and hardness.

[0127] In step S40, refer to Figure 1Step S40 in Fig.15 , a second vertical transistor 31 is formed on one or more interlayer insulating dielectric layers 30 .

[0128] In one embodiment, Fig.16 As shown, the above step S40 includes:

[0129] S401 : forming a second stacked structure 311 on the upper surface of one or more interlayer insulating dielectric layers 30 , wherein the second stacked structure 311 includes a third conductive layer 3111 , a fourth dielectric layer 3112 , a fourth conductive layer 3113 and a fifth dielectric layer 3114 stacked sequentially from bottom to top.

[0130] like Fig.17 As shown, a multi-pass deposition process can be used to form a second stacked structure 311 on the substrate 1, and the second stacked structure 311 includes a third conductive layer 3111, a fourth dielectric layer 3112, a fourth conductive layer 3113, and a fifth dielectric layer 3114 stacked in sequence from bottom to top. Each deposition process may include: an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, or a low pressure chemical vapor deposition (LPCVD) process.

[0131] The first electrode of the second vertical transistor 31 may be a source, and the second electrode of the second vertical transistor 31 may be a drain, or the first electrode of the second vertical transistor 31 may be a drain, and the second electrode of the second vertical transistor 31 may be a source.

[0132] The materials of the fourth dielectric layer 3112 and the fifth dielectric layer 3114 may include insulating materials, such as silicon oxide, silicon nitride, etc., or may be other suitable insulating materials. In order to reduce the influence of parasitic capacitance, the fourth dielectric layer 3112 and the fifth dielectric layer 3114 may be made of insulating materials with small dielectric constants as much as possible. The materials of the fourth dielectric layer 3112 and the fifth dielectric layer 3114 may be the same or different.

[0133] The materials of the third conductive layer 3111 and the fourth conductive layer 3113 may be conductive materials, such as titanium nitride, tungsten metal, molybdenum metal, etc., or materials that can be conductive after ion doping, etc., or other suitable conductive materials. In order to reduce the influence of parasitic capacitance, the third conductive layer 3111 and the fourth conductive layer 3113 may be made of conductive materials with low resistivity as much as possible. The materials of the third conductive layer 3111 and the fourth conductive layer 3113 may be the same or different.

[0134] S402 : forming a second gate hole 3121 in the second stacked structure 311 , wherein the second gate hole 3121 penetrates the fifth dielectric layer 3114 , the fourth conductive layer 3113 , and the fourth dielectric layer 3112 , and extends into the third conductive layer 3111 .

[0135] like Fig.18 As shown, a process combining photolithography and etching may be used to remove a portion of the second stacked structure 311 , so as to form a second gate hole 3121 in the second stacked structure 311 .

[0136] S403 : forming a second gate structure 312 in the second gate hole 3121 , wherein the second gate structure 312 further extends to the upper surface of the second stacked structure 311 .

[0137] like Fig.19 As shown, the second gate hole 3121 penetrates the fifth dielectric layer 3114, the fourth conductive layer 3113, and the fourth dielectric layer 3112, and extends into the third conductive layer 3111. In addition, the thickness of the fourth dielectric layer 3112 determines the length of the channel of the second vertical transistor 31.

[0138] In one embodiment, Fig. 20 As shown, the above step S403 includes:

[0139] S4031 : forming a second channel material layer 3122 a at the bottom of the second gate hole 3121 , the sidewall of the second gate hole 3121 , and the upper surface of the second stacked structure 311 .

[0140] like Fig.21 As shown, the second channel material layer 3122a may be formed by a deposition process, wherein the material of the second channel material layer 3122a may be the same as or different from the material of the first channel material layer 2121.

[0141] S4032: forming a second gate dielectric material layer 3123a on the surface of the second channel material layer 3122a.

[0142] like Fig. 22As shown, the second gate dielectric material layer 3123a may be formed by a deposition process, wherein the material of the second gate dielectric material layer 3123a may be the same as or different from the material of the first gate dielectric material layer 2131.

[0143] S4033 : forming a second gate conductive material layer 3124 a on the surface of the second gate dielectric material layer 3123 a and in the second gate hole 3121 .

[0144] like Fig.23 As shown, the second gate conductive material layer 3124a may be formed by a deposition process, wherein the material of the second gate conductive material layer 3124a and the first gate conductive material layer 2141 may be the same or different.

[0145] S4034: removing part of the second channel material layer 3122a, part of the second gate dielectric material layer 3123a and part of the second gate conductive material layer 3124a located on the second stacked structure 311 and around the second gate hole 3121 to form a second channel layer 3122, a second gate dielectric layer 3123 and a second gate conductive layer 3124; wherein the second gate dielectric layer 3123 and the second gate conductive layer 3124 together constitute the second gate structure 312, and the second channel layer 3122 serves as the channel layer of the second vertical transistor.

[0146] like Fig.24 As shown, a removal process combining photolithography and etching can be used to remove part of the second channel material layer 3122a, part of the second gate dielectric material layer 3123a and part of the second gate conductive material layer 3124a, so that the second channel layer 3122, the second gate dielectric layer 3123 and the second gate conductive layer 3124 include not only the part located in the second gate hole 3121, but also the extended part located at the opening of the second gate hole 3121, and the extended part can prevent impurities from the external environment from directly entering 3121.

[0147] The present invention also provides a semiconductor structure, which can be formed by adopting the above process method.

[0148] like Fig.15 As shown, the semiconductor structure includes a substrate 1, and the semiconductor structure also includes a first vertical transistor 2 and a second vertical transistor 31 stacked on the substrate 1, and one or more interlayer insulating dielectric layers 30 are provided between the first vertical transistor 2 and the second vertical transistor 31; the interlayer insulating dielectric layer 30 is deposited at a preset temperature and is subjected to plasma treatment; the preset temperature is not greater than 300°C; wherein the materials of the channel layers of the first vertical transistor 2 and the second vertical transistor 31 are both metal oxide semiconductor materials.

[0149] The semiconductor structure includes a substrate 1, and the semiconductor structure also includes a first vertical transistor 2 and a second vertical transistor 31 stacked on the substrate 1, and one or more interlayer insulating dielectric layers 30 are provided between the first vertical transistor 2 and the second vertical transistor 31; the interlayer insulating dielectric layer 30 is deposited at a preset temperature and subjected to plasma treatment; the preset temperature is not greater than 300°C; wherein the materials of the channel layers of the first vertical transistor 2 and the second vertical transistor 31 are both metal oxide semiconductor materials. Plasma treatment can reduce or eliminate impurity ions in the interlayer insulating dielectric layer 30, thereby preventing the impurity ions from diffusing into the channel, thereby improving device performance.

[0150] In addition, the density and hardness of the interlayer insulating dielectric layer 30 obtained after the interlayer insulating dielectric material layer 301 is subjected to plasma treatment will be better than those of the interlayer insulating dielectric material layer 301 that has not been subjected to plasma treatment, thereby further improving device performance.

[0151] The present invention also provides an electronic device, which includes the semiconductor structure in any one of the above embodiments. The electronic device may include a smart phone, a computer, a tablet computer, an artificial intelligence, a wearable device, or a smart mobile terminal. Since the use of plasma treatment can reduce or eliminate impurity ions in the low-temperature deposited interlayer insulating dielectric layer between vertical transistors, and at the same time improve the density of the interlayer insulating dielectric layer, it can reduce or prevent the impurity ions in the interlayer insulating dielectric layer from diffusing into the channel, thereby improving the device performance.

[0152] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0153] The above embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for those of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: providing a substrate; forming a first vertical transistor on the substrate; Depositing one or more interlayer insulating dielectric material layers on the first vertical transistor, and performing plasma treatment on the one or more interlayer insulating dielectric material layers to form one or more interlayer insulating dielectric layers; forming a second vertical transistor on the one or more interlayer insulating dielectric layers; At least one of the first channel layer of the first vertical transistor and the second channel layer of the second vertical transistor comprises a metal oxide semiconductor material.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The interlayer insulating dielectric material layer before the plasma treatment is deposited at low temperature, the temperature range of the low temperature deposition is not higher than 300° C., the interlayer insulating dielectric material layer contains impurity ions, and the impurity ions include at least one of carbon ions and hydrogen ions; The plasma treatment of the one or more interlayer insulating dielectric material layers comprises: The one or more interlayer insulating dielectric material layers are plasma-treated using at least one of nitrogen plasma, fluorine plasma, sulfur plasma, and oxygen plasma.

3. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The number of the interlayer insulating dielectric layers is two or three; the materials of the two or three interlayer insulating dielectric layers are the same or different.

4. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The forming of a first vertical transistor on the substrate comprises: forming a first stacked structure on the substrate, wherein the first stacked structure comprises a first dielectric layer, a first conductive layer, a second dielectric layer, a second conductive layer and a third dielectric layer stacked in sequence from bottom to top; forming a first gate hole in the first stacked structure, wherein the first gate hole penetrates the second dielectric layer, the second conductive layer and the third dielectric layer, and extends into the first conductive layer; A first gate structure is formed in the first gate hole.

5. The method for manufacturing a semiconductor structure according to claim 4, characterized in that: Before forming the first gate structure in the first gate hole, the method further includes: Depositing a first channel material layer on the bottom of the first gate hole, the sidewall of the first gate hole and the upper surface of the first stacked structure, and patterning the first channel material layer to form the first channel layer; The first gate structure includes a first gate dielectric layer and a first gate conductive layer; A first gate structure is formed in the first gate hole, including: depositing a first gate dielectric material layer on the surface of the first channel material layer, depositing a first gate conductive material layer on the surface of the first gate dielectric material layer and in the first gate hole, and patterning the first gate dielectric material layer and the first gate conductive material layer to form the first gate dielectric layer and the first gate conductive layer.

6. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The forming of a second vertical transistor on the one or more interlayer insulating dielectric layers comprises: forming a second stacked structure on the upper surface of the one or more interlayer insulating dielectric layers, wherein the second stacked structure comprises a third conductive layer, a fourth dielectric layer, a fourth conductive layer and a fifth dielectric layer stacked sequentially from bottom to top; forming a second gate hole in the second stacked structure, wherein the second gate hole penetrates the fifth dielectric layer, the fourth conductive layer, the fourth dielectric layer, and extends into the third conductive layer; A second gate structure is formed in the second gate hole.

7. The method for manufacturing a semiconductor structure according to claim 6, characterized in that: Before forming the second gate structure in the second gate hole, the method further includes: forming a second channel material layer at the bottom of the second gate hole, the sidewall of the second gate hole and the upper surface of the second stacked structure, and patterning the second channel material layer to form the second channel layer; The second gate structure includes a second gate dielectric layer and a second gate conductive layer; A second gate structure is formed in the second gate hole, including: forming a second gate conductive material layer on the surface of the second gate dielectric material layer and in the second gate hole, and patterning the second gate dielectric material layer and the second gate conductive material layer to form the second gate dielectric layer and the second gate conductive layer.

8. The method for manufacturing a semiconductor structure according to claim 1, wherein: The number of the interlayer insulating dielectric layers is multiple, and the plasma treatment of the multiple interlayer insulating dielectric material layers includes: After the deposition of the interlayer insulating dielectric material layer of the previous layer is completed, the interlayer insulating dielectric material layer of the previous layer is subjected to plasma treatment, and then the deposition of the interlayer insulating dielectric material layer of the next layer is performed, so that the multiple interlayer insulating dielectric material layers are all subjected to plasma treatment; or After the deposition of the multiple interlayer insulating dielectric material layers is completed, the multiple interlayer insulating dielectric material layers are simultaneously subjected to plasma treatment.

9. A semiconductor structure, characterized in that: The semiconductor structure includes a substrate, and the semiconductor structure also includes a first vertical transistor and a second vertical transistor stacked on the substrate, and one or more interlayer insulating dielectric layers are provided between the first vertical transistor and the second vertical transistor; the interlayer insulating dielectric layer is subjected to plasma treatment; wherein the material of at least one of the first channel layer of the first vertical transistor and the second channel layer of the second vertical transistor is a metal oxide semiconductor material.

10. The semiconductor structure according to claim 9, characterized in that: The plasma used in the plasma treatment includes at least one of nitrogen plasma, fluorine plasma, sulfur plasma and oxygen plasma.

11. The semiconductor structure according to claim 9, characterized in that: The first vertical transistor comprises: The first stacked structure includes a first dielectric layer, a first conductive layer, a second dielectric layer, a second conductive layer and a third dielectric layer stacked in sequence from bottom to top; the first conductive layer serves as a first electrode of the first vertical transistor, and the second conductive layer serves as a second electrode of the second vertical transistor; a first gate hole, penetrating the second dielectric layer, the second conductive layer and the third dielectric layer, and extending to the first conductive layer; The first gate structure fills the first gate hole; the first gate structure includes a first gate dielectric layer and a first gate conductive layer.

12. The semiconductor structure according to claim 9, characterized in that: The second vertical transistor comprises: The second stacked structure includes a third conductive layer, a fourth dielectric layer, a fourth conductive layer and a fifth dielectric layer stacked in sequence from bottom to top; the third conductive layer serves as a first electrode of the second vertical transistor, and the fourth conductive layer serves as a second electrode of the second vertical transistor; a second gate hole, penetrating the fifth dielectric layer, the fourth conductive layer, the fourth dielectric layer, and extending into the third conductive layer; The second gate structure fills up the second gate hole; the second gate structure includes a second gate dielectric layer and a second gate conductive layer.

13. An electronic device, characterized in that: The electronic device comprises the semiconductor structure according to any one of claims 9 to 12.

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