Display panel and display device

Abstract

The application provides a display panel and a display device. The display panel comprises a substrate, a light shielding layer, a first semiconductor layer and a second semiconductor layer arranged on the substrate. The first semiconductor layer is formed with a first active part of a driving transistor. The second semiconductor layer is formed with a third active part of a compensation transistor and a fourth active part of a first initialization transistor. The light shielding layer comprises first, second and third light shielding patterns arranged at intervals in a first direction. A first light shielding part on the first light shielding pattern can shield the first active part from light. A second light shielding part on the second light shielding pattern can shield the third active part from light. A third light shielding part on the third light shielding pattern can shield the fourth active part from light. The third active part of the compensation transistor and the fourth active part of the first initialization transistor are prevented from being affected by light, thereby improving the light sensitivity and electrical properties of the compensation transistor and the first initialization transistor.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] With the development of display devices, the requirements of existing display devices for power consumption and screen ratio are higher and higher. In order to reduce power consumption and improve screen ratio, the existing display devices will adopt low temperature polysilicon oxide (LTPO) technology. The LTPO technology refers to the use of low temperature polysilicon thin film transistor and oxide thin film transistor at the same time, so that the driving circuit takes into account the advantages of low temperature polysilicon thin film transistor and oxide thin film transistor, thereby reducing power consumption and reducing leakage current.

[0003] The existing display device using the LTPO technology has a large number of film layers, and accordingly a large number of mask plates are required, resulting in a complex process and high cost. In order to reduce the number of mask plates, the existing display device will remove some gate layers and insulating layers, but this will cause the bottom gate of the oxide thin film transistor to be missing, and the photosensitivity and electrical properties of the thin film transistor to be poor.

[0004] Therefore, the existing display device using the LTPO technology has the technical problem of poor photosensitivity and electrical properties caused by the missing bottom gate of the oxide thin film transistor. SUMMARY

[0005] The present application provides a display panel and a display device to alleviate the technical problem of poor photosensitivity and electrical properties caused by the missing bottom gate of the oxide thin film transistor in the existing display device using the LTPO technology.

[0006] To solve the above problems, the technical solutions provided by the present application are as follows:

[0007] In a first aspect, the embodiments of the present application provide a display panel, which comprises a substrate and a plurality of sub-pixels arranged on the substrate. Each of the sub-pixels comprises a driving transistor, a switching transistor, a compensation transistor and a first initialization transistor. The switching transistor and the driving transistor are connected to a first node. One electrode of the compensation transistor and one electrode of the first initialization transistor are connected to a second node with the driving transistor. The other electrode of the compensation transistor is connected to a third node with the driving transistor. The gate of the compensation transistor is connected to a first scan signal line. The gate of the first initialization transistor is connected to a second scan signal line. The display panel further comprises:

[0008] A light shielding layer arranged on one side of the substrate.

[0009] A first semiconductor layer is disposed on a side of the light shielding layer away from the substrate, and includes a first active part of the driving transistor and a second active part of the switching transistor.

[0010] A second semiconductor layer is disposed on a side of the first semiconductor layer away from the substrate, and includes a third active part of the compensation transistor and a fourth active part of the first initialization transistor.

[0011] The light shielding layer includes a first light shielding pattern, a second light shielding pattern and a third light shielding pattern which are spaced apart in a first direction, the first light shielding pattern, the second light shielding pattern and the third light shielding pattern all extend along a second direction different from the first direction, the second light shielding pattern is connected with the first scan signal line, the third light shielding pattern is connected with the second scan signal line, the first light shielding pattern includes a first light shielding part corresponding to the first active part, the second light shielding pattern includes a second light shielding part corresponding to the third active part, and the third light shielding pattern includes a third light shielding part corresponding to the fourth active part.

[0012] In a second aspect, the embodiments of the present application further provide a display device, which includes the display panel as any one of the foregoing embodiments.

[0013] The display panel and the display device provided by the application have the following beneficial effects: the display panel comprises a substrate and a light shielding layer, a first semiconductor layer and a second semiconductor layer arranged on the substrate, the first semiconductor layer is formed with a first active part of a driving transistor, the second semiconductor layer is formed with a third active part of a compensation transistor and a fourth active part of a first initialization transistor, the gate of the compensation transistor is connected with a first scan signal line, the gate of the first initialization transistor is connected with a second scan signal line, the light shielding layer comprises a first light shielding pattern, a second light shielding pattern and a third light shielding pattern arranged at intervals in a first direction, a first light shielding part on the first light shielding pattern can shield light for the first active part, a second light shielding part on the second light shielding pattern can shield light for the third active part, and a third light shielding part on the third light shielding pattern can shield light for the fourth active part, so that the third active part of the compensation transistor and the fourth active part of the first initialization transistor are prevented from being affected by light, thereby improving the light sensitivity and electrical properties of the compensation transistor and the first initialization transistor, and solving the problem of poor light sensitivity and electrical properties caused by the bottom-gate loss of the oxide thin film transistor of the display device using the LTPO technology; in addition, the second light shielding pattern is connected with the first scan signal line, and the third light shielding pattern is connected with the second scan signal line, so that the second light shielding pattern and the third light shielding pattern can respectively serve as the bottom gate of the compensation transistor and the first initialization transistor under the premise of realizing the light shielding function, thereby improving the gate control ability of the transistor, and at the same time, compared with being connected with other signal lines (such as a high-potential power supply line), the problem of threshold voltage offset can be solved. BRIEF DESCRIPTION OF DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description only some embodiments of the application, and for those skilled in the art, other drawings can also be obtained without creative labor.

[0015] Figure 1 The first comparative display device provided by the embodiment of the application.

[0016] Figure 2 The second comparative display device provided by the embodiment of the application.

[0017] Figure 3 The third comparative display device provided by the embodiment of the application.

[0018] Figure 4 The film layer schematic diagram of the display panel provided by the embodiment of the application.

[0019] Figure 5 A circuit diagram of a sub-pixel of a display panel provided in an embodiment of the present application.

[0020] Figure 6 A first stack diagram of partial film layers of a display panel provided in an embodiment of the present application.

[0021] Figure 7 A stack diagram of a light shielding layer of a display panel in Figure 6

[0022] A stack diagram of a first semiconductor layer of a display panel in Figure 8 Figure 6 A stack diagram of the first semiconductor layer and a structure in

[0023] Figure 9 A stack diagram of a first gate layer of a display panel in Figure 8 Figure 7 A stack diagram of the first gate layer and a structure in

[0024] Figure 10 A stack diagram of a second semiconductor layer of a display panel in Figure 6

[0025] A stack diagram of the second semiconductor layer and a structure in Figure 11 Figure 10 Figure 9 A stack diagram of a second gate layer of a display panel in

[0026] Figure 12 A stack diagram of the second gate layer and a structure in Figure 6

[0027] A stack diagram of a first source-drain layer of a display panel in Figure 13 Figure 12 Figure 11 A stack diagram of the first source-drain layer and a structure in

[0028] Figure 14 A stack diagram of a second source-drain layer of a display panel in Figure 6

[0029] A stack diagram of the second source-drain layer and a structure in Figure 15 Figure 14 Figure 13 A stack diagram of a first source-drain layer of a display panel in

[0030] Figure 16 A stack diagram of the first source-drain layer and a structure in Figure 6

[0031] A stack diagram of a second source-drain layer of a display panel in Figure 17 Figure 16 Figure 15 A stack diagram of the second source-drain layer and a structure in

[0032] Figure 18 A stack diagram of a first source-drain layer of a display panel in​​​​​​​​​​Figure 6 A cross-sectional view of a second source / drain layer of a display panel in DETAILED DESCRIPTION

[0033] The following description of the embodiments is presented to illustrate certain embodiments of the application. The terms used in the present application, such as [up], [down], [front], [back], [left], [right], [inner], [outer], [side] and the like, are only used to refer to the directions in the accompanying drawings. Therefore, the directional terms used are used to illustrate and understand the present application, not to limit the present application. In the drawings, similar elements are denoted by the same reference numerals. In the drawings, the thicknesses of some layers and regions are exaggerated for clarity of understanding and ease of description. That is, the size and thickness of each component shown in the drawings are arbitrarily shown, but the present application is not limited thereto.

[0034] Referring to Figures 1 to 3 , as a lead-in to the embodiments of the present application, some comparative display devices are provided, Figure 1 a schematic diagram of a first comparative display device provided for the embodiments of the present application, Figure 2 a schematic diagram of a second comparative display device provided for the embodiments of the present application, Figure 3 a schematic diagram of a third comparative display device provided for the embodiments of the present application. Referring to Figure 1 , a comparative display device using LTPO technology includes a substrate 101, a light shielding film 102, a barrier film 103, a buffer film 104, a low-temperature polysilicon film 105, a first gate insulating film 106, a first gate film 107, a second gate insulating film 108, a second gate film 109, a first interlayer insulating film 111, an oxide semiconductor film 112, a third gate insulating film 113, a third gate film 114, a second interlayer insulating film 115, a first source / drain film 116, a first planarization film 117, a second source / drain film 118, a second planarization film 119, a third source / drain film 121, a third planarization film 122, an anode film 123, a pixel definition film 124, and a support film 125. As can be seen from Figure 1 , the comparative display device includes three layers of source / drain films and three layers of gate films, so that the comparative display device needs to be formed using 16 mask plates, which is relatively complex and high in cost.

[0035] In order to solve the problem of complex process of the comparative display device, another comparative display device removes one of the gate films and the insulating films, as shown in Figure 2 , it can be seen that the second gate film 109 and the second gate insulating film 108 are removed from the comparative display device, and the number of mask plates can be reduced to 14, but the problem of too many mask plates, complex process and high cost still exists.

[0036] In order to solve the problem of complex process of the contrast display device, another contrast display device further removes a source-drain film and an insulating film, as shown in Figure 3 . By removing the third source-drain film 121 and the third planarization film 122, the number of mask plates can be reduced to 13, as shown in Figure 2 , Figure 3 . However, it can be seen from ,

[0037] that there is no shielding under the oxide semiconductor film 112, resulting in the absence of the bottom gate of the oxide thin film transistor, and the photosensitivity and electrical properties of the thin film transistor are poor. Figures 1 to 14 , Figure 4 The film layer schematic diagram of the display panel provided by the embodiment of the present application is shown in the following. Figure 5 The circuit diagram of the sub-pixel of the display panel provided by the embodiment of the present application is shown in the following. Figure 6 The first kind of stack diagram of the partial film layer of the display panel provided by the embodiment of the present application is shown in the following. Figure 7 The exploded view of the light shielding layer of the display panel in Figure 6 is shown in the following. Figure 8 The exploded view of the first semiconductor layer of the display panel in Figure 6 is shown in the following. Figure 9 The stack schematic diagram of the first semiconductor layer in Figure 8 and the structure in Figure 7 is shown in the following. Figure 10 The exploded view of the first gate layer of the display panel in Figure 6 is shown in the following. Figure 11 The stack schematic diagram of the first gate layer in Figure 10 and the structure in Figure 9 is shown in the following. Figure 12 The exploded view of the second semiconductor layer of the display panel in Figure 6 is shown in the following. Figure 13 The stack schematic diagram of the second semiconductor layer in Figure 12 and the structure in Figure 11 is shown in the following. Figure 14 The exploded view of the second gate layer of the display panel in Figure 6 is shown in the following. Figure 15 The stack schematic diagram of the second gate layer in Figure 14 and the structure in Figure 13 is shown in the following. Figure 16 The exploded view of the first source-drain layer of the display panel in Figure 6 is shown in the following. Figure 17 The stack schematic diagram of the first source-drain layer in Figure 16 and the structure in Figure 15 is shown in the following. Figure 18 The exploded view of the second source-drain layer of the display panel in Figure 6 is shown in the following.

[0038] Please refer to Figures 4 to 18The display panel 2 includes a substrate 201 and a plurality of sub-pixels 31 disposed on the substrate 201, each of the sub-pixels 31 includes a switching transistor T2, a driving transistor T1, a compensation transistor T3 and a first initialization transistor T4, the switching transistor T2 and the driving transistor T1 are connected to a first node A; one electrode of the compensation transistor T3 and one electrode of the first initialization transistor T4 are connected to a second node Q with the driving transistor T1, and the other electrode of the compensation transistor T3 is connected to a third node B with the driving transistor T1. The gate of the compensation transistor T3 is connected to a first scan signal line Nscan1, and the gate of the first initialization transistor T4 is connected to a second scan signal line Nscan2.

[0039] The display panel 2 further includes a light shielding layer 202, a first semiconductor layer 207 and a second semiconductor layer 212 disposed on the substrate 201, the light shielding layer 202 is disposed between the substrate 201 and the first semiconductor layer 207, and the first semiconductor layer 207 is disposed between the light shielding layer 202 and the second semiconductor layer 212.

[0040] The first semiconductor layer 207 is disposed on the side of the light shielding layer 202 away from the substrate 201, and the first semiconductor layer 207 includes a first active part T1A of the driving transistor T1 and a second active part T2A of the switching transistor T2.

[0041] The second semiconductor layer 212 is disposed on the side of the first semiconductor layer 207 away from the substrate 201, and the second semiconductor layer 212 includes a third active part T3A of the compensation transistor T3 and a fourth active part T4A of the first initialization transistor T4.

[0042] The light shielding layer 202 includes a first light shielding pattern 202a, a second light shielding pattern 202b and a third light shielding pattern 202c which are spaced apart in the first direction Y, and the first light shielding pattern 202a, the second light shielding pattern 202b and the third light shielding pattern 202c all extend along the second direction X. The second light shielding pattern 202b is connected to the first scan signal line Nscan1, and the third light shielding pattern 202c is connected to the second scan signal line Nscan2. The first light shielding pattern 202a includes a first light shielding part 311 corresponding to the first active part T1A, the second light shielding pattern 202b includes a second light shielding part 313 corresponding to the third active part T3A, and the third light shielding pattern 202c includes a third light shielding part 315 corresponding to the fourth active part T4A. Wherein, the first direction Y and the second direction X are different, such as the first direction Y is the vertical direction and the second direction X is the horizontal direction, that is, the first direction Y is the column direction and the second direction X is the row direction, of course, the present application is not limited to this, the first direction Y and the second direction X in the present application can also be at other angles, such as an angle greater than 0 degrees and less than 90 degrees.

[0043] The display panel 2 provided in the embodiment of the present application includes a substrate 201, and a light shielding layer 202, a first semiconductor layer 207, and a second semiconductor layer 212 disposed on the substrate 201. The first semiconductor layer 207 is formed with a first active part T1A of a driving transistor T1. The second semiconductor layer 212 is formed with a third active part T3A of a compensation transistor T3 and a fourth active part T4A of a first initialization transistor T4. The light shielding layer 202 includes first, second, and third light shielding patterns 202a, 202b, and 202c arranged along a first direction Y. A first light shielding part 311 on the first light shielding pattern 202a can shield light for the first active part T1A. A second light shielding part 313 on the second light shielding pattern 202b can shield light for the third active part T3A. A third light shielding part 315 on the third light shielding pattern 202c can shield light for the fourth active part T4A. The third active part T3A of the compensation transistor T3 and the fourth active part T4A of the first initialization transistor T4 are prevented from being affected by light, thereby improving the light sensitivity and electrical properties of the compensation transistor T3 and the first initialization transistor T4, and solving the problem of poor light sensitivity and electrical properties caused by the absence of a bottom gate of an oxide thin film transistor in a display device using the LTPO technology.

[0044] Specifically, in the embodiment of the present application, the light shielding parts on the light shielding patterns formed by the light shielding layer 202 are arranged corresponding to the active parts of the transistors, which means that the light shielding parts are arranged corresponding to at least the channel parts of the active parts of the transistors, and the projections of the light shielding parts on the substrate 201 overlap the projections of the channel parts of the transistors on the substrate 201. It can be understood that the active part of each transistor includes a doped part and a channel part, and the channel part is easily affected by light to cause changes in performance. Therefore, the light shielding parts can be arranged corresponding to the channel parts of the transistors. Specifically, for example, the second light shielding part 313 is arranged corresponding to the third active part T3A of the compensation transistor T3, which means that the second light shielding part 313 is arranged corresponding to at least the third channel part of the compensation transistor T3.

[0045] The first light shielding part 311 is arranged corresponding to the first active part T1A of the driving transistor T1. The second light shielding part 313 is arranged corresponding to the third active part T3A of the compensation transistor T3. The third light shielding part 315 is arranged corresponding to the fourth active part T4A of the first initialization transistor T4.

[0046] Specifically, the first active region T1A of the driving transistor T1 is located in the first light shielding region 311, the third active region T3A of the compensation transistor T3 is located in the second light shielding region 313, and the fourth active region T4A of the first initialization transistor T4 is located in the third light shielding region 315, so that the light can not irradiate on the first active region T1A of the driving transistor T1, the third active region T3A of the compensation transistor T3 and the fourth active region T4A of the first initialization transistor T4, and the electrical property and the photosensitivity of the driving transistor T1, the compensation transistor T3 and the first initialization transistor T4 can be improved.

[0047] Specifically, the area of the first light shielding region 311 can be greater than or equal to the area of the first active region T1A of the driving transistor T1, the area of the second light shielding region 313 can be greater than or equal to the area of the third active region T3A of the compensation transistor T3, and the area of the third light shielding region 315 can be greater than or equal to the area of the fourth active region T4A of the first initialization transistor T4.

[0048] Referring to Figure 6 , Figure 7 and Figure 8 , the first light shielding regions 311 are arranged in the second direction X, the second light shielding regions 313 are arranged in the second direction X, and the third light shielding regions 315 are arranged in the second direction X. The first light shielding pattern 202a further comprises first connection lines 312a, 312b connected between two adjacent first light shielding regions 311, the second light shielding pattern 202b further comprises a second connection line 314a connected between two adjacent second light shielding regions 313, and the third light shielding pattern 202c further comprises a third connection line 316a connected between two adjacent third light shielding regions 315. The first connection lines 312a, 312b, the second connection line 314a and the third connection line 316a are arranged in the first direction Y.

[0049] The display panel 2 further comprises a plurality of repeating units 30 arranged in an array on the substrate 201, each of the repeating units 30 comprising two mirror-symmetrical sub-pixels 31, two mirror-symmetrical first light shielding portions 311, two mirror-symmetrical second light shielding portions 313 and two mirror-symmetrical third light shielding portions 315; in the same repeating unit 30, the first connecting line connecting the two first light shielding portions 311 is a first-type first connecting line 312a, the second connecting line connecting the two second light shielding portions 313 is a first-type second connecting line, and the third connecting line connecting the two third light shielding portions 315 is a first-type third connecting line; in the second direction X, the length of the first-type first connecting line 312a is smaller than the length of the first-type second connecting line 314a, and the length of the first-type first connecting line 312a is smaller than the length of the first-type third connecting line 316a.

[0050] The first connecting line connecting the first light shielding portions 311 in the adjacent two repeating units 30 is a second-type first connecting line 312b, and of course, the second connecting line 314a and the third connecting line 316a are also divided into connecting lines connecting the adjacent two repeating units 30, for example, the second connecting line connecting the second light shielding portions 313 in the adjacent two repeating units 30 is a second-type second connecting line, and the third connecting line connecting the third light shielding portions 315 in the adjacent two repeating units 30 is a second-type third connecting line. In the second direction X, the second-type first connecting line 312b is arranged alternately with the first-type first connecting line 312a. The first-type second connecting line 314a comprises a recessed portion 321 arranged close to the first-type first connecting line 312a, and the recessed portion 321 is arranged corresponding to the gap between the adjacent two first light shielding portions 311.

[0051] The adjacent second light shielding portion 313 and the third light shielding portion 315 coincide in the first direction Y. In the repeating unit 30, the first light shielding portion 311 is arranged corresponding to the gap between the adjacent two second light shielding portions 313, and in the first direction Y, the first light shielding portion 311 partially overlaps the second light shielding portion 313, and the first light shielding portion 311 partially overlaps the third light shielding portion 315.

[0052] The gate of the compensation transistor T3 is connected to the first scan signal line Nscan1, the gate of the first initialization transistor T4 is connected to the second scan signal line Nscan2, the second light-shielding pattern 202b is connected to the first scan signal line Nscan1, the third light-shielding pattern 202c is connected to the second scan signal line Nscan2, and the first light-shielding pattern 202a is connected to the high-potential power supply line VDD. Thus, by arranging the first light-shielding pattern 202a, the second light-shielding pattern 202b, and the third light-shielding pattern 202c at intervals in the first direction Y, and by isolating the first light-shielding pattern 202a, the second light-shielding pattern 202b, and the third light-shielding pattern 202c from each other, different signals can be connected to the first light-shielding pattern 202a, the compensation transistor T3 and the first initialization transistor T4 can be prevented from having a threshold voltage negative bias when the second light-shielding pattern 202b and the third light-shielding pattern 202c are connected to the same high-potential power supply signal as the first light-shielding pattern 202a.

[0053] Specifically, it is understood that the display panel 2 will include a plurality of repeating units 30 arranged in an array, and the sub-pixels 31 within each repeating unit 30 can refer to the design within a repeating unit 30 in the embodiments of this application.

[0054] In some embodiments, such as Figure 5 As shown, the gate of switching transistor T2 is connected to the third scan signal line Pscan, the first electrode of switching transistor T2 is connected to the data line DATA, and the second electrode of switching transistor T2 is connected to the first electrode of driving transistor T1 at the first node A; the gate of compensation transistor T3 is connected to the first scan signal line Nscan1, the first electrode of compensation transistor T3 is connected to the gate of driving transistor T1 at the second node Q, and the second electrode of compensation transistor T3 is connected to the second electrode of driving transistor T1; the gate of first initialization transistor T4 is connected to the second scan signal line Nscan2, the first electrode of first initialization transistor T4 is connected to the first initialization signal line VI-G, and the second electrode of first initialization transistor T4 is connected to the gate of driving transistor T1 at the second node B; sub-pixel 31 further includes:

[0055] The first light-emitting control transistor T5 has its gate connected to the light-emitting control signal line EM, its first electrode connected to the high-potential power supply line VDD, and its second electrode connected to the first electrode of the driving transistor T1 at the first node A.

[0056] A second light emitting control transistor T6, a gate of the second light emitting control transistor T6 is connected with the light emitting control signal line EM, a first electrode of the second light emitting control transistor T6 is connected with the second electrode of the driving transistor T1 at a third node B;

[0057] A second initialization transistor T7, a gate of the second initialization transistor T7 is connected with the fourth scan signal line Pscan2, a first electrode of the second initialization transistor T7 is connected with the second initialization signal line VI-ANO, a second electrode of the second initialization transistor T7 is connected with the second electrode of the second light emitting control transistor T6 at a fourth node C;

[0058] A third initialization transistor T8, a gate of the third initialization transistor T8 is connected with the fourth scan signal line Pscan2, a first electrode of the third initialization transistor T8 is connected with the third initialization signal line VI3, a second electrode of the third initialization transistor T8 is connected with the first electrode of the driving transistor T1 at the first node A;

[0059] A storage capacitor Cst, one plate of the storage capacitor Cst is connected with the high potential power supply line VDD, the other plate of the storage capacitor Cst is connected with the gate of the driving transistor T1 at a second node Q;

[0060] A boost capacitor Cboost, one plate of the boost capacitor Cboost is connected with the third scan signal line Pscan, the other plate of the boost capacitor Cboost is connected with the second electrode of the first initialization transistor T4.

[0061] Specifically, as shown in Figure 4 、 Figure 5 the display panel 2 further includes a light emitting layer 23, the light emitting layer 23 includes a light emitting device LED, a positive electrode of the light emitting device LED is connected with the second electrode of the second initialization transistor T7, and a negative electrode of the light emitting device LED is connected with the low potential power supply line VSS.

[0062] In some embodiments, as shown in Figure 4 the display panel 2 further includes a first gate layer 209, a second gate layer 214, a first source-drain layer 216 and a second source-drain layer 218, the first gate layer 209 is arranged between the first semiconductor layer 207 and the second semiconductor layer 212, the second gate layer 214 is arranged between the second semiconductor layer 212 and the first source-drain layer 216, and the first source-drain layer 216 is arranged between the second gate layer 214 and the second source-drain layer 218. By making the display panel include the first gate layer 209, the second gate layer 214, the first source-drain layer 216 and the second source-drain layer 218, the process steps of the display panel can be reduced, and the mask plate required for forming the display panel can be reduced.

[0063] In some embodiments, asFigures 4 to 6 , Figure 8 , Figure 9 As shown, the first semiconductor layer 207 includes a first active portion T1A of a driving transistor T1, a second active portion T2A of a switching transistor T2, a fifth active portion T5A of a first light-emitting control transistor T5, a sixth active portion T6A of a second light-emitting control transistor T6, a seventh active portion T7A of a second initialization transistor T7, and an eighth active portion T8A of a third initialization transistor T8. The first light-shielding portion 311 on the first light-shielding pattern 202a is correspondingly disposed to the first active portion T1A, as shown... Figure 9 As shown. The first active portion T1A of the driving transistor T1 is disposed along the second direction X, and the first active portion T1A of the driving transistor T1 is connected to the second active portion T2A of the switching transistor T2, the fifth active portion T5A of the first light-emitting control transistor T5, and the sixth active portion T6A of the second light-emitting control transistor T6. The second active portion T2A of the switching transistor T2 and the fifth active portion T5A of the first light-emitting control transistor T5 are disposed along the first direction Y, and the sixth active portion T6A of the second light-emitting control transistor T6 is connected to the second initialization transistor T7. The seventh active part T7A is disposed along the first direction Y, and the sixth active part T6A of the second light-emitting control transistor T6 is connected to the seventh active part T7A of the second initialization transistor T7. The eighth active part T8A of the third initialization transistor T8 is disposed at intervals with the first active part T1A of the driving transistor T1, the second active part T2A of the switching transistor T2, the fifth active part T5A of the first light-emitting control transistor T5, the sixth active part T6A of the second light-emitting control transistor T6, and the seventh active part T7A of the second initialization transistor T7.

[0064] Specifically, it can be seen that within a repeating unit 30, the fifth active part T5A of two adjacent first light-emitting control transistors T5 is connected.

[0065] In some embodiments, such as Figures 4 to 6 , Figure 10 , Figure 11 As shown, the first gate layer 209 includes a first initialization signal line VI-G, a third scan signal line Pscan, a light emission control signal line EM, a fourth scan signal line Pscan2, a gate T1G of a driving transistor T1, a gate T2G of a switching transistor T2, a gate T5G of a first light emission control transistor T5, a gate T6G of a second light emission control transistor T6, a gate T7G of a second initialization transistor T7, a gate T8G of a third initialization transistor T8, and a first plate Cst1 of a storage capacitor Cst. The first initialization signal line VI-G, the third scan signal line Pscan, the first plate Cst1 of the storage capacitor Cst, the light emission control signal line EM, and the fourth scan signal line Pscan2 are arranged sequentially at intervals along the first direction Y.

[0066] Specifically, as can be seen from Figure 10 , the gate T2G of the switch transistor T2 is part of the third scan signal line Pscan, and it can be understood that, since the gates T2G of all the switch transistors T2 in a row of sub-pixels 31 are connected to the same third scan signal line Pscan, when the third scan signal line Pscan is formed, the part of the third scan signal line Pscan corresponding to the channel of the switch transistor T2 of each sub-pixel 31 is taken as the gate of the switch transistor T2 of each pixel unit, therefore, the same structure will be marked with two labels, and by analogy, the gate T1G of the drive transistor T1 is both the gate and the first plate Cst1 of the storage capacitor Cst, the part of the emission control signal line EM corresponding to the channel of the first emission control transistor T5 is taken as the gate T5G of the first emission control transistor T5, the part of the emission control signal line EM corresponding to the channel of the second emission control transistor T6 is taken as the gate T6G of the second emission control transistor T6, the part of the fourth scan signal line Pscan2 corresponding to the channel of the second initialization transistor T7 is taken as the gate T7G of the second initialization transistor T7, and the part of the fourth scan signal line Pscan2 corresponding to the channel of the third initialization transistor T8 is taken as the gate T8G of the third initialization transistor T8.

[0067] Referring to Figure 10 and Figure 11 , the position where the gate of each transistor overlaps the first semiconductor layer 207 is the channel portion of the corresponding transistor, for example, the position where the gate T2G of the switch transistor T2 overlaps the first semiconductor layer 207 is the channel portion of the switch transistor T2; the position where the gate T1G of the drive transistor T1 overlaps the first semiconductor layer 207 is the channel portion of the drive transistor T1; the position where the gate T5G of the first emission control transistor T5 overlaps the first semiconductor layer 207 is the channel portion of the first emission control transistor T5; the position where the gate T6G of the second emission control transistor T6 overlaps the first semiconductor layer 207 is the channel portion of the second emission control transistor T6; the position where the gate T7G of the second initialization transistor T7 overlaps the first semiconductor layer 207 is the channel portion of the second initialization transistor T7; and the position where the gate T8G of the third initialization transistor T8 overlaps the first semiconductor layer 207 is the channel portion of the third initialization transistor T8.

[0068] In some embodiments, as Figures 4 to 6 , Figure 12 , Figure 13As shown in FIG. 12, the second semiconductor layer 212 includes a third active part T3A of the compensation transistor T3, a fourth active part T4A of the first initialization transistor T4, and a second plate Cst2 of the storage capacitor Cst. The third active part T3A of the compensation transistor T3 is connected to the fourth active part T4A of the first initialization transistor T4, and both the third active part T3A and the fourth active part T4A extend along the first direction Y. The second plate Cst2 of the storage capacitor Cst is arranged on one side of the third active part T3A of the compensation transistor T3 along the first direction Y, and is arranged corresponding to the gap between two adjacent third active parts T3A. The second plate Cst2 is arranged corresponding to the first light shielding part 311, and the first plate Cst2 is connected to the high potential power line VDD. A through hole 331 is arranged on the second plate Cst2 of the storage capacitor Cst. By forming the second plate Cst2 of the storage capacitor Cst in the second semiconductor layer 212, the storage capacitor Cst can be arranged in the sub-pixel 31, and the through hole arranged on the second plate Cst2 of the storage capacitor Cst allows the first electrode of the compensation transistor T3 to be normally connected to the gate of the driving transistor T1.

[0069] Specifically, it can be understood that the second semiconductor layer 212 forms the second plate of the storage capacitor Cst, and thus it is necessary to make the second plate of the storage capacitor Cst have good electrical properties. The second plate of the storage capacitor Cst can be doped to keep the electrical properties of the second plate of the storage capacitor Cst consistent with or even better than the electrical properties of the doped part of the active part, so that the electrical properties of the storage capacitor Cst are good.

[0070] Specifically, by arranging the through hole on the second plate of the storage capacitor Cst, the first electrode of the compensation transistor T3 can pass through the second plate of the storage capacitor Cst to be connected to the gate of the driving transistor T1, so that the sub-pixel 31 normally works.

[0071] Specifically, as shown in FIG. 12, Figure 10 , Figure 12 , Figure 13 the first gate layer 209 further includes a first plate Cboost1 of a boost capacitor Cboost, and the second semiconductor layer 212 further includes a second plate Cboost2 of the boost capacitor Cboost. The overlapping part of the third scan signal line Pscan and the fourth active part T4A of the first initialization transistor T4 is the first plate Cboost1 of the boost capacitor Cboost, and the overlapping part of the fourth active part T4A of the first initialization transistor T4 and the third scan signal line Pscan is the second plate Cboost2 of the boost capacitor Cboost.

[0072] In some embodiments, as shown in FIG. 12, Figures 4 to 6 , Figure 14 andFigure 15 As shown, the second gate layer 214 includes a second scan signal line Nscan2, a first scan signal line Nscanl, a third initialization signal line VI3, a gate T3G of the compensation transistor T3, and a gate T4G of the first initialization transistor T4. The position where the gate T3G of the compensation transistor T3 overlaps with the second semiconductor layer 212 is the channel portion of the compensation transistor T3, and the position where the gate T4G of the first initialization transistor T4 overlaps with the second semiconductor layer 212 is the channel portion of the first initialization transistor T4.

[0073] Referring to Figure 14 and Figure 15 , the second scan signal line Nscan2, the first scan signal line Nscanl, and the third initialization signal line VI3 are sequentially arranged along the first direction Y. The orthogonal projection of the first scan signal line Nscanl on the substrate 201 at least partially overlaps with the orthogonal projection of the second light shielding pattern 202b on the substrate 201, and / or the orthogonal projection of the second scan signal line Nscan2 on the substrate 201 at least partially overlaps with the orthogonal projection of the third light shielding pattern 202c on the substrate 201. Specifically, the projection of the second light shielding pattern 202b on the substrate 201 can coincide with the projection of the first scan signal line Nscanl on the substrate 201, thereby reducing the coupling capacitance of the second light shielding pattern 202b and other signal lines, and even if the second light shielding pattern 202b is coupled with the first scan signal line Nscanl, since the second light shielding portion 313 shields the third active portion T3A of the compensation transistor T3, the potential of the second light shielding pattern 202b is the same as the potential of the second light shielding portion 313, which can be the potential of the first scan signal line Nscanl, and the gate control capability of the compensation transistor T3 can be improved.

[0074] Specifically, the projection of the second light shielding pattern 202b on the substrate 201 can coincide with the projection of the first scan signal line Nscanl on the substrate 201, and the projection of the third light shielding portion 315 on the substrate 201 can coincide with the projection of the second scan signal line Nscan2 on the substrate 201, thereby reducing the overlapping area of the second light shielding pattern 202b and the third light shielding pattern 202c with other traces, reducing the interference of the second light shielding pattern 202b and the third light shielding pattern 202c on other signals, and when the second light shielding pattern 202b is coupled with the first scan signal line Nscanl and the third light shielding pattern 202c is coupled with the second scan signal line Nscan2, the second light shielding portion 313 and the third light shielding portion 315 can be used as the bottom gate of the compensation transistor T3 and the first initialization transistor T4, respectively, thereby improving the gate control capability of the compensation transistor T3 and the first initialization transistor T4.

[0075] In some embodiments, as Figures 4 to 6 , Figure 16and Figure 17 As shown in the stack diagram in FIG. 2, the first source-drain layer 216 includes a first electrode T2S of the switch transistor T2, a first electrode T3S of the compensation transistor T3, a second electrode T3D of the compensation transistor T3, a first electrode T4S of the first initialization transistor T4, a second electrode T4D of the first initialization transistor T4, a first electrode T5S of the first light-emitting control transistor T5, a second electrode T5D of the first light-emitting control transistor T5, a first electrode T6S of the second light-emitting control transistor T6, a second electrode T6D of the second light-emitting control transistor T6, a first electrode T7S of the second initialization transistor T7, a second electrode T7D of the second initialization transistor T7, a first electrode T8S of the third initialization transistor T8, a second electrode T8D of the third initialization transistor T8, and a second initialization signal line VI-ANO, wherein the second initialization signal line VI-ANO is not shown in the stack diagram in FIG. 2. Figure 17 As shown in the stack diagram in FIG. 2, the first source-drain layer 216 includes a first electrode T2S of the switch transistor T2, a first electrode T3S of the compensation transistor T3, a second electrode T3D of the compensation transistor T3, a first electrode T4S of the first initialization transistor T4, a second electrode T4D of the first initialization transistor T4, a first electrode T5S of the first light-emitting control transistor T5, a second electrode T5D of the first light-emitting control transistor T5, a first electrode T6S of the second light-emitting control transistor T6, a second electrode T6D of the second light-emitting control transistor T6, a first electrode T7S of the second initialization transistor T7, a second electrode T7D of the second initialization transistor T7, a first electrode T8S of the third initialization transistor T8, a second electrode T8D of the third initialization transistor T8, and a second initialization signal line VI-ANO, wherein the second initialization signal line VI-ANO is not shown in the stack diagram in FIG. 2.

[0076] Specifically, as shown in FIG. 2, it can be understood that the electrodes of the transistors are connected together, but in actual design, in order to improve the aperture ratio, the electrodes of the transistors share the same structure, so in the stack diagram in FIG. 2, the same structure is identified by multiple labels, for example, a structure is both the first electrode T3S of the compensation transistor T3 and the second electrode T4D of the first initialization transistor T4, and from the stack diagram in FIG. 2, it can be seen that this is the position connected by the second node Q. Similarly, other structures also serve as multiple electrodes, and the positions of the nodes can be determined accordingly. Figure 16 Figure 16 Figure 5

[0077] Specifically, as shown in FIG. 2, it can be understood that the electrodes of the transistors are connected together, but in actual design, in order to improve the aperture ratio, the electrodes of the transistors share the same structure, so in the stack diagram in FIG. 2, the same structure is identified by multiple labels, for example, a structure is both the first electrode T3S of the compensation transistor T3 and the second electrode T4D of the first initialization transistor T4, and from the stack diagram in FIG. 2, it can be seen that this is the position connected by the second node Q. Similarly, other structures also serve as multiple electrodes, and the positions of the nodes can be determined accordingly. Figure 11 Figure 16 Figure 17 ​​​​​As shown, the first initialization signal line VI-G and the first electrode T4S of the first initialization transistor T4 are connected through the first connection terminal K1. Given the small distance between the projections of the first initialization signal line VI-G and the second scan signal line Nscan2 on the substrate, directly forming a via in the corresponding region of the first electrode of the first initialization transistor to connect the first initialization signal line would result in the via forming on the second scan signal line Nscan2. Therefore, the first connection terminal K1 can be set on the first source-drain layer, connecting the first electrode of the first initialization transistor T4 through the first connection terminal K1. Simultaneously, a via is formed in the corresponding region of the first connection terminal K1, connecting the first connection terminal K1 to the first initialization signal line VI-G. This achieves the connection between the first initialization signal line VI-G and the first electrode T4S of the first initialization transistor T4. Furthermore, the first connection terminal K1 is positioned on the axis of symmetry of the two symmetrically arranged sub-pixels 31, allowing the first electrodes of the first initialization transistor T4 in the two symmetrically arranged sub-pixels 31 to be connected to the first initialization signal line through the same first connection terminal K1, reducing the number of vias and improving yield.

[0078] Specifically, such as Figures 6 to 16 As shown, the first electrode T3S of the compensation transistor T3 is connected to the gate T1G of the driving transistor T1. Therefore, a second connection terminal K2 can be provided in the first source-drain layer. The second connection terminal K2 passes through the through hole 331 and is connected to the gate T1G of the driving transistor T1, thereby realizing the connection between the gate of the driving transistor T1 and the first electrode T3S of the compensation transistor T3.

[0079] The third initialization signal line VI3 is connected to the first electrode T8S of the third initialization transistor T8 through the third connection terminal K3.

[0080] In some embodiments, such as Figures 4 to 6 , Figure 18 As shown, within a repeating unit 30, the second source-drain layer 218 includes two data lines DATA and two high-potential power lines VDD. The two data lines are arranged in a mirror-symmetric configuration, and the two high-potential power lines VDD are arranged in a mirror-symmetric configuration.

[0081] Specifically, it is understood that due to the design of the sub-pixel 31 in the display area shown in the embodiments of this application, and the connection points of some traces located in the non-display area, some traces may not be connected together. However, in reality, they will be connected. For example, in order to adopt the technology of setting the fanout line in the display area (Fanout In AA, FIAA), the data line will be provided with a first data connection line set along the first direction Y and a second data connection line set along the second direction X, and will be connected to the data line outside the display area. However, the embodiments of this application show the design of the sub-pixel 31 in the display area, so its connection point is not shown, but in reality, it will be connected.

[0082] Meanwhile, in order to realize the mesh structure design of the initialization signal line, the embodiments of this application will set an initialization signal connection line. The initialization signal connection line can realize the mesh structure design of at least one of the first initialization signal line VI-G, the second initialization signal line VI-ANO, and the third initialization signal line VI3. Similarly, the initialization signal connection line will be connected to the initialization signal line.

[0083] For example, the first initialization signal line VI-G is connected to the initialization signal connection line outside the display area, thereby realizing the mesh structure design of the first initialization signal line VI-G. Similarly, the mesh structure design of the second initialization signal line VI-ANO and the third initialization signal line VI3 can be realized. However, the embodiments of this application are not limited to this. Some initialization signal connection lines can be connected to one of the first initialization signal line VI-G, the second initialization signal line VI-ANO, and the third initialization signal line VI3, and some initialization signal connection lines can be connected to another of the first initialization signal line VI-G, the second initialization signal line VI-ANO, and the third initialization signal line VI3. Alternatively, some initialization signal connection lines can be connected to another of the first initialization signal line VI-G, the second initialization signal line VI-ANO, and the third initialization signal line VI3, thereby realizing the mesh structure design of each initialization signal line.

[0084] Specifically, such as Figure 4 As shown, the display panel 2 also includes a first barrier layer 203, a second barrier layer 205, a buffer layer 206, a first gate insulating layer 208, a first interlayer insulating layer 211, a second gate insulating layer 213, a second interlayer insulating layer 215, a first planarization layer 217, and a second planarization layer 219.

[0085] Specifically, such as Figure 4 As shown, the display panel 2 also includes a light-emitting layer 23, which includes a pixel electrode layer 221, a pixel definition layer 222, a light-emitting material layer, a common electrode layer, and a support pillar 223.

[0086] Specifically, in the above embodiments, the first electrode of the transistor is the source and the second electrode is the drain; or in the above embodiments, the first electrode of the transistor is the drain and the second electrode is the source.

[0087] Specifically, the third scan signal line Pscan, the first scan signal line Nscan1, the second scan signal line Nscan2, the fourth scan signal line Pscan2 and the light-emitting control signal line EM can be connected to different gate drive circuits, and specifically, five groups of gate drive circuits can be used to output signals to the third scan signal line Pscan, the first scan signal line Nscan1, the second scan signal line Nscan2, the fourth scan signal line Pscan2 and the light-emitting control signal line EM, wherein the gate drive circuit connected to the third scan signal line Pscan can use bilateral driving, and the other gate drive circuits use unilateral driving.

[0088] Specifically, the material of the first semiconductor layer 207 includes a silicon semiconductor material, and specifically can be low-temperature polysilicon.

[0089] Specifically, the material of the second semiconductor layer 212 includes an oxide semiconductor material, and specifically can be a metal oxide semiconductor material, and more specifically can be indium gallium zinc oxide.

[0090] Specifically, the material of the light-blocking layer 202 includes a metal material.

[0091] Specifically, the driving transistor T1, the switching transistor T2, the first light-emitting transistor, the second light-emitting transistor, the second initialization transistor and the third initialization transistor are P-type transistors, and the first initialization transistor T4 and the compensation transistor T3 are N-type transistors.

[0092] Specifically, the above embodiments respectively describe the display panel in detail from the structure of the sub-pixel 31 in the display panel 2, the film layer structure, the specific structure of each layer, the material and the potential, and it can be understood that the embodiments can be combined when there is no conflict between the embodiments.

[0093] Meanwhile, the display device provided by the embodiment of the present application includes the display panel 2 of any one of the above embodiments.

[0094] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0095] The above describes the embodiments of the present application in detail, and the specific examples are applied to the principle and implementation mode of the present application, and the above embodiment description is only used to help understand the technical solution and core idea of the present application; those skilled in the art should understand that the technical solution recorded in the above embodiments can be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solution deviate from the scope of the technical solution of the embodiments of the present application.

Claims

1. A display panel, characterized in that, It includes multiple sub-pixels, each sub-pixel including a driving transistor, a compensation transistor and a storage capacitor. The first active part of the driving transistor is located in the first semiconductor layer, the third active part of the compensation transistor and one plate of the storage capacitor are both located in the second semiconductor layer, the gate of the driving transistor and the other plate of the storage capacitor are both located in the first gate layer, and the first semiconductor layer, the second semiconductor layer and the first gate layer are all disposed in different layers. The display panel further includes a light-shielding layer, which includes a first light-shielding part corresponding to the first active part and a second light-shielding part corresponding to the third active part. The electrical signals on the first light-shielding part and the second light-shielding part are different. The light-shielding layer further includes a second light-shielding pattern, which includes a plurality of second light-shielding portions. The first light-shielding pattern is connected to a high-potential power line, and the second light-shielding pattern is connected to the gate of the compensation transistor. The gate of the compensation transistor is connected to a first scan signal line, and the second light-shielding pattern is connected to the first scan signal line.

2. The display panel according to claim 1, characterized in that, The light-shielding layer further includes a first light-shielding pattern and a second light-shielding pattern arranged at intervals, the first light-shielding pattern and the second light-shielding pattern extending in the same direction, and the first light-shielding pattern including a plurality of light-shielding portions.

3. The display panel according to claim 2, characterized in that, The orthographic projection of the first scanning signal line on the substrate of the display panel at least partially overlaps with the orthographic projection of the second light-shielding pattern on the substrate of the display panel.

4. The display panel according to claim 2, characterized in that, The first light-shielding pattern and the second light-shielding pattern are arranged at intervals in a first direction. Both the first light-shielding pattern and the second light-shielding pattern extend along a second direction, which is different from the first direction. The high-potential power lines extend along the first direction and are arranged at intervals along the second direction. A plurality of first light-shielding portions are arranged at intervals in the second direction, and a plurality of second light-shielding portions are arranged at intervals in the second direction; The first light-shielding pattern further includes a first connecting line connecting two adjacent first light-shielding portions, and the second light-shielding pattern further includes a second connecting line connecting two adjacent second light-shielding portions, with the first connecting line and the second connecting line arranged at intervals in the first direction.

5. The display panel according to claim 4, characterized in that, The display panel also includes multiple repeating units, each of which includes two mirror-symmetrical sub-pixels, two mirror-symmetrical first light-blocking portions, and two mirror-symmetrical second light-blocking portions; Within the same repeating unit, the first connecting line connecting two first light-shielding parts is a first type of first connecting line, and the second connecting line connecting two second light-shielding parts is a first type of second connecting line. In the second direction, the length of the first type of first connecting line is less than the length of the first type of second connecting line.

6. The display panel according to claim 5, characterized in that, The first connecting line connecting the first light-shielding part in two adjacent repeating units is a second type of first connecting line. In the second direction, the second type of first connecting line and the first type of first connecting line are staggered.

7. The display panel according to claim 5, characterized in that, The first type of second connecting line includes a recessed portion disposed near the first type of first connecting line, the recessed portion being disposed between two adjacent first light-shielding portions.

8. The display panel according to claim 5, characterized in that, Within the repeating unit, the first light-shielding part is arranged at the gap between two adjacent second light-shielding parts.

9. The display panel according to any one of claims 2 to 8, characterized in that, The sub-pixel further includes a first initialization transistor, the fourth active portion of the first initialization transistor being located in the second semiconductor layer, and the light-shielding layer further includes a third light-shielding pattern located in the second light-shielding pattern away from the first light-shielding pattern, the third light-shielding pattern including a third light-shielding portion disposed corresponding to the fourth active portion, the third light-shielding portion having the same electrical signal as the second light-shielding portion.

10. The display panel according to claim 9, characterized in that, The third light-shielding pattern is connected to the gate of the first initialization transistor, and the gate of the first initialization transistor is connected to the second scan signal line; the orthographic projection of the second scan signal line on the substrate of the display panel and the orthographic projection of the third light-shielding pattern on the substrate of the display panel at least partially overlap.

11. The display panel according to claim 10, characterized in that, The sub-pixel further includes a switching transistor, the gate of which is connected to a third scan signal line, the first electrode of which is connected to a data line, and the second electrode of which is connected to the first electrode of the driving transistor at a first node; the first electrode of the compensation transistor is connected to the gate of the driving transistor at a second node, and the second electrode of the compensation transistor is connected to the second electrode of the driving transistor; the first electrode of the first initialization transistor is connected to a first initialization signal line, and the second electrode of the first initialization transistor is connected to the gate of the driving transistor at a second node; The sub-pixel also includes: The first light-emitting control transistor has its gate connected to the light-emitting control signal line, its first electrode connected to the high-potential power supply line, and its second electrode connected to the first electrode of the driving transistor at the first node. The second light-emitting control transistor has its gate connected to the light-emitting control signal line, and its first electrode is connected to the second electrode of the driving transistor at the third node. The second initialization transistor has its gate connected to the fourth scan signal line, its first electrode connected to the second initialization signal line, and its second electrode connected to the second light-emitting control transistor at the fourth node. The third initialization transistor has its gate connected to the fourth scan signal line, its first electrode connected to the third initialization signal line, and its second electrode connected to the first electrode of the driving transistor at the first node. One plate of the storage capacitor is connected to the high-potential power line, and the other plate of the storage capacitor is connected to the gate of the driving transistor at the second node. A boost capacitor, one plate of which is connected to the third scan signal line, and the other plate of which is connected to the second electrode of the first initialization transistor.

12. The display panel according to claim 11, characterized in that, The second semiconductor layer further includes a second electrode plate of the storage capacitor. The second electrode plate is disposed corresponding to the first light-shielding part and is connected to the high-potential power line. A through hole is provided on the second electrode plate.

13. The display panel according to claim 12, characterized in that, The first semiconductor layer further includes a second active portion of the switching transistor, a fifth active portion of the first light-emitting control transistor, a sixth active portion of the second light-emitting control transistor, a seventh active portion of the second initialization transistor, and an eighth active portion of the third initialization transistor. The first active portion is connected to the second active portion, the fifth active portion, and the sixth active portion. The sixth active portion is connected to the seventh active portion. The eighth active portion is spaced apart from the first active portion, the second active portion, the fifth active portion, the sixth active portion, and the seventh active portion, and is located between the fifth active portion and the seventh active portion.

14. The display panel according to claim 13, characterized in that, The first gate layer is disposed between the first semiconductor layer and the second semiconductor layer. The first gate layer includes the first initialization signal line, the third scan signal line, the light emission control signal line, the fourth scan signal line, the gate of the driving transistor, the gate of the switching transistor, the gate of the first light emission control transistor, the gate of the second light emission control transistor, the gate of the second initialization transistor, the gate of the third initialization transistor, and the first plate of the storage capacitor. The first initialization signal line, the third scan signal line, the first plate of the storage capacitor, the light emission control signal line, and the fourth scan signal line are arranged sequentially at intervals.

15. The display panel according to claim 14, characterized in that, The display panel further includes a second gate layer, which is disposed on the side of the second semiconductor layer away from the first gate layer. The second gate layer includes the first scan signal line, the second scan signal line, the third initialization signal line, the gate of the compensation transistor, and the gate of the first initialization transistor. The third initialization signal line, the first scan signal line, and the second scan signal line are arranged sequentially at intervals.

16. A display device, characterized in that, Includes the display panel as claimed in any one of claims 1 to 15.

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