Array substrate, preparation method thereof and display device

Abstract

The invention provides an array substrate. The array substrate comprises a substrate body; the active layer is positioned on one side of the substrate; the first metal layer at least comprises a first metal region; the second metal layer comprises a grid electrode and a third metal region, and the second metal layer is located on the side, away from the substrate, of the first metal layer; the first interlayer insulating layer is located on one side, far away from the substrate, of the active layer, the first metal layer and the second metal layer, and a first via hole is formed in the first interlayer insulating layer; wherein the orthographic projection of the first metal area on the substrate is at least partially overlapped with the orthographic projection of the first via hole on the substrate, and the orthographic projection of the third metal area on the substrate is at least partially overlapped with the orthographic projection of the first via hole on the substrate; the array substrate further comprises an electrode layer, and the electrode layer is at least partially filled in the first via hole and enables the first metal area to be connected with the third metal area through the first via hole.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate and a preparation method thereof, and a display device. Background Art

[0002] In the field of semiconductor technology, compared with traditional silicon-based thin film transistors (Si-TFTs), metal oxide thin film transistors have developed rapidly due to their high mobility, simple preparation process, low cost, high uniformity, etc., and have become key devices for driving LCD display panels and OLED display panels. In the related art, the oxide backplane based on the top gate structure needs to be manufactured through a multi-pass mask process, which requires a large number of mask plates, resulting in complex processes and high costs. In addition, in the related art, the structure of the oxide backplane based on the top gate structure is difficult to meet the needs of high PPI products.

[0003] The above information disclosed in this section is only for understanding the background of the inventive concept of the present disclosure and therefore the above information may contain information that does not constitute the prior art. Summary of the invention

[0004] In order to solve at least one aspect of the above problems, embodiments of the present disclosure provide an array substrate and a method for manufacturing the same, and a display device.

[0005] According to one aspect of an embodiment of the present disclosure, an array substrate is provided, including:

[0006] substrate substrate;

[0007] An active layer, located on one side of the substrate;

[0008] A first metal layer including a first metal region;

[0009] A second metal layer, comprising a gate and a third metal region, wherein the second metal layer is located on a side of the first metal layer away from the substrate;

[0010] A first interlayer insulating layer is located on a side of the active layer, the first metal layer, and the second metal layer away from the substrate, wherein a first via hole is provided in the first interlayer insulating layer; and

[0011] an electrode layer, located on a side of the first interlayer insulating layer away from the base substrate, the electrode layer comprising an electrode filling portion,

[0012] wherein the orthographic projection of the first metal area on the base substrate at least partially overlaps with the orthographic projection of the first via hole on the base substrate, and the orthographic projection of the third metal area on the base substrate at least partially overlaps with the orthographic projection of the first via hole on the base substrate; and

[0013] The electrode filling portion at least partially fills the first via hole and connects the first metal region and the third metal region.

[0014] In some embodiments, an orthographic projection of the first metal region on the base substrate at least partially overlaps with an orthographic projection of the third metal region on the base substrate.

[0015] In some embodiments, the first via includes a first channel and a second channel that are interconnected, the first channel is arranged on a side of the second channel away from the substrate, the orthographic projection of the first channel on the substrate covers the orthographic projection of the second channel on the substrate, the first channel exposes at least a portion of the surface of the third metal area away from the substrate, and the second channel exposes at least a portion of the surface of the first metal area away from the substrate and at least a portion of the side of the third metal area close to the first metal area.

[0016] In some embodiments, at least part of the electrode filling portion covers the exposed surface of the third metal region away from the substrate, the surface of the first metal region away from the substrate, and the side surface of the third metal region close to the first metal region.

[0017] In some embodiments, the array substrate further includes:

[0018] A first insulating portion is located between the first metal area and the third metal area; an orthographic projection of the first insulating portion on the substrate at least partially overlaps with an orthographic projection of the first metal area on the substrate, and an orthographic projection of the first insulating portion on the substrate at least partially overlaps with an orthographic projection of the third metal area on the substrate.

[0019] In some embodiments, the first via hole exposes a side surface of the first insulating portion close to the first metal region; and at least a portion of the electrode filling portion covers the exposed side surface of the first insulating portion close to the first metal region.

[0020] In some embodiments, the array substrate comprises:

[0021] A gate insulating portion is located between the active layer and the gate, and at least a portion of the gate insulating portion is located in the same layer as the first insulating portion.

[0022] In some embodiments, the gate insulating portion includes a first gate insulating portion and a second gate insulating portion, and a thickness of the first gate insulating portion is smaller than a thickness of the second gate insulating portion;

[0023] The second gate insulating portion and the first insulating portion are located in the same layer.

[0024] In some embodiments, the active layer includes a first conductor region, a second conductor region, and a channel region between the first conductor region and the second conductor region;

[0025] The first metal layer includes a second metal region, which is located at a side of the first conductor region away from the base substrate and connected to a surface of the first conductor region away from the base substrate.

[0026] In some embodiments, the second conductor region is multiplexed as a pixel electrode;

[0027] The electrode layer further includes a common electrode, and an orthographic projection of the common electrode on the base substrate at least partially overlaps with an orthographic projection of the pixel electrode on the base substrate.

[0028] In some embodiments, the array substrate further includes:

[0029] A buffer layer is located between the substrate and the active layer, and the buffer layer covers the first metal region.

[0030] In some embodiments, a second via is provided in the buffer layer, the second via is interconnected with the first via, and the second via exposes at least a portion of the surface of the first metal area away from the substrate and the side of the buffer layer away from the substrate.

[0031] In some embodiments, the first metal region is located in the light shielding layer;

[0032] The third metal region is located at a side of the first conductor region away from the base substrate and is connected to a surface of the first conductor region away from the base substrate.

[0033] Another aspect of the embodiments of the present disclosure provides a display device, comprising the array substrate according to any one of the above items.

[0034] Another aspect of the embodiments of the present disclosure provides a method for preparing an array substrate, the method comprising the following steps:

[0035] An active material layer is formed on a substrate, and a first patterning process is performed on the active material layer to form an active layer;

[0036] Forming a first metal material layer on the base substrate, performing a second patterning process on the first metal material layer to form a first metal layer, wherein the first metal layer at least includes a first metal region;

[0037] Forming a second metal material layer on the substrate, performing a third patterning process on the second metal material layer to form a second metal layer, wherein the second metal layer includes a gate and a third metal region, and the second metal layer is located on a side of the first metal layer away from the substrate;

[0038] An interlayer insulating material layer is formed on a side of the active layer, the first metal layer, and the second metal layer away from the base substrate, and a fourth patterning process is performed on the interlayer insulating material layer to form a first interlayer insulating layer and a first via hole; wherein the orthographic projection of the first metal region on the base substrate at least partially overlaps with the orthographic projection of the first via hole on the base substrate, and the orthographic projection of the third metal region on the base substrate at least partially overlaps with the orthographic projection of the first via hole on the base substrate;

[0039] An electrode material layer is formed on the interlayer insulating material layer, and a fifth patterning process is performed on the electrode material layer to form an electrode layer, wherein the electrode layer at least partially fills the first via hole and connects the first metal area with the third metal area through the first via hole.

[0040] In some embodiments, performing a first patterning process on the active material layer includes:

[0041] A photoresist layer is formed on the gate insulating material layer, and a half-tone mask is used for exposure;

[0042] Performing development and etching processes to form a gate insulating portion and a first insulating portion, wherein the first insulating portion is located between the first metal region and the third metal region;

[0043] The ashing treatment and the conductor treatment process are performed to form the active material layer into an active layer, wherein the active layer includes a first conductor region, a second conductor region and a channel region between the first conductor region and the second conductor region.

[0044] Another aspect of the embodiments of the present disclosure provides a method for preparing an array substrate, the method comprising the following steps:

[0045] Forming a first metal material layer on the base substrate, performing a first patterning process on the first metal material layer to form a first metal layer, wherein the first metal layer includes a first metal region;

[0046] forming a buffer layer and an active material layer in sequence on a side of the first metal layer away from the base substrate, and performing a second patterning process on the active material layer to form an active layer;

[0047] Forming a second metal material layer on a side of the active layer away from the substrate, performing a third patterning process on the second metal material layer to form a second metal layer, wherein the second metal layer includes a gate and a third metal region, wherein the third metal region is located on a side of the first metal region away from the substrate;

[0048] An interlayer insulating material layer is formed on a side of the second metal layer away from the base substrate, and a fourth patterning process is performed on the interlayer insulating material layer to form a first via hole; wherein the orthographic projection of the first metal region on the base substrate at least partially overlaps with the orthographic projection of the first via hole on the base substrate, and the orthographic projection of the third metal region on the base substrate at least partially overlaps with the orthographic projection of the first via hole on the base substrate;

[0049] An electrode material layer is formed on a side of the interlayer insulating material layer away from the base substrate, and a fifth patterning process is performed on the electrode material layer to form an electrode layer, wherein the electrode layer includes an electrode filling portion, and the electrode filling portion at least partially fills the first via hole and connects the first metal area with the third metal area. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Other objects and advantages of the present disclosure will be apparent from the following description of the present disclosure with reference to the accompanying drawings, and will help to have a comprehensive understanding of the present disclosure.

[0051] Figure 1A A schematic diagram of a planar structure of an array substrate in the related art is shown;

[0052] Figure 1B A cross-sectional view of an array substrate in the related art is schematically shown;

[0053] Figure 2A Schematically showing a planar structural diagram of an array substrate according to some exemplary embodiments of the present disclosure;

[0054] Figure 2B Schematically showing a cross-sectional view of an array substrate according to some exemplary embodiments of the present disclosure;

[0055] Figure 2C Schematically showing a cross-sectional view of an array substrate according to some exemplary embodiments of the present disclosure;

[0056] Figure 3 Schematically showing a cross-sectional view of an array substrate according to some other exemplary embodiments of the present disclosure;

[0057] Figure 4A Schematically showing a cross-sectional view of an array substrate according to some other exemplary embodiments of the present disclosure;

[0058] Figure 4B Schematically showing a cross-sectional view of an array substrate according to some other exemplary embodiments of the present disclosure;

[0059] Figure 5 A schematic diagram of the structure of a display device provided in an embodiment of the present disclosure;

[0060] Figure 6 A flow chart schematically shows a method for preparing an array substrate according to an embodiment of the present disclosure;

[0061] Figure 7A-7D A cross-sectional view schematically shows a process of preparing an array substrate according to an embodiment of the present disclosure;

[0062] Figure 8 A flow chart schematically shows a method for preparing an array substrate according to another embodiment of the present disclosure;

[0063] Figure 9A-9C The cross-sectional view during the preparation of the array substrate according to the embodiment of the present disclosure is schematically shown.

[0064] It should be noted that, for the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the sizes of layers, structures or regions may be enlarged or reduced, that is, these drawings are not drawn according to the actual scale. DETAILED DESCRIPTION

[0065] The technical solution of the present disclosure is further specifically described below through examples and in conjunction with the accompanying drawings. In the specification, the same or similar figure numbers indicate the same or similar parts. The following description of the embodiments of the present disclosure with reference to the accompanying drawings is intended to explain the overall inventive concept of the present disclosure and should not be construed as a limitation of the present disclosure.

[0066] In addition, in the following detailed description, for the purpose of explanation, numerous specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is apparent that one or more embodiments may also be implemented without these specific details.

[0067] It should be understood that, although the terms first, second, etc. can be used here to describe different elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the exemplary embodiment, the first element can be named as the second element, and similarly, the second element can be named as the first element. The term "and / or" as used herein includes any combination and all combinations of one or more related listed items.

[0068] It should be understood that when an element or layer is referred to as being "formed on" another element or layer, the element or layer may be formed directly or indirectly on another element or layer. That is, for example, there may be an intermediate element or intermediate layer. On the contrary, when an element or layer is referred to as being "formed directly on" another element or layer, there is no intermediate element or intermediate layer. Other words used to describe the relationship between elements or layers (e.g., "between" and "directly between", "adjacent" and "directly adjacent", etc.) should be interpreted in a similar manner. In addition, the X-axis, Y-axis and Z-axis are not limited to the three axes of the rectangular coordinate system, and can be interpreted in a broader sense. For example, the X-axis, Y-axis and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purpose of this disclosure, "at least one of X, Y and Z" and "at least one selected from the group consisting of X, Y and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y and Z such as XYZ, XY, XZ and YZ.

[0069] The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the exemplary embodiments. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. It will also be understood that when the terms "comprise" and / or "include" are used herein, the description indicates the presence of the features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0070] In this document, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection or an indirect connection through an intermediate medium.

[0071] Herein, unless otherwise specified, the expression “the same layer” is generally intended to express the following meaning: at least two layers, patterns, elements, components or parts are formed on the same substrate or film layer through the same patterning process.

[0072] Figure 1A A schematic diagram of a planar structure of an array substrate in the related art is shown; Figure 1B A cross-sectional view of an array substrate in the related art is schematically shown, for example, Figure 1B It can be the array substrate along Figure 1A A cross-sectional view taken along line AA'.

[0073] Reference Figure 1A-1BThe array substrate 10 includes a signal wiring 028 and a buffer layer 012 arranged on a base substrate 011, the signal wiring 028 is, for example, a data line; a first interlayer insulating layer 013, an organic insulating layer 014, and a second interlayer insulating layer 015 are sequentially arranged on a side of the buffer layer 012 away from the base substrate 011; an active layer 023 is arranged on a side of the buffer layer 012 away from the base substrate 011; a gate insulating portion 024 and a gate electrode 0251 are sequentially arranged on a side of the active layer 023 away from the base substrate 011; a third metal region 0252 is, for example, a source electrode, a part of the third metal region 0252 is connected to the signal wiring 028 through a via in the buffer layer 012, and the other part is connected to the active layer 023 in a semi-covering manner to expose a part of the active layer 023 to ensure current conduction. However, the exposed portion of the active layer 023 increases the distance between the source and the gate 0251, making it impossible to further reduce the distance between the third metal region 0252 and the gate 0251, and also impossible to further improve the resolution, thereby making it difficult to prepare a high PPI display panel.

[0074] In addition, the array substrate 10 also includes a common electrode 0273 arranged on the side of the organic insulating layer 014 away from the base substrate 011; a pixel electrode 0271 arranged on the side of the second interlayer insulating layer 015 away from the base substrate 011, and the pixel electrode 0271 is directly connected to the conductor area of ​​the active layer 023 through vias in the first interlayer insulating layer 013, the organic insulating layer 014 and the second interlayer insulating layer 015. This contact method will affect the output current of the TFT in subsequent processes, and thus cause driving problems.

[0075] In order to solve at least one aspect of the above problems, embodiments of the present disclosure provide an array substrate and a method for manufacturing the same, and a display device.

[0076] Figure 2A The planar structural diagram of the array substrate according to some exemplary embodiments of the present disclosure is schematically shown. Figure 2B Schematically showing a cross-sectional view of an array substrate according to some exemplary embodiments of the present disclosure, for example, Figure 2B It can be the array substrate along Figure 2A A cross-sectional view taken along line BB'. Figure 2C A cross-sectional view of an array substrate according to some exemplary embodiments of the present disclosure is schematically shown, wherein the structure of the first via hole is specifically shown.

[0077] Reference Figure 2A to Figure 2BThe array substrate 20 includes: a base substrate 11; an active layer 23, located on one side of the base substrate 11; a first metal layer 22, including a first metal region 221; a second metal layer 25, including a gate 251 and a third metal region 252, the second metal layer 25 is located on the side of the first metal layer 22 away from the base substrate 11; a first interlayer insulating layer 13, located on the side of the second metal layer 25 away from the base substrate 11, a first via 29 is provided in the first interlayer insulating layer 13; and an electrode layer 27, located on the side of the first interlayer insulating layer 13 away from the base substrate 11, the electrode layer 27 includes an electrode filling portion 271. Among them, the orthographic projection of the first metal area 221 on the base substrate 11 at least partially overlaps with the orthographic projection of the first via 29 on the base substrate 11, and the orthographic projection of the third metal area 252 on the base substrate 11 at least partially overlaps with the orthographic projection of the first via 29 on the base substrate 11; and the electrode filling portion 271 at least partially fills the first via 29 and connects the first metal area 221 and the third metal area 252.

[0078] In an exemplary embodiment, the substrate 11 may be a rigid substrate (substrate) or a flexible substrate (substrate), including but not limited to glass and polyimide.

[0079] In some embodiments, the active layer 23 includes a first conductor region 231, a second conductor region 232, and a channel region 233 located between the first conductor region 231 and the second conductor region 232. The channel region 233 may include an oxide semiconductor, and the first conductor region 231 and the second conductor region 232 may be prepared by conducting oxide semiconductors. Metal oxide semiconductors used as materials for thin film transistors (TFTs) have the advantage of low power consumption.

[0080] In the embodiment of the present disclosure, the first metal region 221 and the third metal region 252 at different positions are exposed through the first via hole 29 , and the connection of metals at different positions is achieved by using the electrode filling portion 271 .

[0081] According to some exemplary embodiments, an orthographic projection of the first metal region 221 on the base substrate 11 at least partially overlaps with an orthographic projection of the third metal region 252 on the base substrate 11 .

[0082] In the embodiment of the present disclosure, by setting the orthographic projections of the first metal area 221 and the third metal area 252 on the base substrate 11 to at least partially overlap, it is beneficial to save space, improve space utilization, and provide convenience for the preparation of a high PPI display panel.

[0083] According to some exemplary embodiments, the first via 29 includes a first channel 291 and a second channel 292 that are interconnected, the first channel 291 is arranged on a side of the second channel 292 away from the substrate substrate 11, the orthographic projection of the first channel 291 on the substrate substrate 11 covers the orthographic projection of the second channel 292 on the substrate substrate 11, the first channel 291 exposes at least a portion of the surface of the third metal area 252 away from the substrate substrate 11, and the second channel 292 exposes at least a portion of the surface of the first metal area 221 away from the substrate substrate 11 and at least a portion of the side of the third metal area 252 close to the first metal area 221.

[0084] According to some exemplary embodiments, electrode filling portion 271 covers the exposed surface of third metal region 252 away from substrate 11 , the surface of first metal region 221 away from substrate 11 , and the side surface of third metal region 252 close to first metal region 221 .

[0085] Reference Figure 2C The first via hole 29 extends along a third direction perpendicular to the base substrate 11, the first channel 291 exposes the upper surface of the third metal area 252, the second channel 292 exposes the upper surface of the first metal area 221, and the first via hole 29 is filled with the electrode filling portion 271 so that the first metal area 221 is indirectly connected to the third metal area 252. Exemplarily, the third direction intersects with the first direction, for example, in the illustrated example, the first direction is the X direction, the third direction is the Z direction, and the first direction X and the third direction Z are perpendicular to each other.

[0086] In an exemplary embodiment of the present disclosure, the array substrate further includes: a first insulating portion 243, located between the first metal region 221 and the third metal region 252; the orthographic projection of the first insulating portion 243 on the base substrate 11 at least partially overlaps with the orthographic projection of the first metal region 221 on the base substrate 11, and the orthographic projection of the first insulating portion 243 on the base substrate 11 at least partially overlaps with the orthographic projection of the third metal region 252 on the base substrate 11. The first via 29 exposes the side surface of the first insulating portion 243 close to the first metal region 221; the electrode filling portion 271 covers the exposed side surface of the first insulating portion 243 close to the first metal region 221.

[0087] For example, the first insulating portion 243 may be made of SiO x 、SiN x or a composite film layer of the two, the thickness range is The first insulating portion 243 isolates the first metal region 221 from the third metal region 252 to avoid overlapping of the two metal layers.

[0088] Figure 3Cross-sectional views of array substrates according to other exemplary embodiments of the present disclosure are schematically shown. Figure 3 The middle gate insulating portion 24 is a one-layer structure. Figure 2B-2C The middle gate insulating portion 24 has a two-layer structure.

[0089] In an exemplary embodiment of the present disclosure, the array substrate includes a gate insulating portion 24 located between the active layer 23 and the gate electrode 251 , and at least a portion of the gate insulating portion 24 is located in the same layer as the first insulating portion 243 .

[0090] Reference Figure 3 In the array substrate 30, the first insulating portion 243 can be manufactured in the same layer as the single-layer gate insulating portion 24 and include the same material, which is beneficial to simplifying the manufacturing process of the array substrate, reducing production costs, and improving production efficiency.

[0091] In an exemplary embodiment of the present disclosure, referring to Figure 2B The gate insulating portion 24 includes a first gate insulating portion 241 and a second gate insulating portion 242. The thickness of the first gate insulating portion 241 is smaller than the thickness of the second gate insulating portion 242. The second gate insulating portion 242 and the first insulating portion 243 are located in the same layer.

[0092] For example, the thickness of the first gate insulating portion 241 is The thickness of the second gate insulating portion 242 is The thickness of the first gate insulating portion 241 is set to be relatively small, which is beneficial to the preparation of the second gate insulating portion 242. The thickness of the second gate insulating portion 242 is set to be relatively large, which is beneficial to avoiding bright spots and dark spots caused by missing gate insulating layers.

[0093] It should be noted that, in this document, unless otherwise specifically described or limited, the term “thickness” refers to a dimension along a direction perpendicular to the main surface of the base substrate 11 .

[0094] Reference Figure 2B In the array substrate 20, the first gate insulating portion 241 is arranged on the side of the second gate insulating portion 242 close to the base substrate 11, and the first gate insulating portion 241 is in contact with the surface of the channel region 233 away from the base substrate 11; the second gate insulating portion 242 is arranged on the surface of the first gate insulating portion 241 away from the base substrate 11, and is in contact with the first gate insulating portion 241.

[0095] In an exemplary embodiment, the orthographic projection of the first gate insulating portion 241 on the base substrate 11 may overlap with the orthographic projection of the second gate insulating portion 242 on the base substrate 11. In the process of forming the first conductor region 231 and the second conductor region 232 by conductorization, the first gate insulating portion 241 may serve as a shielding layer to protect the channel region 233 and prevent the channel region 233 from being conductorized. The second gate insulating portion 242 and the gate 251 may be formed by a single patterning process, which is conducive to reducing the number of process steps.

[0096] In an exemplary embodiment of the present disclosure, the first metal layer 22 includes a second metal region 222 , which is located on a side of the first conductor region 231 away from the base substrate 11 and connected to a surface of the first conductor region 231 away from the base substrate 11 .

[0097] Exemplarily, the second metal region 222 is a source electrode, which is connected to the surface of the first conductor region 231 of the active layer 23 . The connection has good contact resistance and is conducive to reducing the distance between the source electrode and the gate electrode 25 , thereby realizing a high PPI display panel.

[0098] In an exemplary embodiment of the present disclosure, the second conductor region 232 is simultaneously used as the source / drain and pixel electrode of the thin film transistor, and the electrode layer 27 also includes a common electrode 272 , whose orthographic projection on the base substrate 11 at least partially overlaps with the orthographic projection of the pixel electrode on the base substrate 11 .

[0099] Figure 4A Cross-sectional views of array substrates according to other exemplary embodiments of the present disclosure are schematically shown. Figure 4B The cross-sectional views of array substrates according to some other exemplary embodiments of the present disclosure are schematically shown, wherein the specific structures of the first via hole and the second via hole are schematically shown.

[0100] In an exemplary embodiment of the present disclosure, the array substrate 40 further includes a buffer layer 12 located between the base substrate 11 and the active layer 23, and the buffer layer 12 covers the first metal region 221. For example, the first metal region 221 may be located in the light shielding layer.

[0101] Reference Figure 4A , exemplarily, the first metal region 221 may be a data line, along the second direction Y (in Figure 4AThe first metal region 221 extends in the first direction X, and the orthographic projection of a portion of the first metal region 221 on the substrate 11 overlaps with the orthographic projection of one end of the active layer 23 on the substrate 11 in the first direction X. The third metal region 252 and the gate 251 are located in the same film layer and include the same material, which is conducive to simplifying the manufacturing process of the array substrate. The second conductor region 232 is used as the source / drain and pixel electrode of the thin film transistor at the same time, and at least a portion of the common electrode 272 is arranged opposite to the second conductor region 232.

[0102] In an exemplary embodiment of the present disclosure, a second via 31 is provided in the buffer layer 12, and the second via 31 is interconnected with the first via 29, and the second via 31 exposes at least a portion of the surface of the first metal region 221 away from the substrate 11 and the side of the buffer layer 12 away from the substrate 11.

[0103] Reference Figure 4B The first via hole 29 penetrates the first interlayer insulating layer 13, and the second via hole 31 and the first via hole 29 extend continuously in the third direction Z, exposing the upper surface of the first metal region 221. The third metal region 252, the first conductor region 231 and the first metal region 221 are electrically connected through the electrode filling portion 271, thereby avoiding the problem of current drop caused by direct connection of different metals. By connecting the light shielding layer to the first conductor region 231, a stable voltage is generated on the light shielding layer, thereby effectively improving the working stability of the TFT.

[0104] It should be noted that, although the positions of the first via 29, the first metal area 221 and the third metal area 252 in this embodiment and the connection relationships with other structures are not exactly the same as those of the first via 29, the first metal area 221 and the third metal area 252 in the aforementioned embodiments, in this article, they are all used to describe the lead-out structure and connection structure of the signal line, so they are described using the same expression.

[0105] The embodiments of the present disclosure also provide a display device, and the type of the display device is not limited, and can be a liquid crystal display device (Liquid Crystal Display, LCD for short) or an electroluminescent display device. In the case where the display device is an electroluminescent display device, the electroluminescent display device can be an organic electroluminescent display device (Organic Light-Emitting Diode, OLED for short) or a quantum dot electroluminescent display device (Quantum DotLight Emitting Diodes, QLED for short).

[0106] Figure 5A structural schematic diagram of a display device 100 provided in an embodiment of the present disclosure, wherein the display device 100 includes a device body 50 and an array substrate 20, 30 or 40 disposed on the device body 50, wherein the device body 50 includes a shell and components such as a processor, a power supply, and a camera disposed in the shell, and the display device 100 can adopt the array substrate 20, 30 or 40 provided in the above-mentioned embodiment.

[0107] The display device 100 may include any device or product having a display function. For example, the display device 100 may be a smart phone, a mobile phone, an e-book reader, a desktop computer (PC), a laptop PC, a netbook PC, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital audio player, a mobile medical device, a camera, a wearable device (such as a head-mounted device, an electronic clothing, an electronic bracelet, an electronic necklace, an electronic accessory, an electronic tattoo, or a smart watch), a television, etc.

[0108] It should be understood that the display device 100 according to some exemplary embodiments of the present disclosure has all the features and advantages of the above-mentioned array substrate 20, 30 or 40, and these features and advantages can be referred to the above description of the array substrate 20, 30 or 40, which will not be repeated here.

[0109] Figure 6 The flowchart of the method for preparing an array substrate according to an embodiment of the present disclosure is schematically shown. Figure 7A-7D The cross-sectional view during the preparation of the array substrate according to the embodiment of the present disclosure is schematically shown.

[0110] According to some exemplary embodiments, referring to Figure 2A-2C and Figure 3 The method for preparing the array substrate 20 or 30 includes the following steps S610 to S650.

[0111] In step S610 , an active material layer is formed on the base substrate 11 , and a first patterning process is performed on the active material layer to form an active layer 23 .

[0112] In step S620 , a first metal material layer is formed on the base substrate 11 , and a second patterning process is performed on the first metal material layer to form a first metal layer 22 . The first metal layer 22 at least includes a first metal region 221 .

[0113] In step S630, a second metal material layer is formed on the base substrate 11, and a third patterning process is performed on the second metal material layer to form a second metal layer 25, wherein the second metal layer 25 includes a gate 251 and a third metal region 252, and the second metal layer 25 is located on a side of the first metal layer 22 away from the base substrate 11.

[0114] In step S640, an interlayer insulating material layer is formed on the side of the active layer 23, the first metal layer 22 and the second metal layer 25 away from the base substrate 11, and a fourth patterning process is performed on the interlayer insulating material layer to form a first interlayer insulating layer 13 and a first via 29; wherein the orthographic projection of the first metal region 22 on the base substrate 11 at least partially overlaps with the orthographic projection of the first via 29 on the base substrate 11, and the orthographic projection of the third metal region 25 on the base substrate 11 at least partially overlaps with the orthographic projection of the first via 29 on the base substrate 11.

[0115] In step S650 , an electrode material layer is formed on the interlayer insulating material layer, and a fifth patterning process is performed on the electrode material layer to form an electrode layer 27 . The electrode layer 27 at least partially fills the first via hole 29 and connects the first metal region 22 with the third metal region 25 through the first via hole 29 .

[0116] Before forming the active material layer on the substrate 11, a buffer layer 12 may be deposited on the substrate. The buffer layer 12 is usually made of SiO x or SiN x or a composite film layer of the two, the thickness range is Then, an active material layer is formed on the buffer layer 12. The active material layer is a metal oxide semiconductor material, such as indium gallium zinc oxide (IGZO) or indium zinc tin oxide (ITZO). The thickness range is Metal oxide semiconductors used as materials for thin film transistors have the advantage of low power consumption.

[0117] In step S610 , performing a first patterning process on the active material layer includes two schemes.

[0118] The first solution is to directly perform a first patterning process on the active material layer to form an active layer 23, and then deposit a gate insulating material layer on the active layer 23, such as Fig. 7A shown.

[0119] The second solution is to first deposit a gate insulating material layer on the active material layer, and then form a gate insulating portion 24, a conductive region and a channel region through a halftone mask.

[0120] Specifically, a photoresist film is first formed on the side of the gate insulating material layer away from the base substrate 11; then, the photoresist film is exposed and developed through a half-tone mask template to form a photoresist layer 31. Figure 7BAs shown. The photoresist layer 31 includes a first region 311 and a second region 312 and a third region 313 arranged on opposite sides of the first region 311 along the first direction X. The orthographic projection of the first region 311 on the substrate 11 completely overlaps with the orthographic projection of the first preset channel region 2301 of the active layer 23 on the substrate 11; the orthographic projection of the second region 312 on the substrate 11 completely overlaps with the orthographic projection of the second preset conductor region 2302 of the active layer 23 on the substrate 11; the orthographic projection of the third region 313 on the substrate 11 completely overlaps with the orthographic projection of the third preset conductor region 2303 of the active layer 23 on the substrate 11. The thickness of the first region 311 is greater than the thickness of the second region 312, and the thickness of the first region 311 is greater than the thickness of the third region 313.

[0121] Next, performing a first patterning process includes: etching the photoresist layer 31 and the gate insulating material layer on the substrate substrate 11 on which the aforementioned pattern is formed, so that the gate insulating material layer forms a gate insulating portion 24, the orthographic projection of the gate insulating portion 24 on the substrate substrate 11 completely overlaps with the orthographic projection of the first preset channel region 2301 of the active layer 23 on the substrate substrate 11, and the orthographic projection of the gate insulating portion 24 on the substrate substrate 11 does not overlap with the orthographic projections of the second preset conductor region 2302 and the third preset conductor region 2303 of the active layer 23 on the substrate substrate 11, so that the second preset conductor region 2302 and the third preset conductor region 2303 are exposed, as shown in FIG. Figure 7C shown.

[0122] It should be noted that, since the thickness of the first region 311 of the photoresist layer 31 is greater than the thickness of the second region 312 and the third region 313 of the photoresist layer 31, when the photoresist layer 31 is etched and removed, at least a portion of the gate insulating material layer corresponding to the first region 311 of the photoresist layer 31 is retained to form a gate insulating portion 24; the gate insulating material layer corresponding to the second region 312 and the third region 313 of the photoresist layer 31 is completely etched and removed to expose the second preset conductor region 2302 and the third preset conductor region 2303 of the active layer 23.

[0123] Next, performing the first patterning process further includes: on the substrate 11 formed with the aforementioned pattern, performing a conductorization process on the exposed second predetermined conductor region 2302 and the third predetermined conductor region 2303, such as performing a helium plasma conductorization process, so that the second predetermined conductor region 2302 forms the first conductor region 231, and the third predetermined conductor region 2303 forms the second conductor region 232, as shown in FIG. Fig.7D The channel region 233 , the first conductor region 231 and the second conductor region 232 form an active layer 23 .

[0124] In the method for preparing the array substrate provided in the embodiment of the present disclosure, the gate insulating portion 24 can be used as a shielding layer to protect the channel region 233 of the active layer 23 to avoid the above-mentioned conductor processing step from affecting the channel region 233 and ensure the semiconductor performance of the channel region 233.

[0125] In step S620 , a first metal layer 22 is formed. The first metal layer 22 includes a first metal region 221 and a second metal region 222 . The first metal region 221 is deposited on the buffer layer 12 , and the second metal region 222 is deposited on the surface of the first conductor region 231 of the active layer 23 .

[0126] In step S630, a second metal layer 25 is formed, and the second metal layer 25 includes a gate 251 deposited on the upper surface of the gate insulating portion 24 and a third metal region 252 deposited on the upper surface of the first insulating portion 243, and the orthographic projection of the first metal region 221 on the base substrate 11 at least partially overlaps with the orthographic projection of the third metal region 252 on the base substrate 11.

[0127] In step S640, a first interlayer insulating layer 13 and a first via 29 are formed, and the orthographic projection of the first via 29 on the base substrate 11 at least partially overlaps with the orthographic projection of the first metal area 221 on the base substrate 11, and the orthographic projection of the first via 29 on the base substrate 11 at least partially overlaps with the orthographic projection of the third metal area 252 on the base substrate 11.

[0128] In step S650 , the electrode layer 27 is formed, and the electrode filling portion 271 fills the first via hole 29 so that the first metal region 221 is indirectly connected to the third metal region 252 .

[0129] When the gate insulating portion 24 includes the first gate insulating portion 241 and the second gate insulating portion 242 , the first gate insulating portion 241 and the active layer 23 are formed by a first patterning process using a Half tone mask; the second gate insulating portion 242 is formed by a second patterning process, and the gate 251 is formed by a self-alignment process.

[0130] According to the above preparation process, if the first solution is adopted, it is necessary to prepare the array substrate through 6 patterning processes; if the second solution is adopted, it is only necessary to prepare the array substrate through 5 patterning processes. Compared with the 8-time patterning process in the related technology, the process is more streamlined and the cost advantage is obvious.

[0131] In the structure of the above-mentioned array substrate 20 or 30, the electrode filling part 271 is not connected to the active layer 23, and will not be affected by subsequent processes to cause the problem of decreased TFT output current; the second metal area 222 is directly overlapped with the first conductor area 231 of the active layer 23, and there is no problem of half-overlapping at the via in the related process, which leads to a larger size, and the design requirements of high PPI can be met.

[0132] Figure 8 A flow chart of a method for preparing an array substrate according to another embodiment of the present disclosure is schematically shown. Figure 9A-9C The cross-sectional view during the preparation of the array substrate according to the embodiment of the present disclosure is schematically shown.

[0133] According to some exemplary embodiments, referring to Figure 4A-4B , the method for preparing the array substrate 40 includes the following steps S810 to S850.

[0134] In step S810 , a first metal material layer is formed on the base substrate 11 , and a first patterning process is performed on the first metal material layer to form at least a first metal region 221 .

[0135] In step S820 , a buffer layer 12 , an active material layer, and a gate insulating material layer are sequentially formed on the first metal region, and a second patterning process is performed on the gate insulating material layer to form a gate insulating portion 24 .

[0136] In step S830, a second metal material layer is formed on a side of the gate insulation portion 24 away from the base substrate 11, and a third patterning process is performed on the second metal material layer to form a gate 251 and a third metal region 252, wherein the third metal region 252 is located on a side of the first metal region 221 away from the base substrate 11.

[0137] In step S840, an interlayer insulating material layer is formed on the side of the second metal layer 25 away from the base substrate 11, and a fourth patterning process is performed on the interlayer insulating material layer to form a first via 29; wherein the orthographic projection of the first metal region 221 on the base substrate 11 at least partially overlaps with the orthographic projection of the first via 29 on the base substrate 11, and the orthographic projection of the third metal region 252 on the base substrate 11 at least partially overlaps with the orthographic projection of the first via 29 on the base substrate 11.

[0138] In step S850, an electrode material layer is formed on a side of the interlayer insulating material layer away from the base substrate 11, and a fifth patterning process is performed on the electrode material layer to form an electrode layer 27, wherein the electrode layer 27 includes an electrode filling portion 271, and the electrode filling portion 271 at least partially fills the first via hole 29 and connects the first metal region 221 and the third metal region 252. The first metal region 221 is, for example, a data line.

[0139] Specifically, in step S820, while forming the gate insulating portion 24, the active layer 23 is subjected to a conductor treatment to form a first conductor region 231, a second conductor region 232, and a channel region 233 located between the first conductor region 231 and the second conductor region 232. Fig. 9A shown.

[0140] In step S830, a gate electrode 251 and a third metal region 252 are formed, wherein the second metal material layer is covered on the portion that needs to be connected to the first metal region 221, and a gate electrode pattern of the TFT is formed at the same time. Fig. 9B The gate 251 and the active layer 23 are patterned by a Half tone Mask process. In this step, since the channel region 233 is protected by a gate insulating portion 24, the second metal material layer can be made of Cu or a dry etching type metal (eg, Mo).

[0141] In step S840, an interlayer insulating material layer is formed and a hole is opened at the first metal region 221, and the first metal region 221 and the third metal region 252 are exposed at the opening position. Fig. 9C shown.

[0142] In step S850, the first metal region 221 is connected to the third metal region 252 at the via through the electrode material layer. It should be pointed out that at this time, the electrode filling portion 271 only needs to be connected to the third metal region 252 at the via. Even if the resistance of the active layer 23 in the via is increased due to subsequent processes, it does not affect the resistance of the via, because the third metal region 252 has formed a good electrical connection with the active layer 23 outside the via, and does not affect the output current of the TFT.

[0143] According to the above preparation process, the array substrate 40 only needs to be prepared through 5 patterning processes. Compared with the 8-time patterning process in the related art, the process is more streamlined and has obvious cost advantages.

[0144] As used herein, the terms "substantially," "approximately," "approximately," and other similar terms are used as terms of approximation rather than as terms of degree, and they are intended to account for the inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. Taking into account factors such as process fluctuations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), "approximately" or "approximately" as used herein include the stated value and mean that the particular value is within an acceptable range of deviation as determined by one of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within ±10% or ±5% of the stated value.

[0145] Although some embodiments according to the general inventive concept of the present disclosure have been illustrated and described, it will be appreciated by those skilled in the art that changes may be made to these embodiments without departing from the principles and spirit of the general inventive concept of the present disclosure, the scope of which is defined by the claims and their equivalents.

Claims

1. An array substrate, comprising: substrate substrate; An active layer, located on one side of the substrate; A first metal layer including a first metal region; A second metal layer, comprising a gate and a third metal region, wherein the second metal layer is located on a side of the first metal layer away from the substrate; A first interlayer insulating layer is located on a side of the active layer, the first metal layer, and the second metal layer away from the substrate, wherein a first via hole is provided in the first interlayer insulating layer; and an electrode layer, located on a side of the first interlayer insulating layer away from the base substrate, the electrode layer comprising an electrode filling portion, The orthographic projection of the first metal area on the base substrate at least partially overlaps with the orthographic projection of the first via hole on the base substrate, and the orthographic projection of the third metal area on the base substrate at least partially overlaps with the orthographic projection of the first via hole on the base substrate; as well as The electrode filling portion at least partially fills the first via hole and connects the first metal region and the third metal region.

2. The array substrate according to claim 1, wherein: An orthographic projection of the first metal region on the base substrate at least partially overlaps with an orthographic projection of the third metal region on the base substrate.

3. The array substrate according to claim 1, wherein: The first via includes a first channel and a second channel that are interconnected, the first channel is arranged on a side of the second channel away from the substrate, the orthographic projection of the first channel on the substrate covers the orthographic projection of the second channel on the substrate, the first channel exposes at least a portion of the surface of the third metal area away from the substrate, and the second channel exposes at least a portion of the surface of the first metal area away from the substrate and at least a portion of the side of the third metal area close to the first metal area.

4. The array substrate according to claim 1, wherein: At least a portion of the electrode filling portion covers the exposed surface of the third metal region away from the substrate, the surface of the first metal region away from the substrate, and the side surface of the third metal region close to the first metal region.

5. The array substrate according to claim 1, wherein: The array substrate further includes: A first insulating portion is located between the first metal area and the third metal area; an orthographic projection of the first insulating portion on the substrate at least partially overlaps with an orthographic projection of the first metal area on the substrate, and an orthographic projection of the first insulating portion on the substrate at least partially overlaps with an orthographic projection of the third metal area on the substrate.

6. The array substrate according to claim 5, wherein: The first via hole exposes a side surface of the first insulating portion close to the first metal region; at least a portion of the electrode filling portion covers the exposed side surface of the first insulating portion close to the first metal region.

7. The array substrate according to claim 5, wherein: The array substrate comprises: A gate insulating portion is located between the active layer and the gate, and at least a portion of the gate insulating portion is located in the same layer as the first insulating portion.

8. The array substrate according to claim 7, wherein: The gate insulating portion includes a first gate insulating portion and a second gate insulating portion, and a thickness of the first gate insulating portion is smaller than a thickness of the second gate insulating portion; The second gate insulating portion and the first insulating portion are located in the same layer.

9. The array substrate according to claim 1, wherein: The active layer includes a first conductor region, a second conductor region, and a channel region between the first conductor region and the second conductor region; The first metal layer further includes a second metal region, which is located at a side of the first conductor region away from the base substrate and connected to a surface of the first conductor region away from the base substrate.

10. The array substrate according to claim 9, wherein: The second conductor area is multiplexed as a pixel electrode; The electrode layer further includes a common electrode, and an orthographic projection of the common electrode on the base substrate at least partially overlaps with an orthographic projection of the pixel electrode on the base substrate.

11. The array substrate according to claim 1, wherein: The array substrate further includes: A buffer layer is located between the substrate and the active layer, and the buffer layer covers the first metal region.

12. The array substrate according to claim 11, wherein: The buffer layer is provided with a second via hole, the second via hole is interconnected with the first via hole, and the second via hole exposes at least a portion of the surface of the first metal region away from the substrate and a side surface of the buffer layer away from the substrate.

13. The array substrate according to claim 11, wherein: The first metal area is located in the light shielding layer; The third metal region is located at a side of the first conductor region away from the base substrate and is connected to a surface of the first conductor region away from the base substrate.

14. A display device, characterized in that: The display device comprises the array substrate according to any one of claims 1 to 13.

15. A method for preparing an array substrate, the method comprising the following steps: An active material layer is formed on a substrate, and a first patterning process is performed on the active material layer to form an active layer; Forming a first metal material layer on the base substrate, performing a second patterning process on the first metal material layer to form a first metal layer, wherein the first metal layer includes a first metal region; Forming a second metal material layer on the substrate, performing a third patterning process on the second metal material layer to form a second metal layer, wherein the second metal layer includes a gate and a third metal region, and the second metal layer is located on a side of the first metal layer away from the substrate; An interlayer insulating material layer is formed on a side of the active layer, the first metal layer, and the second metal layer away from the base substrate, and a fourth patterning process is performed on the interlayer insulating material layer to form a first interlayer insulating layer and a first via hole; wherein the orthographic projection of the first metal region on the base substrate at least partially overlaps with the orthographic projection of the first via hole on the base substrate, and the orthographic projection of the third metal region on the base substrate at least partially overlaps with the orthographic projection of the first via hole on the base substrate; An electrode material layer is formed on the interlayer insulating material layer, and a fifth patterning process is performed on the electrode material layer to form an electrode layer, wherein the electrode layer includes an electrode filling portion, and the electrode filling portion at least partially fills the first via hole and connects the first metal area and the third metal area.

16. The method for preparing an array substrate according to claim 15, wherein: Performing a first patterning process on the active material layer includes: A photoresist layer is formed on the gate insulating material layer, and a half-tone mask is used for exposure; Performing development and etching processes to form a gate insulating portion and a first insulating portion, wherein the first insulating portion is located between the first metal region and the third metal region; The ashing treatment and the conductor treatment process are performed to form the active material layer into an active layer, wherein the active layer includes a first conductor region, a second conductor region and a channel region between the first conductor region and the second conductor region.

17. A method for preparing an array substrate, the method comprising the following steps: Forming a first metal material layer on the base substrate, performing a first patterning process on the first metal material layer to form a first metal layer, wherein the first metal layer includes a first metal region; forming a buffer layer and an active material layer in sequence on a side of the first metal layer away from the base substrate, and performing a second patterning process on the active material layer to form an active layer; Forming a second metal material layer on a side of the active layer away from the substrate, performing a third patterning process on the second metal material layer to form a second metal layer, wherein the second metal layer includes a gate and a third metal region, wherein the third metal region is located on a side of the first metal region away from the substrate; An interlayer insulating material layer is formed on a side of the second metal layer away from the base substrate, and a fourth patterning process is performed on the interlayer insulating material layer to form a first via hole; wherein the orthographic projection of the first metal region on the base substrate at least partially overlaps with the orthographic projection of the first via hole on the base substrate, and the orthographic projection of the third metal region on the base substrate at least partially overlaps with the orthographic projection of the first via hole on the base substrate; An electrode material layer is formed on a side of the interlayer insulating material layer away from the base substrate, and a fifth patterning process is performed on the electrode material layer to form an electrode layer, wherein the electrode layer includes an electrode filling portion, and the electrode filling portion at least partially fills the first via hole and connects the first metal area with the third metal area.

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