Display device

Abstract

Provided is a display device including: a substrate including a first cell region, a second cell region, and an intermediate region between the first cell region and the second cell region; an organic insulating layer disposed on the substrate; an emission element layer disposed on the organic insulating layer, the emission element layer including a first emission element overlapping the first cell region and a second emission element overlapping the second cell region; and an encapsulation layer disposed on the emission element layer, in which the emission element layer and the encapsulation layer define a valley portion overlapping the intermediate region and exposing an upper surface of the organic insulating layer.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2023-0134326, filed on October 10, 2023, and all rights arising therefrom, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] One or more embodiments relate to a display device. Background Art

[0003] With the advancement of display devices for visually displaying electrical signals, various display devices having excellent characteristics such as thinness, light weight, and low power consumption have been introduced. For example, flexible display devices that can be folded or rolled into a roll have been introduced. Recently, research and development of display devices of various structures such as stretchable display devices that can be deformed into various shapes have been actively conducted. Summary of the invention

[0004] One or more embodiments include a display device, such as a flexible display device.

[0005] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the disclosed embodiments.

[0006] According to one or more embodiments, a display device includes: a substrate including a first unit region, a second unit region, and an intermediate region between the first unit region and the second unit region; an organic insulating layer disposed on the substrate; an emission element layer disposed on the organic insulating layer, the emission element layer including a first emission element overlapping the first unit region and a second emission element overlapping the second unit region; and an encapsulation layer disposed on the emission element layer, wherein the emission element layer and the encapsulation layer define a valley overlapping the intermediate region and exposing an upper surface of the organic insulating layer.

[0007] Each of the first emission element and the second emission element may include a pixel electrode, a counter electrode, and an emission layer arranged between the pixel electrode and the counter electrode, and the emission element layer may further include: an inorganic dam layer, which is disposed on the organic insulating layer and defines a pixel opening that exposes a portion of the pixel electrode; and a metal dam layer, which is disposed on the inorganic dam layer and includes a first metal layer and a second metal layer disposed on the first metal layer, the first metal layer may define a first dam opening that overlaps with the pixel opening, and the second metal layer may define a second dam opening that overlaps with the pixel opening.

[0008] The width of the first dam opening may be greater than the width of the second dam opening.

[0009] The inorganic bank barrier layer and the metal bank barrier layer may be arranged to be separated from the middle region.

[0010] The encapsulation layer may cover a side surface of the metal bank layer facing the middle region.

[0011] The display device may further include: a cover layer between the encapsulation layer and a side surface of the metal bank layer facing the middle region.

[0012] The display device may further include: a voltage line disposed under the organic insulating layer and configured to transmit a common power supply voltage, wherein the metal bank layer is electrically connected to the voltage line through one or more contact holes defined in the inorganic bank layer and the organic insulating layer.

[0013] The one or more contact holes may include a plurality of contact holes, wherein a first contact hole of the plurality of contact holes is located in the first cell region, and a second contact hole of the plurality of contact holes is located in the second cell region.

[0014] The counter electrode may directly contact a side surface of the first metal layer facing a center of the pixel opening.

[0015] The encapsulation layer may include: a first inorganic encapsulation layer overlapping the first unit region; a second inorganic encapsulation layer overlapping the second unit region; a third inorganic encapsulation layer disposed on the first inorganic encapsulation layer; and a fourth inorganic encapsulation layer disposed on the second inorganic encapsulation layer.

[0016] The encapsulation layer may further include: a first organic encapsulation layer disposed between the first inorganic encapsulation layer and the third inorganic encapsulation layer; and a second organic encapsulation layer disposed between the second inorganic encapsulation layer and the fourth inorganic encapsulation layer.

[0017] The emission element layer may further include a third emission element overlapping with the first unit area and arranged separately from the first emission element, the encapsulation layer may further include a third organic encapsulation layer between the first inorganic encapsulation layer and the third inorganic encapsulation layer, the first organic encapsulation layer may be arranged so that the first organic encapsulation layer overlaps with the first emission element, and the third organic encapsulation layer may overlap with the third emission element and may be arranged separately from the first organic encapsulation layer.

[0018] The emission element layer may further include a third emission element overlapping the first unit region and arranged apart from the first emission element, and the first organic encapsulation layer may be arranged such that the first organic encapsulation layer overlaps the first emission element and the third emission element.

[0019] The second inorganic encapsulating layer and the fourth inorganic encapsulating layer may be arranged to be spaced apart from each other with the intermediate region between the second inorganic encapsulating layer and the fourth inorganic encapsulating layer.

[0020] The second inorganic encapsulating layer and the fourth inorganic encapsulating layer may constitute side surfaces of the valley portion.

[0021] The display device may further include: an inorganic insulating layer between the substrate and the organic insulating layer, wherein the inorganic insulating layer defines a first opening overlapping the middle region.

[0022] The substrate may include at least one base layer and at least one barrier layer, and the at least one barrier layer may define a second opening overlapping the first opening.

[0023] The center of the first opening and the center of the valley may be offset from each other.

[0024] The display device may further include: a filler layer filling the first opening, wherein a modulus of the filler layer is about 3 MPa to about 20 MPa.

[0025] The substrate may define a recessed portion overlapping the first opening and recessed in a thickness direction, and the filler layer may fill the recessed portion.

[0026] The display device may further include: a bridge line disposed on the inorganic insulating layer and the filler layer and spanning the first opening.

[0027] The bridging line may have an arched shape.

[0028] An upper surface of the packing layer may have unevenness, and the bridging line may have a shape corresponding to the shape of the upper surface of the packing layer.

[0029] The bridging line may include: a first bridging line having a concave shape in a thickness direction; and a second bridging line disposed on the first bridging line and having an arch shape.

[0030] The display device may further include: a planarization layer, which is arranged on the encapsulation layer; and a touch sensor layer, which is arranged on the planarization layer, the touch sensor layer including a first touch electrode, a second touch electrode, a first touch insulating layer between the planarization layer and the first touch electrode, and a second touch insulating layer between the first touch electrode and the second touch electrode, wherein, in a plan view, a shape of the first touch insulating layer corresponds to a shape of the first touch electrode.

[0031]

[0013] Other aspects, features, and advantages in addition to those described herein will become apparent from the following drawings, claims, and detailed description of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0033] Figure 1 is a perspective view schematically illustrating a display device according to an embodiment;

[0034] Figure 2A and Figure 2B The diagram is stretched in the first direction. Figure 1 A perspective view of a display device in FIG.

[0035] Figure 2C The diagram is stretched in the second direction. Figure 1 A perspective view of a display device in FIG.

[0036] Figure 2D is a diagram showing the stretched in the first direction and the second direction Figure 1 A perspective view of a display device in FIG.

[0037] Figure 2E The diagram is stretched in the third direction. Figure 1 A perspective view of a display device in FIG.

[0038] Figure 3 is a plan view schematically illustrating a display device according to an embodiment;

[0039] FIG. 4A to FIG. 4C is an equivalent circuit diagram of a sub-pixel of a display device according to an embodiment;

[0040] Figure 5 is a cross-sectional view schematically illustrating a display device according to an embodiment;

[0041] FIG. 6A to FIG. 6C is a cross-sectional view schematically illustrating a display device according to one or more embodiments;

[0042] 7A to 7H is a cross-sectional view schematically illustrating some operations of a process of manufacturing a display device according to an embodiment;

[0043] FIG. 8A to FIG. 8C is a cross-sectional view schematically illustrating some operations of a process of manufacturing a display device according to an embodiment;

[0044] 9A to 9C is a cross-sectional view schematically illustrating some operations of a process of manufacturing a display device according to an embodiment;

[0045] Fig.10 is a cross-sectional view schematically illustrating a display device according to an embodiment;

[0046] FIG. 11A to FIG. 11B is a plan view schematically illustrating a pixel arrangement of a display device according to an embodiment;

[0047] Fig.12 is a cross-sectional view schematically illustrating a display device according to an embodiment;

[0048] FIG. 13A to FIG. 13C is a diagram illustrating elongation of each region of a substrate, an inorganic insulating film, and a wire when an inorganic insulating film is integrally formed on the entire surface of a substrate;

[0049] FIG. 14A to FIG. 14C is a diagram illustrating the elongation of each region of the substrate, the inorganic insulating film, and the wire when the inorganic insulating film is divided with the divided region therebetween;

[0050] Fig.15 is a cross-sectional view schematically illustrating a display device according to an embodiment;

[0051] FIG. 16A to FIG. 16F is a cross-sectional view schematically illustrating a bridge line included in a display device according to one or more embodiments;

[0052] Fig.17 is a graph illustrating a segmentation width strain rate according to a width of a segmentation region;

[0053] Fig.18 is a graph illustrating the elongation of the inorganic insulating layer and the elongation of the bridge line according to the modulus of the filler layer;

[0054] Fig.19 is a cross-sectional view schematically illustrating a display device according to an embodiment; and

[0055] FIG. 20A to FIG. 20G is a perspective view schematically illustrating one or more embodiments of an electronic device including a display device according to the embodiments. DETAILED DESCRIPTION

[0056] Now will be referred to in detail the embodiment of its example illustrated in the accompanying drawings, wherein the same reference numerals refer to the same elements from beginning to end. In this regard, the current embodiment can have different forms and should not be construed as being limited to the description set forth in this article. Accordingly, embodiments are described herein only by reference to the various figures to illustrate the various aspects of the current description. As used in this article, the term "and / or" includes any and all combinations of one or more of the associated listed items. Throughout this disclosure, the statement "at least one of a, b and c" represents only a, only b, only c, both a and b, both a and c, both b and c, all of a, b and c or its variants.

[0057] Since the present disclosure allows various changes and numerous embodiments, specific embodiments will be illustrated in the drawings and described in detail in the written description. Hereinafter, the effects and features of the present disclosure and methods for achieving them will be more fully described with reference to the drawings in which embodiments of the present disclosure are illustrated. However, the present disclosure can be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein.

[0058] Herein, one or more embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. The same or corresponding components are given the same reference numerals regardless of the figure numbers, and redundant descriptions thereof are omitted.

[0059] In the present disclosure, terms such as "first" and "second" are used herein only to describe various elements, but the elements are not limited by these terms. Such terms are for the purpose of distinguishing one element from another element.

[0060] In the present disclosure, an expression used in the singular includes an expression in the plural unless it has an apparently different meaning in the context.

[0061] In the present disclosure, terms such as “include” or “comprising” may be interpreted as indicating a certain characteristic or element or a combination thereof, but may not be interpreted as excluding the possibility of the existence or addition of one or more other characteristics, elements or a combination thereof.

[0062] It will be understood that when a layer, region or element is referred to as being formed “on” another layer, region or element, it can be directly or indirectly formed on the other layer, region or element. That is, for example, intervening layers, regions or elements may be present.

[0063] It will be understood that when a layer, region, or element is referred to as being “connected” to another layer, region, or element, it may be “directly connected” to the other layer, region, or element and / or may be “indirectly connected” to the other layer, region, or element with other layers, regions, or elements therebetween. For example, it will be understood that when a layer, region, or element is referred to as being “electrically connected” to another layer, region, or element, it may be “directly electrically connected” to the other layer, region, or element and / or may be “indirectly electrically connected” to the other layer, region, or element with other layers, regions, or elements therebetween.

[0064] In the present disclosure, "A and / or B" may include "A", "B" or "A and B". In addition, in the present disclosure, "at least one of A and B" may include "A", "B" or "A and B".

[0065] In the present disclosure, the x-axis, y-axis, and z-axis are not limited to the three axes of the rectangular coordinate system, and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other.

[0066] In the present disclosure, when a certain embodiment can be implemented differently, a specific process order can be performed differently from the described order. For example, two processes described successively can be performed substantially simultaneously or in an order opposite to the described order.

[0067] For the convenience of explanation, the size of the elements in the drawings may be exaggerated or reduced. In other words, since the size and thickness of the components in the drawings are arbitrarily illustrated for the convenience of explanation, the following embodiments are not limited thereto.

[0068] The terms "about" or "approximately" as used herein include the stated value and include an appropriate range of deviations for that particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of a particular quantity. For example, the term "about" can mean within one or more standard deviations, or within ±30%, 20%, 10%, 5% of the stated value.

[0069] As used herein, the term "substantially" means approximately or virtually. As used herein, the term "substantially equal" means approximately or virtually equal (e.g., within a threshold percentage of being equal). As used herein, the term "substantially the same" means approximately or virtually the same (e.g., within a threshold difference).

[0070] Embodiments of the present disclosure support one or more processes (methods, flow charts) that support the features and embodiments described herein. Descriptions of elements "may be provided," "may be formed," "may be deposited," and "may be formed," etc. include processes (methods, flow charts) and techniques for providing, forming, placing, modifying, and constructing the elements according to the example aspects described herein.

[0071] Figure 1 is a perspective view schematically illustrating a display device 1 according to the embodiment. Figure 2A and Figure 2B The diagram is stretched in the first direction. Figure 1 A perspective view of the display device 1 in FIG. Figure 2C The diagram is stretched in the second direction. Figure 1 A perspective view of the display device 1 in FIG. Figure 2D is a diagram showing the stretched in the first direction and the second direction Figure 1 A perspective view of the display device 1 in FIG. Figure 2E The diagram is stretched in the third direction. Figure 1 A perspective view of the display device 1 in FIG.

[0072] refer to Figure 1 , the display device 1 may include a display area DA and a non-display area NDA. The display area DA may include a plurality of pixels. The display device 1 may provide a specific image by using light emitted from a plurality of pixels. The non-display area NDA may be arranged outside the display area DA. The non-display area NDA is an area in which no pixels are arranged, and may completely surround the display area DA.

[0073] The display device 1 may be stretched or compressed in various directions. The display device 1 may be stretched in a first direction (eg, x direction and / or -x direction) by an external force applied by an external object or a user. Figure 2A and Figure 2B As shown in FIG. 1 , the display area DA and / or the non-display area NDA of the display device 1 may be stretched in a first direction (eg, the x direction and / or the −x direction). Figure 2A As shown in FIG. 1 , the display device 1 can be stretched in the x direction and the −x direction, or as Figure 2B As illustrated in , the display device 1 can be stretched in the x-direction while one side of the display device 1 is fixed.

[0074] The display device 1 may be stretched in the second direction (eg, the y direction and / or the −y direction) by an external force applied by an external object or a user. Figure 2C As shown in FIG. 1 , the display area DA and / or the non-display area NDA of the display device 1 may be stretched in the y direction and the −y direction. In another embodiment, the display device 1 may be stretched in the y direction or the −y direction while one side of the display device 1 is fixed.

[0075] The display device 1 can be stretched in multiple directions (for example, in a first direction (for example, the x direction and / or the −x direction) and in a second direction (for example, the y direction and / or the −y direction)) by an external force applied by an external object or a body part of a user. Figure 2D As illustrated in FIG. 1 , the display area DA and / or the non-display area NDA of the display device 1 may be stretched in the ±x direction and the ±y direction.

[0076] The display device 1 may be stretched in a third direction (eg, z direction or -z direction) by an external force applied by an external object or a body part of a user. Figure 2E The diagram shows a portion of the display device 1, for example, a portion of the display area DA protruding in the z direction. In another embodiment, a portion of the display device 1 (for example, a portion of the display area DA) may protrude in the -z direction (or be recessed in the z direction).

[0077] exist FIG. 2A to FIG. 2E In the embodiment, the display device 1 is stretched in the first direction, in the second direction, and / or in the third direction. However, one or more embodiments are not limited thereto. In another embodiment, the display device 1 may be deformed into various irregular shapes such as being bent or twisted along two or more axes.

[0078] Figure 3 is a plan view schematically illustrating a display device 1 according to the embodiment.

[0079] A plurality of pixels may be arranged in a display area DA of the display device 1. Each of the pixels may include sub-pixels that emit light of different colors from each other. Emission elements corresponding to the respective sub-pixels may be arranged in the display area DA. A circuit for providing electrical signals to the emission elements arranged in the display area DA and transistors electrically connected to the emission elements may be located in a non-display area NDA around the display area DA. The gate drive circuit GDC may be arranged in each of a first non-display area NDA1 and a second non-display area NDA2, the first non-display area NDA1 and the second non-display area NDA2 being arranged at opposite sides and the display area DA between the first non-display area NDA1 and the second non-display area NDA2.

[0080] The gate driving circuit GDC may include a driver for providing an electrical signal to a gate electrode of a transistor electrically connected to the emission element. Figure 3 In the embodiment, the gate driving circuit GDC is arranged in each of the first non-display area NDA1 and the second non-display area NDA2. However, one or more embodiments are not limited thereto. In another embodiment, the gate driving circuit GDC may be arranged in one of the first non-display area NDA1 and the second non-display area NDA2.

[0081] The data driving circuit DDC may be disposed in the third non-display area NDA3 and / or the fourth non-display area NDA4 connecting the first non-display area NDA1 and the second non-display area NDA2 to each other. Figure 3 It is illustrated that the data driving circuit DDC is arranged in the fourth non-display area NDA4. In another embodiment, the data driving circuit DDC may be arranged in each of the third non-display area NDA3 and the fourth non-display area NDA4.

[0082] exist Figure 3 In the embodiment, the data driving circuit DDC is arranged in the fourth non-display area NDA4 of the display device 1. However, one or more embodiments are not limited thereto. In another embodiment, the display device 1 may further include a flexible circuit board (not shown) electrically connected through a terminal unit (not shown) arranged in the fourth non-display area NDA4, and the display device 1 may be provided on the flexible circuit board described herein.

[0083] In some embodiments, the elongation of the non-display area NDA may be less than or equal to the elongation of the display area DA. In an embodiment, the elongation of the non-display area NDA may be different for each area. For example, the first non-display area NDA1, the second non-display area NDA2, and the third non-display area NDA3 may have substantially the same elongation as each other, but the elongation of the fourth non-display area NDA4 may be less than the elongation of each of the first non-display area NDA1, the second non-display area NDA2, and the third non-display area NDA3.

[0084] FIG. 4A to FIG. 4C is an equivalent circuit diagram of a sub-pixel of a display device according to an embodiment.

[0085] refer to Figure 4A , the emission element ED corresponding to the sub-pixel may be electrically connected to the pixel driving circuit unit PC, and the pixel driving circuit unit PC may include a first transistor T1, a second transistor T2, and a storage capacitor Cst. The pixel driving circuit unit PC may be electrically connected to a signal line and a voltage line. The signal line may include a gate line and a data line DL such as a first scan line SL1, and the voltage line may include a first voltage line (driving power supply voltage) VDDL.

[0086] The second transistor T2 may be electrically connected to the first scan line SL1 and the data line DL. The first scan line SL1 may provide the first scan signal GW1 to the gate electrode of the second transistor T2. The second transistor T2 may transfer the data signal Dm received via the data line DL to the first transistor T1 according to the first scan signal GW1 received via the first scan line SL1.

[0087] The storage capacitor Cst may be electrically connected to the second transistor T2 and the first voltage line VDDL, and may store a voltage corresponding to a voltage difference between a voltage received from the second transistor T2 and a first power supply voltage VDD supplied through the first voltage line VDDL.

[0088] The first transistor T1 is a driving transistor and can control a driving current flowing through the emission element ED. The first transistor T1 can be connected to a first voltage line VDDL and a storage capacitor Cst. The first transistor T1 can control a driving current flowing through the emission element ED from the first voltage line VDDL to correspond to a voltage value stored in the storage capacitor Cst. The emission element ED can emit light with a specific brightness according to the driving current. A first electrode (pixel electrode) of the emission element ED can be electrically connected to the first transistor T1, and a second electrode (common electrode) can be electrically connected to a second voltage line VSSL configured to supply a second power supply voltage (common power supply voltage) VSS.

[0089] exist Figure 4A In the embodiment, the pixel driving circuit unit PC includes two transistors and one storage capacitor. However, in another embodiment, the pixel driving circuit unit PC may include three or more transistors.

[0090] refer to Figure 4B , the pixel driving circuit unit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and a storage capacitor Cst.

[0091] The pixel driving circuit unit PC may be electrically connected to a signal line and a voltage line. The signal line may include a gate line such as a first scan line SL1, a second scan line SL2, a third scan line SL3, and an emission control line EML, and a data line DL. The voltage line may include a first initialization voltage line VIL1 and a second initialization voltage line VIL2 and a first voltage line VDDL.

[0092] The first voltage line VDDL may be configured to transmit the first power supply voltage VDD to the first transistor T1. The first initialization voltage line VIL1 may be configured to transmit the first initialization voltage Vint for initializing the first transistor T1 to the pixel driving circuit unit PC. The second initialization voltage line VIL2 may be configured to transmit the second initialization voltage Vaint for initializing the first electrode of the emission element ED to the pixel driving circuit unit PC.

[0093] The first transistor T1 may be electrically connected to the first voltage line VDDL via the fifth transistor T5 and may be electrically connected to the emission element ED via the sixth transistor T6. The first transistor T1 may function as a driving transistor and may receive the data signal Dm and supply a driving current to the emission element ED according to a switching operation of the second transistor T2.

[0094] The second transistor T2 as a data write transistor may be electrically connected to the first scan line SL1 and the data line DL. The second transistor T2 may be electrically connected to the first voltage line VDDL via the fifth transistor T5. The second transistor T2 may be turned on according to the first scan signal GW received via the first scan line SL1, and may perform a switching operation for transmitting the data signal Dm transmitted via the data line DL to the first node N1.

[0095] The third transistor T3 may be electrically connected to the first scan line SL1 and may be electrically connected to the emission element ED via the sixth transistor T6. The third transistor T3 may be turned on according to the first scan signal GW received via the first scan line SL1 to diode-connect the first transistor T1.

[0096] The fourth transistor T4 as the first initialization transistor may be electrically connected to the third scan line SL3 and the first initialization voltage line VIL1. The fourth transistor T4 may be turned on according to the third scan signal GI received via the third scan line SL3, and the fourth transistor T4 may transmit the first initialization voltage Vint from the first initialization voltage line VIL1 to the gate electrode of the first transistor T1 so as to initialize the voltage of the gate electrode of the first transistor T1. The third scan signal GI may correspond to the first scan signal of another pixel driving circuit unit arranged in a previous row of the pixel driving circuit unit PC.

[0097] The fifth transistor T5 may be an operation control transistor, and the sixth transistor T6 may be an emission control transistor. The fifth transistor T5 and the sixth transistor T6 may be electrically connected to an emission control line EML, and may be simultaneously turned on according to an emission control signal EM received via the emission control line EML to form a current path so that a driving current can flow from the first voltage line VDDL in a direction toward the emission element ED.

[0098] The seventh transistor T7 as the second initialization transistor may be electrically connected to the second scan line SL2, the second initialization voltage line VIL2, and the sixth transistor T6. The seventh transistor T7 may be turned on according to the second scan signal GB received via the second scan line SL2, and may transmit the second initialization voltage Vaint from the second initialization voltage line VIL2 to the first electrode of the emission element ED to initialize the first electrode of the emission element ED.

[0099] The storage capacitor Cst may include a first capacitor electrode CE1 and a second capacitor electrode CE2. The first capacitor electrode CE1 may be electrically connected to the gate electrode of the first transistor T1, and the second capacitor electrode CE2 may be electrically connected to the first voltage line VDDL. The storage capacitor Cst may store and maintain a voltage corresponding to a voltage difference between the first voltage line VDDL and the opposite ends of the gate electrode of the first transistor T1, thereby maintaining a voltage applied to the gate electrode of the first transistor T1.

[0100] refer to Figure 4C The pixel driving circuit unit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a storage capacitor Cst and an auxiliary capacitor Ca.

[0101] The pixel driving circuit unit PC may be electrically connected to a signal line and a voltage line. The signal line may include a gate line such as a first scan line SL1, a second scan line SL2, a third scan line SL3, and an emission control line EML, and a data line DL. The voltage line may include a first initialization voltage line VIL1 and a second initialization voltage line VIL2, a maintenance voltage line VSL, and a first voltage line VDDL.

[0102] The first voltage line VDDL may be configured to transmit the first power supply voltage VDD to the first transistor T1. The first initialization voltage line VIL1 may be configured to transmit the first initialization voltage Vint for initializing the first transistor T1 to the pixel driving circuit unit PC. The second initialization voltage line VIL2 may be configured to transmit the second initialization voltage Vaint for initializing the first electrode of the emission element ED to the pixel driving circuit unit PC. In the initialization period and the data writing period, the hold voltage line VSL may provide the hold voltage VSUS to the second node N2 (e.g., the second capacitor electrode CE2 of the storage capacitor Cst).

[0103] The first transistor T1 may be electrically connected to the first voltage line VDDL via the fifth transistor T5 and the eighth transistor T8, and may be electrically connected to the emission element ED via the sixth transistor T6. The first transistor T1 may function as a driving transistor, and may receive the data signal Dm and supply a driving current to the emission element ED according to a switching operation of the second transistor T2.

[0104] The second transistor T2 may be electrically connected to the first scan line SL1 and the data line DL, and may be electrically connected to the first voltage line VDDL via the fifth transistor T5 and the eighth transistor T8. The second transistor T2 may be turned on according to the first scan signal GW received via the first scan line SL1, and may perform a switching operation for transmitting the data signal Dm transmitted via the data line DL to the first node N1.

[0105] The third transistor T3 may be electrically connected to the first scan line SL1 and may be electrically connected to the emission element ED via the sixth transistor T6. The third transistor T3 may be turned on according to the first scan signal GW received via the first scan line SL1 to diode-connect the first transistor T1, thereby compensating for a threshold voltage of the first transistor T1.

[0106] The fourth transistor T4 may be electrically connected to the third scan line SL3 and the first initialization voltage line VIL1, and the fourth transistor T4 may be turned on according to the third scan signal GI received via the third scan line SL3 to transfer the first initialization voltage Vint from the first initialization voltage line VIL1 to the gate electrode of the first transistor T1 so as to initialize the voltage of the gate electrode of the first transistor T1. The third scan signal GI may correspond to the first scan signal of another pixel driving circuit unit arranged in a previous row of the pixel driving circuit unit PC.

[0107] The fifth transistor T5, the sixth transistor T6 and the eighth transistor T8 can be electrically connected to the emission control line EML and can be simultaneously turned on according to the emission control signal EM received via the emission control line EML to form a current path so that the driving current can flow from the first voltage line VDDL in a direction toward the emission element ED.

[0108] The seventh transistor T7 as the second initialization transistor may be electrically connected to the second scan line SL2, the second initialization voltage line VIL2, and the sixth transistor T6. The seventh transistor T7 may be turned on according to the second scan signal GB received via the second scan line SL2, and may transmit the second initialization voltage Vaint from the second initialization voltage line VIL2 to the first electrode of the emission element ED to initialize the first electrode of the emission element ED.

[0109] The ninth transistor T9 may be electrically connected to the second scan line SL2 and the second capacitor electrode CE2 of the storage capacitor Cst and the holding voltage line VSL. The ninth transistor T9 may be turned on according to the second scan signal GB received via the second scan line SL2, and may transmit the holding voltage VSUS to the second node N2 (e.g., the second capacitor electrode CE2 of the storage capacitor Cst) in the initialization period and the data writing period.

[0110] Each of the eighth transistor T8 and the ninth transistor T9 may be electrically connected to the second node N2 (e.g., the second capacitor electrode CE2 of the storage capacitor Cst). In some embodiments, in the initialization period and the data writing period, the eighth transistor T8 may be turned off and the ninth transistor T9 may be turned on, and in the light emitting period, the eighth transistor T8 may be turned on and the ninth transistor T9 may be turned off. In the initialization period and the data writing period, the second node N2 receives the hold voltage VSUS, and therefore, the brightness uniformity (e.g., long range uniformity (LRU)) of the display device according to the voltage drop of the first voltage line VDDL may be improved.

[0111] The storage capacitor Cst may include a first capacitor electrode CE1 and a second capacitor electrode CE2. The first capacitor electrode CE1 may be electrically connected to a gate electrode of the first transistor T1, and the second capacitor electrode CE2 may be electrically connected to the eighth transistor T8 and the ninth transistor T9.

[0112] The auxiliary capacitor Ca may be electrically connected to the sixth transistor T6, the holding voltage line VSL, and the first electrode of the emission element ED. When the seventh transistor T7 and the ninth transistor T9 are turned on, the auxiliary capacitor Ca may store and hold a voltage corresponding to a voltage difference between the first electrode of the emission element ED and the holding voltage line VSL, thereby preventing the black brightness from increasing when the sixth transistor T6 is turned off.

[0113] Figure 5 is a cross-sectional view schematically illustrating a display device 1 according to the embodiment.

[0114] refer to Figure 5 The display device 1 according to the embodiment may include a substrate 100, first and second pixel circuits PC1 and PC2 disposed on the substrate 100, a first emission element ED1 electrically connected to the first pixel circuit PC1, and a second emission element ED2 electrically connected to the second pixel circuit PC2.

[0115] The display device 1 may include a first unit area UA1 in which the first emission element ED1 is arranged, a second unit area UA2 in which the second emission element ED2 is arranged, and an intermediate area MA located between the first unit area UA1 and the second unit area UA2. The intermediate area MA may be defined as an area that does not overlap with the emission element layer EDL and the encapsulation layer 500 described herein. Alternatively, the intermediate area MA may be defined as an area overlapping with the valley V. The first unit area UA1, the second unit area UA2, and the intermediate area MA may be included in the display area DA (see Figure 3 )middle.

[0116] Since the elements constituting the display device 1 are disposed on the substrate 100, the substrate 100 may include an area corresponding to the first unit area UA1, an area corresponding to the second unit area UA2, and an area corresponding to the middle area MA. In one or more embodiments, the description that the substrate 100 includes the first unit area UA1 in which the first emission element ED1 is arranged, the second unit area UA2 in which the second emission element ED2 is arranged, and the middle area MA located between the first unit area UA1 and the second unit area UA2 means that the substrate 100 includes an area corresponding to the first unit area UA1, an area corresponding to the second unit area UA2, and an area corresponding to the middle area MA.

[0117] The substrate 100 may include an insulating material such as glass, quartz or a polymer resin. The polymer resin may include, for example, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose acetate propionate or any mixture thereof.

[0118] In some embodiments, the substrate 100 may be provided such that barrier layers that are inorganic material layers and base layers that are organic material layers are alternately arranged with each other. Figure 5 In the embodiment, the substrate 100 includes a first base layer 101, a first barrier layer 103, and a second base layer 105. However, one or more embodiments are not limited thereto. Figure 5 Although not illustrated in FIG. 1 , the display device 1 may include a second barrier layer disposed between the substrate 100 and the buffer layer 201 .

[0119] The first base layer 101 and the second base layer 105 may include an inorganic material such as a polymer resin. The first barrier layer 103 may prevent or minimize impurities from penetrating from under the substrate 100. The first barrier layer 103 may include an inorganic material such as an oxide or a nitride, and may have a single layer or a multilayer structure. In some embodiments, the first barrier layer 103 may include silicon oxide, silicon nitride, and / or silicon oxynitride.

[0120] The buffer layer 201 may be disposed on the substrate 100. The buffer layer 201 may prevent or reduce impurities from penetrating from the substrate 100, and the buffer layer 201 may provide a flat surface for the first pixel circuit PC1 and the second pixel circuit PC2 disposed on the buffer layer 201. The buffer layer 201 may include an inorganic material such as an oxide or a nitride, and may have a single-layer or multi-layer structure. In some embodiments, the buffer layer 201 may include silicon oxide, silicon nitride, and / or silicon oxynitride.

[0121] The first pixel circuit PC1 and the second pixel circuit PC2 may be disposed on the buffer layer 201. Each of the first pixel circuit PC1 and the second pixel circuit PC2 may include a first thin film transistor TFT1, a second thin film transistor TFT2, and a storage capacitor Cst. The first thin film transistor TFT1 may include a first semiconductor layer A1, a first gate electrode G1, a first source electrode S1, and a first drain electrode D1. The second thin film transistor TFT2 may include a second semiconductor layer A2, a second gate electrode G2, a second source electrode S2, and a second drain electrode D2. The storage capacitor Cst may include a first capacitor electrode CE1 and a second capacitor electrode CE2. The first pixel circuit PC1 and the second pixel circuit PC2 may be similar to each other, or may have substantially the same configuration as each other.

[0122] The first semiconductor layer A1 of the first thin film transistor TFT1 may be disposed on the buffer layer 201. The first semiconductor layer A1 may include a channel region and impurity regions disposed at opposite sides of the channel region. One of the impurity regions disposed at opposite sides of the channel region may be a source region, and the other of the impurity regions may be a drain region.

[0123] The first semiconductor layer A1 may include a silicon-based semiconductor material such as polysilicon. In some embodiments, the first semiconductor layer A1 may include amorphous silicon.

[0124] The first gate insulating layer 203 may be disposed on the first semiconductor layer A1. The first gate electrode G1 may be disposed on the first gate insulating layer 203. The first gate electrode G1 may be arranged so that the first gate electrode G1 overlaps with the channel region of the first semiconductor layer A1. The first gate electrode G1 may include a conductive material such as molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), and may have a single-layer or multi-layer structure.

[0125] The second gate insulating layer 205 may be disposed on the first gate electrode G1. The second capacitor electrode CE2 may be disposed on the second gate insulating layer 205. The second capacitor electrode CE2 may be arranged so that the second capacitor electrode CE2 overlaps the first gate electrode G1. The first gate electrode G1 may be integrally provided as a single body with the first capacitor electrode CE1 of the storage capacitor Cst. The first capacitor electrode CE1 and the second capacitor electrode CE2 may constitute the storage capacitor Cst. The second capacitor electrode CE2 may include a conductive material such as Mo, Al, Cu, and Ti, and may have a single layer or a multilayer structure.

[0126] The first interlayer insulating layer 207 may be disposed on the second capacitor electrode CE2. The second semiconductor layer A2 of the second thin film transistor TFT2 may be disposed on the first interlayer insulating layer 207. The second semiconductor layer A2 may include a channel region and an impurity region arranged at the opposite side of the channel region. The second semiconductor layer A2 may include an oxide semiconductor material such as a zinc oxide (Zn) material. The second semiconductor layer A2 may be an In-Ga-Zn-O (IGZO), In-Sn-Zn-O (ITZO) or In-Ga-Sn-Zn-O (IGTZO) semiconductor in which a metal such as indium (In), gallium (Ga) and tin (Sn) is contained in zinc oxide (ZnO).

[0127] The shielding layer SHD may be disposed between the first interlayer insulating layer 207 and the second gate insulating layer 205 and overlap the second semiconductor layer A2. The shielding layer SHD may prevent or reduce the characteristics of the second thin film transistor TFT2 from being degraded due to external light.

[0128] The third gate insulating layer 209 may be disposed on the second semiconductor layer A2. The second gate electrode G2 may be disposed on the third gate insulating layer 209. The second gate electrode G2 may be arranged so that the second gate electrode G2 overlaps the channel region of the second semiconductor layer A2. The second gate electrode G2 may include a conductive material such as Mo, Al, Cu, and Ti, and may have a single-layer or multi-layer structure.

[0129] The second interlayer insulating layer 211 may be disposed on the second gate electrode G2. The first source electrode S1, the first drain electrode D1, the second source electrode S2, and the second drain electrode D2 may be disposed on the second interlayer insulating layer 211. In some embodiments, one or more of the first source electrode S1, the first drain electrode D1, the second source electrode S2, and the second drain electrode D2 may be omitted. The first source electrode S1, the first drain electrode D1, the second source electrode S2, and the second drain electrode D2 may include Mo, Al, Cu, or Ti, and may have a single-layer or multi-layer structure.

[0130] Elements of the first pixel circuit PC1 and the second pixel circuit PC2 may be connected to each other via a connection line CL. Figure 5 , the connection line CL is arranged between the first gate insulating layer 203 and the second gate insulating layer 205. However, one or more embodiments are not limited thereto. In some embodiments, the connection line CL may be arranged between the buffer layer 201 and the first gate insulating layer 203, and may connect the first semiconductor layer A1 of the first pixel circuit PC1 and the first semiconductor layer of the second pixel circuit PC2 to each other. In some embodiments, the connection line CL may be arranged between the second interlayer insulating layer 211 and the first planarizing layer 213, and may connect any one of the first source electrode S1, the first drain electrode D1, the second source electrode S2, and the second drain electrode D2 of the first pixel circuit PC1 to any one of the first source electrode S1, the first drain electrode D1, the second source electrode S2, and the second drain electrode D2 of the second pixel circuit PC2 to each other.

[0131] Each of the buffer layer 201, the first gate insulating layer 203, the second gate insulating layer 205, the first interlayer insulating layer 207, the third gate insulating layer 209, and the second interlayer insulating layer 211 may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, and / or zinc oxide. The inorganic material layer arranged between the substrate 100 and the emission element layer EDL may be defined as an inorganic insulating layer IIL. For example, the inorganic insulating layer IIL may include the buffer layer 201, the first gate insulating layer 203, the second gate insulating layer 205, the first interlayer insulating layer 207, the third gate insulating layer 209, and the second interlayer insulating layer 211.

[0132] The first planarization layer 213 may be disposed on the inorganic insulating layer IIL and cover the first source electrode S1, the first drain electrode D1, the second source electrode S2, and the second drain electrode D2. The second planarization layer 215 may be disposed on the first planarization layer 213. The first planarization layer 213 and the second planarization layer 215 may include a general polymer such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethylmethacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a paraxylene polymer, or a vinyl alcohol polymer. The first planarization layer 213 and the second planarization layer 215 may provide a flat substrate surface for the elements disposed on the first planarization layer 213 and the second planarization layer 215.

[0133] The organic material layer disposed between the inorganic insulating layer IIL and the emission element layer EDL may be defined as an organic insulating layer OIL. For example, the organic insulating layer OIL may include a first planarization layer 213 and a second planarization layer 215. In some embodiments, the organic insulating layer OIL may have a relatively low modulus. For example, the modulus of each of the first planarization layer 213 and the second planarization layer 215 may be about 3 MPa to about 20 MPa.

[0134] The first and second connection electrodes CM1 and CM2 may be disposed between the first and second planarization layers 213 and 215. The first and second connection electrodes CM1 and CM2 may include Mo, Al, Cu, or Ti, and may have a single-layer or multi-layer structure.

[0135] The first emission element ED1, the second emission element ED2, and the emission element layer EDL including the inorganic bank barrier layer 250 and the metal bank barrier layer 300 may be disposed on the organic insulating layer OIL. The first emission element ED1 may be disposed such that the first emission element ED1 overlaps the first unit area UA1, and the second emission element ED2 may be disposed such that the second emission element ED2 overlaps the second unit area UA2. The first emission element ED1 may include a first pixel electrode 411, a first pair of electrodes 431, and a first intermediate layer 421 disposed between the first pixel electrode 411 and the first pair of electrodes 431. The second emission element ED2 may include a second pixel electrode 412, a second pair of electrodes 432, and a second intermediate layer 422 disposed between the second pixel electrode 412 and the second pair of electrodes 432. The first emission element ED1 and the second emission element ED2 may have structures that are substantially the same or similar to each other.

[0136] The first pixel electrode 411 and the second pixel electrode 412 may be disposed on the second planarization layer 215. The first pixel electrode 411 may be electrically connected to the first pixel circuit PC1 via the first connection electrode CM1. The second pixel electrode 412 may be electrically connected to the second pixel circuit PC2 via the second connection electrode CM2.

[0137] The first pixel electrode 411 and the second pixel electrode 412 may include, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium gallium oxide (IGO) or aluminum zinc oxide (AZO) as an example. In some embodiments, the first pixel electrode 411 and the second pixel electrode 412 may include a reflective layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) or any compound thereof. In some embodiments, the first pixel electrode 411 and the second pixel electrode 412 may further include a reflective layer including ITO, IZO, ZnO, AZO or In on or below the reflective layer described herein. 2 O 3 layer.

[0138] Each of the first intermediate layer 421 and the second intermediate layer 422 may include an emission layer that emits light of a specific color. The emission layer may include a polymer or a low molecular weight organic material. The first intermediate layer 421 and the second intermediate layer 422 may include a first functional layer disposed under the emission layer and a second functional layer disposed above the emission layer, respectively. The first functional layer may include a hole transport layer (HTL) and / or a hole injection layer (HIL). The second functional layer may include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0139] The first pair of electrodes 431 and the second pair of electrodes 432 may each include a conductive material having a low work function. For example, the first pair of electrodes 431 and the second pair of electrodes 432 may each include a (semi) transparent layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, lithium (Li), calcium (Ca) or any alloy thereof. Alternatively, the first pair of electrodes 431 and the second pair of electrodes 432 may each further include a conductive material including ITO, IZO, ZnO, AZO or In on the (semi) transparent layer including the material described herein. 2 O 3 layer.

[0140] The inorganic bank barrier layer 250 may be disposed on the organic insulating layer OIL and cover an edge of each of the first pixel electrode 411 and the second pixel electrode 412. The inorganic bank barrier layer 250 may define a pixel opening exposing a portion of each of the first pixel electrode 411 and the second pixel electrode 412. The pixel opening may define an emission region of a corresponding emission element.

[0141] The inorganic dam blocking layer 250 may include an inorganic material such as silicon oxide, silicon nitride and / or silicon oxynitride, and may have a single layer or a multilayer structure. The inorganic dam blocking layer 250 may increase the distance between the edge of the first pixel electrode 411 and the first pair of electrodes 431 and the distance between the edge of the second pixel electrode 412 and the second pair of electrodes 432, thereby preventing arcing etc. from occurring between the first pixel electrode 411 and the first pair of electrodes 431 and / or between the second pixel electrode 412 and the second pair of electrodes 432.

[0142] The metal dam layer 300 may be disposed on the inorganic dam layer 250. The metal dam layer 300 may include a first metal layer 310 and a second metal layer 320 disposed on the first metal layer 310. The first metal layer 310 and the second metal layer 320 may include metals different from each other. In some embodiments, the first metal layer 310 may include Al or Mo, and the second metal layer 320 may include Ti or Ta. The first metal layer 310 may define a first dam opening overlapping with a pixel opening, and the second metal layer 320 may define a second dam opening overlapping with the pixel opening. The width (or area) of the first dam opening defined in the first metal layer 310 may be greater than the width (or area) of the second dam opening defined in the second metal layer 320. In other words, an undercut structure in which the second metal layer 320 protrudes by removing a portion of the first metal layer 310 disposed under the second metal layer 320 may be formed. The second metal layer 320 may have a tip protruding from a side surface of the first metal layer 310 defining the first dam opening.

[0143] The dummy stack may be provided on the upper surface of the second metal layer 320. The first dummy stack located in the region adjacent to the first emission element ED1 may include dummy layers respectively including the same material as the first intermediate layer 421 and the first counter electrode 431. The second dummy stack located in the region adjacent to the second emission element ED2 may include dummy layers respectively including the same material as the second intermediate layer 422 and the second counter electrode 432.

[0144] The first pair of electrodes 431 may be in direct contact with the side surface of the first metal layer 310 facing the central portion of the pixel opening. The second pair of electrodes 432 may be in direct contact with the side surface of the first metal layer 310 facing the central portion of the pixel opening. Because the metal bank layer 300 is electrically connected to a voltage line configured to transmit a common power supply voltage, the first pair of electrodes 431 and the second pair of electrodes 432 may receive the common power supply voltage.

[0145] The encapsulation layer 500 may be disposed on the emission element layer EDL. The encapsulation layer 500 may include a first inorganic encapsulation layer 511 overlapping the first unit area UA1, a second inorganic encapsulation layer 512 overlapping the second unit area UA2, a third inorganic encapsulation layer 531 disposed on the first inorganic encapsulation layer 511, a fourth inorganic encapsulation layer 532 disposed on the second inorganic encapsulation layer 512, a first organic encapsulation layer 521 disposed between the first inorganic encapsulation layer 511 and the third inorganic encapsulation layer 531, and a second organic encapsulation layer 522 disposed between the second inorganic encapsulation layer 512 and the fourth inorganic encapsulation layer 532.

[0146] The first inorganic encapsulating layer 511 , the second inorganic encapsulating layer 512 , the third inorganic encapsulating layer 531 , and the fourth inorganic encapsulating layer 532 may include an inorganic material such as, for example, silicon oxide, silicon nitride, and / or silicon oxynitride, and may have a single-layer or multi-layer structure.

[0147] The first inorganic encapsulation layer 511 and the second inorganic encapsulation layer 512 may be formed by chemical vapor deposition (CVD) or the like. The first inorganic encapsulation layer 511 has a relatively excellent step coverage (e.g., a step coverage greater than a threshold value), and may be in direct contact with the surface of the first metal layer 310 and the surface of the second metal layer 320 that are not covered by the first intermediate layer 421 and the first pair of electrodes 431 to form an inorganic contact region for sealing the first emission element ED1. In some aspects, similar to the first inorganic encapsulation layer 511, the second inorganic encapsulation layer 512 may be in direct contact with the surface of the first metal layer 310 and the surface of the second metal layer 320 that are not covered by the second intermediate layer 422 and the second pair of electrodes 432 to form an inorganic contact region for sealing the second emission element ED2.

[0148] The first organic encapsulation layer 521 may be disposed on the first inorganic encapsulation layer 511, and the second organic encapsulation layer 522 may be disposed on the second inorganic encapsulation layer 512. Each of the first organic encapsulation layer 521 and the second organic encapsulation layer 522 may fill the pixel opening and provide a flat substrate surface to the elements disposed on the first organic encapsulation layer 521, the second organic encapsulation layer 522 and / or the pixel opening. The first organic encapsulation layer 521 and the second organic encapsulation layer 522 may include a polymer material. The polymer material may include, for example, an acrylic resin, an epoxy resin, polyimide, and polyethylene. In some embodiments, the first organic encapsulation layer 521 and the second organic encapsulation layer 522 may be arranged to correspond to the first emission element ED1 and the second emission element ED2, respectively, by an inkjet process or a photopatterning process.

[0149] The third inorganic encapsulation layer 531 may be disposed on the first organic encapsulation layer 521, and the fourth inorganic encapsulation layer 532 may be disposed on the second organic encapsulation layer 522. The third inorganic encapsulation layer 531 may cover the entire surface of the first unit area UA1, and the fourth inorganic encapsulation layer 532 may cover the entire surface of the second unit area UA2. The first inorganic encapsulation layer 511 and the third inorganic encapsulation layer 531 may constitute an inorganic contact region surrounding the first emission element ED1. The second inorganic encapsulation layer 512 and the fourth inorganic encapsulation layer 532 may constitute an inorganic contact region surrounding the second emission element ED2.

[0150] The emission element layer EDL and the encapsulation layer 500 may define a valley V that overlaps with the middle area MA and exposes the upper surface of the organic insulating layer OIL. The valley V may be arranged so that the valley V surrounds each of the first unit area UA1 and the second unit area UA2. For example, the portion of the emission element layer EDL overlapping with the first unit area UA1 may be arranged to be separated from the portion of the emission element layer EDL overlapping with the second unit area UA2 with the middle area MA between these portions of the emission element layer EDL. Similarly, for example, the portion of the encapsulation layer 500 overlapping with the first unit area UA1 may be arranged to be separated from the portion of the encapsulation layer 500 overlapping with the second unit area UA2 with the middle area MA between these portions of the encapsulation layer 500. In other words, each of the emission element layer EDL and the encapsulation layer 500 may not overlap with the middle area MA. Accordingly, in the middle area MA, the inorganic material layer may not be arranged between the organic insulating layer OIL and the third planarization layer 600.

[0151] When the display device 1 is stretched or bent, stress may be concentrated in the middle area MA not overlapping the emission element layer EDL and the encapsulation layer 500. Therefore, cracks and the like in the inorganic films included in the emission element layer EDL and the encapsulation layer 500 may be prevented or reduced.

[0152] The encapsulation layer 500 may cover the side surface of the inorganic bank barrier layer 250 facing the middle area MA and the side surface of the metal bank barrier layer 300 facing the middle area MA. In this case, the side surfaces of the first metal layer 310 and the second metal layer 320 facing the middle area MA may be smoothly connected so as not to form a tip or a groove. Figure 5 The third inorganic encapsulating layer 531 is shown extending to the upper surface of the organic insulating layer OIL and covering the first side surface of the inorganic bank layer 250 and the first side surface of the metal bank layer 300 facing the middle area MA. Figure 5 The fourth inorganic encapsulating layer 532 is shown to extend to the upper surface of the organic insulating layer OIL and cover the second side surface of the inorganic bank barrier layer 250 facing the middle area MA and the second side surface of the metal bank barrier layer 300 facing the middle area MA. Here, the first side surface and the second side surface may be arranged to face each other.

[0153] The capping layer 540 may be arranged between the encapsulation layer 500 and the side surface of the inorganic dam barrier layer 250 facing the middle area MA, and between the encapsulation layer 500 and the side surface of the metal dam barrier layer 300 facing the middle area MA. The capping layer 540 may include an inorganic material such as silicon oxide, silicon nitride and / or silicon oxynitride, and may have a single-layer or multi-layer structure. In some embodiments, in the process of forming the valley V, due to the difference in etching rates of the materials included in each layer, irregularities may be formed. The capping layer 540 may fill these irregularities to prevent cracks from appearing from the side surface of the valley V.

[0154] The third planarization layer 600 may be disposed on the encapsulation layer 500. The third planarization layer 600 may provide a flat substrate surface for the elements disposed on the third planarization layer 600 and the encapsulation layer 500. The third planarization layer 600 may include a polymer material. The polymer material may include, for example, acrylic resin, epoxy resin, polyimide, and polyethylene. In some embodiments, the third planarization layer 600 may have a relatively low modulus. For example, the modulus of the third planarization layer 600 may be about 3 MPa to about 20 MPa.

[0155] The touch sensor layer 700 may be disposed on the third planarization layer 600. The touch sensor layer 700 may be a layer configured to obtain coordinate information according to an external input such as a touch event. The touch sensor layer 700 may include a sensing electrode (or touch electrode) and a trace connected to the sensing electrode. The touch sensor layer 700 may detect an external input by using a mutual capacitance method and / or a self-capacitance method.

[0156] The touch sensor layer 700 may include a first touch electrode 710 , a second touch electrode 720 , a first touch insulating layer 701 between the first touch electrode 710 and the second touch electrode 720 , and a second touch insulating layer 703 on the second touch electrode 720 .

[0157] The first touch electrode 710 and the second touch electrode 720 may include a metal layer or a transparent conductive layer. The metal layer may include Mo, mendelevium (Md), silver (Ag), Ti, Cu, Al or any alloy thereof. The transparent conductive layer may include a transparent conductive oxide such as indium tin oxide, indium zinc oxide, zinc oxide, indium oxide, indium gallium oxide or aluminum zinc oxide. In addition, the transparent conductive layer may include a conductive polymer such as poly (3,4-ethylenedioxythiophene) (PEDOT), a metal nanowire, a carbon nanotube and graphene.

[0158] In some embodiments, the first touch electrode 710 and the second touch electrode 720 may have a mesh structure including a plurality of holes. The plurality of holes may be arranged so that the holes overlap with the emission area of ​​the first emission element ED1 and the emission area of ​​the second emission element ED2. In some embodiments, the first touch electrode 710 and the second touch electrode 720 may have a serpentine shape for ease of stretching.

[0159] The first touch insulating layer 701 and the second touch insulating layer 703 may include a polymer material. The polymer material may include, for example, acrylic resin, epoxy resin, polyimide, and polyethylene. In some embodiments, the touch sensor layer 700 may include a third touch insulating layer between the first touch electrode 710 and the third planarization layer 600. The third touch insulating layer may be an inorganic material layer.

[0160] FIG. 6A to FIG. 6C is a cross-sectional view schematically illustrating a display device 1 according to one or more embodiments.

[0161] refer to Fig. 6A , one or more emitting elements may overlap with the first unit area UA1. For example, the first emitting element ED1 and the third emitting element ED3 may be arranged so that the first emitting element ED1 and the third emitting element ED3 overlap with the first unit area UA1. The first unit area UA1 may be surrounded by the middle area MA. In other words, in a plan view, the first unit area UA1 may have an island shape separated from other adjacent unit areas while the middle area MA is between the first unit area UA1 and the other adjacent unit areas.

[0162] The organic insulating layer OIL may include a first planarization layer 213 and a second planarization layer 215. The voltage line VL may be disposed between the first planarization layer 213 and the second planarization layer 215. The voltage line VL may include a first connection electrode CM1 (see Figure 5 ) and the second connection electrode CM2 (see Figure 5 ) of the same material. The voltage line VL may be configured to transmit a common power supply voltage VSS (see Figure 4A ). For example, the voltage line VL may be electrically connected to the second voltage line VSSL (see Figure 4A ) and can extend to the display area DA (see FIG. 2A to FIG. 2E In some embodiments, the voltage line VL may be located in the display area DA (see FIG. 2A to FIG. 2E ) has a grid structure including multiple horizontal voltage lines and multiple vertical voltage lines crossing each other.

[0163] The first emission element ED1 and the third emission element ED3 may be disposed on the organic insulating layer OIL. The first emission element ED1 may include a first pixel electrode 411, a first counter electrode 431, and a first intermediate layer 421 disposed between the first pixel electrode 411 and the first counter electrode 431. The third emission element ED3 may include a third pixel electrode 413, a third counter electrode 433, and a third intermediate layer 423 disposed between the third pixel electrode 413 and the third counter electrode 433. The first emission element ED1 and the third emission element ED3 may have structures substantially the same as or similar to each other.

[0164] The first pixel electrode 411 and the third pixel electrode 413 may be disposed on the second planarization layer 215. Figure 5 As described above, the first pixel electrode 411 and the third pixel electrode 413 may be electrically connected to corresponding pixel circuits respectively through connection electrodes disposed between the first planarization layer 213 and the second planarization layer 215 .

[0165] The inorganic bank blocking layer 250 may be disposed on the organic insulating layer OIL and cover an edge of each of the first pixel electrode 411 and the third pixel electrode 413. The inorganic bank blocking layer 250 may have a first pixel opening OP1 exposing a portion of the first pixel electrode 411 and a third pixel opening OP3 exposing a portion of the third pixel electrode 413. The first pixel opening OP1 may define an emission region of the first emission element ED1, and the third pixel opening OP3 may define an emission region of the third emission element ED3.

[0166] A portion of the first sacrificial layer 401 may remain between the inorganic dam blocking layer 250 and the first pixel electrode 411. The first sacrificial layer 401 may be a layer configured to prevent damage to the surface of the first pixel electrode 411 during the process of forming the first pixel opening OP1. A portion of the third sacrificial layer 403 may remain between the inorganic dam blocking layer 250 and the third pixel electrode 413. The third sacrificial layer 403 may be a layer configured to prevent damage to the surface of the third pixel electrode 413 during the process of forming the third pixel opening OP3. In some aspects, the first sacrificial layer 401 and the third sacrificial layer 403 may include a conductive oxide, IZO and / or IGZO.

[0167] The metal dam layer 300 may be disposed on the inorganic dam layer 250. The metal dam layer 300 may include a first metal layer 310 and a second metal layer 320. The first metal layer 310 may define a 1-1 dam opening 310OP1 overlapping the first pixel opening OP1 and a 1-3 dam opening 310OP3 overlapping the third pixel opening OP3. The second metal layer 320 may define a 2-1 dam opening 320OP1 overlapping the first pixel opening OP1 and a 2-3 dam opening 320OP3 overlapping the third pixel opening OP3.

[0168] The width (or area) of the 1-1st bank stop opening 310OP1 may be greater than the width (or area) of the 2-1st bank stop opening 320OP1. The width (or area) of the 1-3rd bank stop opening 310OP3 may be greater than the width (or area) of the 2-3rd bank stop opening 320OP3. Accordingly, for example, an undercut structure may be formed in which the second metal layer 320 protrudes by removing a portion of the first metal layer 310 disposed under the second metal layer 320. For example, the second metal layer 320 may have a first tip PT1 protruding from a side surface of the first metal layer 310 in a central direction of the first pixel opening OP1 and a third tip PT3 protruding from a side surface of the first metal layer 310 in a central direction of the third pixel opening OP3.

[0169] The first metal layer 310 of the metal bank layer 300 may be electrically connected to the voltage line VL through the contact hole CNT defined in the inorganic bank layer 250 and the second planarization layer 215. In each cell region, at least one contact hole CNT may be arranged to electrically connect the metal bank layer 300 and the voltage line VL to each other.

[0170] The first intermediate layer 421 may be disposed on the first pixel electrode 411 so that the first intermediate layer 421 overlaps with the first pixel opening OP1, and the third intermediate layer 423 may be disposed on the third pixel electrode 413 so that the third intermediate layer 423 overlaps with the third pixel opening OP3. Each of the first intermediate layer 421 and the third intermediate layer 423 may include an emission layer that emits light of one color. Each emission layer may be formed by using a fine metal mask (FMM) or the like to correspond to the first pixel electrode 411 and the third pixel electrode 413. The material of the first intermediate layer 421 and the material of the third intermediate layer 423 may be deposited on the second metal layer 320 to form a dummy layer.

[0171] The first pair of electrodes 431 may be disposed on the first intermediate layer 421 so that the first pair of electrodes 431 overlaps the first pixel opening OP1, and the third pair of electrodes 433 may be disposed on the third intermediate layer 423 so that the third pair of electrodes 433 overlaps the third pixel opening OP3. The first pair of electrodes 431 may be in direct contact with the side surface of the first metal layer 310 facing the center of the first pixel opening OP1. The third pair of electrodes 433 may be in direct contact with the side surface of the first metal layer 310 facing the center of the third pixel opening OP3. Because the metal bank barrier layer 300 is electrically connected to the voltage line VL configured to transmit the common power supply voltage through the contact hole CNT, the first pair of electrodes 431 and the third pair of electrodes 433 may receive the common power supply voltage.

[0172] The materials of the first pair of electrodes 431 and the third pair of electrodes 433 may be deposited on the second metal layer 320 to form a dummy layer. For example, the material of the first intermediate layer 421 and the material of the first pair of electrodes 431 may be deposited on the second metal layer 320 adjacent to the first emission element ED1 to form a first dummy stack dm1. The material of the third intermediate layer 423 and the material of the third pair of electrodes 433 may be deposited on the second metal layer 320 adjacent to the third emission element ED3 to form a second dummy stack dm2. Since the first pair of electrodes 431 and the third pair of electrodes 433 may be formed by the same process, the material of the first pair of electrodes 431 and the material of the third pair of electrodes 433 may be the same as each other.

[0173] The first dummy stack dm1 may be separated and spaced apart from the first intermediate layer 421 and the first counter electrode 431 by the first tip PT1. The second dummy stack dm2 may be separated and spaced apart from the third intermediate layer 423 and the third counter electrode 433 by the third tip PT3.

[0174] The encapsulation layer 500 may be arranged such that the encapsulation layer 500 covers the first and third emission elements ED1 and ED3 . The encapsulation layer 500 may include a first inorganic encapsulation layer 511 , a first organic encapsulation layer 521 , a third organic encapsulation layer 523 , and a third inorganic encapsulation layer 531 covering the first and third organic encapsulation layers 521 and 523 .

[0175] The first inorganic encapsulation layer 511 may overlap the first emission element ED1 and the third emission element ED3. The first inorganic encapsulation layer 511 may directly contact the surface of the first metal layer 310 and the surface of the second metal layer 320 that are not covered by the first intermediate layer 421, the first counter electrode 431, the third intermediate layer 423, and the third counter electrode 433, and may form an inorganic contact region for sealing each of the first emission element ED1 and the second emission element ED2.

[0176] The first organic encapsulation layer 521 may be arranged to correspond to the first emission element ED1 so as to fill the 1-1st bank opening 310OP1 and the 2-1st bank opening 320OP1. The third organic encapsulation layer 523 may be arranged to correspond to the third emission element ED3 so as to fill the 1-3rd bank opening 310OP3 and the 2-3rd bank opening 320OP3. The first organic encapsulation layer 521 and the third organic encapsulation layer 523 may be arranged to be spaced apart from each other.

[0177] The third inorganic encapsulation layer 531 may cover the entire surface of the first unit area UA1. The third inorganic encapsulation layer 531 may overlap the first emission element ED1 and the third emission element ED3. The third inorganic encapsulation layer 531 may be in direct contact with the first inorganic encapsulation layer 511 in an area where the first organic encapsulation layer 521 and the third organic encapsulation layer 523 are not arranged, so that the third inorganic encapsulation layer 531 and the first inorganic encapsulation layer 511 form an inorganic contact area. The third inorganic encapsulation layer 531 and the first inorganic encapsulation layer 511 may form an inorganic contact area surrounding the first emission element ED1 and the third emission element ED3.

[0178] The emission element layer EDL and the encapsulation layer 500 may define a valley V that overlaps with the middle area MA and exposes the upper surface of the organic insulating layer OIL. For example, the valley V may be formed by the overlap of the opening 250OPv of the inorganic dam barrier layer 250, the opening 310OPv of the first metal layer 310, the opening 320OPv of the second metal layer 320, the first encapsulation opening 510OPv, and the second encapsulation opening 530OPv. Here, the first encapsulation opening 510OPv may be formed by the first inorganic encapsulation layer 511 and an inorganic encapsulation layer (e.g., Figure 5Likewise, the second encapsulation opening 530OPv may be defined by the third inorganic encapsulation layer 531 and an inorganic encapsulation layer (eg, Figure 5 The fourth inorganic encapsulation layer 532 shown in FIG.

[0179] The third inorganic encapsulating layer 531 may extend so that the third inorganic encapsulating layer 531 is in direct contact with the upper surface of the organic insulating layer OIL. Accordingly, the third inorganic encapsulating layer 531 may form a side surface of the valley V.

[0180] The valley V may be arranged so that the valley V surrounds the first unit area UA1. For example, a portion of the inorganic bank layer 250, a portion of the metal bank layer 300, and a portion of the encapsulation layer 500 overlapping the first unit area UA1 may have an island shape separated from surrounding areas by the valley V.

[0181] The covering layer 540 may be disposed between the encapsulation layer 500 and the side surface of the inorganic dam barrier layer 250 facing the middle area MA and between the encapsulation layer 500 and the side surface of the metal dam barrier layer 300 facing the middle area MA. For example, the covering layer 540 may be disposed under the third inorganic encapsulation layer 531 and cover the inner surface of each of the opening 250OPv of the inorganic dam barrier layer 250, the opening 310OPv of the first metal layer 310, the opening 320OPv of the second metal layer 320, and the first encapsulation opening 510OPv. In the process of forming the opening 250OPv of the inorganic dam barrier layer 250, the opening 310OPv of the first metal layer 310, the opening 320OPv of the second metal layer 320, and the first encapsulation opening 510OPv, the covering layer 540 may fill irregularities, notches, protrusions, cracks, etc. formed due to the difference in etching rates of the materials, so that the valley V may have a flatter side surface.

[0182] Figure 6B and Fig. 6A The fourth organic encapsulation layer 525 overlapping the first emission element ED1 and the third emission element ED3 is similar, except that the fourth organic encapsulation layer 525 overlapping the first inorganic encapsulation layer 511 and the third inorganic encapsulation layer 531 is arranged between the first inorganic encapsulation layer 511 and the third inorganic encapsulation layer 531. The fourth organic encapsulation layer 525 may be arranged so that the fourth organic encapsulation layer 525 overlaps with the plurality of emission elements arranged in the first unit area UA1. Therefore, the fourth organic encapsulation layer 525 may provide a flatter base surface for the third inorganic encapsulation layer 531.

[0183] In some embodiments, Figure 6CAs illustrated in FIG. 5 , the first organic encapsulating layer 521 , the third organic encapsulating layer 523 , and the fourth organic encapsulating layer 525 may all be omitted, and the first inorganic encapsulating layer 511 and the third inorganic encapsulating layer 531 may directly contact each other.

[0184] 7A to 7H 1 is a cross-sectional view schematically illustrating some operations of a process for manufacturing a display device according to an embodiment. 7A to 7H In, omitted Figure 5 1 shows a configuration from the substrate 100 to the first planarizing layer 213 of the display device 1 illustrated in FIG. 1 , and mainly illustrates the second planarizing layer 215 , the emission element layer EDL, and the encapsulation layer 500 .

[0185] refer to Fig. 7A , the display device may include a first unit area UA1, a second unit area UA2, and an intermediate area MA disposed between the first unit area UA1 and the second unit area UA2. The first connection electrode CM1 may be disposed on the first unit area UA1, and the second connection electrode CM2 may be disposed on the second unit area UA2. The second planarization layer 215 may be disposed such that the second planarization layer 215 covers the first connection electrode CM1 and the second connection electrode CM2.

[0186] The first pixel electrode 411 overlapping the first unit area UA1 and the second pixel electrode 412 overlapping the second unit area UA2 may be disposed on the second planarization layer 215. The first sacrificial layer 401 may be disposed on the first pixel electrode 411, and the second sacrificial layer 402 may be disposed on the second pixel electrode 412. The shape of the first sacrificial layer 401 may correspond to the shape of the first pixel electrode 411, and the shape of the second sacrificial layer 402 may correspond to the shape of the second pixel electrode 412. Here, "the shape of A corresponds to the shape of B" means that the shape of A is the same as or similar to the shape of B. For example, A and B can be formed by using the same mask. In this case, depending on the process and material properties, the boundaries of A and B may be substantially equal to each other or partially separated.

[0187] The first sacrificial layer 401 and the second sacrificial layer 402 may include a conductive oxide such as, for example, IZO and / or IGZO.

[0188] The inorganic bank layer 250 and the metal bank layer 300 may be sequentially formed on the second planarization layer 215 and cover the first sacrificial layer 401 and the second sacrificial layer 402. The metal bank layer 300 may include a first metal layer 310 and a second metal layer 320. The first metal layer 310 and the second metal layer 320 may include metals having different etching rates from each other.

[0189] refer to Figure 7BOpenings that respectively expose the upper surfaces of the first pixel electrode 411 and the second pixel electrode 412 may be formed by etching a portion of the metal bank layer 300 and a portion of the inorganic bank layer 250 .

[0190] By etching a portion of the first metal layer 310 and a portion of the second metal layer 320, a 1-1 bank opening 310OP1 and a 2-1 bank opening 320OP1 overlapping the first pixel electrode 411 may be formed, and a 1-2 bank opening 310OP2 and a 2-2 bank opening 320OP2 overlapping the second pixel electrode 412 may be formed. Through the wet etching process, the 1-1 bank opening 310OP1 may have a first width w1, and the 2-1 bank opening 320OP1 may have a second width w2 less than the first width w1. Similarly, the width of the 1-2 bank opening 310OP2 may be greater than the width of the 2-2 bank opening 320OP2. In other words, the metal bank layer 300 may have an undercut structure obtained by removing a portion of the first metal layer 310 under the second metal layer 320.

[0191] By etching a portion of the inorganic bank blocking layer 250, a first pixel opening OP1 exposing a portion of the upper surface of the first pixel electrode 411 and a second pixel opening OP2 exposing a portion of the upper surface of the second pixel electrode 412 may be formed. Thereafter, the first sacrificial layer 401 and the second sacrificial layer 402 exposed by the first pixel opening OP1 and the second pixel opening OP2, respectively, may be removed by wet etching. In this case, a portion of the first sacrificial layer 401 and a portion of the second sacrificial layer 402 overlapping the inorganic bank blocking layer 250 may remain without being removed.

[0192] refer to Figure 7C , the material included in the first intermediate layer 421 and the material included in the second intermediate layer 422 may be deposited in the first unit area UA1, the second unit area UA2, and the intermediate area MA. The first intermediate layer 421 may be disposed on the first pixel electrode 411 so that the first intermediate layer 421 overlaps the first pixel opening OP1, and the second intermediate layer 422 may be disposed on the second pixel electrode 412 so that the second intermediate layer 422 overlaps the second pixel opening OP2. The first dummy intermediate layer 421dm may be formed on the second metal layer 320 adjacent to the first pixel opening OP1, and the second dummy intermediate layer 422dm may be formed on the second metal layer 320 adjacent to the second pixel opening OP2.

[0193] The first intermediate layer 421 and the first dummy intermediate layer 421dm may be separated and spaced apart from each other by a first tip PT1 of the second metal layer 320 protruding from a side surface of the first metal layer 310 in a central direction of the first pixel opening OP1. The second intermediate layer 422 and the second dummy intermediate layer 422dm may be separated and spaced apart from each other by a second tip PT2 of the second metal layer 320 protruding from a side surface of the first metal layer 310 in a central direction of the second pixel opening OP2.

[0194] The materials included in the first pair of electrodes 431 and the second pair of electrodes 432 may be deposited on the first unit area UA1, the second unit area UA2, and the middle area MA. The first pair of electrodes 431 may be disposed on the first intermediate layer 421 and overlap with the first pixel opening OP1, and the second pair of electrodes 432 may be disposed on the second intermediate layer 422 and overlap with the second pixel opening OP2. The first pair of electrodes 431 may be in direct contact with the side surface of the first metal layer 310 facing the center of the first pixel opening OP1. The second pair of electrodes 432 may be in direct contact with the side surface of the first metal layer 310 facing the center of the second pixel opening OP2.

[0195] The first dummy electrode layer 431dm may be formed on the first dummy intermediate layer 421dm and may constitute a first dummy stack dm1. The second dummy electrode layer 432dm may be formed on the second dummy intermediate layer 422dm and may constitute a second dummy stack dm2. The first dummy electrode layer 431dm may be integrally provided with the second dummy electrode layer 432dm as a single body.

[0196] The first pair of electrodes 431 and the first dummy electrode layer 431dm may be separated and spaced apart from each other by the first tip PT1. The second pair of electrodes 432 and the second dummy electrode layer 432dm may be separated and spaced apart from each other by the second tip PT2. In other words, the first pair of electrodes 431 and the second pair of electrodes 432 may each have an island shape and may be spaced apart from each other.

[0197] The first pixel electrode 411 , the first intermediate layer 421 , and the first counter electrode 431 may constitute a first emission element ED1 , and the second pixel electrode 412 , the second intermediate layer 422 , and the second counter electrode 432 may constitute a second emission element ED2 .

[0198] refer to Fig.7D The first inorganic film 510 may be formed such that the first inorganic film 510 covers the first emission element ED1 and the second emission element ED2. The first inorganic film 510 may be formed such that the first inorganic film 510 overlaps the first unit area UA1, the second unit area UA2, and the middle area MA.

[0199] Since the first inorganic film 510 has a relatively high step coverage, the first inorganic film 510 may directly contact the side surface of the first metal layer 310 and the lower surface of the second metal layer 320 on which the first intermediate layer 421 and the first counter electrode 431 are not formed, through the first tip PT1. Likewise, the first inorganic film 510 may directly contact the side surface of the first metal layer 310 and the lower surface of the second metal layer 320 on which the second intermediate layer 422 and the second counter electrode 432 are not formed, through the second tip PT2. Accordingly, the first inorganic film 510 may seal the first emission element ED1 and the second emission element ED2.

[0200] refer to Fig. 7E A mask layer ML may be formed on the first inorganic film 510, and a portion of the first inorganic film 510, a portion of the metal bank layer 300, and a portion of the inorganic bank layer 250 may be etched by using the opening of the mask layer ML. In some embodiments, the mask layer ML may include a conductive oxide such as, for example, IZO and / or IGZO.

[0201] The portion of the emission element layer EDL overlapping the first unit area UA1 and the portion of the emission element layer EDL overlapping the second unit area UA2 may be spaced apart and separated from each other with the intermediate area MA between these portions of the emission element layer EDL. The first inorganic film 510 may be separated into a first inorganic encapsulation layer 511 and a second inorganic encapsulation layer 512 spaced apart from each other with the intermediate area MA between the first inorganic encapsulation layer 511 and the second inorganic encapsulation layer 512.

[0202] The opening 250OPv of the inorganic dam barrier layer 250, the opening 310OPv of the first metal layer 310, the opening 320OPv of the second metal layer 320, and the first encapsulation opening 510OPv may overlap with each other so as to form a valley opening portion OPv. As described herein, the first encapsulation opening 510OPv may be defined by a side of the first inorganic encapsulation layer 511 facing the middle area MA and a side of the second inorganic encapsulation layer 512 facing the middle area MA.

[0203] refer to Figure 7F , a second inorganic film 541 may be formed on the mask layer ML. The second inorganic film 541 may overlap the first unit area UA1, the second unit area UA2, and the middle area MA, and cover the inner surface of the valley opening portion OPv. The second inorganic film 541 may include silicon oxide, silicon nitride, and / or silicon oxynitride.

[0204] refer to Figure 7G, by using the difference between the horizontal etching rate and the vertical etching rate of the second inorganic film 541, the second inorganic film 541 located on the upper surface of the mask layer ML and the second inorganic film 541 located on the bottom surface of the valley opening portion OPv can be selectively removed, and a capping layer 540 covering the inner surface of the valley opening portion OPv can be formed. The capping layer 540 can cover the inner surface of each of the opening 250OPv of the inorganic dam barrier layer 250, the opening 310OPv of the first metal layer 310, the opening 320OPv of the second metal layer 320, and the first package opening 510OPv. Then, the mask layer ML can be removed.

[0205] refer to Figure 7H , the first organic encapsulation layer 521 may be disposed on the first inorganic encapsulation layer 511 and overlap with the first unit area UA1, and the third inorganic encapsulation layer 531 may be disposed on the first organic encapsulation layer 521 and overlap with the first unit area UA1. The second organic encapsulation layer 522 may be disposed on the second inorganic encapsulation layer 512 and overlap with the second unit area UA2, and the fourth inorganic encapsulation layer 532 may be disposed on the second organic encapsulation layer 522 and overlap with the second unit area UA2. The encapsulation layer 500 may include a first inorganic encapsulation layer 511, a second inorganic encapsulation layer 512, a first organic encapsulation layer 521, a second organic encapsulation layer 522, a third inorganic encapsulation layer 531, and a fourth inorganic encapsulation layer 532.

[0206] In some embodiments, as shown in reference Fig. 6A As described above, the first organic encapsulation layer 521 and the second organic encapsulation layer 522 can be arranged to correspond to each emission element by an inkjet process or a photo patterning process. For example, the first organic encapsulation layer 521 can be arranged to correspond to the first emission element ED1, and the second organic encapsulation layer 522 can be arranged to correspond to the second emission element ED2.

[0207] In some embodiments, as shown in reference Figure 6B As described above, the first organic encapsulation layer 521 may be arranged so that the first organic encapsulation layer 521 overlaps with a plurality of emission elements arranged in the first unit area UA1. The second organic encapsulation layer 522 may be arranged so that the second organic encapsulation layer 522 overlaps with a plurality of emission elements arranged in the second unit area UA2.

[0208] In some embodiments, as shown in reference Figure 6C As described above, the first organic encapsulation layer 521 and the second organic encapsulation layer 522 may be omitted.

[0209] The third inorganic encapsulation layer 531 and the fourth inorganic encapsulation layer 532 may be formed by removing a portion of an inorganic film formed by the same deposition process. The third inorganic encapsulation layer 531 and the fourth inorganic encapsulation layer 532 may define a second encapsulation opening 530OPv between the third inorganic encapsulation layer 531 and the fourth inorganic encapsulation layer 532. The second encapsulation opening 530OPv may overlap the middle area MA.

[0210] The emission element layer EDL and the encapsulation layer 500 may define a valley V overlapping the middle area MA and exposing the upper surface of the second planarization layer 215. The valley V may be a region in which layers included in the emission element layer EDL and the encapsulation layer 500 are not arranged.

[0211] The third and fourth inorganic encapsulating layers 531 and 532 may extend so as to directly contact the upper surface of the second planarization layer 215. Accordingly, the third and fourth inorganic encapsulating layers 531 and 532 may constitute side surfaces of the valley V.

[0212] The valley V may be arranged so that the valley V surrounds the first unit area UA1 and the second unit area UA2. For example, a portion of the inorganic bank layer 250, a portion of the metal bank layer 300, and a portion of the encapsulation layer 500 overlapping the first unit area UA1 may have an island shape separated from surrounding areas by the valley V.

[0213] Likewise, a portion of the inorganic bank layer 250 , a portion of the metal bank layer 300 , and a portion of the encapsulation layer 500 overlapping the second unit area UA2 may have an island shape partitioned from the surrounding area by the valley V.

[0214] FIG. 8A to FIG. 8C are cross-sectional views schematically illustrating some operations of a process of manufacturing a display device according to an embodiment. FIG. 8A to FIG. 8C Schematically illustrates the reference 7A to 7F Some actions after the described actions.

[0215] refer to Fig. 8A , a photoresist PR may be formed to fill the reference Figure 7F The valley opening portion OPv in the structure described above can be removed by etching the second inorganic film 541 exposed from the photoresist PR (see FIG. Figure 7F ). The residual inorganic film 541p covering the side surfaces and the bottom surface of the valley opening portion OPv may be located under the photoresist PR.

[0216] The photoresist PR may overlap the valley opening portion OPv and the mask layer ML adjacent to the valley opening portion OPv, and the residual inorganic film 541 p may be located between the mask layer ML and the photoresist PR.

[0217] refer to Figure 8B , the mask layer ML and the photoresist PR may be removed. In this case, the residual mask layer MLp overlapping the residual inorganic film 541p may remain. When the mask layer ML is removed by using a wet etching process, the mask layer ML under the residual inorganic film 541p may be removed so that the residual inorganic film 541p has a fourth tip PT4 protruding outside the residual mask layer MLp. The fourth tip PT4 may protrude in the center direction of the first unit area UA1 or in the center direction of the second unit area UA2.

[0218] refer to Figure 8C , the first organic encapsulation layer 521 may be formed on the first inorganic encapsulation layer 511 and overlap the first unit area UA1, and the third inorganic encapsulation layer 531 may be formed on the first organic encapsulation layer 521 and overlap the first unit area UA1. The second organic encapsulation layer 522 may be formed on the second inorganic encapsulation layer 512 and overlap the second unit area UA2, and the fourth inorganic encapsulation layer 532 may be formed on the second organic encapsulation layer 522 and overlap the second unit area UA2.

[0219] The third and fourth inorganic encapsulating layers 531 and 532 may be formed by removing a portion of a third inorganic film formed by the same deposition process. The third and fourth inorganic encapsulating layers 531 and 532 may define a second encapsulation opening 530OPv therebetween.

[0220] During the etching process for forming the second encapsulation opening 530OPv, the residual inorganic film 541p may also be etched, so that the capping layer 540 and the opening 540OPv of the capping layer 540 are formed. The capping layer 540 may extend to the upper surface of the second planarization layer 215, and the third and fourth inorganic encapsulation layers 531 and 532 may be disposed on the capping layer 540.

[0221] The second package opening 530OPv may overlap with the opening 540OPv of the cover layer 540. The second package opening 530OPv and the opening 540OPv of the cover layer 540 may overlap with the middle area MA.

[0222] The emission element layer EDL and the encapsulation layer 500 may define a valley V overlapping the middle area MA and exposing the upper surface of the second planarization layer 215. The valley V may be an area in which the layers included in the emission element layer EDL and the encapsulation layer 500 are not arranged. The third inorganic encapsulation layer 531 and the fourth inorganic encapsulation layer 532 may extend toward the middle area MA along the cover layer 540. Accordingly, the third inorganic encapsulation layer 531 and the fourth inorganic encapsulation layer 532 may constitute a side surface of the valley V. The valley V may be arranged such that the valley V surrounds the first unit area UA1 and the second unit area UA2.

[0223] 9A to 9C are cross-sectional views schematically illustrating some operations of a process of manufacturing a display device according to an embodiment. 9A to 9C Schematically illustrates the reference 7A to 7D Some actions after the described actions.

[0224] refer to Fig.9A , can be found in the reference Fig.7D The first inorganic film 510 of the structure described above (see Fig.7D ) is formed on the first inorganic film 510 to define an opening overlapping with the valley opening portion OPv. Thereafter, by etching a portion of the first inorganic film 510, a portion of the second metal layer 320, and a portion of the first metal layer 310 through the opening of the photoresist PR, a first encapsulation opening 510OPv, an opening 320OPv of the second metal layer 320, and an opening 310OPv of the first metal layer 310 may be formed.

[0225] The valley opening portion OPv exposing the upper surface of the inorganic bank barrier layer 250 may be formed by the opening 320OPv of the second metal layer 320 and the opening 310OPv of the first metal layer 310 overlapping each other. The first inorganic film 510 may be separated into the first inorganic encapsulation layer 511 and the second inorganic encapsulation layer 512 spaced apart from each other with the middle area MA between the first inorganic encapsulation layer 511 and the second inorganic encapsulation layer 512. Then, the photoresist PR may be removed.

[0226] refer to Fig. 9B , the first organic encapsulation layer 521 may be disposed on the first inorganic encapsulation layer 511 and overlap the first unit area UA1, and the second organic encapsulation layer 522 may be disposed on the second inorganic encapsulation layer 512 and overlap the second unit area UA2. The third inorganic film 530 may be formed so that the third inorganic film 530 covers the first organic encapsulation layer 521 and the second organic encapsulation layer 522. The third inorganic film 530 may overlap the first unit area UA1, the second unit area UA2, and the middle area MA. The third inorganic film 530 may cover the side surface and the bottom surface of the valley opening portion OPv.

[0227] refer to Fig. 9C , the first organic encapsulation layer 521 may be formed on the first inorganic encapsulation layer 511 and overlap the first unit area UA1, and the third inorganic encapsulation layer 531 may be formed on the first organic encapsulation layer 521 and overlap the first unit area UA1. The second organic encapsulation layer 522 may be formed on the second inorganic encapsulation layer 512 and overlap the second unit area UA2, and the fourth inorganic encapsulation layer 532 may be formed on the second organic encapsulation layer 522 and overlap the second unit area UA2.

[0228] The third and fourth inorganic encapsulating layers 531 and 532 may be formed by removing a portion of the third inorganic film 530. The third and fourth inorganic encapsulating layers 531 and 532 may define a second encapsulating opening 530OPv therebetween.

[0229] During the etching process for forming the second encapsulation opening 530OPv, the inorganic bank barrier layer 250 may also be removed and an opening 250OPv of the inorganic bank barrier layer 250 may be formed. The second encapsulation opening 530OPv and the opening 250OPv of the inorganic bank barrier layer 250 may overlap the middle area MA.

[0230] The emission element layer EDL and the encapsulation layer 500 may define a valley V overlapping the middle area MA and exposing the upper surface of the second planarization layer 215. The valley V may be an area in which the layers included in the emission element layer EDL and the encapsulation layer 500 are not arranged. The third inorganic encapsulation layer 531 and the fourth inorganic encapsulation layer 532 may constitute a side surface of the valley V. The valley V may be arranged such that the valley V surrounds the first unit area UA1 and the second unit area UA2.

[0231] exist Fig. 9C , the first organic encapsulation layer 521 and the second organic encapsulation layer 522 are arranged to correspond to the first emission element ED1 and the second emission element ED2, respectively. However, in some embodiments, the first organic encapsulation layer 521 may be arranged so that the first organic encapsulation layer 521 overlaps with a plurality of emission elements arranged in the first unit area UA1. The second organic encapsulation layer 522 may be arranged so that the second organic encapsulation layer 522 overlaps with a plurality of emission elements arranged in the second unit area UA2. In some embodiments, the first organic encapsulation layer 521 and the second organic encapsulation layer 522 may be omitted.

[0232] Fig.10 is a cross-sectional view schematically illustrating a display device 1 according to the embodiment. Fig.10 and Figure 5Similar, except that the inorganic insulating layer 111 defines the first openings 103OP, and the first barrier layer 103 defines the second openings 103OP.

[0233] refer to Fig.10 , the display device 1 may include a first unit area UA1, a second unit area UA2, an intermediate area MA, and a partition area SA. The partition area SA may be defined as an area that does not overlap with the inorganic insulating layer IIL and / or the first barrier layer 103. Alternatively, the partition area SA may be defined as an area that overlaps with the first opening 1OP of the inorganic insulating layer IIL and / or the second opening 103OP of the first barrier layer 103. In one or more embodiments, the description of the case where the substrate 100 includes the partition area SA indicates that the substrate 100 includes an area overlapping with the intermediate area MA.

[0234] The substrate 100 may be provided such that a barrier layer which is an inorganic material layer and a base layer which is an organic material layer are alternately arranged with each other. For example, the substrate 100 may include a first base layer 101 and a second base layer 105 including an organic material and a first barrier layer 103 located between the first base layer 101 and the second base layer 105.

[0235] The first barrier layer 103 may overlap the partition area SA and define a second opening 103OP passing through the first barrier layer 103. The second opening 103OP may overlap the valley V because the partition area SA overlaps the middle area MA.

[0236] The partition area SA may be arranged along the edge of the first unit area UA1 and the edge of the second unit area UA2. Accordingly, a portion of the first barrier layer 103 overlapping the first unit area UA1 and a portion of the first barrier layer 103 overlapping the second unit area UA2 may be spaced apart from each other with the partition area SA between these portions of the first barrier layer 103.

[0237] The first pixel circuit PC1, the second pixel circuit PC2 and the inorganic insulating layer IIL may be disposed on the substrate 100. The inorganic insulating layer IIL may include an inorganic material layer between the substrate 100 and the emission element layer EDL. For example, the inorganic insulating layer IIL may include a buffer layer 201, a first gate insulating layer 203, a second gate insulating layer 205, a first interlayer insulating layer 207, a third gate insulating layer 209 and a second interlayer insulating layer 211.

[0238] The inorganic insulating layer 111 may overlap the partition area SA and define a first opening 10P exposing the upper surface of the second base layer 105. The first opening 10P may be formed by an opening of the buffer layer 201, an opening of the first gate insulating layer 203, an opening of the second gate insulating layer 205, an opening of the first interlayer insulating layer 207, an opening of the third gate insulating layer 209, and an opening of the second interlayer insulating layer 211 overlapping each other.

[0239] The portion of the inorganic insulating layer IIL overlapping the first unit area UA1 and the portion of the inorganic insulating layer IIL overlapping the second unit area UA2 may be arranged to be spaced apart from each other with the partition area SA being between these portions of the inorganic insulating layer IIL. Since the first opening 10OP of the inorganic insulating layer IIL and the second opening 103OP of the first barrier layer 103 overlap with the partition area SA, an inorganic material layer may not be provided under the organic insulating layer OIL in the partition area SA.

[0240] The first opening 1OP of the inorganic insulating layer 11L may be filled with a filler layer 217. In some embodiments, the upper surface of the filler layer 217 may be located at the same or similar level as the level at which the upper surface of the second interlayer insulating layer 211 is located. In some embodiments, the upper surface of the filler layer 217 may have a convex shape higher than the upper surface of the second interlayer insulating layer 211 (e.g., at least a portion of the convex shape is higher than the upper surface of the second interlayer insulating layer 211), a concave shape lower than the upper surface of the second interlayer insulating layer 211 (e.g., at least a portion of the concave shape is lower than the upper surface of the second interlayer insulating layer 211), or a shape having uneven portions in which protrusions and recesses alternate with each other.

[0241] The filler layer 217 may include a polymer material. The polymer material may include, for example, acrylic resin, epoxy resin, polyimide, and polyethylene. The filler layer 217 may have a relatively low modulus. The modulus of the filler layer 217 may be about 3 MPa to about 20 MPa.

[0242] The bridge wire BL may be disposed on the packing layer 217 and connect the elements of the first pixel circuit PC1 and the corresponding elements of the second pixel circuit PC2 to each other. The bridge wire BL may be disposed between the packing layer 217 and the first planarization layer 213. In some embodiments, the bridge wire BL may be disposed on the same layer as the layer on which the source electrode and / or the drain electrode of the thin film transistor are disposed. The bridge wire BL may include, for example, Mo, Al, Cu, and Ti, and may have a single-layer or multi-layer structure. In some embodiments, the bridge wire BL may be a single-layer or multi-layer structure and include one or more of Mo, Al, Cu, and Ti.

[0243] Because the partition area SA overlaps the middle area MA, the first opening IOP may overlap the valley V. In some embodiments, the width of the middle area MA may be smaller than the width of the partition area SA. In some embodiments, the width of the middle area MA may be the same as the width of the partition area SA.

[0244] When the display device 1 is stretched or bent, stress may be concentrated on the segmentation area SA that does not overlap with the first barrier layer 103 and / or the inorganic insulating layer IIL. Therefore, cracks in the inorganic films included in the substrate 100, the inorganic insulating layer IIL, the emission element layer EDL, and the encapsulation layer 500 can be prevented or reduced. The display device 1 can have a more robust anti-stretching structure.

[0245] FIG. 11A to FIG. 11B is a plan view schematically illustrating a pixel arrangement of a display device according to an embodiment.

[0246] refer to Fig.11A , the plurality of unit areas UA1, UA2, UA3, and UA4 may be arranged apart from each other and the middle area MA may be between the plurality of unit areas UA1, UA2, UA3, and UA4. For example, the second unit area UA2 may be arranged apart from the first unit area UA1 in a first direction (e.g., x direction), the third unit area UA3 may be arranged apart from the first unit area UA1 in a second direction (e.g., y direction), and the fourth unit area UA4 may be arranged apart from the third unit area UA3 in the first direction (e.g., x direction).

[0247] The middle area MA may be arranged such that the middle area MA surrounds each of the unit areas UA1, UA2, UA3, and UA4. Fig.10 ) and encapsulation layer 500 (see Fig.10 ) may overlap with the middle area MA. Accordingly, portions of the emission element layer EDL respectively overlapping with the unit areas UA1, UA2, UA3, and UA4 may be separated from each other with the middle area MA being between these portions of the emission element layer EDL. Portions of the encapsulation layer 500 overlapping with the unit areas UA1, UA2, UA3, and UA4 may be separated from each other with the middle area MA being between these portions of the encapsulation layer 500.

[0248] One or more pixels may be arranged in each of the unit areas UA1, UA2, UA3, and UA4. In this regard, Fig.11ATwo pixels arranged in one unit area are illustrated. For example, the first pixel PX1 and the second pixel PX2 may be arranged in the first unit area UA1, the third pixel PX3 and the second pixel PX2 may be arranged in the second unit area UA2, the third pixel PX3 and the second pixel PX2 may be arranged in the third unit area UA3, and the first pixel PX1 and the second pixel PX2 may be arranged in the fourth unit area UA4.

[0249] The first pixel PX1, the second pixel PX2, and the third pixel PX3 may emit light of different colors from each other. For example, the first pixel PX1 may emit red light, the second pixel PX2 may emit green light, and the third pixel PX3 may emit blue light. However, one or more embodiments are not limited thereto. Fig.11A In , the boundary of each pixel represents the boundary of the emission area.

[0250] At least one contact hole CNT may be arranged in each of the unit areas UA1, UA2, UA3, and UA4. FIG. 6A to FIG. 6C As described above, the contact hole CNT may be a hole configured to electrically connect the voltage line VL and the metal bank layer 300 to each other. In some embodiments, the contact hole CNT may be disposed between adjacent pixels in one unit region.

[0251] The first emission area EA1 of the first pixel PX1, the second emission area EA2 of the second pixel PX2, and the third emission area EA3 of the third pixel PX3 may have the same rectangular shape as each other and may be arranged in a matrix in a first direction (e.g., x direction) and in a second direction (e.g., y direction).

[0252] The distance between pixels emitting light of the same color in a first direction (e.g., x direction) may be substantially the same as the distance between pixels emitting light of the same color in a second direction (e.g., y direction). For example, a first distance d1 between the center of a second pixel PX2 arranged in the first unit area UA1 and the center of a second pixel PX2 arranged in the second unit area UA2 may be the same as a second distance d2 between the center of a second pixel PX2 arranged in the second unit area UA2 and the center of a second pixel PX2 arranged in the fourth unit area UA4. Therefore, the spacing between pixels may be uniformly formed.

[0253] The inorganic insulating layer IIL (see Fig.10 ) may be greater than the width of the valley V. Accordingly, the width of the segmentation area SA may be greater than the width of the middle area MA. Fig.11AWhen the pixel circuit of each pixel is arranged in the form shown in FIG. 1 , the pixel circuit of each pixel can be arranged inside the unit region. Accordingly, the center of the valley V can be formed to correspond to the center of the first opening IOP.

[0254] In some embodiments, the width of the first opening IOP may be substantially the same as or similar to the width of the valley V. In this case, the partition area SA and the middle area MA may have corresponding shapes.

[0255] refer to Fig. 11B , the first unit area UA1 and the second unit area UA2 may be arranged to be spaced apart from each other with the middle area MA between the first unit area UA1 and the second unit area UA2. The second unit area UA2 may be arranged to be spaced apart from the first unit area UA1 in a first direction (eg, x direction).

[0256] The middle area MA may be arranged such that the middle area MA surrounds the first unit area UA1 and the second unit area UA2. Fig.10 ) and encapsulation layer 500 (see Fig.10 )The valley V defined by the embodiment of the present invention may overlap with the middle area MA.

[0257] One or more pixels may be arranged in each of the first unit area UA1 and the second unit area UA2. In this regard, Fig. 11B Two pixels arranged in one unit area are illustrated. For example, the first pixel PX1 and the second pixel PX2 may be arranged in the first unit area UA1, and the third pixel PX3 and the second pixel PX2 may be arranged in the second unit area UA2. The first pixel PX1, the second pixel PX2, and the third pixel PX3 may emit light of different colors from each other. For example, the first pixel PX1 may emit red light, the second pixel PX2 may emit green light, and the third pixel PX3 may emit blue light. However, one or more embodiments are not limited thereto. Fig. 11B In , the boundary of each pixel represents the boundary of the emission area.

[0258] The emission areas EA1, EA2 and EA3 of each pixel can be arranged in a rhombus or honeycomb matrix structure. In this case, the pixel electrode of each pixel can deviate from the area where the pixel circuit is arranged. For example, the pixel electrode 410a of the first pixel PX1 can be located inside the boundary of the area where the pixel circuit is arranged, but the pixel electrode 410b can protrude outside the boundary where the pixel circuit is arranged.

[0259] Because the middle area MA does not overlap with the pixel electrode, and the segment area SA does not overlap with the pixel circuit, the width of the middle area MA can be smaller than the width of the segment area SA. In some embodiments, depending on the arrangement of the pixel electrodes, the middle area MA can have a shape different from the square lattice shape. In this case, the middle area MA and the segment area SA can be offset from each other.

[0260] At least one contact hole CNT may be disposed in each of the first unit area UA1 and the second unit area UA2 .

[0261] Fig.12 is a cross-sectional view schematically illustrating a display device 1 according to the embodiment. Fig.12 and Fig.10 Similar, except that the middle area MA and the segmented area SA are offset from each other.

[0262] refer to Fig.12 , the second emission element ED2 may protrude further toward the first unit area UA1 from the area where the second pixel circuit PC2 is arranged. Because the first opening IOP of the inorganic insulating layer IIL is arranged between the first pixel circuit PC1 and the second pixel circuit PC2, the first opening IOP of the inorganic insulating layer IIL may partially overlap with the second pixel electrode 412 of the second emission element ED2.

[0263] In some aspects, because the valley V is arranged between the first emission element ED1 and the second emission element ED2, the valley V and the first opening 10OP of the inorganic insulating layer 11L may be offset from each other. Accordingly, the partition area SA in which the first opening 10OP of the inorganic insulating layer 11L and the second opening 103OP of the first barrier layer 103 are arranged and the middle area MA in which the valley V is arranged may be offset from each other.

[0264] exist Fig.12 In the embodiment, a portion of the partition area SA overlaps a portion of the middle area MA. However, depending on the arrangement of the pixel circuit and the emission element, the partition area SA and the middle area MA may not overlap each other.

[0265] FIG. 13A to FIG. 13C is a diagram illustrating the elongation of each region of a substrate, an inorganic insulating film, and a wire when an inorganic insulating film is integrally formed on the entire surface of a substrate. FIG. 13A to FIG. 13C The diagram illustrates the results of simulated elongation of the substrate, the inorganic insulating film formed on the entire surface of the substrate, and the conductive line extending in the x direction across the substrate when the structure including the substrate, the inorganic insulating film, and the conductive line is stretched 5% in the x direction and the -x direction.

[0266] refer to FIG. 13A to FIG. 13C, the substrate has a total elongation of about 5% except for the two ends in the x direction, the inorganic insulating film has a total elongation of about 4.8% except for the two ends in the x direction, and the wire has a total elongation of about 4.8% except for the two ends in the x direction.

[0267] FIG. 14A to FIG. 14C is a diagram illustrating the elongation of each region of the substrate, the inorganic insulating film, and the wire when the inorganic insulating film is divided with the divided region therebetween. FIG. 14A to FIG. 14C The diagram shows the results of simulated elongation of the substrate, the inorganic insulating film formed by being divided with the divided area SA therebetween, and the conductive line extending in the x direction across the substrate when the structure including the substrate, the inorganic insulating film and the conductive line is stretched 5% in the x direction and the -x direction.

[0268] refer to FIG. 14A to FIG. 14C , the strain of the substrate may be concentrated in the segmentation area SA, and the substrate may have an elongation of about 16% in the center of the segmentation area SA, and the substrate may have an elongation of about 3% in the segmentation area SA and in the area other than the two ends in the x direction. The inorganic insulating film may be segmented into two parts with the segmentation area SA between the two parts, and it can be seen that the elongation of each of these parts has been reduced to about 3% or less. The conductive wire has an elongation of about 3% in the segmentation area SA and in the area other than the two ends in the x direction, but it is confirmed that the conductive wire has a slightly higher elongation of about 8% or more in the segmentation area SA.

[0269] Therefore, the structure in which the inorganic insulating film is divided with the divided area SA therebetween reduces the total elongation of each element, thereby reducing and preventing defects due to cracks and the like.

[0270] Fig.15 is a cross-sectional view schematically illustrating a display device 1 according to the embodiment. Fig.15 and Fig.10 Similar, except that the substrate 100 defines a recessed portion 100R overlapping the first opening IOP of the inorganic insulating layer IIL, and the bridge line BL has an arch shape.

[0271] refer to Fig.15 , the display device 1 may include a first unit area UA1, a second unit area UA2, a middle area MA, and a split area SA.

[0272] The substrate 100 may be provided such that a barrier layer which is an inorganic material layer and a base layer which is an organic material layer are alternately arranged with each other. For example, the substrate 100 may include a first base layer 101 and a second base layer 105 including an organic material and a first barrier layer 103 located between the first base layer 101 and the second base layer 105.

[0273] The substrate 100 may define a concave portion 100R that is concave from the uppermost surface of the substrate (eg, the upper surface of the second substrate layer 105) in a thickness direction (eg, ±z direction). The thickness direction indicates the thickness of the display device 1 (see Figure 1 For example, the recessed portion 100R may include a third opening 105OP defined in the second substrate layer 105, a second opening 103OP defined in the first barrier layer 103, and a first recess 101R defined in the first substrate layer 101.

[0274] The third opening 105OP may pass through the second base layer 105 and the second opening 103OP may pass through the first barrier layer 103, but the first recess 101R may not pass through the first base layer 101 and the first base layer 101 may constitute the bottom surface of the first recess 101R. Because the first base layer 101 is not completely separated by the first recess 101R, when the substrate 100 is separated from the mother substrate during the manufacturing process of the display device 1, the substrate 100 may be prevented from being torn along the recessed portion 100R. The inorganic insulating layer IIL may overlap the partition area SA and define the first opening IOP exposing the upper surface of the second base layer 105.

[0275] The first pixel circuit PC1, the second pixel circuit PC2 and the inorganic insulating layer IIL may be disposed on the substrate 100. The inorganic insulating layer IIL may include an inorganic material layer between the substrate 100 and the emission element layer EDL. For example, the inorganic insulating layer IIL may include a buffer layer 201, a first gate insulating layer 203, a second gate insulating layer 205, a first interlayer insulating layer 207, a third gate insulating layer 209 and a second interlayer insulating layer 211.

[0276] The inorganic insulating layer IIL may overlap the partition area SA and define a first opening IOP exposing the upper surface of the second base layer 105. A portion of the inorganic insulating layer IIL overlapping the first unit area UA1 and a portion of the inorganic insulating layer IIL overlapping the second unit area UA2 may be spaced apart from each other with the partition area SA between the portions of the inorganic insulating layer IIL.

[0277] The recessed portion 100R may overlap the partition area SA. In other words, the recessed portion 100R may overlap the first opening IOP of the inorganic insulating layer IIL. A side surface of the recessed portion 100R may extend from a side surface of the first opening IOP of the inorganic insulating layer IIL.

[0278] The first opening 1OP of the inorganic insulating layer 11L and the recessed portion 100R of the substrate 100 may be filled with a filler layer 217. In some embodiments, the upper surface of the filler layer 217 may be located at the same or similar level as the level at which the upper surface of the second interlayer insulating layer 211 is located. In some embodiments, the upper surface of the filler layer 217 may have a convex shape higher than the upper surface of the second interlayer insulating layer 211, a concave shape lower than the upper surface of the second interlayer insulating layer 211, or a shape having an uneven portion including one or more protrusions and / or one or more recesses. In some embodiments, the upper surface of the filler layer 217 may have a shape with an uneven portion in which protrusions and recesses alternate with each other.

[0279] On this point, Fig.15 It is illustrated that the upper surface of the packing layer 217 has a convex shape. Since the upper surface of the packing layer 217 has a convex shape, the bridge line BL disposed on the packing layer 217 may have an arch shape. The bridge line BL having the arch shape may be more robust against stretching.

[0280] The filler layer 217 may include a polymer material. The polymer material may include, for example, acrylic resin, epoxy resin, polyimide, and polyethylene. The filler layer 217 may have a relatively low modulus. The modulus of the filler layer 217 may be about 3 MPa to about 20 MPa.

[0281] The bridge line BL may be disposed on the filler layer 217 and connect the elements of the first pixel circuit PC1 and the corresponding elements of the second pixel circuit PC2 to each other. The bridge line BL may be arranged between the filler layer 217 and the first planarization layer 213 .

[0282] Because the partition area SA overlaps the middle area MA, the first opening IOP may overlap the valley V. In some embodiments, the width of the middle area MA may be smaller than the width of the partition area SA. In some embodiments, the width of the middle area MA may be the same as the width of the partition area SA.

[0283] When the display device 1 is stretched or bent, stress may be concentrated on the filler layer 217 having a relatively low modulus. Therefore, cracks and the like in the inorganic films included in the substrate 100, the inorganic insulating layer IIL, the emission element layer EDL, and the encapsulation layer 500 may be prevented or reduced. The display device 1 may have a more robust structure resistant to stretching.

[0284] FIG. 16A to FIG. 16F is a cross-sectional view schematically illustrating a bridge line included in a display device according to one or more embodiments. FIG. 16A to FIG. 16F Pictured Fig.15 An enlarged portion of the display device 1 is shown in FIG.

[0285] refer to Fig.16A and Fig. 16B The filler layer 217 may fill the first opening IOP defined in the inorganic insulating layer IIL. The upper surface of the filler layer 217 may have a convex shape higher than the upper surface of the inorganic insulating layer IIL. The bridge line BL extending along the upper surface of the filler layer 217 may have an arch shape. The bridge line BL may be as shown in FIG. Fig.16A The arc shape with a single curvature as shown in FIG. 1 or can be as shown in FIG. Fig. 16B An arched shape with double curvature is shown in FIG.

[0286] The organic insulating layer OIL may be disposed on the inorganic insulating layer IIL and the filler layer 217 and cover the bridge line BL. The organic insulating layer OIL may include a first planarization layer 213 and a second planarization layer 215.

[0287] refer to Fig. 16C and Fig.16D , the upper surface of the packing layer 217 may have a concavo-convex shape in which protrusions 217p convex compared to the surrounding area and recesses 217r concave compared to the surrounding area are alternately arranged with each other. The angle θ formed between the upper surface and the side surface of the protrusion 217p may be as follows: Fig. 16C The diagram shows a right angle, or it can be Fig.16D The bridge line BL may have a shape corresponding to the upper surface of the filler layer 217. In other words, the bridge line BL may have a swing shape along the uneven portion.

[0288] refer to Fig.16E , the upper surface of the packing layer 217 may include a recess 217r that is recessed compared to the surrounding area. In some embodiments, the bottom surface of the recess 217r may be flat, but the side surface of the recess 217r may be gently curved (e.g., having a curvature). The bridge line BL may have a shape corresponding to the upper surface of the packing layer 217.

[0289] refer to Fig.16F , the upper surface of the packing layer 217 may include a recess 217r that is recessed compared to the surrounding area, and the bridge line BL may have a double bridge structure including a first bridge line L1 corresponding to the upper surface of the packing layer 217 and a second bridge line L2 disposed on the first bridge line L1. In some embodiments, an upper packing layer filled in the recess 217r may be further disposed between the first bridge line L1 and the second bridge line L2, and the center of the upper packing layer may have a convex shape. Accordingly, the first bridge line L1 may have a concave shape in the thickness direction (e.g., z direction), and the second bridge line L2 may have an arched shape.

[0290] FIG. 16A to FIG. 16FThe structure of the filler layer 217 and the bridge line BL illustrated in FIG. 2 may disperse strain concentrated in some areas of the bridge line BL, thereby preventing or reducing cracks in the bridge line BL when the display device is stretched.

[0291] Fig.17 is a graph illustrating a division width strain rate according to the width of the division region, and Fig.18 is a graph illustrating the elongation of the inorganic insulating layer and the elongation of the bridge line according to the modulus of the filler layer.

[0292] Fig.17 The diagram shows the results of simulating the strain rate of the segmentation (region) width according to the initial width of the segmentation region when a structure including a substrate having a recessed portion overlapping the segmentation region, an inorganic insulating film formed by being segmented with the segmentation region therebetween, and a conductive line extending in the x-direction across the substrate is stretched in one axial direction.

[0293] See also Fig.17 , the larger the initial width of the segmented region, the smaller the segmented width strain rate according to the increase in the width of the segmented region. For example, when the initial width of the segmented region is 4 μm and the substrate is stretched by 5%, it can be seen that the segmented width is deformed by about 170%, and when the initial width is 8 μm and the substrate is stretched by 5%, it can be seen that the segmented width is deformed by about 150%. Therefore, as the width of the segmented region increases, the segmented width strain rate decreases, but the resolution of the display device may decrease.

[0294] Fig.18 The diagram shows the results of simulating the strain rate of each of the inorganic insulating film IIL and the wire BL according to the modulus of the filler layer filled in the recessed portion when a structure including a substrate having a recessed portion overlapping a segmentation region, an inorganic insulating film formed by being segmented with the segmentation region therebetween, and a wire extending in the x-direction across the substrate is stretched by 5% in one axial direction.

[0295] refer to Fig.18 , when the modulus of the filler layer is 20 MPa or less, it can be seen that the elongation of the inorganic insulating film IIL is 0.13% or less, and the elongation of the wire BL is about 2.01% or less.

[0296] Because the threshold elongation for cracks to occur in the conductor BL is 2.0% and the threshold elongation for cracks to occur in the inorganic insulating film IIL is 0.7%, even when the substrate is stretched by 5%, cracks in the inorganic insulating film IIL and the conductor BL can be prevented or reduced when the modulus of the filler layer is approximately 3 MPa to approximately 20 MPa.

[0297] Fig.19is a cross-sectional view schematically illustrating a display device 1 according to the embodiment. Fig.19 and Figure 5 Similar to the embodiment of the present invention, the difference is that the touch sensor layer 700 further includes a third touch insulation layer 730 .

[0298] refer to Fig.19 The display device 1 according to the embodiment may include a substrate 100, first and second pixel circuits PC1 and PC2 disposed on the substrate 100, a first emission element ED1 electrically connected to the first pixel circuit PC1, and a second emission element ED2 electrically connected to the second pixel circuit PC2.

[0299] The display device 1 may include a first unit area UA1 in which the first emission element ED1 is arranged, a second unit area UA2 in which the second emission element ED2 is arranged, and a middle area MA between the first unit area UA1 and the second unit area UA2 .

[0300] The first pixel circuit PC1, the second pixel circuit PC2 and the inorganic insulating layer IIL may be disposed on the substrate 100. The inorganic insulating layer IIL may include an inorganic material layer between the substrate 100 and the emission element layer EDL. For example, the inorganic insulating layer IIL may include a buffer layer 201, a first gate insulating layer 203, a second gate insulating layer 205, a first interlayer insulating layer 207, a third gate insulating layer 209 and a second interlayer insulating layer 211.

[0301] Elements of the first pixel circuit PC1 and the second pixel circuit PC2 may be connected to each other via a connection line CL. Fig.19 In the embodiment, the connection line CL is disposed between the first gate insulating layer 203 and the second gate insulating layer 205. However, one or more embodiments are not limited thereto.

[0302] The organic insulating layer OIL including the first planarizing layer 213 and the second planarizing layer 215 may be disposed on the inorganic insulating layer IIL. The first and second connection electrodes CM1 and CM2 may be disposed between the first and second planarizing layers 213 and 215.

[0303] The first emission element ED1, the second emission element ED2, and the emission element layer EDL including the inorganic bank layer 250 and the metal bank layer 300 may be disposed on the organic insulating layer OIL. The first emission element ED1 may be disposed such that the first emission element ED1 overlaps the first unit area UA1, and the second emission element ED2 may be disposed such that the second emission element ED2 overlaps the second unit area UA2.

[0304] The first emission element ED1 may include a first pixel electrode 411, a first counter electrode 431, and a first intermediate layer 421 disposed therebetween. The second emission element ED2 may include a second pixel electrode 412, a second counter electrode 432, and a second intermediate layer 422 disposed therebetween.

[0305] The first emission element ED1 may be electrically connected to the first pixel circuit PC1 via the first connection electrode CM1. The second emission element ED2 may be electrically connected to the second pixel circuit PC2 through the second connection electrode CM2.

[0306] The inorganic bank barrier layer 250 may be disposed on the organic insulating layer OIL and cover an edge of each of the first pixel electrode 411 of the first emission element ED1 and the second pixel electrode 412 of the second emission element ED2. The inorganic bank barrier layer 250 may define a pixel opening exposing a portion of each of the first pixel electrode 411 and the second pixel electrode 412. The metal bank barrier layer 300 may be disposed on the inorganic bank barrier layer 250. The metal bank barrier layer 300 may include a first metal layer 310 and a second metal layer 320 disposed on the first metal layer 310.

[0307] The first counter electrode 431 may directly contact a side surface of the first metal layer 310 facing the center of the pixel opening. The second counter electrode 432 may directly contact a side surface of the first metal layer 310 facing the center of the pixel opening.

[0308] The encapsulation layer 500 may be disposed on the emission element layer EDL. The encapsulation layer 500 may include a first inorganic encapsulation layer 511 overlapping the first unit area UA1, a second inorganic encapsulation layer 512 overlapping the second unit area UA2, a third inorganic encapsulation layer 531 disposed on the first inorganic encapsulation layer 511, a fourth inorganic encapsulation layer 532 disposed on the second inorganic encapsulation layer 512, a first organic encapsulation layer 521 disposed between the first inorganic encapsulation layer 511 and the third inorganic encapsulation layer 531, and a second organic encapsulation layer 522 disposed between the second inorganic encapsulation layer 512 and the fourth inorganic encapsulation layer 532.

[0309] The first organic encapsulation layer 521 and the second organic encapsulation layer 522 may be patterned to correspond to each emission element, or may be patterned so that the first organic encapsulation layer 521 and the second organic encapsulation layer 522 overlap with the emission elements arranged in each unit area. In some embodiments, the first organic encapsulation layer 521 and the second organic encapsulation layer 522 may be omitted.

[0310] The emission element layer EDL and the encapsulation layer 500 may define a valley V overlapping the middle area MA and exposing the upper surface of the organic insulation layer OIL. The valley V may be arranged such that the valley V surrounds the first and second unit areas UA1 and UA2.

[0311] In the middle area MA, the inorganic material layer may not be disposed between the organic insulating layer OIL and the third planarization layer 600 .

[0312] In some embodiments, as shown in reference Fig.10 As described above, the display device 1 may include a segmentation area SA overlapping the second opening 103OP defined in the first barrier layer 103 and / or the first opening 10OP defined in the inorganic insulating layer 11L. Fig.15 As described above, the display device 1 may include the partition area SA overlapping the first opening IOP defined by the inorganic insulating layer IIL and the concave portion 100R defined in the substrate 100 .

[0313] The third planarization layer 600 may be disposed on the encapsulation layer 500 , and the touch sensor layer 700 may be disposed on the third planarization layer 600 .

[0314] The touch sensor layer 700 may include a first touch electrode 710 , a second touch electrode 720 , a first touch insulating layer 701 between the first touch electrode 710 and the second touch electrode 720 , a second touch insulating layer 703 on the second touch electrode 720 , and a third touch insulating layer 730 under the first touch electrode 710 .

[0315] Since the third planarization layer 600 includes an organic material, in order to prevent damage to the first touch electrode 710 due to the third planarization layer 600 during a manufacturing process, a third touch insulating layer 730 may be disposed between the third planarization layer 600 and the first touch electrode 710. The third touch insulating layer 730 may include an inorganic material such as silicon oxide, silicon nitride, and / or silicon oxynitride.

[0316] Since the first touch electrode 710 and the second touch electrode 720 are arranged so that the first touch electrode 710 and the second touch electrode 720 overlap the valley V, cracks may occur in the third touch insulating layer 730 including an inorganic material. In order to minimize cracks caused by the third touch insulating layer 730, the third touch insulating layer 730 may have a shape corresponding to that of the first touch electrode 710. In other words, the third touch insulating layer 730 may be patterned by using the same mask as the first touch electrode 710.

[0317] Therefore, the area of ​​the third touch insulation layer 730 may be minimized, so that the display device 1 may have a more robust anti-stretching structure.

[0318] FIG. 20A to FIG. 20G is a perspective view schematically illustrating one or more embodiments of an electronic device including a display device according to the embodiments.

[0319] refer to Fig. 20A The display device according to the embodiment may be used in a wearable electronic device 3100 that can be worn on a part of a user's body. The wearable electronic device 3100 may include a main body unit 3110 and a display unit 3120 provided on the main body unit 3110. The display device according to one or more embodiments may be used as the display unit 3120 of the wearable electronic device 3100. Fig. 20A As shown in , the wearable electronic device 3100 may be deformable. In an embodiment, the wearable electronic device 3100 may be used as a smart watch or a smart phone depending on the user's choice.

[0320] Fig. 20B A medical electronic device 3200 is illustrated. In an embodiment, the medical electronic device 3200 may include a main unit 3210 and a transmitting unit 3220. The display device according to one or more embodiments may be used as the transmitting unit 3220 of the medical electronic device 3200. The transmitting unit 3220 may transmit light of a specific wavelength band (e.g., infrared light and visible light, etc.) to the patient's body. In an embodiment, the main unit 3210 may have a stretchable fiber material and may have a structure that can be worn on the body of a user of the transmitting unit.

[0321] Fig. 20C An educational electronic device 3300 is illustrated. In an embodiment, the educational electronic device 3300 may include a display unit 3320 provided in a frame 3310. A display device according to one or more embodiments may be used as the display unit 3320. The display unit 3320 may provide an image such as an ocean with waves, a snow-covered mountain, or a volcano with flowing lava, and in this case, the display unit 3320 may reflect the height of the waves, the mountain, or the volcano and may be stretched in the height direction (e.g., the z direction). In some embodiments, a portion of the display unit 3320 may illustrate the movement of the lava in three dimensions by sequentially changing the height in the direction in which the lava flows. The educational electronic device 3300 may include a plurality of pins (or stroke units) 3330 arranged on the rear surface of the display unit 3320 so that the display unit 3320 extends in the height direction. As the pins 3330 move in a third direction (e.g., the z direction or the -z direction), the image represented on the display unit 3320 may be implemented to have a three-dimensional height. Fig. 20C The educational electronic device 3300 is illustrated, but the use of the device is not limited as long as the educational electronic device 3300 provides specific image information.

[0322] FIG. 20A to FIG. 20C The electronic device illustrated in the figure is described as an electronic device having a variable shape, but one or more embodiments are not limited thereto. In one or more embodiments as described herein, the display device according to one or more embodiments can be used in an electronic device in which a portion (e.g., a screen) capable of displaying an image is fixed.

[0323] Fig.20D A robot 3400 as an electronic device according to an embodiment is illustrated. The robot 3400 can recognize motion or an object by using a camera unit 3440, and can display a specific image to a user through display units 3420 and 3430. In some embodiments, since the display device according to the embodiment can be stretched in various directions as described herein, the display device can be assembled together with a main body frame having a hemispherical shape, and accordingly, the robot 3400 can include display units 3420 and 3430 having hemispherical display units.

[0324] Fig.20E A vehicle display device 3500 is illustrated as an electronic device according to an embodiment. The vehicle display device 3500 may include an instrument panel 3510, a central information display (CID) 3520, and / or a passenger driver display 3530. Since the display device according to the embodiment can be stretched in various directions, the display device can be used in the instrument panel 3510, the CID 3520, and / or the passenger driver display 3530 regardless of the shape of the internal frame.

[0325] Fig.20E The instrument panel 3510, CID 3520 and / or co-pilot display 3530 are shown as being separated from each other. However, one or more embodiments are not limited thereto. In another embodiment, at least two selected from the instrument panel 3510, CID 3520 and co-pilot display 3530 may be integrally connected as a single body.

[0326] In some embodiments, the vehicle display device 3500 may include a button 3540 for displaying a specific image. Fig.20E , the button 3540 having a hemispherical shape may include an object 3542 for providing a feeling of using the button while moving in the z direction or the -z direction, and a display device disposed on the object 3542. In some embodiments, when the object 3542 has a three-dimensional circular surface, the display device may also have a three-dimensional circular surface.

[0327] Fig.20FThe electronic device according to the embodiment is illustrated as an electronic device 3600 for advertisement or exhibition. In some embodiments, the electronic device 3600 for advertisement or exhibition can be installed on a fixed structure 3610 such as a wall or a pillar. Fig.20F As shown in FIG. 36 , when the structure 3610 includes an uneven surface, the electronic device 3600 for advertisement or exhibition may also be arranged along the uneven surface of the structure 3610. In some embodiments, the electronic device 3600 for advertisement or exhibition may be mounted on the structure 3610 by using a heat shrink film or the like.

[0328] Figure 20G An example in which the electronic device according to the embodiment is a controller 3700 is illustrated. The controller 3700 may include an image-type button. For example, the controller 3700 may include a first button area to a third button area 3720, 3730, and 3740, wherein a partial area of ​​the display unit 3710 protrudes in the z direction or in the -z direction (or is recessed in the z direction). In some embodiments, the first button area 3720 and the third button area 3740 may protrude in the z direction, and the second button area 3730 may protrude in the -z direction (or be recessed in the z direction).

[0329] According to the embodiment, a display device that can be stretched in various directions while preventing damage due to concentration of stress can be provided. However, these effects are examples, and the scope of one or more embodiments is not limited by these effects.

[0330] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for the purpose of limitation. The description of features or aspects within each embodiment should generally be considered to be applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and details may be made thereto without departing from the spirit and scope defined by the claims.

Claims

1. A display device, comprising: A substrate comprising a first unit region, a second unit region, and an intermediate region between the first unit region and the second unit region; An organic insulating layer, disposed on the substrate; an emission element layer, disposed on the organic insulating layer, the emission element layer comprising a first emission element overlapping the first unit region and a second emission element overlapping the second unit region; as well as A packaging layer, disposed on the emitting element layer; The emission element layer and the encapsulation layer define a valley portion overlapping the middle region and exposing an upper surface of the organic insulating layer.

2. The display device according to claim 1, wherein: Each of the first emission element and the second emission element includes a pixel electrode, a counter electrode, and an emission layer arranged between the pixel electrode and the counter electrode. The emission element layer further comprises: an inorganic bank layer disposed on the organic insulating layer and defining a pixel opening exposing a portion of the pixel electrode; and a metal dam layer, disposed on the inorganic dam layer and comprising a first metal layer and a second metal layer disposed on the first metal layer, The first metal layer defines a first bank opening overlapping the pixel opening, and The second metal layer defines a second bank opening overlapping the pixel opening.

3. The display device according to claim 2, wherein: The width of the first dam opening is greater than the width of the second dam opening.

4. The display device according to claim 2, wherein: The inorganic barrier layer and the metal barrier layer are arranged apart from the middle region.

5. The display device according to claim 4, wherein: The encapsulation layer covers a side surface of the metal bank layer facing the middle region.

6. The display device according to claim 5, further comprising: A covering layer is provided between the encapsulation layer and the side surface of the metal barrier layer facing the middle region.

7. The display device according to claim 2, further comprising: a voltage line disposed under the organic insulating layer and configured to transmit a common power supply voltage, The metal bank layer is electrically connected to the voltage line through one or more contact holes defined in the inorganic bank layer and the organic insulating layer.

8. The display device according to claim 7, wherein: The one or more contact holes include a plurality of contact holes, wherein a first contact hole of the plurality of contact holes is located in the first cell region, and a second contact hole of the plurality of contact holes is located in the second cell region.

9. The display device according to claim 2, wherein: The counter electrode is in direct contact with a side surface of the first metal layer facing the center of the pixel opening.

10. The display device according to claim 1, wherein: The encapsulation layer comprises: a first inorganic encapsulation layer, overlapping the first unit region; a second inorganic encapsulation layer, overlapping the second unit region; a third inorganic encapsulation layer, disposed on the first inorganic encapsulation layer; and The fourth inorganic encapsulation layer is disposed on the second inorganic encapsulation layer.

11. The display device according to claim 10, wherein: The encapsulation layer further comprises: a first organic encapsulation layer disposed between the first inorganic encapsulation layer and the third inorganic encapsulation layer; and The second organic encapsulation layer is arranged between the second inorganic encapsulation layer and the fourth inorganic encapsulation layer.

12. The display device according to claim 11, wherein: The emission element layer further includes a third emission element overlapping the first unit region and spaced apart from the first emission element. The encapsulation layer further includes a third organic encapsulation layer between the first inorganic encapsulation layer and the third inorganic encapsulation layer, The first organic encapsulation layer is arranged such that the first organic encapsulation layer overlaps the first emission element, and The third organic encapsulation layer overlaps the third emission element and is arranged spaced apart from the first organic encapsulation layer.

13. The display device according to claim 11, wherein: The emission element layer further includes a third emission element overlapping the first unit region and spaced apart from the first emission element, and The first organic encapsulating layer is arranged such that the first organic encapsulating layer overlaps the first emitting element and the third emitting element.

14. The display device according to claim 10, wherein: The second inorganic encapsulating layer and the fourth inorganic encapsulating layer are arranged to be spaced apart from each other and the intermediate region is between the second inorganic encapsulating layer and the fourth inorganic encapsulating layer.

15. The display device according to claim 10, wherein: The second inorganic encapsulating layer and the fourth inorganic encapsulating layer constitute side surfaces of the valley portion.

16. The display device according to claim 1, further comprising: an inorganic insulating layer, between the substrate and the organic insulating layer, The inorganic insulating layer defines a first opening overlapping the middle region.

17. The display device according to claim 16, wherein: The substrate comprises at least one base layer and at least one barrier layer, and The at least one barrier layer defines a second opening overlapping the first opening.

18. The display device according to claim 16, wherein: A center of the first opening and a center of the valley are offset from each other.

19. The display device according to claim 16, further comprising: a packing layer, filling the first opening, Wherein, the modulus of the filler layer is 3MPa to 20MPa.

20. The display device according to claim 19, wherein: The substrate defines a recessed portion overlapping the first opening and recessed in a thickness direction, and The filler layer fills the recessed portion.

21. The display device according to claim 19, further comprising: A bridge line is disposed on the inorganic insulating layer and the filler layer and spans across the first opening.

22. The display device according to claim 21, wherein: The bridge line has an arch shape.

23. The display device according to claim 21, wherein: The upper surface of the packing layer has unevenness, and The bridging line has a shape corresponding to a shape of the upper surface of the packing layer.

24. The display device according to claim 21, wherein: The bridge line comprises: a first bridging line having a concave shape in a thickness direction; and The second bridge wire is disposed on the first bridge wire and has an arch shape.

25. The display device according to any one of claims 1 to 24, further comprising: A planarization layer, disposed on the encapsulation layer; as well as a touch sensor layer, disposed on the planarization layer, the touch sensor layer comprising a first touch electrode, a second touch electrode, a first touch insulating layer between the planarization layer and the first touch electrode, and a second touch insulating layer between the first touch electrode and the second touch electrode, Wherein, in a plan view, a shape of the first touch insulating layer corresponds to a shape of the first touch electrode.

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