Display device and method of manufacturing same

Abstract

The invention discloses a display device and a manufacturing method thereof. The display device includes: a display panel including a display area and a non-display area, in which the display panel includes: a substrate layer overlapping the display area and the non-display area; a pad electrode exposed through a lower surface of the base layer; a pixel disposed on an upper surface of the base layer and including a light emitting element overlapping the display area; a data line disposed on an upper surface of the base layer and overlapping the display area and the non-display area, and electrically connected to the pad electrode; and an electrostatic protection circuit electrically connected to the data line, in which the electrostatic protection circuit includes a first diode disposed in the non-display area and a second diode overlapping at least a portion of the first diode in a plan view.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0134748 filed in the Korean Intellectual Property Office on October 11, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device capable of back-side bonding with a flexible circuit board and a method for manufacturing the same. Background Art

[0004] Electronic devices such as smart phones, tablet computers, notebook computers, car navigation systems, and smart TVs are being developed. These electronic devices may be equipped with display devices to provide information.

[0005] Various types of display devices are being developed to satisfy users' UX / UI (or user experience / user interface). Display devices are being developed to provide not only a wide display area but also a narrow non-display area. Summary of the invention

[0006] The present disclosure provides a display device having a reduced non-display area and a method of manufacturing the display device.

[0007] Embodiments of the present disclosure (or inventive concept) provide a display device, which may include: a display panel including a display area and a non-display area, wherein the display panel may include: a substrate layer overlapping the display area and the non-display area and including a lower surface and an upper surface opposite to the lower surface; a pad electrode exposed through the lower surface of the substrate layer; a pixel disposed on the upper surface of the substrate layer and including a light emitting element overlapping the display area and a transistor electrically connected to the light emitting element; a data line disposed on the upper surface of the substrate layer, overlapping the display area and the non-display area, and electrically connected to the transistor; an electrostatic protection circuit electrically connected to the data line; and a connecting electrode electrically connecting the data line and the pad electrode to each other in the non-display area, wherein the electrostatic protection circuit may include: a first diode disposed in the non-display area; and a second diode disposed on the first diode and overlapping at least a portion of the first diode in a plan view. The first diode may include a silicon semiconductor, and the second diode may include an oxide semiconductor.

[0008] In an embodiment, the second diode may completely overlap the first diode.

[0009] In an embodiment, the data line may extend in a first direction, and a length of the electrostatic protection circuit in the first direction may be in a range of about 200 micrometers to about 300 micrometers.

[0010] In an embodiment, the display panel may further include a plurality of insulating layers disposed on the upper surface of the base layer. The connection electrode may be electrically connected to the pad electrode through a first contact hole, the first contact hole may pass through at least one of the plurality of insulating layers and may be defined in the base layer, and the connection electrode may be electrically connected to the data line through a second contact hole passing through at least one of the plurality of insulating layers.

[0011] In an embodiment, the base layer may include: a first synthetic resin layer providing a lower surface of the base layer and having a first opening, the first opening exposing the pad electrode; a first inorganic base layer disposed on the first synthetic resin layer and having a second opening, the second opening exposing the pad electrode, the second opening corresponding to the first opening; a second inorganic base layer disposed on the first inorganic base layer and covering the pad electrode; and a second synthetic resin layer disposed on the second inorganic base layer. The first contact hole may pass through the second synthetic resin layer and the second inorganic base layer.

[0012] In an embodiment, the display panel may further include an additional electrostatic protection circuit electrically connected to the data line and disposed closer to the display area than the electrostatic protection circuit.

[0013] In an embodiment, the plurality of insulating layers may include a first inorganic insulating layer. At least a portion of the first diode may be disposed below the first inorganic insulating layer, and the second diode may be disposed above the first inorganic insulating layer.

[0014] In an embodiment, the first diode may include a first pattern disposed under the first inorganic insulating layer, the first pattern may include a silicon semiconductor, and the second diode may include a second pattern disposed over the first inorganic insulating layer, the second pattern may include an oxide semiconductor.

[0015] In an embodiment, the first pattern and the second pattern may overlap each other in a plan view.

[0016] In an embodiment, the substrate layer may include a first substrate portion overlapping the display area and a second substrate portion protruding from the first substrate portion in a first direction. The width of the second substrate portion in a second direction intersecting the first direction may be smaller than the width of the first substrate portion, and the electrostatic protection circuit may be disposed on the second substrate portion.

[0017] In an embodiment, the display panel may further include a lighting pad line disposed on the second substrate portion, extending to an end of the second substrate portion, and having a width greater than that of the data line.

[0018] In an embodiment, the display panel may further include a molding portion covering an end of the second substrate portion.

[0019] In an embodiment, the data line may extend in a first direction, and the electrostatic protection circuit may include a plurality of electrostatic protection circuit portions spaced apart from each other in a second direction crossing the first direction.

[0020] In an embodiment, the transistor may include a silicon transistor including a silicon semiconductor and an oxide transistor disposed on the silicon transistor and including an oxide semiconductor. The first diode may be disposed in the same layer as the silicon transistor, and the second diode may be disposed in the same layer as the oxide transistor.

[0021] In an embodiment of the present disclosure, a display device may include a display panel, the display panel including a display area and a non-display area. The display panel may include: a substrate layer, overlapping the display area and the non-display area and including a lower surface and an upper surface opposite to the lower surface; a pad electrode, exposed through the lower surface of the substrate layer; a pixel, arranged on the upper surface of the substrate layer and including a light-emitting element overlapping the display area and a transistor electrically connected to the light-emitting element; a data line, arranged on the upper surface of the substrate layer, overlapping the display area and the non-display area, and electrically connected to the transistor; and an electrostatic protection circuit, electrically connected to the data line. The electrostatic protection circuit may include: a first diode, arranged in the non-display area and including a silicon semiconductor; and a second diode, arranged on the first diode and including an oxide semiconductor.

[0022] In an embodiment of the present disclosure, a method for manufacturing a display device including a display area and a non-display area, the method may include: performing a test by applying a voltage via a retest pad disposed in the non-display area and removing a portion of the non-display area. During the execution of the test, an electrostatic protection circuit may be electrically connected to the retest pad. The electrostatic protection circuit includes: a first diode disposed in the non-display area; and a second diode disposed on the first diode and overlapping at least a portion of the first diode in a plan view.

[0023] In an embodiment, in the removal of a portion of the non-display area, a first portion in which the retest pad is disposed may be removed.

[0024] In an embodiment, in the removal of a portion of the non-display area, a first portion in which the retest pad is disposed and a second portion in which the electrostatic protection circuit is disposed may be removed.

[0025] In an embodiment of the present disclosure, the method of manufacturing a display device may further include: after removing the portion of the non-display area, forming a molding portion to cover at least a portion of the non-display area. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the disclosure and together with the description serve to explain the principles of the disclosure.

[0027] In the attached picture:

[0028] Figure 1 is a perspective view of an electronic device according to an embodiment of the present disclosure;

[0029] Figure 2 is an exploded perspective view of an electronic device according to an embodiment of the present disclosure;

[0030] Figure 3 is a display device according to an embodiment of the present disclosure corresponding to Figure 2 A schematic cross-sectional view of line II' in FIG.

[0031] Figure 4 is a simplified schematic cross-sectional view of a display module according to an embodiment of the present disclosure;

[0032] Figure 5 is a plan view of a display panel according to an embodiment of the present disclosure;

[0033] Figure 6 is a schematic cross-sectional view of a display module according to an embodiment of the present disclosure;

[0034] Fig. 7A is a plan view of an input sensor according to an embodiment of the present disclosure;

[0035] Figure 7B is the input sensor corresponding to Fig. 7A A schematic cross-sectional view of line II-II' in FIG.

[0036] Figure 8 is an enlarged plan view of a non-display area of ​​a display module according to an embodiment of the present disclosure;

[0037] Fig.9A is an enlarged plan view of a non-display area of ​​a display module according to an embodiment of the present disclosure;

[0038] Fig. 9B The display module corresponds to Fig.9A A schematic cross-sectional view of line III-III';

[0039] Fig. 9C yes Fig.9A A schematic diagram of an additional electrostatic protection circuit is shown in FIG.

[0040] Fig. 10A is an enlarged plan view of a non-display area of ​​a display module according to an embodiment of the present disclosure;

[0041] Fig. 10B Is the display module corresponding to Fig. 10A A schematic cross-sectional view of line IV-IV';

[0042] Fig. 10C yes Fig. 10B A schematic diagram of an electrostatic protection circuit portion shown in FIG.

[0043] Fig.11A and Fig. 11B is a plan view of an electrostatic protection circuit portion according to an embodiment of the present disclosure;

[0044] Fig.12 Is the display module corresponding to Fig. 10A A schematic cross-sectional view of line V-V';

[0045] Fig.13 is a flowchart illustrating a method of manufacturing a display device according to an embodiment of the present disclosure; and

[0046] FIG. 14A to FIG. 14C is a plan view illustrating steps of a method of manufacturing a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0047] In the following description, for the purpose of explanation, many specific details are set forth in order to provide a thorough understanding of various embodiments or implementations of the present disclosure. As used herein, "embodiment" and "implementation" are interchangeable words for non-limiting examples of the apparatus or method disclosed herein. However, it is apparent that various embodiments may be practiced without these specific details or with one or more equivalent arrangements. Here, various embodiments do not have to be exclusive and do not limit the present disclosure. For example, the specific shape, configuration, and characteristics of one embodiment may be used or implemented in another embodiment.

[0048] Unless otherwise specified, the illustrated embodiments will be understood to provide features of the present disclosure. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects of various embodiments (hereinafter individually or collectively referred to as "elements") may be combined, separated, interchanged and / or rearranged in other ways without departing from the present invention.

[0049] The use of cross hatching and / or shadows in the accompanying drawings is generally provided to make the boundaries between adjacent elements clear. Therefore, unless otherwise specified, the presence or absence of cross hatching or shadows does not convey or indicate any preference or demand for a specific material, material properties, size, ratio, commonality between the illustrated elements and / or any other features, attributes, properties, etc. of the elements. In addition, in the accompanying drawings, the size and relative size of the elements may be exaggerated for clarity and / or descriptive purposes. When the embodiment can be implemented in different ways, the specific process sequence can be performed differently from the described order. For example, two processes described in succession can be performed substantially simultaneously or in an order opposite to the described order. In addition, the same reference numerals and / or reference characters represent the same elements.

[0050] When an element or layer is referred to as being "on" another element or layer, "connected to" or "coupled to" another element or layer, the element or layer may be directly on, directly connected to or coupled to the other element or layer, or there may be an intervening element or layer. However, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. For this reason, the term "connection" may refer to a physical connection, an electrical connection, and / or a fluid connection with or without an intervening element. In addition, the X-axis, the Y-axis, and the Z-axis are not limited to the three axes of a rectangular coordinate system (such as an x-axis, a y-axis, and a z-axis), and may be interpreted in a broader sense. For example, the X-axis, the Y-axis, and the Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other.

[0051] For the purpose of this disclosure, "at least one of A and B" may be understood as only A, only B, or any combination of A and B. In addition, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0052] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, the first element discussed below may be referred to as the second element without departing from the teachings of the present disclosure.

[0053] For descriptive purposes, spatially relative terms such as "below," "below," "under," "down," "above," "on," "above," "above," "side" (e.g., as in "sidewall") may be used herein and thereby describe the relationship of one element to another element(s) as shown in the figures. In addition to the orientations depicted in the figures, spatially relative terms are intended to cover different orientations of the device in use, operation, and / or manufacture. For example, if the device in the figure is flipped, an element described as being "below" or "below" other elements or features will then be oriented to be "above" the other elements or features. Thus, the term "below" can cover both above and below orientations. In addition, the device can be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and therefore, the spatially relative descriptors used herein should be interpreted accordingly.

[0054] The terms used herein are only for the purpose of describing specific embodiments, and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "one", "the (described)" as used herein are also intended to include plural forms. In addition, when used in this specification, the terms "include" and / or "comprise" indicate that there are stated features, integral bodies, steps, operations, elements, parts and / or their groups, but do not exclude the presence or addition of one or more other features, integral bodies, steps, operations, elements, parts and / or their groups. It should also be noted that, as used herein, the terms "substantially", "about" and other similar terms are used as approximate terms and not as terms of degree, and are therefore used to include the inherent deviations in the values ​​measured, calculated and / or provided that are recognized by those of ordinary skill in the art.

[0055] Various embodiments are described herein with reference to cross-sectional views and / or exploded views, which are schematic diagrams of embodiments and / or intermediate structures. Therefore, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances should be expected. Therefore, the embodiments disclosed herein should not necessarily be interpreted as being limited to the shapes of the specifically illustrated areas, but rather include shape deviations caused by, for example, manufacturing. In this way, the areas shown in the drawings may be schematic in nature, and the shapes of these areas may not reflect the actual shapes of the areas of the device, and therefore, are not necessarily intended to be limiting.

[0056] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and should not be interpreted in an idealized or overly formal sense, unless clearly defined as such herein.

[0057] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0058] Figure 1 is a perspective view of an electronic device ED according to an embodiment of the present disclosure. Figure 2 is an exploded perspective view of an electronic device ED according to an embodiment of the present disclosure. Figure 3 is a display device DD according to an embodiment of the present disclosure corresponding to Figure 2 Schematic cross-sectional view along line II' in FIG.

[0059] refer to Figure 1 , the electronic device ED according to an embodiment of the present disclosure may include a display surface DS defined by a first direction DR1 and a second direction DR2 crossing the first direction DR1. The electronic device ED may provide an image IM to a user through the display surface DS.

[0060] The display surface DS may include a display area DA and a non-display area NDA surrounding the display area DA. The display area DA may display an image IM, and the non-display area NDA may not display the image IM. The non-display area NDA may surround the display area DA. However, this is not limited thereto, and the shape of the display area DA and the shape of the non-display area NDA may be changed.

[0061] Hereinafter, a direction substantially perpendicularly intersecting a plane defined by the first direction DR1 and the second direction DR2 may be defined as a third direction DR3. The third direction DR3 serves as a reference for distinguishing the front surface and the rear surface of each member. In the present specification, the expression "on a plane" may be defined as observed in the third direction DR3, and may correspond to "in a plan view". Hereinafter, the first to third directions DR1, DR2, and DR3 refer to the same reference numerals as the directions indicated by the first direction axis to the third direction axis, respectively.

[0062] In an embodiment of the present disclosure, the electronic device ED may be a foldable electronic device that can be folded around a folding axis. The folding axis may be parallel to the first direction DR1 or the second direction DR2, and the folding area may be defined in a portion of the display area DA. The electronic device ED may be folded inwardly so that portions of the display area DA face each other, or folded outwardly so that portions of the display area DA face away from each other.

[0063] like Figure 2 As shown in FIG, the electronic device ED may include a display device DD, an electronic module EM, a power supply module PSM and a housing HM. Figure 2 The electronic device ED is briefly illustrated, which may further include a mechanical structure (eg, a hinge) for controlling the operation (eg, folding or rolling) of the display device DD.

[0064] The display device DD generates an image and senses an external input. The display device DD includes a window WM, an upper member UM, a display module DM, a lower member LM, a flexible circuit board FCB, and a driving chip DIC. The upper member UM includes a member disposed above the display module DM, and the lower member LM includes a member disposed below the display module DM.

[0065] The window WM provides a front surface of the electronic device ED. The window WM includes a transmissive area TA and a bezel area BA. Figure 1 The display area DA and the non-display area NDA of the display surface DS illustrated in FIG. 4 may be defined by the transmission area TA and the bezel area BA, respectively. The transmission area TA may be an area through which an image passes, and the bezel area BA may be an area covering a structure / member disposed under the window WM.

[0066] The display module DM may include at least a display panel DP. Figure 2 Only the display panel DP among the stacked structure of the display module DM is shown, but the display module DM may substantially include not only the display panel DP but also additional components disposed above the display panel DP. A detailed description of the stacked structure of the display module DM will be given later.

[0067] The display panel DP may not be particularly limited, and may include, for example, an organic light emitting display panel or an inorganic light emitting display panel. Figure 1 , and the display area DA and the non-display area NDA are shown in FIG. 1 and 2 . In the present specification, the expression “an area / portion corresponds to another area / portion” means that these areas / portions overlap each other, and the expression may not be limited to having the same area.

[0068] The pad area PA of the display panel DP may be disposed on one side of the non-display area DP-NDA. The pad area PA may be an area electrically coupled (or electrically connected) to a flexible circuit board FCB to be described later. In the present embodiment, the pad area PA may be defined on the rear surface of the display panel DP.

[0069] The display panel DP has a basic quadrilateral shape. Here, the "basic quadrilateral shape" includes not only a quadrilateral shape in a mathematical sense, but also a shape similar to a quadrilateral shape that can be perceived as a quadrilateral shape by a user. For example, the basic quadrilateral shape may include a quadrilateral shape with rounded corners. Regarding the basic quadrilateral shape, the edge of the display panel DP may not be limited to being straight, and the edge may include a curved portion.

[0070] The upper member UM may include a protective film or an optical film. The optical film may include a polarizer and a retarder for reducing reflection of external light. The lower member LM may include a protective film for protecting the display panel DP, a supporting member for supporting the display panel DP, and a digital converter, etc. A detailed description of the upper member UM and the lower member LM will be given later.

[0071] Figure 2 The flexible circuit board FCB illustrated in FIG. 1 may be disposed under the display panel DP. The flexible circuit board FCB may be bonded to the rear surface of the display panel DP and may electrically connect the display panel DP and the main circuit board to each other. The flexible circuit board FCB includes at least one insulating layer and at least one conductive layer. The conductive layer may include a plurality of signal lines.

[0072] The driving chip DIC may be mounted on the flexible circuit board FCB. The driving chip DIC may include a driving circuit (eg, a data driving circuit) for driving pixels of the display panel DP. Figure 2 The structure in which the driving chip DIC may be mounted on the flexible circuit board FCB is illustrated, but the present disclosure is not limited thereto. For example, the driving chip DIC may be mounted on the display panel DP or the main circuit board.

[0073] The electronic module EM may include a control module, a wireless communication module, a video input module, an audio input module, an audio output module, a memory, an external interface module, etc. The electronic module EM may include a main circuit board, and these modules may be mounted on the main circuit board or electrically connected to the main circuit board through a flexible circuit board. The electronic module EM may be electrically connected to the power supply module PSM.

[0074] Although not shown separately, the electronic device ED may further include an electro-optical module. The electro-optical module may be an electronic component that outputs or receives an optical signal. The electro-optical module may include a camera module and / or a proximity sensor. The camera module may capture an external image through a partial area of ​​the display panel DP.

[0075] Figure 2 The housing HM shown in the figure can be combined with the display device DD (especially the window WM) to accommodate other modules. The housing HM can be illustrated as having an integral shape, but is not limited thereto. The housing HM can include a plurality of parts (e.g., side parts and a bottom part) that can be combined with each other.

[0076] Figure 3 Also shown are Figure 21 to 4. The window WM may include a base substrate BS and a frame pattern BM disposed on a lower surface of the base substrate BS. The base substrate BS may include a synthetic resin film or a glass substrate. The base substrate BS may have a multi-layer structure. The base substrate BS may include a thin film glass substrate, a protective film disposed on the thin film glass substrate, and an adhesive layer bonding the thin film glass substrate and the protective film to each other.

[0077] The frame pattern BM may be a colored light shielding film and may be formed, for example, by a coating method. The frame pattern BM may include a base material and a dye or pigment mixed with the base material. Figure 1 The non-display area NDA and Figure 2 The frame pattern BM may overlap the frame area BA shown in the figure. The frame pattern BM may be disposed on the lower surface of the base substrate BS. In the case where the base substrate BS has a multi-layer structure, the frame pattern BM may be disposed between interfaces defined by the multiple layers. For example, the frame pattern BM may be disposed between the thin film glass substrate and the protective film. Although not separately illustrated, the window WM may further include at least one of a hard coating layer, an anti-fingerprint layer, and an anti-reflection layer located on the upper surface of the base substrate BS.

[0078] The upper member UM may include an upper film UF. The upper film UF may include a synthetic resin film. The synthetic resin film may include polyimide, polycarbonate, polyamide, triacetyl cellulose, polymethyl methacrylate, or polyethylene terephthalate.

[0079] The upper film UF can absorb external impact applied to the front surface of the display device DD. In an embodiment of the present disclosure, the upper film UF may include a color filter as an anti-reflection member instead of a polarizing film, so that the impact strength on the front surface of the display device DD can be reduced. The upper film UF can compensate for the reduced impact strength by applying a color filter.

[0080] The upper film UF overlaps the frame area BA and the transmission area TA. The upper film UF may overlap only a portion of the frame area BA. A portion of the frame pattern BM may be exposed from the upper film UF. In an embodiment of the present disclosure, the upper film UF may be omitted. In an embodiment of the present disclosure, an optical film including a polarizer and a retarder may be used instead of the upper film UF.

[0081] The upper member UM may further include a first adhesive layer AL1 that bonds the upper film UF and the window WM to each other and a second adhesive layer AL2 that bonds the upper film UF and the display module DM to each other. The first adhesive layer AL1 and the second adhesive layer AL2 may be a pressure-sensitive adhesive (PSA) film or an optically clear adhesive (OCA) member. The adhesive layer described below may also include the same adhesive as that of the first adhesive layer AL1.

[0082] The display module DM may be disposed below the upper film UF. The display module DM overlaps the frame area BA and the transmission area TA. The display module DM may completely overlap the upper film UF in the frame area BA. In a plan view, the side of the display module DM may be aligned with the side of the upper film UF, and the edge of the display module DM may be aligned with the edge of the upper film UF.

[0083] In the frame area BA, the pad area PA may overlap with the upper film UF. The portion of the display module DM corresponding to the pad area PA may be bonded to the lower surface of the upper film UF through the second adhesive layer AL2. Since the pad area PA overlaps with the upper film UF and the portion of the display module DM overlapping with the pad area PA may be bonded to the upper film UF, the upper film UF may fully support the pad area PA when the flexible circuit board FCB may be bonded to the pad area PA.

[0084] The lower member LM may include a lower film PF, a cover panel CP, a third adhesive layer AL3, and a fourth adhesive layer AL4. In an embodiment of the present disclosure, the lower member LM may further include a support plate and a digitizer.

[0085] The lower film PF may be disposed below the display module DM and bonded to the lower surface of the display module DM through the third adhesive layer AL3. The lower film PF may protect the lower portion of the display module DM. The lower film PF may include a flexible synthetic resin film. For example, the lower film PF may include, but may not be limited to, polyethylene terephthalate or polyimide.

[0086] The lower film PF exposes at least the pad area PA. The lower film PF may have an area smaller than that of the display module DM. For example, the lower film PF may overlap only the display area DA.

[0087] The lower film PF may have an area substantially the same as that of the display module DM. Figure 2 Although the lower film PF protects the entire lower surface of the display module DM, the open area PF-OP may be defined so that the flexible circuit board FCB approaches the pad area PA.

[0088] like Figure 3As shown in , the fourth adhesive layer AL4 bonds the lower film PF and the cover panel CP to each other. The cover panel CP can improve the resistance to the compressive force caused by the external pressure. Accordingly, the cover panel CP can be used to prevent the deformation of the display panel DP. The cover panel CP may include a flexible plastic material such as polyimide or polyethylene terephthalate. The cover panel CP may be a colored film with low light transmittance. The cover panel CP may absorb light incident from the outside. For example, the cover panel CP may be a black synthetic resin film. In a case where the display device DD can be viewed from above the window WM, the components arranged below the cover panel CP may not be visually recognized by the user.

[0089] A support plate may be further provided below the cover panel CP. The support plate may include a high-strength metal material. The support plate may also include a reinforced fiber composite material. The support plate may include reinforcing fibers provided in the base portion. The reinforcing fibers may be carbon fibers or glass fibers. The base portion may include a polymer resin. The base portion may include a thermoplastic resin. For example, the base portion may include a polyamide resin or a polypropylene resin. For example, the reinforced fiber composite material may be a carbon fiber reinforced plastic (CFRP) or a glass fiber reinforced plastic (GFRP).

[0090] Figure 4 is a simplified schematic cross-sectional view of a display module DM according to an embodiment of the present disclosure.

[0091] refer to Figure 4 The display module DM may include a display panel DP and an input sensor ISL. The display panel DP may include a base layer 110 , a driving element layer 120 , a light emitting element layer 130 , and an encapsulation layer 140 .

[0092] The driving element layer 120 may be disposed on the upper surface of the base layer 110. The base layer 110 may be a flexible substrate that can be bent, folded, or rolled, etc. The base layer 110 may be a glass substrate, a metal substrate, a polymer substrate, etc., or a combination thereof. However, the embodiments of the present disclosure are not limited thereto, and the base layer 110 may be an inorganic layer, an organic layer, or a composite material layer. The base layer 110 may have a shape substantially the same as that of the display panel DP.

[0093] The base layer 110 may have a multilayer structure. For example, the base layer 110 may include a first synthetic resin layer, a second synthetic resin layer, and an inorganic layer disposed therebetween. Each of the first synthetic resin layer and the second synthetic resin layer may include a polyimide-based resin, but the embodiments of the present disclosure are not particularly limited thereto.

[0094] The driving element layer 120 may be disposed on the base layer 110. The driving element layer 120 may include a plurality of insulating layers, a plurality of semiconductor patterns, a plurality of conductive patterns, and signal lines, etc. The driving element layer 120 may include a pixel driving circuit. Hereinafter, unless otherwise specified, in the case where component A and component B are disposed on the same layer, this may be interpreted as that since they may be formed by the same process as each other, they contain the same material as each other or have the same stacking structure as each other. The conductive pattern or semiconductor pattern disposed on the same layer may be interpreted as described above.

[0095] The light emitting element layer 130 may be disposed on the driving element layer 120. The light emitting element layer 130 may include a light emitting element. For example, the light emitting element may include an organic light emitting material, an inorganic light emitting material, an organic-inorganic light emitting material, a quantum dot, a quantum rod, a micro-LED or a nano-LED.

[0096] The encapsulation layer 140 may be disposed on the light emitting element layer 130. The encapsulation layer 140 may protect the light emitting element layer 130 (i.e., the light emitting element) from moisture, oxygen, and foreign matter such as dust particles. The encapsulation layer 140 may include at least one inorganic encapsulation layer. The encapsulation layer 140 may include a stacked structure of a first inorganic encapsulation layer / an organic encapsulation layer / a second inorganic encapsulation layer.

[0097] The input sensor ISL may be disposed (e.g., directly disposed) on the display panel DP. The input sensor ISL may sense the user's input, for example, by an electromagnetic induction method or a capacitive method. The display panel DP and the input sensor ISL may be formed by a continuous process. Here, the expression "directly disposed" may mean that no third component may be disposed between the input sensor ISL and the display panel DP. For example, no separate adhesive layer may be disposed between the input sensor ISL and the display panel DP.

[0098] Figure 5 is a plan view of a display panel DP according to an embodiment of the present disclosure. Figure 6 is a schematic cross-sectional view of a display module DM according to an embodiment of the present disclosure.

[0099] like Figure 5 As shown in FIG. 1 , the display panel DP may include a scan drive circuit SDC, a plurality of signal lines SGL, and a plurality of pixels PX. The pixels PX may be arranged in the display area DP-DA. Each of the pixels PX may include a light emitting element and a pixel drive circuit electrically connected to the light emitting element. The scan drive circuit SDC, the signal lines SGL, and the pixel drive circuit may include Figure 4 In the driving element layer 120 shown in the figure.

[0100] The scan drive circuit SDC may include a gate drive circuit. The gate drive circuit may generate a plurality of scan signals and may sequentially output the scan signals to a plurality of scan lines GL to be described later. The scan drive circuit SDC may further include a light emitting drive circuit that may be different from the gate drive circuit. The light emitting drive circuit may output the scan signals to another group of scan lines.

[0101] The scan driving circuit SDC may include a plurality of thin film transistors formed by the same process as that of the pixel driving circuit, for example, a low temperature polysilicon (LTPS) process or a low temperature polycrystalline oxide (LTPO) process.

[0102] The signal lines SGL include scan lines GL, data lines DL, power lines PL, and control signal lines CSL. Each of the scan lines GL may be electrically connected to a corresponding pixel PX among the pixels PX, and each of the data lines DL may be electrically connected to a corresponding pixel PX among the pixels PX. The power lines PL may be electrically connected to a plurality of pixels PX. The data lines DL provide data signals to the pixels PX. The control signal lines CSL may provide control signals to the scan drive circuit SDC.

[0103] like Figure 8 As shown in , the power line PL may include a first power line PL1 for receiving a first power voltage and a second power line PL2 for receiving a second power voltage higher than the first power voltage. The first power voltage may be provided to the pixel PX through the first power line PL1, and the second power voltage may be provided to the pixel PX through the second power line PL2. Although one control signal line CSL is illustrated as an example, the control signal line CSL may be provided in plurality.

[0104] The scan line GL, the data line DL and the power line PL may overlap the display area DP-DA and the non-display area DP-NDA, and the control signal line CSL may overlap the non-display area DP-NDA. The ends of the signal lines SGL may be aligned on one side of the non-display area DP-NDA. Each of the signal lines SGL may have an integral shape, but may include a plurality of parts arranged in different layers. The different parts separated by the insulating layer may be electrically connected through contact holes passing through the insulating layer. For example, the data line DL may include a first part arranged in the display area DP-DA and a second part arranged in the non-display area DP-NDA and arranged on a layer different from the layer of the first part. The first part and the second part may include different materials and have different stacking structures.

[0105] The display panel DP may include insulating patterns DMP1 and DMP2 . Figure 5The first insulating pattern DMP1 and the second insulating pattern DMP2 are illustrated. The first insulating pattern DMP1 and the second insulating pattern DMP2 may be disposed in the non-display area DP-NDA and surround the display area DP-DA. Each of the first insulating pattern DMP1 and the second insulating pattern DMP2 may have a closed line shape. The first insulating pattern DMP1 and the second insulating pattern DMP2 serve as a dam for preventing the liquefied organic material from overflowing in the inkjet process of the display panel DP. A detailed description of this will be provided later.

[0106] Figure 5 The outer shape of the display panel DP illustrated in the plan view may substantially correspond to the outer shape of the base layer 110 included in the display panel DP. The base layer 110 may include a first base portion 110-1 including the display area DP-DA and a second base portion 110-2 protruding from the first base portion 110-1 in the second direction DR2. The width of the second base portion 110-2 in the first direction DR1 may be smaller than the width of the first base portion 110-1 in the first direction DR1. Each component included in the display panel DP may be disposed above the base layer 110.

[0107] Figure 6 The diagram shows Figure 5 Schematic cross section of the display module DM corresponding to the pixel PX.

[0108] The pixel driving circuit for driving the light emitting element LD may include a plurality of pixel driving elements. The pixel driving circuit may include a plurality of transistors and a capacitor Cst.

[0109] refer to Figure 6 , the base layer 110 may be illustrated as a single layer. The base layer 110 may include a synthetic resin such as polyimide. The base layer 110 may be formed by coating a synthetic resin layer on a working substrate. In the case where the display module DM is completed after subsequent processes are performed, the working substrate may be removed.

[0110] refer to Figure 6 , the barrier layer 10br may be disposed on the base layer 110. The barrier layer 10br prevents foreign matter from entering from the outside. The barrier layer 10br may include at least one inorganic layer. The barrier layer 10br may include a silicon oxide layer and a silicon nitride layer. Each of these may be provided in plural, and the silicon oxide layer and the silicon nitride layer may be alternately stacked with each other.

[0111] The barrier layer 10br may include a lower barrier layer 10br1 and an upper barrier layer 10br2. The first shielding electrode BMLa may be disposed between the lower barrier layer 10br1 and the upper barrier layer 10br2. The first shielding electrode BMLa may be disposed to correspond to the silicon transistor S-TFT. The first shielding electrode BMLa may include metal.

[0112] The first shielding electrode BMLa may receive a bias voltage. The first shielding electrode BMLa may receive a first power supply voltage. The first shielding electrode BMLa may prevent the potential due to polarization from affecting the silicon transistor S-TFT. The first shielding electrode BMLa may block external light from reaching the silicon transistor S-TFT. In an embodiment of the present disclosure, the first shielding electrode BMLa may be a floating electrode isolated from other electrodes or lines.

[0113] The buffer layer 10bf may be disposed on the barrier layer 10br. The buffer layer 10bf may prevent metal atoms or impurities from diffusing from the base layer 110 to the first semiconductor pattern SC1 disposed above the base layer 110. The buffer layer 10bf may include at least one inorganic layer. The buffer layer 10bf may include a silicon oxide layer and a silicon nitride layer.

[0114] The first semiconductor pattern SC1 may be disposed on the buffer layer 10bf. The first semiconductor pattern SC1 may include a silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon and polycrystalline silicon, etc. For example, the first semiconductor pattern SC1 may include low temperature polycrystalline silicon.

[0115] The first semiconductor pattern SC1 may have different electrical characteristics depending on whether it is doped or not. The first semiconductor pattern SC1 may include a first region having high conductivity and a second region having low conductivity. The first region may be doped with an N-type dopant or a P-type dopant. A P-type transistor may include a doped region doped with a P-type dopant, and an N-type transistor may include a doped region doped with an N-type dopant. The second region may be an undoped region or a region doped at a lower concentration than that of the first region. In the present embodiment, the first semiconductor pattern SC1 may be an N-type transistor.

[0116] The conductivity of the first region may be greater than that of the second region, and the first region may substantially serve as an electrode or a signal line. The second region may substantially correspond to a channel region (or an active region) of a transistor. In other words, a portion of the first semiconductor pattern SC1 may be a channel of a transistor, another portion thereof may be a source or drain of the transistor, and another portion thereof may be a connection electrode or a connection signal line.

[0117] A source region SE1, a channel region AC1 (or active region), and a drain region DE1 of the silicon transistor S-TFT may be formed by the first semiconductor pattern SC1. In cross section, the source region SE1 and the drain region DE1 may extend from the channel region AC1 in opposite directions to each other.

[0118] The first insulating layer 10 may be disposed on the buffer layer 10bf. The first insulating layer 10 may cover the first semiconductor pattern SC1. The first insulating layer 10 may be an inorganic layer. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The first insulating layer 10 may be a single-layer silicon oxide. Not only the first insulating layer 10, but also other insulating layers of the driving element layer 120 to be described later may have a single-layer structure or a multi-layer structure and include at least one of the above materials, but the embodiments of the present disclosure are not limited thereto.

[0119] The gate GT1 of the silicon transistor S-TFT may be disposed on the first insulating layer 10. The gate GT1 may be a portion of the metal pattern. The gate GT1 overlaps the channel region AC1. In the process of doping the first semiconductor pattern SC1, the gate GT1 may be a mask. The first electrode CE10 of the storage capacitor Cst may be disposed on the first insulating layer 10. Figure 6 Unlike shown in FIG. 2 , the first electrode CE10 may have an integral shape with the gate electrode GT1 .

[0120] The second insulating layer 20 may be disposed on the first insulating layer 10 and cover the gate GT1. In an embodiment of the present disclosure, an upper electrode overlapping the gate GT1 may be further disposed on the second insulating layer 20. The second electrode CE20 overlapping the first electrode CE10 may be disposed on the second insulating layer 20. In a plan view, the upper electrode may have an integral shape with the second electrode CE20.

[0121] The second shielding electrode BMLb may be disposed on the second insulating layer 20. The second shielding electrode BMLb may be disposed to correspond to the oxide transistor O-TFT. In an embodiment of the present disclosure, the second shielding electrode BMLb may be omitted. According to an embodiment of the present disclosure, the first shielding electrode BMLa may extend under the oxide transistor O-TFT and replace the second shielding electrode BMLb.

[0122] The third insulating layer 30 may be disposed on the second insulating layer 20. The second semiconductor pattern SC2 may be disposed on the third insulating layer 30. The second semiconductor pattern SC2 may include a channel region AC2 of an oxide transistor O-TFT. The second semiconductor pattern SC2 may include an oxide semiconductor. The second semiconductor pattern SC2 may include an indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnOx ), indium oxide (In 2 O 3 ) or a combination thereof.

[0123] The oxide semiconductor may include a plurality of regions SE2, AC2, and DE2 divided depending on whether the transparent conductive oxide is reduced. The region in which the transparent conductive oxide may be reduced (hereinafter, referred to as the reduction region) has a greater conductivity than the region in which the transparent conductive oxide may not be reduced (hereinafter, referred to as the non-reduction region). The reduction region substantially acts as a source / drain or a signal line of the transistor. The non-reduction region substantially corresponds to a semiconductor region (or channel) of the transistor. In other words, a portion of the second semiconductor pattern SC2 may be a semiconductor region of the transistor, another portion thereof may be a source region SE2 / drain region DE2 of the transistor, and another portion thereof may be a signal transmission region.

[0124] The fourth insulating layer 40 may be disposed on the third insulating layer 30. Figure 6 As shown in , the fourth insulating layer 40 may cover the second semiconductor pattern SC2. In an embodiment of the present disclosure, the fourth insulating layer 40 may overlap the gate GT2 of the oxide transistor O-TFT and is an insulating pattern exposing the source region SE2 and the drain region DE2 of the oxide transistor O-TFT.

[0125] The gate GT2 of the oxide transistor O-TFT may be disposed on the fourth insulating layer 40. The gate GT2 of the oxide transistor O-TFT may be a portion of the metal pattern. The gate GT2 of the oxide transistor O-TFT may overlap with the channel region AC2.

[0126] The fifth insulating layer 50 may be disposed on the fourth insulating layer 40, and the fifth insulating layer 50 may cover the gate GT2. Each of the first to fifth insulating layers 10 to 50 may be an inorganic layer.

[0127] The first connection pattern CNP1 may be disposed on the fifth insulating layer 50. The first connection pattern CNP1 may be electrically connected to the drain region DE1 of the silicon transistor S-TFT through a contact hole passing through the first to fifth insulating layers 10, 20, 30, 40, and 50.

[0128] The sixth insulating layer 60 may be disposed on the fifth insulating layer 50. The second connection pattern CNP2 may be disposed on the sixth insulating layer 60. The second connection pattern CNP2 may be electrically connected to the first connection pattern CNP1 through a contact hole passing through the sixth insulating layer 60. The data line DL may be disposed on the sixth insulating layer 60. The seventh insulating layer 70 may be disposed on the sixth insulating layer 60 and cover the second connection pattern CNP2 and the data line DL. Since the second connection pattern CNP2 and the data line DL may be formed by the same process, they may have the same material and the same stack structure. Each of the sixth insulating layer 60 and the seventh insulating layer 70 may be an organic layer.

[0129] The first shielding electrode BMLa, the gate electrode GT1 of the silicon transistor S-TFT, the second electrode CE20, and the gate electrode GT2 of the oxide transistor O-TFT may include molybdenum (Mo) having good heat resistance, an alloy containing molybdenum, titanium (Ti), an alloy containing titanium, or a combination thereof. The first connection pattern CNP1 and the second connection pattern CNP2 may include aluminum having high conductivity. The first connection pattern CNP1 and the second connection pattern CNP2 may have a three-layer stacked structure of titanium / aluminum / titanium.

[0130] The light emitting element LD may include an anode AE ​​(or a first electrode), a light emitting layer EL, and a cathode CE (or a second electrode). The anode AE ​​of the light emitting element LD may be disposed on the seventh insulating layer 70. The anode AE ​​may be a (semi) transmissive electrode or a reflective electrode. The anode AE ​​may include a stacked structure of ITO / Ag / ITO that may be sequentially stacked with each other. The positions of the anode AE ​​and the cathode CE may be interchanged with each other.

[0131] The pixel defining film PDL may be disposed on the seventh insulating layer 70. The pixel defining film PDL may be an organic layer. The pixel defining film PDL may have a characteristic of absorbing light. For example, the pixel defining film PDL may have a black color. The pixel defining film PDL may include a black colorant. The black colorant may include a black dye and a black pigment. The black colorant may include carbon black, a metal such as chromium, or an oxide thereof. The pixel defining film PDL may correspond to a light shielding pattern having a light shielding characteristic.

[0132] The pixel defining film PDL may cover a portion of the anode AE. For example, an opening PDL-OP exposing a portion of the anode AE ​​may be defined in the pixel defining film PDL. The light-emitting area LA may be defined to correspond to the opening PDL-OP. In an embodiment of the present disclosure, a hole control layer may be disposed between the anode AE ​​and the light-emitting layer EL. The hole control layer may include a hole transport layer and may further include a hole injection layer. The electron control layer may be disposed between the light-emitting layer EL and the cathode CE. The electron control layer may include an electron transport layer and may further include an electron injection layer.

[0133] The encapsulation layer 140 may cover the light emitting element LD. The encapsulation layer 140 may include an inorganic encapsulation layer 141, an organic encapsulation layer 142, and an inorganic encapsulation layer 143, which may be sequentially stacked on each other, but the layers constituting the encapsulation layer 140 are not necessarily limited thereto. The inorganic encapsulation layers 141 and 143 may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, or the like, or a combination thereof. Each of the inorganic encapsulation layers 141 and 143 may have a multilayer structure. The organic encapsulation layer 142 may include an acrylic organic layer, but is not limited thereto.

[0134] The input sensor ISL may include at least one conductive layer (or at least one sensor conductive layer) and at least one insulating layer (or at least one sensor insulating layer). In this embodiment, the input sensor ISL may include a first insulating layer 210 (or a first sensor insulating layer), a first conductive layer 220, a second insulating layer 230 (or a second sensor insulating layer), a second conductive layer 240, and a third insulating layer 250 (or a third sensor insulating layer). Figure 6 The conductive lines of the first conductive layer 220 and the conductive lines of the second conductive layer 240 are illustrated.

[0135] The first insulating layer 210 may be disposed (e.g., directly disposed) on the display panel DP. The first insulating layer 210 may be an inorganic layer including at least one of silicon nitride, silicon oxynitride, silicon oxide, and a combination thereof. Each of the first conductive layer 220 and the second conductive layer 240 may have a single-layer structure or a multi-layer structure in which the layers may be stacked on each other in the third direction DR3. The first conductive layer 220 and the second conductive layer 240 may include conductive wires defining a grid-like electrode. The conductive wires of the first conductive layer 220 and the conductive wires of the second conductive layer 240 may or may not be electrically connected to each other through contact holes passing through the second insulating layer 230. The connection relationship between the conductive wires of the first conductive layer 220 and the conductive wires of the second conductive layer 240 may be determined depending on the type of sensor forming the input sensor ISL.

[0136] The first conductive layer 220 and the second conductive layer 240 having a single-layer structure may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum, silver, titanium, copper, aluminum, an alloy thereof, or a combination thereof. The transparent conductive layer may include an indium tin oxide (ITO), an indium zinc oxide (IZO), a zinc oxide (ZnO x ), indium zinc tin oxide (IZTO), etc., or a combination thereof. The transparent conductive layer may include a conductive polymer such as PEDOT, a metal nanowire, and graphene.

[0137] The first conductive layer 220 and the second conductive layer 240 having a multilayer structure may include a metal layer. The metal layer may have a three-layer structure of, for example, titanium / aluminum / titanium. The multilayer conductive layer may include at least one metal layer and at least one transparent conductive layer. The second insulating layer 230 may be disposed between the first conductive layer 220 and the second conductive layer 240. The third insulating layer 250 may cover the second conductive layer 240. In an embodiment of the present disclosure, the third insulating layer 250 may be omitted. The second insulating layer 230 and the third insulating layer 250 may include an inorganic layer or an organic layer.

[0138] Fig. 7A is a plan view of an input sensor ISL according to an embodiment of the present disclosure. Figure 7B is the input sensor ISL corresponding to Fig. 7A Schematic cross-sectional view along line II-II'.

[0139] like Fig. 7A As shown in FIG. 1 , the input sensor ISL includes a sensing area IS-DA and a non-sensing area IS-NDA adjacent to the sensing area IS-DA. The sensing area IS-DA and the non-sensing area IS-NDA are respectively Figure 5 The display area DP-DA and the non-display area DP-NDA shown in the figure correspond to each other. The input sensor ISL includes first electrodes E1-1 to E1-5 (or first sensing electrodes), second electrodes E2-1 to E2-4 (or second sensing electrodes), first signal lines SL1 (or first sensor signal lines), and second signal lines SL2 (or second sensor signal lines). The first insulating pattern DMP1 and the second insulating pattern DMP2 may be additionally shown in FIG. Fig. 7A , so as to show the relative positions of the first insulation pattern DMP1 and the second insulation pattern DMP2 with respect to the input sensor ISL.

[0140] The first electrodes E1-1 to E1-5 and the second electrodes E2-1 to E2-4, which may be insulated from and intersecting each other, may be disposed in the sensing area IS-DA. The first signal line SL1 electrically connected to the first electrodes E1-1 to E1-5 and the second signal line SL2 electrically connected to the second electrodes E2-1 to E2-4 may be disposed in the non-sensing area IS-NDA. Any one of the first signal line SL1 and the second signal line SL2 transmits a driving signal for sensing an external input from an external circuit to the corresponding electrode, and the other of them outputs a sensing signal. Based on the sensing signal, the capacitance change between the first electrodes E1-1 to E1-5 and the second electrodes E2-1 to E2-4 may be measured. In the present embodiment, a mutual capacitance input sensor may be illustrated as an example, but the embodiments of the present disclosure are not limited thereto. A self-capacitance input sensor may also be applied. The self-capacitance input sensor may include a type of sensing electrode.

[0141] Each of the first electrodes E1-1 to E1-5 and the second electrodes E2-1 to E2-4 may have a mesh shape in which a plurality of openings are defined. The openings may be defined to be aligned with the light emitting area LA of the display panel DP (see FIG. Figure 6 ) corresponding to. Figure 6 An opening E-OP corresponding to one light emitting area is illustrated. The second electrodes E2-1 to E2-4 may be insulated from and intersect the first electrodes E1-1 to E1-5. Any one of the first electrodes E1-1 to E1-5 and the second electrodes E2-1 to E2-4 may have an integral shape. In the present embodiment, the first electrodes E1-1 to E1-5 having an integral shape may be illustrated as an example. The first electrodes E1-1 to E1-5 may include a sensing pattern SP1 and a middle portion CP1.

[0142] Each of the second electrodes E2 - 1 to E2 - 4 may include a sensing pattern SP2 and a bridge pattern CP2 (or a connection pattern). Two adjacent sensing patterns SP2 may be electrically connected to two bridge patterns CP2 , but the number of the bridge patterns is not limited thereto.

[0143] refer to Figures 6 to 7B , the bridge pattern CP2 may be formed of the first conductive layer 220, and the first electrodes E1-1 to E1-5 and the sensing pattern SP2 may be formed of the second conductive layer 240. The bridge pattern CP2 may be electrically connected to the sensing pattern SP2 through a contact hole TH-1 formed in the second insulating layer 230.

[0144] In this embodiment, Fig. 7A Each of the first signal line SL1 and the second signal line SL2 may be composed of Figure 6 The first conductive layer 220 is formed. Accordingly, Fig. 7A Each of the first signal line SL1 and the second signal line SL2 may be connected to Figure 7B However, not limited thereto, each of the first signal line SL1 and the second signal line SL2 may be formed by the second conductive layer 240. Each of the first signal line SL1 and the second signal line SL2 may include both a line formed by the first conductive layer 220 and a line formed by the second conductive layer 240.

[0145] Figure 8 is an enlarged plan view of a non-display area DP-NDA of a display module DM according to an embodiment of the present disclosure.

[0146] Figure 8 The display area DP-DA and the non-display area DP-NDA of the display module DM are respectively referred to as Figure 5The display area DP-DA and the non-display area DP-NDA of the display panel DP in FIG. Fig. 7A The sensing area IS-DA corresponds to the non-sensing area IS-NDA. Figure 8 In the display area DP-DA, you can Fig. 7A The electrodes E1-5 and E1-5 among the first electrodes E1-1 to E1-5 shown in FIG. Fig. 7A Some of the electrodes E2-1 to E2-3 among the second electrodes E2-1 to E2-4 illustrated in FIG. 1 and components of the display panel DP in the display area DP-DA may be omitted.

[0147] based on Figure 5 and Fig. 7A , Figure 8 The diagram shows an enlarged view of a corner area CA (or vertex area) and a portion of a non-display area DP-NDA disposed below the display area DP-DA in a plan view. Figure 8 Among the components shown in the figure, components overlapping each other may be arranged in different layers.

[0148] The first power line PL1 and the second power line PL2 may be disposed in the non-display area DP-NDA. The first power line PL1 may extend through the corner area CA to Figure 5 The left side of the non-display area DP-NDA illustrated in FIG. In a plan view, a boundary line between the display area DP-DA and the non-display area DP-NDA in the corner area CA may substantially have a curve. Figure 8 In the figure, a boundary line between the display area DP-DA and the non-display area DP-NDA may be illustrated as a dotted line.

[0149] The first power line PL1 can pass through Figure 5 The second power line PL2 may be disposed in the non-display area DP-NDA disposed below the display area DP-DA in a plan view and extend in the first direction DR1. The first power line PL1 and the second power line PL2 may be disposed in the non-display area DP-NDA disposed below the display area DP-DA in a plan view and extend in the first direction DR1. Figure 6 The second connection pattern CNP2 shown in FIG. 1 is provided on the same layer.

[0150] The first voltage line VL1 and the second voltage line VL2 may be disposed in the non-display area DP-NDA. Figure 8 One first voltage line VL1 and one second voltage line VL2 are illustrated, but the embodiments of the present disclosure are not limited thereto, and a plurality of first and second voltage lines VL1 and VL2 may be provided. The first voltage line VL1 may receive a first voltage VGL (see Fig. 9C), and the second voltage line VL2 may receive a second voltage VGH (see Fig. 9C ). In an embodiment of the present disclosure, the first voltage VGL may be a first power supply voltage, and the second voltage VGH may be a second power supply voltage.

[0151] Each of the first voltage line VL1 and the second voltage line VL2 may include a portion extending in the second direction DR2 and a portion extending in the first direction DR1. The first voltage line VL1 and the second voltage line VL2 do not overlap with the second power line PL2 and may be disposed lower than the second power line PL2 in a plan view. The first voltage line VL1 and the second voltage line VL2 may be disposed adjacent to an edge EG of the display module DM disposed lower than the second power line PL2 in a plan view. The edge EG of the display module DM may be Figure 8 The first power line PL1 and the second power line PL2 may be connected to the edge 110-EG of the base layer 110 shown in FIG. Figure 6 The second connection pattern CNP2 illustrated in FIG. 1 is provided on the same layer, or may be provided on the same layer as the first connection pattern CNP1 .

[0152] At least one control signal line CSL may be disposed in the non-display area DP-NDA. The control signal line CSL may pass through the corner area CA and be electrically connected to the Figure 5 The control signal line CSL may overlap with the first power line PL1. The control signal line CSL may overlap with the first power line PL2. Figure 6 Any of the first shield electrode BMLa, the gate electrode GT1 of the silicon transistor S-TFT, the second electrode CE20, and the gate electrode GT2 of the oxide transistor O-TFT shown in the figure is provided in the same layer.

[0153] The data lines DL may be disposed in the display area DP-DA and the non-display area DP-NDA. Some of the data lines DL that overlap the display area DP-DA may overlap with the non-display area DP-NDA. Figure 6 Any one of the first connection pattern CNP1 and the second connection pattern CNP2 illustrated in the figure is disposed in the same layer. Some of the data lines DL overlapping the non-display area DP-NDA may be disposed in the same layer as any one of the first shielding electrode BMLa, the gate electrode GT1 of the silicon transistor S-TFT, the second electrode CE20, and the gate electrode GT2 of the oxide transistor O-TFT. Some of the data lines DL overlapping the display area DP-DA and some of the data lines DL overlapping the non-display area DP-NDA may be provided through Figure 6 The contact holes of corresponding insulating layers among the insulating layers 10br to 70 shown in the figure are electrically connected to each other.

[0154] The second signal line SL2 may be disposed in the non-display area DP-NDA. The second signal line SL2 may overlap the control signal line CSL and the first power line PL1 or the second power line PL2. Each of the second signal lines SL2 may be electrically connected to a corresponding electrode among the second electrodes E2-1 to E2-3 disposed in the display area DP-DA.

[0155] As described above, the base layer 110 may include a first base portion 110-1 and a second base portion 110-2. The first base portion 110-1 may include a display area DP-DA, and the second base portion 110-2 may protrude from the first base portion 110-1 in the second direction DR2. The second edge 110-EG2 of the second base portion 110-2 may protrude more than the first edge 110-EG1 of the first base portion 110-1 in the second direction DR2.

[0156] At least some of the data lines DL may extend to the second substrate portion 110-2. Some of the data lines DL extending to the second substrate portion 110-2 may be electrically connected to the electrostatic protection circuit ESD. The electrostatic protection circuit ESD may be disposed on the second substrate portion 110-2. The electrostatic protection circuit ESD may be electrically connected to each of the data lines DL extending to the second substrate portion 110-2. The electrostatic protection circuit ESD may include a plurality of electrostatic protection circuit portions ESU arranged in the first direction DR1. Although Figure 8 Four electrostatic protection circuit portions ESU are illustrated as an example, but the electrostatic protection circuit ESD may include more than four electrostatic protection circuit portions ESU. For example, the electrostatic protection circuit ESD may include 11 electrostatic protection circuit portions ESU.

[0157] The data line DL may cross the first voltage line VL1, the second voltage line VL2, and the second power line PL2. An additional electrostatic protection circuit ESD-I electrically connected to the data line DL, the first voltage line VL1, and the second voltage line VL2 may be disposed in the non-display area DP-NDA. The additional electrostatic protection circuit ESD-I may be disposed adjacent to the first voltage line VL1 and the second voltage line VL2. The additional electrostatic protection circuit ESD-I may be disposed in the non-display area DP-NDA, and when compared with the electrostatic protection circuit ESD, the additional electrostatic protection circuit ESD-I may be disposed adjacent to the display area DP-DA. Although in Figure 8 One additional electrostatic protection circuit ESD-I may be illustrated as an example, but the additional electrostatic protection circuit ESD-I may be electrically connected to each data line DL, and a plurality of additional electrostatic protection circuits ESD-I may be electrically connected to the data lines DL, respectively.

[0158] Fig.9Ais an enlarged plan view of a non-display area DP-NDA of a display module DM according to an embodiment of the present disclosure. Fig. 9B The display module DM corresponds to Fig.9A Schematic cross-sectional view along line III-III'. Fig. 9C yes Fig.9A Schematic diagram of the additional electrostatic protection circuit ESD-I shown in FIG.

[0159] Fig.9A Pictured Figure 8 2 is an enlarged portion of the non-display area DP-NDA shown in FIG. Specifically, Fig.9A A planar arrangement of some of the data lines DL, some of the second signal lines SL2, and first and second connection electrodes CNE1 and CNE2 electrically connected to some of the data lines DL and some of the second signal lines SL2 is illustrated.

[0160] The first voltage line VL1 and the second voltage line VL2 may be disposed in the non-display area DP-NDA. The additional electrostatic protection circuit ESD-I may be disposed in the non-display area DP-NDA. The first connection electrode CNE1 and the second connection electrode CNE2 may be disposed in the non-display area DP-NDA. The first connection electrode CNE1 may be disposed in one-to-one correspondence with the data line DL, and the second connection electrode CNE2 may be disposed in one-to-one correspondence with the second signal line SL2.

[0161] refer to Fig.9A and Fig. 9B , a connection relationship between the first link electrode CNE1 and the first pad electrode PD1 will be described in detail. Fig. 9B The first connection electrode CNE1 in Figure 6 The first connection pattern CNP1 in the data line DL is disposed in the same layer, and a portion of the data line DL overlapping the non-display area DP-NDA may overlap with the non-display area DP-NDA. Figure 6 The gate electrode GT1 of the silicon transistor S-TFT is arranged on the same layer.

[0162] Fig. 9B The first pad electrode PD1 is provided at Fig.9A A plurality of first pad electrodes PD1 may be disposed to be spaced apart from each other in the first direction DR1 to be aligned with each other. Fig.9A The arrangement of the first connection electrode CNE1 corresponds to that of the first connection electrode CNE1.

[0163] The first opening B1-OP may expose a plurality of first pad electrodes PD1 together. One first opening B1-OP exposes the first pad electrodes PD1 and the area therebetween to the outside. In contrast, the second opening I1-OP may be formed separately for each of the first pad electrodes PD1. However, not limited thereto, like the second opening I1-OP, the first opening B1-OP may also be formed separately for each of the first pad electrodes PD1. In the case where the first opening B1-OP is formed separately for each of the first pad electrodes PD1, a portion of the first synthetic resin layer 110-B1 may be disposed between the first pad electrodes PD1.

[0164] The first pad electrode PD1 may be exposed to the outside through the lower surface 110-LS of the base layer 110 to be connected to the flexible circuit board FCB (see Figure 2 ) for back bonding. The lower surface 110-LS of the base layer 110 faces the upper surface 110-US of the base layer 110 in the third direction DR3. The lower surface 110-LS of the base layer 110 is connected to the display panel DP (see Figure 5 ) corresponds to the rear surface.

[0165] Fig. 9B The arrangement relationship between the base layer 110 and the first pad electrode PD1 according to an embodiment of the present disclosure is illustrated. In the present embodiment, the first pad electrode PD1 may be embedded in the base layer 110. However, not limited thereto, the first pad electrode PD1 may be disposed on the lower surface 110-LS of the base layer 110. The base layer 110 may include a single synthetic resin layer, or although the base layer 110 may include a plurality of layers, the first opening B1-OP and the second opening I1-OP, which will be described later, may not be limited.

[0166] like Fig. 9BAs shown in , the base layer 110 may include a first synthetic resin layer 110-B1, a first inorganic base layer 110-I1, a second inorganic base layer 110-I2, and a second synthetic resin layer 110-B2. The first synthetic resin layer 110-B1 provides a lower surface 110-LS of the base layer 110, and the first synthetic resin layer 110-B1 has a first opening B1-OP defined therein and exposing the first pad electrode PD1. The first inorganic base layer 110-I1 may be disposed on the first synthetic resin layer 110-B1, exposing the first pad electrode PD1, and having a second opening I1-OP defined therein and corresponding to the first opening B1-OP. The second inorganic base layer 110-I2 may be disposed on the first inorganic base layer 110-I1, and may cover the first pad electrode PD1. The second synthetic resin layer 110-B2 may be disposed on the second inorganic base layer 110-I2. The first and second synthetic resin layers 110 - B1 and 110 - B2 may include polyimide, and the first and second inorganic substrate layers 110 - I1 and 110 - I2 may include silicon nitride, silicon oxide, silicon oxynitride, or a combination thereof.

[0167] The first connection electrode CNE1 may be electrically connected to the first pad electrode PD1 through the first contact hole CH1, and electrically connected to the data line DL through the second contact hole CH2. The first contact hole CH1 may pass through the corresponding insulating layer 10br to 50 among the insulating layers, and extend to the base layer 110. In the present embodiment, the first contact hole CH1 may pass through from the barrier layer 10br to the fifth insulating layer 50. The first contact hole CH1 may further pass through the second inorganic base layer 110-I2 and the second synthetic resin layer 110-B2 under the barrier layer 10br. The second contact hole CH2 may pass through from the second insulating layer 20 to the fifth insulating layer 50.

[0168] refer to Fig.9A and Fig. 9B , a structure in which the first connection electrode CNE1 connects the data line DL and the first pad electrode PD1 to each other may be described as an example. The arrangement relationship between the first connection electrode CNE1 and the first pad electrode PD1 may be similarly applied to Figure 8 For example, the first connection electrode CNE1 and the first pad electrode PD1 may be provided with Figure 8 The first pad electrode PD1 may be provided for each signal line, and may correspond to the control signal line CSL, the first voltage line VL1, the second voltage line VL2, the first power line PL1, and the second power line PL2. Figure 8 and Fig.9AIn the embodiment, a plurality of first pad electrodes PD1 may be arranged in the first direction DR1. The plurality of first pad electrodes PD1 may be provided on some signal lines, for example, the first power line PL1 and the second power line PL2.

[0169] Fig.9A It is illustrated that the first connection electrodes CNE1 may have the same shape and arrangement as each other, but the embodiments of the present disclosure are not limited thereto, and the first connection electrodes CNE1 may have different shapes and arrangements. For example, the positions of the first contact holes CH1 defined in the first connection electrodes CNE1 may be different from each other. More specifically, adjacent first contact holes CH1 may be arranged in a zigzag manner in the first direction DR1.

[0170] The second connection electrode CNE2 may connect the second signal line SL2 to a second pad electrode (not shown), and the second pad electrode may be connected to the reference line SL2. Fig. 9B The first pad electrode PD1 described above is substantially the same. The second pad electrode has the same material and the same stacking structure as the first pad electrode PD1. The second pad electrode may be exposed to the outside through the lower surface 110-LS of the base layer 110 to be connected to the flexible circuit board FCB (see Figure 2 Like the first pad electrode PD1, the second pad electrode may be embedded in the base layer 110.

[0171] The second connection electrode CNE2 may be electrically connected to the second pad electrode. The second connection electrode CNE2 may be electrically connected to the second pad electrode through the third contact hole CH10. The second connection electrode CNE2 may be electrically connected to the second pad electrode through the third contact hole CH10 passing through the corresponding insulating layer among the insulating layers.

[0172] The second signal line SL2 may be electrically connected to the second connection electrode CNE2 through a fourth contact hole CH20 passing through a corresponding one of the insulation layers and the insulation layers 210 , 230 , and 250 of the input sensor ISL.

[0173] refer to Fig. 9C , the additional electrostatic protection circuit ESD-I may include a first transistor T1 diode-connected from the first voltage line VL1 to the data line DL and a second transistor T2 diode-connected from the data line DL to the second voltage line VL2. The first voltage line VL1 may receive a first voltage VGL, and the second voltage line VL2 may receive a second voltage VGH higher than the first voltage VGL.

[0174] The source or drain of the first transistor T1 may be electrically connected to the gate of the first transistor T1, and the source or drain of the second transistor T2 may be electrically connected to the gate of the second transistor T2. Figure 6 The silicon transistor S-TFT shown in FIG. has the same stacking structure. Figure 6 The first connection pattern CNP1 shown in FIG. 1 is provided at the same layer as the connection pattern and can connect the gate of the first transistor T1 and the source or drain of the first transistor T1 to each other. The first voltage line VL1 can be connected to Figure 6 The second connection pattern CNP2 shown in FIG. 1 is disposed in the same layer. The first voltage line VL1 may be electrically connected to a connection pattern that connects the gate of the first transistor T1 and the source or drain of the first transistor T1. Figure 6 The first voltage line VL1 disposed at the same layer as the first connection pattern CNP1 illustrated in FIG. 1 may be electrically connected to the gate of the first transistor T1 and the source or drain of the first transistor T1 .

[0175] In the case where a voltage higher than the second voltage VGH is applied to the data line DL due to static electricity, the second transistor T2 may be turned on and current flows to the second voltage line VL2. Accordingly, the voltage of the data line DL decreases. On the contrary, in the case where a voltage lower than the first voltage VGL may be applied to the data line DL, the first transistor T1 may be turned on so that current flows from the first voltage line VL1 to the data line DL. Accordingly, the voltage of the data line DL increases. Accordingly, the voltage of the data line DL may be maintained at a level between the first voltage VGL and the second voltage VGH. Accordingly, the circuit electrically connected to the data line DL may be protected from static electricity.

[0176] Fig. 10A is an enlarged plan view of a non-display area DP-NDA of a display module DM according to an embodiment of the present disclosure. Fig. 10B The display module DM corresponds to Fig. 10A Schematic cross-sectional view along line IV-IV'. Fig. 10B A cross section of an electrostatic protection circuit portion ESU among components of the display module DM is illustrated. Fig. 10C yes Fig. 10B The circuit diagram of the electrostatic protection circuit part ESU is shown in the figure.

[0177] Fig. 10A Pictured Figure 8 2 is an enlarged portion of the non-display area DP-NDA shown in FIG. Specifically, Fig. 10A A shape in which the data line DL extends to the second substrate portion 110 - 2 and a planar arrangement of the electrostatic protection circuit ESD electrically connected to the data line DL is illustrated.

[0178] refer to Fig. 10A As described above, the base layer 110 may include a first base portion 110-1 and a second base portion 110-2, and at least some of the data lines DL may extend to the second base portion 110-2. Some of the data lines DL extending to the second base portion 110-2 may be electrically connected to the electrostatic protection circuit ESD.

[0179] The data line DL may be electrically connected to the first pad electrode PD1 through the contact hole CH (see FIG. Fig. 9B ) and the first connection electrode CNE1 (see Fig. 9B ). Fig. 10A The data line DL and the first pad electrode PD1 (see FIG. Fig. 9B ) and the first connection electrode CNE1 (see Fig. 9B ), but the structure indicated as the contact hole CH may have the first contact hole CH1 (see Fig. 9B )、the second contact hole CH2 (see Fig. 9B ) and the first connection electrode CNE1 (see Fig. 9B ) connection structure.

[0180] The electrostatic protection circuit ESD may be disposed on the second substrate portion 110-2. The electrostatic protection circuit ESD may be electrically connected to each of the data lines DL extending to the second substrate portion 110-2. The electrostatic protection circuit ESD may include a plurality of electrostatic protection circuit portions ESU arranged in the first direction DR1. Fig. 10A Four electrostatic protection circuit portions ESU are illustrated as an example, but the electrostatic protection circuit ESD may include more than four electrostatic protection circuit portions ESU. For example, the electrostatic protection circuit ESD may include 11 electrostatic protection circuit portions ESU.

[0181] The data line DL electrically connected to the electrostatic protection circuit ESD may extend to the second edge 110-EG2 of the second substrate portion 110-2. In this specification, a portion of the data line DL extending to the second edge 110-EG2 of the second substrate portion 110-2 may be referred to as an extension portion DL-E.

[0182] refer to Fig. 10A and Fig. 10B , each of the electrostatic protection circuit parts ESU included in the electrostatic protection circuit ESD includes a first diode D10 and a second diode D20. Each of the first diode D10 and the second diode D20 may be disposed in the non-display area DP-NDA.

[0183] The first diode D10 and the second diode D20 may be disposed to overlap each other in a plan view. The second diode D20 may be disposed on the first diode D10, and at least a portion of the second diode D20 overlaps at least a portion of the first diode D10 in a plan view.

[0184] The first diode D10 may include a silicon semiconductor, and the second diode D20 may include an oxide semiconductor. The first diode D10 may include, for example, amorphous silicon, polycrystalline silicon, or the like, or a combination thereof. The first diode D10 may include low temperature polycrystalline silicon. The second diode D20 may include, for example, indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO x ), indium oxide (In 2 O 3 ) or a combination thereof.

[0185] The first diode D10 may include a first pattern P1, and a source region SE10, a channel region AC10 (or an active region), and a drain region DE10 may be formed in the first pattern P1. The first pattern P1 and the aforementioned silicon transistor S-TFT (see Figure 6 ) of the first semiconductor pattern SC1 (see Figure 6 ) may include the same material. The first pattern P1 and the first semiconductor pattern SC1 (see Figure 6 ) may be disposed in the same layer and may be formed by the same process. For example, the first pattern P1 may be disposed on the buffer layer 10bf. The first pattern P1 may be disposed under the first insulating layer 10 and covered by the first insulating layer 10. In this specification, the first insulating layer 10 may be referred to as a "first inorganic insulating layer". The first diode D10 may further include a gate GT10, and the gate GT10 may be disposed on the first insulating layer 10. The gate GT10 may be a part of the metal pattern. The gate GT10 may overlap with the channel region AC10.

[0186] The first pattern P1 may include a silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon, polycrystalline silicon, etc. or a combination thereof. For example, the first pattern P1 may include low temperature polycrystalline silicon.

[0187] The second diode D20 may include a second pattern P2, and a source region SE20, a channel region AC20 (or an active region), and a drain region DE20 may be formed in the second pattern P2. The second pattern P2 and the aforementioned oxide transistor O-TFT (see Figure 6 ) of the second semiconductor pattern SC2 (see Figure 6 ) may include the same material. The second pattern P2 and the second semiconductor pattern SC2 (see Figure 6) may be disposed in the same layer and may be formed by the same process. For example, the second pattern P2 may be disposed on the third insulating layer 30. The second pattern P2 may be disposed above the first insulating layer 10 to the third insulating layer 30. The second pattern P2 may be disposed below the fourth insulating layer 40 and covered by the fourth insulating layer 40. The second diode D20 may further include a gate GT20, and the gate GT20 may be disposed on the fourth insulating layer 40. The gate GT20 may be a part of the metal pattern. The gate GT20 may overlap with the channel region AC20.

[0188] Each of the first pattern P1 of the first diode D10 and the second pattern P2 of the second diode D20 may be electrically connected to the data line DL. At least one voltage line may be diode-connected to each of the first diode D10 and the second diode D20 included in the electrostatic protection circuit portion ESU. For example, Fig. 10C As shown in FIG. 1 , a first diode D10 may be electrically connected from a first reference voltage line VL-L to a data line DL, and a second diode D20 may be electrically connected from a data line DL to a second reference voltage line VL-H. The reference voltage lines VL-L and VL-H may receive reference voltages VRL and VRH (e.g., predetermined or selectable reference voltages VRL and VRH) applied to the electrostatic protection circuit portion ESU, respectively.

[0189] The electrostatic protection circuit portion ESU can perform a buffer function in which the electrostatic protection circuit portion ESU can be protected by a retest pad TP (see FIG. Fig.14A ) in the case where an electrical overload such as static electricity occurs during a test performed by applying a voltage (e.g., a predetermined or selectable voltage), the buffer function can prevent electrical overload such as static electricity. For example, in the case where a voltage higher than the voltage of the voltage line is applied to the data line DL due to static electricity or the like during the test, each of the first diode D10 and the second diode D20 can be turned on so that current flows to the voltage line, thereby being able to prevent an excessively high voltage from being applied to the data line DL. Accordingly, during the test, the circuit electrically connected to the data line DL can be protected from static electricity or the like.

[0190] More specifically, in the case where the Fig.14A) is applied to the extended portion DL-E of the data line DL due to static electricity or the like, in a test performed by applying a voltage (e.g., a predetermined or selectable voltage), in a case where a voltage higher than the second reference voltage VRH is applied to the extended portion DL-E of the data line DL due to static electricity or the like, the electrostatic protection circuit portion ESU causes a current to flow to the second reference voltage line VL-H through the second diode D20. Accordingly, the voltage of the data line DL decreases. On the contrary, in a case where a voltage lower than the first reference voltage VRL is applied to the data line DL, a current flows from the first reference voltage line VL-L to the data line DL through the first diode D10. Accordingly, the voltage of the data line DL increases. Therefore, although a high level of static electricity may be generated during the test or a high level of current or voltage may be applied due to other reasons, the voltage of the data line DL can be maintained at a level between the first reference voltage VRL and the second reference voltage VRH. Accordingly, the electrostatic protection circuit portion ESU can protect the circuit electrically connected to the data line DL from static electricity during the test.

[0191] The first diode D10 and the second diode D20 included in each electrostatic protection circuit portion ESU may be arranged to overlap each other in a plan view. By having a structure in which the first diode D10 including a silicon semiconductor and the second diode D20 including an oxide semiconductor may be vertically arranged and overlap each other, the electrostatic protection circuit portion ESU may reduce the occupied area compared to the area occupied by the structure in which the two diodes are arranged in the same layer. Since the electrostatic protection circuit portion ESU includes the first diode D10 and the second diode D20 that may be vertically arranged, the area of ​​the region in which the electrostatic protection circuit ESD may be arranged may be minimized. Accordingly, the area of ​​the non-display area DP-NDA in which the electrostatic protection circuit ESD may be arranged may be reduced.

[0192] Reference again Fig. 10A , the length d1 of the electrostatic protection circuit portion ESU in the second direction DR2 may be in the range of about 200 μm to about 300 μm. Since the electrostatic protection circuit portion ESU has a structure in which the first diode D10 and the second diode D20 may be disposed to overlap each other in a plan view, the length d1 in the second direction DR2 may be reduced to about 300 μm or less.

[0193] The width d2 of the electrostatic protection circuit portion ESU in the first direction DR1 may be in the range of about 70 micrometers to about 130 micrometers. The total width d3 of the electrostatic protection circuit ESD including the plurality of electrostatic protection circuit portions ESU in the first direction DR1 may be in the range of about 900 micrometers to about 1300 micrometers. Since the widths of the electrostatic protection circuit portions ESU and the electrostatic protection circuit ESD in the first direction DR1 and the lengths in the second direction DR2 satisfy the aforementioned ranges, the electrostatic protection circuit ESD may protect the circuit electrically connected to the data line DL from static electricity, etc. during testing while minimizing the area of ​​the region in which the electrostatic protection circuit ESD may be disposed.

[0194] Fig.11A and Fig. 11B 2 is a plan view of electrostatic protection circuit portions ESU and ESU′ according to an embodiment of the present disclosure.

[0195] Reference together Fig. 10A , Fig. 10B and Fig.11A , the electrostatic protection circuit part ESU includes a first diode D10 and a second diode D20, and the first diode D10 and the second diode D20 may be arranged to overlap each other in a plan view. The second diode D20 may be arranged on the first diode D10, and in a plan view, at least a portion of the second diode D20 overlaps at least a portion of the first diode D10.

[0196] like Fig.11A As shown in , the first diode D10 and the second diode D20 can be arranged to completely overlap each other in a plan view. Since the first diode D10 and the second diode D20 have the same planar area as each other and have the same arrangement position as each other, they can completely overlap each other in a plan view. In the electrostatic protection circuit portion ESU according to an embodiment of the present disclosure, the first outer line D10-E of the first diode D10 and the second outer line D20-E of the second diode D20 can be defined to completely overlap each other in a plan view. Fig.11A The first outer line D10 -E of the first diode D10 illustrated in FIG. 1 may be an outer line of the above-mentioned first pattern P1 , and the second outer line D20 -E of the second diode D20 may be an outer line of the above-mentioned second pattern P2 .

[0197] like Fig. 11BAs shown in FIG. 1 , in the electrostatic protection circuit portion ESU′ according to an embodiment of the present disclosure, in a plan view, the first diode D10 and the second diode D20 may be arranged to partially overlap each other, and the remaining portions thereof may be arranged not to overlap each other. The first outer line D10-E of the first diode D10 and the second outer line D20-E of the second diode D20 may not match each other. Fig. 11B The first outer line D10 -E of the first diode D10 illustrated in FIG. 1 may be an outer line of the above-mentioned first pattern P1 , and the second outer line D20 -E of the second diode D20 may be an outer line of the above-mentioned second pattern P2 . Fig. 11B It is illustrated that the second diode D20 has a greater width than the first diode D10 in the first direction DR1 and the first diode D10 has a greater width than the second diode D20 in the second direction DR2 , but the planar shapes and areas of the first and second diodes D10 and D20 are not limited thereto.

[0198] Fig.12 The display module DM corresponds to Fig. 10A Schematic cross-sectional view along line V-V'. Fig.12 A cross section corresponding to a second edge 110 - EG2 from which the data line DL extends is illustrated.

[0199] refer to Fig. 10A and Fig.12 , the display module DM according to an embodiment of the present disclosure may further include a molding part MDP. The molding part MDP may cover the second edge 110-EG2 of the base layer 110. The molding part MDP may be configured to cover at least the side surface of the base layer 110. Since the molding part MDP covers the second edge 110-EG2, the data line DL extending to the second edge 110-EG2 may be covered by the molding part MDP, so that additional static electricity can be prevented from being generated or the data line DL can be prevented from being damaged. The molding part MDP may include an acrylic resin, and the type of the resin may not be particularly limited. The molding part MDP may include polypropylene, polyethylene, polystyrene, acrylonitrile-styrene, polymethyl methacrylate, or a combination thereof. Although not shown in the figure, the molding part MDP may cover not only the display module DM but also the lower member LM (see Figure 3 ) and the upper member UM (see Figure 3 )’s edge.

[0200] Fig.13 is a flowchart illustrating a method of manufacturing a display device according to an embodiment of the present disclosure. FIG. 14A to FIG. 14C is a plan view illustrating steps of a method of manufacturing a display device according to an embodiment of the present disclosure. FIG. 14A to FIG. 14C Graphics and Fig. 10AThe steps in the method for manufacturing a display device in the corresponding plan view. Fig.13 and FIG. 14A to FIG. 14C In describing a method of manufacturing a display device according to an embodiment of the present disclosure, the same reference numerals are assigned to the same components as those described above, and a detailed description thereof is omitted.

[0201] refer to Figure 8 and Fig.13 , in manufacturing a display device DD including a display area DP-DA and a non-display area DP-NDA (see Figure 2 ) method, the method of manufacturing a display device includes performing a test (S100) by applying a voltage (e.g., a predetermined or selectable voltage) via a retest pad provided in a non-display area and removing a portion of the non-display area (S200).

[0202] refer to Figure 8 , Fig.13 and Fig.14A In the method of manufacturing a display device according to an embodiment of the present disclosure, as described above, the base layer 110 of the display module DM may include a first base portion 110-1 and a second base portion 110-2, and at least some of the data lines DL may extend to the second base portion 110-2.

[0203] The display module DM can be electrically connected to a retest pad TP, which is electrically connected to the end of the data line DL. In a step before removing a portion of the non-display area, the retest pad TP can be set adjacent to the preparation edge 110-EGP which can be defined as the end of the second substrate portion 110-2. The test can be performed by applying a voltage (e.g., a predetermined or selectable voltage) via the retest pad TP. In the test that can be performed by applying a voltage (e.g., a predetermined or selectable voltage) via the retest pad TP, the electrostatic protection circuit ESD can perform a buffering function to prevent an electrical overload such as static electricity in the event of an electrical overload such as static electricity. For example, in the event that a voltage higher than the voltage of the voltage line is applied to the data line DL during the test due to static electricity, etc., due to the first diode D10 described above (see Fig. 10B ) and the second diode D20 (see Fig. 10B ) can be turned on and allow current to flow to the voltage line, so that excessive voltage can be prevented from being applied to the data line DL. Accordingly, when a test is performed, the circuit electrically connected to the data line DL can be protected from static electricity, etc.

[0204] The display module DM may further include an illumination pad line TLL extending in parallel with the data line DL. The illumination pad line TLL may be electrically connected to an illumination pad TLP disposed outside the display module DM. In the case where a test is performed via the retest pad TP, the illumination pad TLP may be used to determine whether there is a defect. The illumination pad line TLL may have a width greater than that of the data line DL. For example, the illumination pad line TLL may have a width that may be about 10 times or more of the width of the data line DL.

[0205] The cutting lines CL1 and CL2 defined in the second substrate portion 110-2 may be defined in the display module DM. The cutting lines CL1 and CL2 may be virtual lines on which a cutting process may be performed in removing a portion of the non-display area (S200). In removing a portion of the non-display area (S200), after a cutting process is performed along the cutting lines CL1 and CL2, portions below the cutting lines CL1 and CL2 in a plan view may be removed.

[0206] refer to Figure 8 , Fig.13 , Fig.14A and Fig. 14B , in removing a portion of the non-display area (S200), a cutting process may be performed along a first cutting line CL1, and a first portion in which the retest pad TP is disposed may be removed. When the cutting process is performed along the first cutting line CL1, a second edge 110-EG2 of the second substrate portion 110-2 may be formed. After removing a portion of the non-display area (S200), the data line DL may extend to the second edge 110-EG2 of the second substrate portion 110-2. When the cutting process is performed along the first cutting line CL1, the lighting pad TLP electrically connected to the lighting pad line TLL may be removed together.

[0207] Although not shown, after removing a portion of the non-display area (S200), the step of forming a molding portion to cover at least a portion of the non-display area may further include forming a molding portion MDP (see Fig.12 ) may cover the second edge 110-EG2 of the base layer 110. Since the method of manufacturing a display device according to an embodiment of the present disclosure further includes forming a molding portion, the data line DL extending to the second edge 110-EG2 may be covered, thereby preventing additional static electricity from being generated or preventing the data line DL from being damaged.

[0208] refer to Figure 8 , Fig.13 , Fig.14A and Fig. 14C, in removing a portion of the non-display area (S200), a cutting process may be performed along a second cutting line CL2, and a first portion in which the retest pad TP may be disposed and a second portion in which the electrostatic protection circuit ESD may be disposed may be removed together. When the cutting process is performed along the second cutting line CL2, a second edge 110-EG2' of the second substrate portion 110-2 may be formed. After removing a portion of the non-display area (S200), the data line DL may extend to the second edge 110-EG2' of the second substrate portion 110-2. When the cutting process is performed along the second cutting line CL2, the lighting pad TLP electrically connected to the lighting pad line TLL may also be removed. In the case where the cutting process is performed along the second cutting line CL2, the area of ​​the second substrate portion 110-2 may be minimized. After removing a portion of the non-display area (S200), as described above, a molding portion MDP (see FIG. 1 ) covering the second edge 110-EG2' of the substrate layer 110 may be performed. Fig.12 )’s formation.

[0209] According to the present disclosure, a flexible circuit board can be bonded to the rear surface of a display panel. Since the non-display area of ​​the display panel may not be bent, defects that may occur when the non-display area of ​​the display panel is bent can be prevented. The area of ​​the frame area of ​​the window for covering the non-display area of ​​the display panel can be reduced.

[0210] In order to reduce the non-display area, the electrostatic protection circuit disposed in the non-display area has a structure in which two diodes can be disposed to overlap each other. Accordingly, the area occupied by the electrostatic protection circuit can be minimized, and thus, the non-display area can be reduced.

[0211] Although the above description has been made with reference to the embodiments of the present disclosure, it will be understood by those skilled in the art or those of ordinary skill in the art that various modifications and changes may be made to the present disclosure without departing from the spirit and technical scope of the present disclosure described in the claims. Accordingly, the technical scope of the present disclosure should not be limited to the contents described in the specific embodiments in the specification, but should be determined by the claims.

Claims

1. A display device, comprising: The display panel comprises a display area and a non-display area, wherein the display panel comprises: a base layer overlapping the display area and the non-display area and comprising a lower surface and an upper surface opposite to the lower surface; a pad electrode exposed through the lower surface of the base layer; a pixel disposed on the upper surface of the base layer and including a light emitting element overlapping the display area and a transistor electrically connected to the light emitting element; a data line, disposed on the upper surface of the substrate layer, overlapping the display area and the non-display area, and electrically connected to the transistor; an electrostatic protection circuit electrically connected to the data line; and a connecting electrode electrically connecting the data line and the pad electrode to each other in the non-display area, and The electrostatic protection circuit comprises: A first diode is disposed in the non-display area; and A second diode is disposed on the first diode and overlaps at least a portion of the first diode in a plan view.

2. The display device according to claim 1, wherein: The first diode includes a silicon semiconductor, and The second diode includes an oxide semiconductor.

3. The display device according to claim 1, wherein: The second diode completely overlaps the first diode.

4. The display device according to claim 1, wherein: The data line extends in a first direction, and A length of the electrostatic protection circuit in the first direction is in a range of 200 micrometers to 300 micrometers.

5. The display device according to claim 1, wherein: The display panel further includes a plurality of insulating layers disposed on the upper surface of the base layer, The connection electrode is electrically connected to the pad electrode through a first contact hole, The first contact hole passes through at least one of the plurality of insulating layers and is defined in the base layer, and The connection electrode is electrically connected to the data line through a second contact hole penetrating at least one of the plurality of insulating layers.

6. The display device according to claim 1, wherein: The display panel further includes an additional electrostatic protection circuit electrically connected to the data line and disposed closer to the display area than the electrostatic protection circuit.

7. The display device according to claim 5, wherein: The plurality of insulating layers include a first inorganic insulating layer, At least a portion of the first diode is disposed below the first inorganic insulating layer, and The second diode is disposed above the first inorganic insulating layer.

8. The display device according to claim 7, wherein: The first diode includes a first pattern disposed below the first inorganic insulating layer, the first pattern including a silicon semiconductor, and The second diode includes a second pattern disposed over the first inorganic insulating layer, the second pattern including an oxide semiconductor.

9. The display device according to claim 8, wherein: The first pattern and the second pattern overlap each other in a plan view.

10. A method for manufacturing a display device including a display area and a non-display area, the method comprising: performing a test by applying a voltage through a retest pad disposed in the non-display area; as well as removing a portion of the non-display area, wherein, during the execution of the test, an electrostatic protection circuit is electrically connected to the retest pad, Wherein, the electrostatic protection circuit comprises: A first diode is disposed in the non-display area; and A second diode is disposed on the first diode and overlaps at least a portion of the first diode in a plan view.

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