Wide-temperature-range low-resistance-drift phase change storage material, device and storage and calculation integrated array

Abstract

The invention discloses a wide-temperature-range low-resistance-drift phase change storage material, a device and a storage and calculation integrated array, the phase change storage material comprises a chromium (Cr) element and a tellurium (Te) element, the chemical formula is CrxTe100-x, and x is greater than 0 and less than 100; the resistance drift coefficients of the amorphous film and the crystal film of the phase change storage material in the temperature range of-200 DEG C to 200 DEG C are both smaller than or equal to 0.002. An amorphous phase local mechanism of the phase change storage material is mainly an octahedron, obvious Pearse distortion does not exist, an ultralow resistance drift coefficient can be kept in a wide temperature range, and the problem of resistance drift in an existing phase change storage technology is solved, especially the problem that the resistance drift behavior is complicated under the working condition temperature of the wide temperature range is solved.

Description

Technical Field

[0001] The present invention relates to the field of non-volatile storage technology, and in particular to a phase-change storage material, device and storage-computing integrated array with low resistance drift over a wide temperature range. Background Art

[0002] Phase change storage technology uses the fast reversible phase change and huge resistance difference between the amorphous phase and the crystalline phase of the phase change material to switch between the logical values ​​of "0" (RESET state) and "1" (SET state) for data storage. In addition, the huge resistance window between the SET and RESET states of the phase change memory (for example, the resistance window of the commercial phase change material germanium antimony telluride can reach 3-6 orders of magnitude) enables it to obtain multiple recognizable resistance values ​​in the same storage unit through a gradual phase change, thereby breaking through binary storage and realizing "multi-value storage" technology and "storage and computing in one" technology. Storage and computing in one means that by constructing a storage cell array and directly solving matrix-vector multiplication with electrical measurements, the computing power can be greatly improved. The more recognizable logical values ​​a single storage cell has, the higher the computing efficiency of the array.

[0003] However, the spontaneous structural relaxation of amorphous phase change materials causes the resistance value of the device to continue to increase over time, that is, resistance drift. The amorphous phase drift coefficient of amorphous germanium antimony telluride alloy at room temperature is as high as 0.11. This phenomenon will seriously affect the coding accuracy of storage and computing devices, resulting in a high bit error rate. It also limits the number of logical values ​​that can be recognized by a single node of the storage unit, which is one of the main bottlenecks for improving the computing power of phase change storage and computing chips. In addition, the temperature range faced by memory chips in different service scenarios is extremely wide. For example, the operating temperature of chips in servers and data centers is usually 60 to 80°C, the operating temperature in vehicle embedded environments is -40 to 165°C, and the operating temperature in the external environment of the International Space Station needs to cycle between -120 and 120°C 16 times a day. The wide range and diversity of service environment temperatures make the resistance drift phenomenon of phase change memory more complicated, and it is difficult to compensate through external conditions such as software algorithms and circuit design. Therefore, it is urgent to develop a phase change storage material with intrinsic low resistance drift characteristics in a wide temperature range. Summary of the invention

[0004] In order to overcome the defects of the above-mentioned prior arts, the present invention proposes a phase-change storage material, device and storage-computing integrated array with low resistance drift in a wide temperature range. The local structure of the amorphous phase of the phase-change storage material is mainly octahedral, and there is no obvious Peierls distortion. It can maintain an ultra-low resistance drift coefficient in a wide temperature range, and overcomes the resistance drift problem in the existing phase-change storage technology, especially the problem of complicated resistance drift behavior under wide temperature range operating conditions.

[0005] In order to achieve the above object, the technical solution adopted by the present invention is:

[0006] A phase change memory material with a wide temperature range and low resistance drift, the chemical formula is Cr x Te 100-x , where 0<x<100;

[0007] The resistance drift coefficients of the amorphous and crystalline films of the phase change memory material in the temperature range of -200 to 200° C. are both ≤0.002.

[0008] The crystal phase structure of the phase change memory material has a layered structure characteristic, and the Cr atoms in the layer structure form a [CrTe6] octahedral local structure with the Te atoms, and each octahedral structure is connected in the form of shared angles and shared edges; the interlayer structure is mainly connected by van der Waals force.

[0009] In the amorphous phase structure of the phase change memory material, most of the Cr atoms form a [CrTe6] octahedral local structure with Te atoms, and the remaining Cr atoms form a defective octahedral local structure, and each octahedral or defective octahedral structure is randomly distributed and connected.

[0010] The local structures of the crystal and amorphous phase change memory material are mainly [CrTe6] octahedron, which has stable Cr-Te chemical bonds, and the bond lengths of the Cr-Te bonds along the same direction are basically the same, without obvious Peierls distortion.

[0011] The preparation method of the phase change memory material includes but is not limited to magnetron sputtering, chemical vapor deposition, atomic layer deposition or electron beam evaporation.

[0012] The amorphous film crystallization temperature of the phase change storage material is 250-300° C., and the ten-year data retention temperature is 130-190° C.

[0013] The amorphous phase of the phase change memory material is in a high resistance state, and the resistance value at room temperature is generally about 5×10 4 Ω~about 1×10 6 Ω; the crystal phase is a low resistance state, and the resistance value at room temperature is usually about 1×10 3 Ω~about 5×10 4 Ω; the resistance value varies with temperature and film thickness.

[0014] The phase change storage material can be applied to phase change memory and phase change storage and computing integrated array.

[0015] Phase change memory, the device can use a restricted structure, including a substrate, the substrate is a SiO2 / Si substrate, and above the substrate are a bottom electrode layer, an oxide dielectric layer, a phase change memory material layer and a top electrode layer in sequence; the materials of the bottom electrode layer and the top electrode layer are TiN or W, Cr, Cu high conductivity and high thermal conductivity materials; the oxide dielectric layer is SiO2 low conductivity and low thermal conductivity material;

[0016] The thickness of the bottom electrode layer, oxide dielectric layer, phase change memory material layer and top electrode layer is between 10nm and 1000nm. The phase change memory material layer is located in the middle of the through hole of the oxide dielectric layer. The through hole is cylindrical or columnar and is concentrically arranged with the oxide dielectric layer, and the corresponding diameter or side length is between 10nm and 1000nm.

[0017] The device may adopt a T-type structure, including a substrate, the substrate is a SiO2 / Si substrate, and above the substrate are a bottom electrode layer, an oxide dielectric layer, a heating electrode layer, a phase change storage material layer and a top electrode layer in sequence;

[0018] The materials of the bottom electrode layer, the top electrode layer and the heating electrode layer are high electrical conductivity and high thermal conductivity materials such as TiN or W, Cr, and Cu; the oxide dielectric layer is low electrical conductivity and low thermal conductivity material such as SiO2; the thickness of the bottom electrode layer 1, the oxide dielectric layer, the phase change storage material layer, the top electrode layer and the heating electrode layer are between 10nm and 1000nm; the heating electrode layer is arranged in the middle of the through hole of the oxide dielectric layer; the through hole is cylindrical or columnar and is arranged concentrically with the oxide dielectric layer, and the corresponding diameter or side length is between 10nm and 1000nm.

[0019] The functional layer material of the device is Cr x Te 100-x Materials; by loading current or voltage pulses to achieve the SET and RESET reversible operations of the device, which correspond to the crystallization and amorphization processes of the phase change storage material layer film respectively; by adjusting the amplitude and pulse width of the pulse to achieve partial crystallization or partial amorphization of the functional layer film, different resistance states are obtained, corresponding to different logic values;

[0020] The resistance drift coefficients of the different resistance states of the device are all ≤0.002 in the temperature range of -200 to 200°C. The resistance drift coefficient can be calculated by the formula R=R0(t / t0): v Evaluation is performed, where R0 is the resistance at time t0, t is the test time, and v is the resistance drift coefficient.

[0021] The electrical pulse width range of the SET operation of the device is usually about 1ns to 1000ns, and the amplitude range is usually about 0.5V to 7V; the electrical pulse width range of the RESET operation is usually about 0.1ns to 100ns, and the amplitude range is usually about 3V to 10V; the partial SET operation is performed when the device is in the RESET state, and its parameters can be adjusted in a certain proportion to the parameters of the SET operation according to the required number of intermediate resistance states; the partial RESET operation is performed when the device is in the SET state, and its parameters can be adjusted in a certain proportion to the parameters of the RESET operation according to the required number of intermediate resistance states; the phase change memory film in the device in the partial SET state and the partial RESET state is composed of a mixture of a crystalline phase and an amorphous phase, and different volume ratios of the two correspond to different resistance states.

[0022] The device unit was RESET operated by applying an electrical pulse with a pulse width of 80ns and a voltage of 4.5V. The resistance value of the device was measured to be about 2×10 3 Ω, which is a low resistance state at this time; an electrical pulse with a pulse width of 80ns and a voltage of 2.7V is applied to perform partial SET operation, and the measured device resistance value is about 3×10 4 Ω, which is the first intermediate resistance state; an electrical pulse with a pulse width of 80ns and a voltage of 4V is applied to perform a partial RESET operation, and the measured device resistance value is about 7×10 4 Ω, which is the second intermediate resistance state.

[0023] The storage and computing integrated array is one of a cross-bar structure, a transistor-memristor cascade structure or a three-dimensional stacked structure, and the device unit structure in the array is one of a restricted structure, a T-type structure or a bridge structure;

[0024] The functional layer material of the device unit in the array is Cr x Te 100-x Materials; the logic state programming of the device unit in the array is achieved by loading a current or voltage pulse of a certain amplitude and pulse width, which corresponds to partial crystallization or partial amorphization of the functional layer film; the logic state reconstruction of the device unit in the array can be achieved by SET or RESET operation, which corresponds to complete crystallization or complete amorphization of the functional layer film;

[0025] The resistance drift coefficients of the different logic states of the device units in the array are all ≤0.002 in the temperature range of -200 to 200°C. The resistance drift coefficient can be calculated by the formula R=R0(t / t0): v Evaluation is performed, where R0 is the resistance at time t0, t is the test time, and v is the resistance drift coefficient.

[0026] Beneficial effects of the present invention:

[0027] The amorphous structure of the traditional phase change material germanium antimony telluride contains a large number of germanium tetrahedral defects, and the bond lengths of chemical bonds along the same direction in the local structure are different, forming long and short bonds. During the process of structural relaxation, obvious Peierls distortion will occur, resulting in a large resistance drift. x Te 100-x Phase change material does not contain germanium, and the local structural unit in its amorphous phase is basically consistent with the crystal phase, which is mainly [CrTe6] octahedron. The bond length of Cr-Te bond along the same direction is basically the same, and there is no obvious Peierls distortion, which effectively decouples the direct relationship between structural relaxation and resistance drift. Therefore, the resistance drift coefficient of its amorphous film is ≤0.002. In addition, Cr x Te 100-x The crystallization temperature of the amorphous film of phase change material can reach 250-300℃, which is much higher than ~150℃ of germanium, antimony and tellurium. Therefore, its amorphous film has excellent thermal stability, and the resistance drift coefficient in the temperature range of -200-200℃ is ≤0.002.

[0028] Phase change memory devices and integrated storage and computing arrays are programmed with multiple logic values ​​by adjusting the volume ratio of crystal and amorphous in the functional layer film, wherein the resistance drift of the amorphous part will cause decoding errors of the logic value. The device and array proposed by the present invention use Cr x Te 100-x As a functional layer material, the amorphous film has an ultra-low resistance drift coefficient in a wide temperature range. Therefore, the resistance drift coefficient of different logic states of the device unit is ≤0.002 in the temperature range of -200 to 200°C, which effectively improves the programming and reading and writing accuracy of the logic state. It is expected to expand the storage density of phase change devices and the array scale of in-memory computing. At the same time, it broadens the operating temperature range of devices and arrays, and can maintain high accuracy and consistency of operation programming and data recognition at a variety of service temperatures.

[0029] The Cr x Te 100-x Phase change storage materials, devices and integrated storage and computing arrays, the preparation methods of their films include but are not limited to magnetron sputtering, chemical vapor deposition, atomic layer deposition or electron beam evaporation, and the preparation methods of devices and arrays include but are not limited to ultraviolet exposure, electron beam lithography, dry etching or wet etching, etc., all of which are compatible with existing mature CMOS semiconductor processing technology, easy to achieve large-scale integration and engineering preparation, and have broad application prospects and important application value in the fields of data-intensive multi-value storage, embedded non-volatile storage, integrated storage and computing, and neuron-inspired brain-like computing. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 Cr x Te 100-xAtomic model of the crystal structure.

[0031] Figure 2 Cr x Te 100-x Atomic model of amorphous structure.

[0032] Figure 3 Cr x Te 100-x Resistance-temperature curve of phase change film.

[0033] Figure 4 Cr x Te 100-x The resistance drift curves of phase change films were measured in multiple temperature zones.

[0034] Figure 5 Cr x Te 100-x Ten-year data retention temperature test of phase change films.

[0035] Figure 6 Cr x Te 100-x Schematic cross-section of a confined electronics unit.

[0036] Figure 7 Cr x Te 100-x Schematic cross-section of a T-shaped electronics unit.

[0037] Figure 8 Cr x Te 100-x Schematic diagram of a phase change device array.

[0039] 1—top electrode layer of the confined phase change device; 2—phase change material layer; 3—oxide dielectric layer; 4—bottom electrode layer; 5—heating electrode layer. DETAILED DESCRIPTION

[0040] The present invention will be further described in detail below in conjunction with the accompanying drawings.

[0041] Figure 1 Cr x Te 100-x The atomic model of the crystal structure, in which the basic unit of the local structure is the [CrTe6] octahedron, and the crystal structure is composed of multiple [CrTe6] octahedron structures connected in the form of shared corners and shared edges. The bond lengths of Cr-Te bonds along the same direction are basically the same, and there is no obvious Peierls distortion.

[0042] Figure 2 Cr x Te 100-xThe atomic model of the amorphous structure, in which most Cr atoms and Te form a local structure of [CrTe6] octahedron, the bond lengths of Cr-Te bonds along the same direction are basically the same, and there is no obvious Peierls distortion.

[0043] Figure 3 Cr x Te 100-x Resistance-temperature curve of phase change film, Cr prepared by magnetron sputtering 25 Te 75 The phase change film is in a low resistance state when deposited. When the heating temperature rises to about 270°C, the resistance value rises sharply, and the film begins to crystallize. When heated to 350°C, the temperature drops to room temperature. Comparing the resistance values ​​before and after annealing, the difference between the crystalline resistance and the amorphous resistance is about one order of magnitude, so the crystalline state of the film is in a high resistance state. The two-point method is used throughout the test process, and the heating rate is 10°C / min.

[0044] Figure 4 Cr x Te 100-x Resistance drift curves of phase change films in multiple temperature zones. 25 Te 75 The phase change film was tested for resistance-time, its resistance changed with time and the results were fitted. It was confirmed that its drift coefficient in multiple temperature ranges such as -150 to 150°C was ≤0.002, which was about two orders of magnitude lower than the drift coefficient of the traditional amorphous germanium antimony tellurium alloy, proving that the material has extremely low resistance drift.

[0045] Figure 5 Cr x Te 100-x The ten-year data retention temperature curve of the phase change film. By selecting four known temperature points below the crystallization temperature for resistance-time testing, the relationship between the resistance failure time and temperature is obtained, where the resistance failure time refers to the time required for the resistance value of the material to drop to half of its initial value when the material is kept at a constant temperature. The resistance failure time and temperature are fitted into the Arrhenius formula to obtain Cr x Te 100-x The ten-year data retention temperature of the phase change film is about 162°C, which is about 70°C higher than the amorphous drift coefficient of traditional germanium antimony tellurium alloy, proving that the material has high amorphous thermal stability.

[0046] Figure 6 Cr x Te 100-xSchematic diagram of the cross section of the restricted device unit. The substrate is a SiO2 / Si substrate. Above the substrate are the bottom electrode layer 1, the oxide dielectric layer 2, the phase change storage material layer 3 and the top electrode layer 4. The materials of the bottom electrode layer 1 and the top electrode layer 4 are usually high conductivity and high thermal conductivity materials such as TiN or W, Cr, Cu; the oxide dielectric layer 2 is usually low conductivity and low thermal conductivity materials such as SiO2. The thickness of the above materials is usually between 10nm and 1000nm. The diameter of the phase change storage material layer 3 is usually between 10nm and 1000nm.

[0047] Figure 7 Cr x Te 100-x Schematic diagram of a cross section of a T-type device unit. The substrate is a SiO2 / Si substrate. Above the substrate are the bottom electrode layer 1, the oxide dielectric layer 2, the heating electrode layer 5, the phase change storage material layer 3 and the top electrode layer 4 in sequence. The materials of the bottom electrode layer 1, the top electrode layer 4 and the heating electrode layer 5 are usually high-conductivity and high-thermal-conductivity materials such as TiN or W, Cr, Cu; the oxide dielectric layer 2 is usually low-conductivity and low-thermal-conductivity materials such as SiO2. The thickness of the bottom electrode layer 1, the oxide dielectric layer 2, the phase change storage material layer 3 and the top electrode layer 4 is usually between 10nm and 1000nm. The diameter of the heating electrode layer 5 is usually between 10nm and 1000nm.

[0048] Figure 8 Cr x Te 100-x Schematic diagram of a phase-change memory material suitable for a storage-computing integrated array. The top and bottom electrodes of the device units are arranged in a cross pattern to form word lines, bit lines, and source lines. The array size can be expanded in the planar direction.

[0049] The phase change storage material is stored in the device array in the form of conductivity information through the write operation, and the voltage input is used as the input quantity. According to Kirchhoff's law, the final current output value is the result of the matrix-vector multiplication calculation. x Te 100-x Phase change storage materials have the characteristics of low drift in multiple temperature zones, thus realizing high-precision edge storage and computing integrated applications.

[0050] The present invention is further described below by taking specific embodiments as examples.

[0051] Example 1

[0052] In this embodiment, Cr 30 Te 70 Taking the magnetron sputtering preparation and electrical performance measurement of phase change films as an example, the specific process is as follows:

[0053] The Cr single target and the Te single target were used for double target co-sputtering to prepare the Cr30 Te 70 Phase change film. The sputtering of Cr single target uses a DC power supply with a power of 20W, and the sputtering of Te single target uses an RF power supply with a power of 37W. The sputtering time is 20 minutes, and the film thickness is ~200nm. Subsequently, a protective layer with a thickness of about 10nm was uniformly sputtered on the surface of the film using a ZnS-SiO2 target to avoid film damage introduced in subsequent tests.

[0054] The resistance-temperature test of the film was carried out using a digital source meter and an in-situ hot and cold stage. The resistance test was obtained by using a digital source meter to load voltage and test current. The test voltage was 0.1V; the temperature was controlled by using an in-situ hot and cold stage, and the heating rate was set to 10℃ / min, heated to 350℃ and then cooled to room temperature. The cooling rate was set to 20℃ / min. The measured resistance-temperature curve is shown in Figure 3 As shown in the figure, it can be seen that the crystallization temperature of the film is about 270°C, and the resistance values ​​of the deposited and annealed states are ~8×10 3 Ω and ~9×10 4 Ω, the resistance value changes inversely during the crystallization process. Subsequently, the same batch of films were used for a ten-year data retention test, and resistance-time tests were performed at 245℃, 250℃, 255℃ and 260℃, respectively. The resistance change of 50% was used as the standard to determine whether the resistance was failed. The Arrhenius formula was used for fitting, and the ten-year data retention of the film was obtained to be ~162℃.

[0055] Example 2

[0056] In this embodiment, Cr 30 Te 70 Taking the preparation and electrical performance test of the restricted phase change memory device unit as an example, the specific process is as follows:

[0057] The phase change memory device unit is prepared on a substrate (SiO2 / Si, SiO2 thickness is about 300nm), including a bottom electrode layer (W, thickness is about 200nm), a dielectric layer (SiO2, thickness is about 100nm), a functional layer (Cr 30 Te 70 , thickness of about 50nm) and a top electrode layer (W, thickness of about 200nm), as shown in the attached Figure 6 All the above layers were deposited by magnetron sputtering, where W used a DC power supply with a power of 80W and a preparation time of 80 minutes; SiO2 used an RF power supply with a power of 50W and a preparation time of 92 minutes; Cr 30 Te 70 A Cr target and a Te target were co-sputtered, wherein Cr used a DC power supply with a power of 20 W, and Te used an RF power supply with a power of 37 W. The preparation time was 5 minutes.

[0058] The electrical performance of the above device units was tested using an electrical test probe station, a digital source meter, and a pulse signal generator. First, a DC test was used to perform a SET operation on the initial state device unit, and the device resistance value was measured to be approximately 3×10 5 Ω, at this time the phase change memory film in the device is in an amorphous phase. By comparing the resistance values ​​before and after the operation, it is confirmed that the initial state is a low resistance state and the SET state is a high resistance state. The device unit is RESET operated by applying an electrical pulse with a pulse width of 80ns and a voltage of 4.5V. The measured device resistance value is about 2×10 3 Ω, at this time, the phase change memory film in the device is in the crystalline phase, and the RESET state is a low resistance state; if an electrical pulse with a pulse width of 80ns and a voltage of 2.7V is loaded in the RESET state to perform a partial SET operation, the measured device resistance value is about 3×10 4 Ω, at this time the phase change memory film in the device is in the first intermediate resistance state; if an electrical pulse with a pulse width of 80ns and a voltage of 4V is loaded in the SET state to perform a partial RESET operation, the measured device resistance value is about 7×10 4 Ω, which is the second intermediate resistance state. After partial SET operation and partial RESET operation, the phase change memory film in the device is a mixture of crystalline phase and amorphous phase, but the volume ratio of the two is different, so different resistance states can be obtained. The resistance values ​​of the SET state, RESET state and two intermediate resistance states were measured at room temperature using an electrical probe station and a digital source meter for 1 hour. According to the measurement results, the resistance drift coefficients of the four resistance states were calculated to be ≤0.002.

[0059] Example 3

[0060] This embodiment is based on Cr 30 Te 70 Taking the preparation of the reconfigurable phase change storage and computing integrated array of T-shaped structure device units and the electrical performance test at different temperatures as an example, the specific process is as follows:

[0061] The device unit in the reconfigurable phase change storage and computing integrated array is a T-shaped structure. The device unit is prepared on a substrate (SiO2 / Si, SiO2 thickness is about 300nm), including a bottom electrode layer (W, thickness is about 200nm), a heating electrode layer (W, through hole diameter is about 200nm), a dielectric layer (SiO2, thickness is about 100nm), and a functional layer (Cr 30 Te 70 , thickness of about 50nm) and a top electrode layer (W, thickness of about 200nm), as shown in the attached Figure 7 The devices are connected to each other in an array by word lines, bit lines and source lines, as shown in the attached figure. Figure 8 shown.

[0062] The prepared device array was placed in an environment of 200°C, and SET, partial SET, RESET, and partial RESET operations were performed on the device units at designated locations in the device array. The resistance values ​​of the device in the SET state and the RESET state differed by more than an order of magnitude, and the resistance values ​​of the partial SET state and the partial RESET state were between the SET state and the RESET state. The resistance drift coefficients of the four resistance states were all ≤0.002 within one hour.

[0063] The prepared device array was placed in a -200℃ environment, and SET, partial SET, RESET, and partial RESET operations were performed on the device units at designated locations in the device array. The resistance values ​​of the device in the SET state and the RESET state differed by more than an order of magnitude, and the resistance values ​​of the partial SET state and the partial RESET state were between the SET state and the RESET state. The resistance drift coefficients of the four resistance states were all ≤0.002 within one hour.

Claims

1. A phase change memory material with low resistance drift over a wide temperature range, characterized in that: The chemical formula is Cr x Te 100-x , where 0<x<100; The resistance drift coefficients of the amorphous and crystalline films of the phase change memory material in the temperature range of -200 to 200° C. are both ≤0.

002.

2. The phase change memory material with a wide temperature range and low resistance drift according to claim 1, characterized in that: The crystal phase structure of the phase change memory material has a layered structure feature, and the Cr atoms in the layer structure form a [CrTe6] octahedral local structure with the Te atoms, and the octahedral structures are connected in the form of shared corners and shared edges; the interlayer structure is mainly connected by van der Waals force; In the amorphous phase structure of the phase change memory material, most of the Cr atoms form a [CrTe6] octahedral local structure with Te atoms, and the remaining Cr atoms form a defective octahedral local structure, and each octahedral or defective octahedral structure is randomly distributed and connected.

3. The phase change memory material with wide temperature range and low resistance drift according to claim 1, characterized in that: The local structures of the crystal and amorphous phase change memory material are mainly [CrTe6] octahedron, which has stable Cr-Te chemical bonds, and the bond lengths of the Cr-Te bonds along the same direction are basically the same, without obvious Peierls distortion.

4. The phase change memory material with a wide temperature range and low resistance drift according to claim 1, characterized in that: The amorphous film crystallization temperature of the phase change storage material is 250-300° C., and the ten-year data retention temperature is 130-190° C.

5. The phase change memory material with wide temperature range and low resistance drift according to claim 1, characterized in that: The amorphous phase of the phase change memory material is in a high resistance state, and the resistance value at room temperature is generally about 5×10 4 Ω~about 1×10 6 Ω; the crystal phase is a low resistance state, and the resistance value at room temperature is usually about 1×10 3 Ω~about 5×10 4 Ω; the resistance value varies with temperature and film thickness.

6. A phase change memory, characterized in that: The phase change memory material layer (3) of the device is the phase change memory material according to claims 1 to 4; When the device adopts a restricted structure, it comprises a substrate, and above the substrate are sequentially a bottom electrode layer (1), an oxide dielectric layer (2), a phase change storage material layer (3) and a top electrode layer (4); The thickness of the bottom electrode layer (1), the oxide dielectric layer (2), the phase change memory material layer (3) and the top electrode layer (4) is between 10 nm and 1000 nm; The phase change storage material layer (3) is located in the middle of the through hole of the oxide dielectric layer (2); the through hole is cylindrical or pillar-shaped, and is arranged concentrically with the oxide dielectric layer (2), and has a corresponding diameter or side length of between 10 nm and 1000 nm; When the device adopts a T-type structure, it comprises a substrate, which is a SiO2 / Si substrate, and above the substrate are a bottom electrode layer (1), an oxide dielectric layer (2), a heating electrode layer (5), a phase change storage material layer (3) and a top electrode layer (4); The thicknesses of the bottom electrode layer (1), the oxide dielectric layer (2), the phase change memory material layer (3), the top electrode layer (4) and the heating electrode layer (5) are respectively between 10 nm and 1000 nm; The heating electrode layer (5) is arranged in the middle of the through hole of the oxide medium layer (2); the through hole is cylindrical or pillar-shaped and is arranged concentrically with the oxide medium layer (2); and the corresponding diameter or side length is between 10nm and 1000nm.

7. The phase change memory according to claim 5, characterized in that: The SET and RESET reversible operations of the device are realized by loading current or voltage pulses, which correspond to the crystallization and amorphization processes of the phase change storage material layer film respectively; the partial crystallization or partial amorphization of the functional layer film is realized by adjusting the amplitude and pulse width of the pulse, and different resistance states are obtained, corresponding to different logic values; The resistance drift coefficients of the different resistance states of the device are all ≤0.002 in the temperature range of -200 to 200°C. The resistance drift coefficient can be calculated by the formula R=R0(t / t0): v Evaluation is performed, where R0 is the resistance at time t0, t is the test time, and v is the resistance drift coefficient.

8. Storage and computing integrated array, characterized in that: The functional layer material of the storage-computing integrated array is the phase-change storage material described in claims 1-4; it is a cross-bar structure, a transistor-memristor cascade structure or a three-dimensional stacked structure, and the device unit structure in the array is a restricted structure, a T-type structure or a bridge structure; The logic state programming of the device unit in the array is achieved by loading a current or voltage pulse of a certain amplitude and pulse width, which corresponds to partial crystallization or partial amorphization of the functional layer film; the logic state reconstruction of the device unit in the array can be achieved by SET or RESET operation, which corresponds to complete crystallization or complete amorphization of the functional layer film; The resistance drift coefficients of the different logic states of the device units in the array are all ≤0.002 in the temperature range of -200 to 200°C. The resistance drift coefficient can be calculated by the formula R=R0(t / t0): v Evaluation is performed, where R0 is the resistance at time t0, t is the test time, and v is the resistance drift coefficient.

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