Signal processing method, system, electronic device and storage medium

Abstract

The present disclosure provides a signal processing method, system, electronic device and storage medium, and relates to the field of computer technology. The method includes: obtaining at least one signal to be processed; performing analog-to-digital conversion on each signal to be processed to obtain a digital signal sequence; storing each digital signal sequence in a corresponding first shift register, determining a first average value of the first half of the data in the first shift register, and a second average value of the second half of the data in the first shift register; based on the first average value and the second average value, smoothing each digital signal sequence to obtain a smoothed digital signal; accumulating the square value of each smoothed digital signal to obtain an accumulated digital signal; calculating the third average value of each accumulated digital signal based on a shift operation; performing a square root operation on the third average value based on a successive approximation correction method to obtain the root mean square value of each signal to be processed. Thus, the accuracy and efficiency of signal processing can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a signal processing method, system, electronic device and storage medium. Background Art

[0002] The root mean square (RMS) value can reflect the effective fluctuation degree of AC voltage or AC current. Based on RMS, we can better understand and analyze the performance of the circuit. Therefore, in power transmission, distribution and various electrical equipment, it is very important to obtain the root mean square value of AC voltage or AC current.

[0003] In the prior art, the acquisition and RMS value calculation of AC voltage or AC current are generally performed by combining an analog-to-digital conversion chip with a digital signal processor (DSP) or a microcontroller unit (MCU). However, the processing speed of DSP and MCU is relatively slow. When the frequency of AC voltage or AC current is high, real-time processing cannot be performed. In addition, DSP and MCU generally have relatively few interfaces. When it is necessary to collect multiple voltages and currents at the same time, DSP and MCU are often unable to cope with it. Summary of the invention

[0004] The present disclosure provides a signal processing method, system, electronic device and storage medium to at least solve the above technical problems existing in the prior art.

[0005] According to a first aspect of the present disclosure, a signal processing method is provided, comprising: obtaining at least one signal to be processed; performing analog-to-digital conversion on each signal to be processed to obtain a digital signal sequence; storing each digital signal sequence in a corresponding first shift register, determining a first average value of the first half of the data in the first shift register, and a second average value of the second half of the data in the first shift register; performing smoothing processing on each digital signal sequence based on the first average value and the second average value to obtain a smoothed digital signal; accumulating the square values ​​of each smoothed digital signal to obtain an accumulated digital signal; calculating a third average value of each accumulated digital signal based on a shift operation; performing a square root operation on the third average value based on a successive approximation correction method to obtain a root mean square value of each signal to be processed; the successive approximation correction method can round off the result of the square root operation.

[0006] In one possible implementation manner, the analog-to-digital conversion is performed on each of the signals to be processed to obtain a digital signal sequence, including: mapping the signals to be processed into digital signals based on an analog-to-digital conversion chip corresponding to each of the signals to be processed; and outputting the digital signals as a digital signal sequence based on a clock signal and a serial data output pin of the analog-to-digital conversion chip.

[0007] In one possible implementation, the smoothing process is performed on each digital signal sequence based on the first average value and the second average value to obtain a smoothed digital signal, including: in response to the initial value of the intermediate data of the first shift register being between the first average value and the second average value, the initial value is determined as the updated value of the intermediate data; in response to the initial value of the intermediate data of the first shift register not being between the first average value and the second average value, the updated value of the intermediate data is determined based on the minimum difference between the initial value of the intermediate data and the first average value and the second average value; the data in the first shift register after the intermediate data is updated is shifted forward by one position, the digital signal sequence is smoothed again based on the moved first shift register, and the updated value of the intermediate data obtained after each smoothing process is output.

[0008] In one possible implementation, the updated value of the intermediate data is determined based on the minimum difference between the initial value of the intermediate data and the first average value and the second average value, comprising: in response to the minimum difference being less than a first threshold, determining the initial value as the updated value of the intermediate data; in response to the minimum difference being not less than the first threshold, determining the average of the first average value and the second average value as the updated value of the intermediate data.

[0009] In one possible implementation manner, the square values ​​of each smoothed digital signal are accumulated to obtain an accumulated digital signal, including: performing a square operation on the smoothed digital signal based on a multiplier to obtain a squared digital signal; and accumulating the squared digital signal based on a counter, an adder, a subtractor and a second shift register to obtain the accumulated digital signal.

[0010] In one possible implementation, the method of accumulating the squared digital signal based on a counter, an adder, a subtractor and a second shift register includes: counting the squared digital signal to be accumulated based on the counter; in response to the value of the counter being less than or equal to the number of stages of the second shift register, accumulating the received squared digital signal based on the adder to obtain the accumulated digital signal, and sequentially storing the accumulated squared digital signal in the second shift register; in response to the value of the counter being greater than the number of stages of the second shift register, adding the latest squared digital signal to the latest accumulated digital signal based on the adder, and subtracting the first squared digital signal in the second shift register from the added digital signal based on the subtractor to obtain the accumulated digital signal.

[0011] In one possible implementation manner, the calculation of the third average value of each accumulated digital signal based on the shift operation includes: obtaining a target number of accumulated square values, and determining the target number to be 2 to the Mth power; and shifting the accumulated digital signal to the right by M bits to obtain the third average value of the accumulated digital signal.

[0012] In one possible implementation, the method of performing a square root operation on the third average value based on the successive approximation correction method to obtain the root mean square value of each signal to be processed includes: determining that an initial result is 0, and the bit width of the initial result is half of the third average value; setting the value of each bit of the initial result to 1 in turn, and determining the value of each bit of the initial result by the square of the set initial result and the size of the third average value to obtain a square root operation result; determining a first difference between the third average value and the square of the square root operation result, and determining a second difference between the third average value and the square of the square root operation result plus 1; adjusting the square root operation result based on the first difference and the second difference to obtain the root mean square value.

[0013] In one possible implementation, the value of each bit of the initial result is set to 1 in sequence, and the value of each bit of the initial result is determined by the square of the set initial result and the size of the third average value, including: setting the first bit of the initial result to 1, in response to the square of the set initial result being greater than the third average value, determining that the first bit of the initial result is 0, and in response to the square of the first result being not greater than the third average value, determining that the first bit of the initial result is 1; setting the second bit of the initial result whose first bit has been determined to 1, and determining the value of the second bit of the initial result based on the square of the set initial result and the size of the third average value, and iterating in sequence until the values ​​of all bits of the initial result are determined to obtain a square root operation result.

[0014] In one possible implementation, the square root operation result is adjusted based on the first difference and the second difference to obtain the root mean square value, including: in response to the first difference being greater than the second difference, adding 1 to the square root operation result to obtain the root mean square value; in response to the first difference being not greater than the second difference, determining the square root operation result as the root mean square value.

[0015] In one possible implementation, a signal processing method further includes: merging the root mean square value of each signal to be processed and storing the merged result in a target memory; and extracting the root mean square value of the signal to be processed from the target memory and transmitting the extracted root mean square value to a target chip.

[0016] According to a second aspect of the present disclosure, a signal processing system is provided, comprising: at least one acquisition module, the acquisition module is used to acquire at least one signal to be processed; analog-to-digital conversion is performed on each signal to be processed to obtain a digital signal sequence; at least one smoothing module is used to store each digital signal sequence in a corresponding first shift register, determine a first average value of the first half of the data in the first shift register, and a second average value of the second half of the data in the first shift register; based on the first average value and the second average value, smoothing is performed on each digital signal sequence to obtain a smoothed digital signal; at least one root mean square calculation module is used to accumulate the square values ​​of each smoothed digital signal to obtain an accumulated digital signal; a third average value of each accumulated digital signal is calculated based on a shift operation; a square root operation is performed on the third average value based on a successive approximation correction method to obtain a root mean square value of each signal to be processed; the successive approximation correction method can round the result of the square root operation.

[0017] In one possible implementation, the acquisition module includes: an analog-to-digital conversion chip, used to map the signal to be processed into a digital signal based on the analog-to-digital conversion chip corresponding to each signal to be processed; based on a clock signal and a serial data output pin of the analog-to-digital conversion chip, outputting the digital signal as a digital signal sequence; a chip control unit, used to generate the clock signal and receive the digital signal sequence output by the serial data output pin of the analog-to-digital conversion chip.

[0018] In one possible implementation, the smoothing module is further used for: in response to the initial value of the intermediate data of the first shift register being between the first average value and the second average value, determining the initial value as the updated value of the intermediate data; in response to the initial value of the intermediate data of the first shift register not being between the first average value and the second average value, determining the updated value of the intermediate data based on the minimum difference between the initial value of the intermediate data and the first average value and the second average value; shifting the data in the first shift register after the intermediate data is updated forward by one position, re-smoothing the digital signal sequence based on the moved first shift register, and outputting the updated value of the intermediate data obtained after each smoothing process.

[0019] In one embodiment, the smoothing module is also used to: in response to the minimum difference being less than a first threshold, determine the initial value as the value after the intermediate data is updated; in response to the minimum difference being not less than the first threshold, determine the average of the first average value and the second average value as the value after the intermediate data is updated.

[0020] In one possible implementation manner, the root mean square calculation module is also used to: perform a square operation on the smoothed digital signal based on a multiplier to obtain a squared digital signal; and accumulate the squared digital signal based on a counter, an adder, a subtractor and a second shift register to obtain the accumulated digital signal.

[0021] In one possible implementation, the root mean square calculation module is also used to: count the squared digital signals to be accumulated based on the counter; in response to the value of the counter being less than or equal to the number of stages of the second shift register, accumulate the received squared digital signals based on the adder to obtain the accumulated digital signal, and store the accumulated squared digital signals in the second shift register in sequence; in response to the value of the counter being greater than the number of stages of the second shift register, add the latest squared digital signal to the latest accumulated digital signal based on the adder, and subtract the first squared digital signal in the second shift register from the added digital signal based on the subtractor to obtain the accumulated digital signal.

[0022] In one possible implementation, the root mean square calculation module is also used to: obtain a target number of accumulated square values, and determine the target number to be 2 to the Mth power; shift the accumulated digital signal to the right by M bits to obtain a third average value of the accumulated digital signal.

[0023] According to a third aspect of the present disclosure, an electronic device is provided, comprising: a signal processing system described in the present disclosure, wherein the signal processing system is capable of executing the signal processing method described in the present disclosure.

[0024] According to a fourth aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to cause the computer to execute the method described in the present disclosure.

[0025] The signal processing method, system, electronic device and storage medium disclosed in the present invention can process multiple channels of signals to be processed in parallel at the same time. For each channel of signals to be processed, analog-to-digital conversion and smoothing processing will be performed on it, and then the root mean square value of the smoothed signal will be calculated. The calculation process of the root mean square value includes square, accumulation, division operation and square root operation, wherein the smoothing processing is performed based on the first shift register, and the square root operation is performed based on the successive approximation correction method. The successive approximation correction method can round off the result of the square root operation. Therefore, the parallel processing of multiple channels of signals to be processed can improve the efficiency of signal processing and ensure the real-time processing of high-frequency signals. Moreover, the smoothing processing based on the first shift register and the square root operation based on the successive approximation correction method can improve the accuracy of signal processing and ensure the accuracy of the signal processing result.

[0026] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other objects, features and advantages of the exemplary embodiments of the present disclosure will become readily understood by reading the detailed description below with reference to the accompanying drawings. In the accompanying drawings, several embodiments of the present disclosure are shown in an exemplary and non-limiting manner, in which:

[0028] In the drawings, the same or corresponding reference numerals represent the same or corresponding parts.

[0029] Figure 1 A schematic diagram showing a process of a signal processing method according to an embodiment of the present disclosure Figure 1 ;

[0030] Figure 2 A schematic diagram showing a process of a signal processing method according to an embodiment of the present disclosure Figure 2 ;

[0031] Figure 3 A schematic diagram showing a process of a signal processing method according to an embodiment of the present disclosure Figure 3 ;

[0032] Figure 4A schematic diagram showing a process of a signal processing method according to an embodiment of the present disclosure Figure 4 ;

[0033] Figure 5 A schematic diagram of the structure of a signal processing system according to an embodiment of the present disclosure is shown;

[0034] Figure 6 A schematic diagram of analog-to-digital conversion of the acquisition module in an embodiment of the present disclosure is shown;

[0035] Figure 7 A schematic diagram of smoothing processing of a smoothing module in an embodiment of the present disclosure is shown;

[0036] Figure 8 A schematic diagram of the structure of a root mean square calculation module in an embodiment of the present disclosure is shown;

[0037] Fig. 9 A schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0038] In order to make the purpose, features, and advantages of the present disclosure more obvious and easy to understand, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present disclosure.

[0039] Figure 1 A schematic diagram showing a process of a signal processing method according to an embodiment of the present disclosure Figure 1 ,like Figure 1 As shown, a signal processing method includes:

[0040] Step S101, obtaining at least one signal to be processed.

[0041] Figure 5 A schematic diagram of the structure of a signal processing system according to an embodiment of the present disclosure is shown. A signal processing method according to the present disclosure can be applied to Figure 5 In the signal processing system shown, the signal processing system includes multiple signal processing branches, each of which includes an acquisition module, a smoothing module, and a root mean square calculation module, and the multiple signal processing branches can process the signals to be processed in parallel. In this embodiment, the signal processing system can obtain at least one signal to be processed, and the signal to be processed can be an AC voltage signal or an AC current signal, and the signal to be processed is an analog signal.

[0042] Step S102, performing analog-to-digital conversion on each channel of the signal to be processed to obtain a digital signal sequence.

[0043] In this embodiment, the signal to be processed needs to be converted from an analog signal to a discrete digital signal so that the signal processing system can process it. In one example, a suitable analog-to-digital conversion chip can be selected to perform analog-to-digital conversion on the signal to be processed according to the performance frequency and signal accuracy of the signal to be processed.

[0044] In one possible implementation, analog-to-digital conversion can be performed on each signal to be processed in the following manner: based on the analog-to-digital conversion chip corresponding to each signal to be processed, the signal to be processed is mapped into a digital signal; based on the clock signal and the serial data output pin of the analog-to-digital conversion chip, the digital signal is output as a digital signal sequence.

[0045] Figure 5 A schematic diagram of the structure of a signal processing system according to an embodiment of the present disclosure is shown. Figure 6 FIG. 4 shows a schematic diagram of analog-to-digital conversion of the acquisition module in an embodiment of the present disclosure. Figure 5 and 6 As shown, the acquisition module includes an analog-to-digital conversion chip and a chip control unit. The chip control unit can trigger the CNV (Conversion Start) signal, which is also the conversion start signal. The CNV signal is used to control the start of the analog-to-digital conversion chip. The chip control unit first sets the CNV signal to high, and after a certain period of time, sets the CNV signal to low to start the analog-to-digital conversion chip. After the analog-to-digital conversion chip is started, it will map the signal to be processed into a digital signal; the chip control unit can trigger the SCK (Serial Clock) signal, which is also the clock signal. The SCK signal can control the transmission rate and timing of data between devices. If the SCK signal has 16 clocks, the analog-to-digital conversion chip outputs a 16-bit digital signal through the serial data output (SDO, Serial Data Out) pin. The chip control unit receives the 16-bit digital signal (D15-D0) and forms a parallel 16-bit signal. Repeating the above process continuously can obtain a discrete digital signal sequence corresponding to the signal to be processed. Among them, is the high level duration of CNV signal, To enable time, The time from high level to data output is is the data stabilization time, The low level duration of SCK signal. is the high level duration of the SCK signal, is the SCK signal period, Disable time.

[0046] Step S103, storing each digital signal sequence into the corresponding first shift register, determining a first average value of the first half of the data in the first shift register, and a second average value of the second half of the data in the first shift register.

[0047] In this embodiment, after the signal to be processed is converted into a digital signal sequence, the digital signal sequence can be stored in the first shift register of the current signal processing branch, and then the first average value of the first half of the data in the first shift register and the second average value of the second half of the data in the first shift register are determined.

[0048] Figure 7 FIG. 4 shows a schematic diagram of smoothing processing of the smoothing module in an embodiment of the present disclosure, such as Figure 7 As shown, in one example, the first shift register can adopt an 11-stage shift register, and 11 data are stored in the first shift register in sequence, such as storing data D0-D10 in the 1st to 11th stages of the first shift register in sequence. The number of stages of the first shift register is not an even number, and the data cannot be evenly divided into two halves, so it is sufficient to ensure that the difference in the number of data on both sides is minimized, that is, data D0-D4 can be used as the first half of the data, and data D5-D10 can be used as the second half of the data, and the average value of D0-D4 is calculated to obtain the first average value A, and the average value of D5-D10 is calculated to obtain the second average value B.

[0049] Step S104: Based on the first average value and the second average value, smoothing is performed on each digital signal sequence to obtain a smoothed digital signal.

[0050] In this embodiment, the value of the intermediate data of the first shift register can be updated based on the value of the intermediate data of the first shift register and the size of the first average value and the second average value, so as to smooth the digital signal sequence, remove the burrs in the digital signal sequence, and obtain a smoothed digital signal. In one example, the intermediate data of the first shift register can be D5. By comparing the size of D5 with the first average value A and the second average value B, it can be determined whether D5 is consistent with the trend of the previous and next data. If D5 is between the first average value A and the second average value B, it means that D5 is consistent with the trend of the previous and next data, that is, D5 is a normal signal. If D5 is not between the first average value A and the second average value B, it means that D5 is inconsistent with the trend of the previous and next data and may be abnormal data, so D5 needs to be updated.

[0051] Step S105, accumulating the square value of each smoothed digital signal to obtain an accumulated digital signal.

[0052] In this embodiment, after the digital signal sequence is smoothed, the root mean square value of the smoothed digital signal needs to be calculated. The calculation formula is as follows: Formula 1:

[0053] Formula 1

[0054] in, is the i-th smoothed digital signal for RMS calculation, including , ,……, , N is the total number of smoothed digital signals for RMS calculation.

[0055] According to the above formula 1, it can be known that calculating the root mean square value requires square operation, accumulation operation, division operation and square root operation. Therefore, when calculating the root mean square value of the smoothed digital signal, it is necessary to first perform a square operation on the smoothed digital signal to obtain the square value of the smoothed digital signal, and then accumulate the square values ​​of the smoothed digital signal to obtain the accumulated digital signal.

[0056] Step S106, calculating a third average value of each channel of accumulated digital signals based on the shift operation.

[0057] In this embodiment, it is necessary to calculate the third average value of the accumulated digital signal, that is, the ratio of the accumulated digital signal to the number of accumulated square values.

[0058] In one possible implementation, the third average value of each accumulated digital signal can be calculated in the following manner: obtain the target number of accumulated square values, and determine that the target number is 2 to the Mth power; shift the accumulated digital signal to the right by M bits to obtain the third average value of the accumulated digital signal. In one example, if the decimal representation of the accumulated digital signal is 16, the binary representation is 10000, and the decimal representation of the target number of accumulated square values ​​is 8, 8 is 2 to the third power, so the binary representation 10000 of the accumulated digital signal can be shifted right by three bits, and the right shift by one bit is 01000, the right shift by two bits is 00100, and the right shift by three bits is 00010, that is, 10, and 10 is converted to decimal to obtain 2, that is, the third average value of the accumulated digital signal is 2.

[0059] Step S107, performing a square root operation on the third average value based on the successive approximation correction method to obtain a root mean square value of each channel of the signal to be processed.

[0060] In this embodiment, the successive approximation correction method can round off the result of the square root operation. When the square root operation is performed based on the successive approximation correction method, the third average value is firstly squared based on the successive approximation method, and then the result of the square root operation is rounded off and corrected, so as to obtain the root mean square value of the signal to be processed. Since the successive approximation method can only round off the result but cannot round off, the result of the square root operation will be inaccurate. In the present disclosure, the result of the square root operation is rounded off and corrected to obtain a more accurate root mean square value of the signal to be processed.

[0061] In the present disclosure, multiple channels of signals to be processed can be processed in parallel at the same time. For each channel of signals to be processed, analog-to-digital conversion and smoothing processing will be performed on it, and then the root mean square value of the smoothed signal will be calculated. The calculation process of the root mean square value includes square, accumulation, division operations and square root operations, wherein smoothing processing is performed based on the first shift register, and square root operations are performed based on the successive approximation correction method. The successive approximation correction method can round off the result of the square root operation. Therefore, the parallel processing of multiple channels of signals to be processed can improve the efficiency of signal processing and ensure the real-time processing of high-frequency signals. Moreover, the smoothing processing based on the first shift register and the square root operation based on the successive approximation correction method can improve the accuracy of signal processing and ensure the accuracy of the signal processing results.

[0062] Figure 2 A schematic diagram showing a process of a signal processing method according to an embodiment of the present disclosure Figure 2 ,like Figure 2 As shown, step S104 "smoothing each digital signal sequence based on the first average value and the second average value to obtain a smoothed digital signal" includes:

[0063] Step S201: in response to the initial value of the intermediate data of the first shift register being between the first average value and the second average value, the initial value is determined as the updated value of the intermediate data.

[0064] In this embodiment, if the initial value of the intermediate data of the first shift register is between the first average value of the first half of the data and the second average value of the second half of the data, the value of the intermediate data remains unchanged and is still the initial value. Figure 7 As shown, if the intermediate data D5 is between the first average value A of the first half of the data and the second average value B of the second half of the data, D5 remains unchanged, that is, U5= D5, where U5 is the value of the intermediate data after D5 is updated.

[0065] Step S202: In response to the initial value of the intermediate data in the first shift register not being between the first average value and the second average value, determine the updated value of the intermediate data based on the minimum difference between the initial value of the intermediate data and the first average value and the second average value.

[0066] In this embodiment, if the initial value of the intermediate data is not between the first average value and the second average value, that is, the initial value of the intermediate data is greater than the first average value and the second average value, or the initial value of the intermediate data is less than the first average value and the second average value. At this time, the first difference between the initial value of the intermediate data and the first average value and the second difference between the initial value of the intermediate data and the second average value can be determined, and the minimum difference between the first difference and the second difference can be determined. The updated value of the intermediate data is determined based on the minimum difference.

[0067] In an implementable manner, the updated value of the intermediate data can be determined based on the minimum difference in the following way: In response to the minimum difference being less than the first threshold, determine the initial value as the updated value of the intermediate data; in response to the minimum difference not being less than the first threshold, determine the average value of the first average value and the second average value as the updated value of the intermediate data. Wherein, the first threshold can be set by itself according to the actual situation, and the present disclosure does not limit it.

[0068] As Figure 7 shown, if the intermediate data D5 is not between the first average value A and the second average value B, and D5 is greater than A and D5 is greater than B, if (D5 - Max(A, B)) < T, then D5 remains unchanged, that is, U5 = D5; if (D5 - Max(A, B)) >= T, then D5 is updated to the average value of A and B, that is . If the intermediate data D5 is not between the first average value A and the second average value B, and D5 is less than A and D5 is less than B, if (Min(A, B) - D5) < T, then D5 remains unchanged, that is, U5 = D5; if (Min(A, B) - D5) >= T, then D5 is updated to the average value of A and B, that is .

[0069] Step S203: Move all the data in the first shift register with the updated intermediate data forward by one bit, re - smooth the digital signal sequence based on the moved first shift register, and output the updated value of the intermediate data obtained by each smoothing process.

[0070] In this embodiment, after the intermediate data is updated, the data in the first shift register after the intermediate data is updated can be moved forward by one position, that is, the data at each level is moved forward by one level, the original data in the first level is removed, and the new data is stored in the last level. Then, the digital signal sequence is smoothed again based on the moved first shift register, and the updated value of the intermediate data obtained by each smoothing process is output.

[0071] like Figure 7 As shown, the data in the first shift register are all moved forward by one position. The data in the first shift register after the shift include D1-D4, U5, and D6-D11. It can be seen that the original data D0 in the first level is removed, and the new data D11 is stored in the 11th level. The intermediate data D6 can be updated based on the first average value A of D1-U5 and the second average value B of D6-D11 to obtain U6, and then the above process is repeated, and the updated values ​​of the intermediate data obtained by each smoothing process are output, such as U5, U6, etc. The updated values ​​of the output intermediate data can be used as smoothed digital signals.

[0072] In this embodiment, based on the first average value of the first half of the data in the first shift register and the second average value of the second half of the data, the intermediate data in the first shift register is updated to obtain a smoothed digital signal. Compared with smoothing using a filter, the smoothing method disclosed in the present invention is simpler, more efficient, less costly, and the smoothing result is more accurate.

[0073] Figure 3 A schematic diagram showing a process of a signal processing method according to an embodiment of the present disclosure Figure 3 ,like Figure 3 As shown, step S105 "accumulate the square value of each smoothed digital signal to obtain an accumulated digital signal" includes:

[0074] Step S301, performing a square operation on the smoothed digital signal based on a multiplier to obtain a squared digital signal.

[0075] Step S302: Based on the counter, the adder, the subtractor and the second shift register, the squared digital signal is accumulated to obtain an accumulated digital signal.

[0076] In this embodiment, when calculating the RMS value of the smoothed digital signal, it is necessary to first perform a square operation on the smoothed digital signal based on a multiplier to obtain a squared digital signal, and then accumulate the squared digital signal based on a counter, an adder, a subtractor and a second shift register to obtain an accumulated digital signal.

[0077] In another embodiment, step S302 “accumulating the squared digital signal based on a counter, an adder, a subtractor, and a second shift register” includes:

[0078] Counting the squared digital signal to be accumulated based on the counter;

[0079] In response to the value of the counter being less than or equal to the number of stages of the second shift register, the received squared digital signal is accumulated based on the adder to obtain an accumulated digital signal, and the accumulated squared digital signal is sequentially stored in the second shift register;

[0080] In response to the counter value being greater than the number of stages of the second shift register, the latest squared digital signal is added to the latest accumulated digital signal based on the adder, and the first squared digital signal in the second shift register is subtracted from the added digital signal based on the subtractor to obtain the accumulated digital signal.

[0081] In this embodiment, the second shift register can be selected based on the window size for performing RMS calculation. For example, if a RMS calculation is performed based on 11 data, the second shift register can be an 11-stage shift register. When performing accumulation, the squared digital signal to be accumulated can be counted based on a counter. If the value of the counter is less than or equal to the number of stages of the second shift register, the input squared digital signal can be accumulated until the number of accumulated data reaches the number of stages of the second shift register, and the accumulated squared digital signal is sequentially stored in the second shift register; if the value of the counter is greater than the number of stages of the second shift register, the latest squared digital signal needs to be added to the latest accumulated digital signal based on an adder, and the first squared digital signal in the second shift register is subtracted from the added digital signal based on a subtractor to obtain the accumulated digital signal.

[0082] In one example, if the second shift register can be an 11-stage shift register, for the input data, if the value of the counter is less than 11, the input data is accumulated, such as D0 + D1 + D2 + D3 + D4 + D5 + D6 + D7 +D8 + D9 + D10= S_old; if the value of the counter is greater than 11, such as when the 12th data D11 is input, it is necessary to calculate the accumulated sum S_new of D1 + D2 + D3 + D4 + D5 + D6 + D7 + D8 + D9 + D10+ D11, then S_new=S_old+ D11- D0, wherein D11 is the latest squared digital signal, S_old is the latest accumulated digital signal, and D0 is the first squared digital signal in the second shift register.

[0083] In this embodiment, accumulation is performed based on a counter and a second shift register. When the value of the counter is greater than the number of stages of the second shift register, the original accumulated sum S_old can be subtracted from the oldest data, and the new data can be added to obtain a new accumulated sum S_new. In this way, there is no need to recalculate the sum of all the data, thereby saving adder resources and improving processing efficiency.

[0084] Figure 4 A schematic diagram showing a process of a signal processing method according to an embodiment of the present disclosure Figure 4 ,like Figure 4 As shown, step S107 "performs a square root operation on the third average value based on the successive approximation correction method to obtain the root mean square value of each signal to be processed" includes:

[0085] Step S401, determining that the initial result is 0, and the bit width of the initial result is half of the third average value.

[0086] In this embodiment, when the square root operation is performed using the successive approximation method, an initial result needs to be determined first. 0 can be set as the initial result, and the bit width of the initial result is half of the third average value. For example, if the decimal representation of the third average value is 144 and its binary representation is 10010000, the binary representation of the initial result is 0000. In one example, if the bit width of the binary representation of the third average value is not an even number, a reserved bit (usually 0) can be added before or after the binary representation of the third average value to make the bit width of the binary representation of the third average value an even number.

[0087] Step S402, sequentially set the value of each digit of the initial result to 1, determine the value of each digit of the initial result by the square of the set initial result and the third average value, and obtain a square root operation result.

[0088] In this embodiment, it is necessary to set the value of each bit of the initial result to 1 in turn, and compare the square of the set initial result with the third average value, determine the value of each bit of the initial result based on the comparison result, and obtain the square root operation result.

[0089] In one implementation mode, the first bit of the initial result can be set to 1 first, and in response to the square of the initial result after the setting being greater than the third average value, the first bit of the initial result is determined to be 0, and in response to the square of the first result being not greater than the third average value, the first bit of the initial result is determined to be 1, and then the second bit of the initial result whose value the first bit has been determined is set to 1, and the value of the second bit of the initial result is determined based on the size of the square of the initial result after the setting and the third average value, and iterates in sequence until the values ​​of all bits of the initial result are determined to obtain the square root operation result.

[0090] In one example, if the decimal representation of the third average value is 144, its binary representation is 10010000, and the binary representation of the initial result D1 is 0000, the first iteration may set the first bit of D1 to 1, that is, D1=1000, which is 8 in decimal. , 64<the third average value 144, so the first bit of D1 remains 1; the second iteration sets the second bit of D1 to 1, that is, D1=1100, which is 12 in decimal. , , so the second bit of D1 remains 1; the third iteration sets the third bit of D1 to 1, that is, D1=1110, , so the third bit of D1 is cleared and remains at 0; the fourth iteration sets the fourth bit of D1 to 1, that is, D1=1101, , so the 4th bit of D1 is cleared and remains 0. At this point, the values ​​of all bits of the initial result D1 have been determined, and the binary representation of the square root operation result is 1100.

[0091] Step S403, determining a first difference between the third average value and the square of the square root operation result, and determining a second difference between the third average value and the square of the square root operation result plus 1.

[0092] In this embodiment, after determining the square root operation result, it is necessary to correct the square root operation result. First, it is necessary to determine the first difference between the third average value and the square of the square root operation result, and determine the second difference between the third average value and the square of the square root operation result plus 1. For example, if the third average value is data and the square root operation result is D2, then the first difference is determined. , the second difference .

[0093] Step S404: adjusting the square root operation result based on the first difference and the second difference to obtain a root mean square value.

[0094] In this embodiment, the square root operation result needs to be adjusted based on the first difference and the second difference. In one example, the square root operation result can be adjusted based on the following method: in response to the first difference being greater than the second difference, the square root operation result is added by 1 to obtain the root mean square value; in response to the first difference being not greater than the second difference, the square root operation result is determined as the root mean square value. For example, if the first difference N> the second difference M, the root mean square value = the square root operation result D2+1; if the first difference N≤ the second difference M, the root mean square value = the square root operation result D2.

[0095] In the present disclosure, based on the first difference between the third average value and the square of the square root operation result, and the second difference between the third average value and the square of the square root operation result plus 1, the square root operation result is adjusted to ensure that the square root operation result is truly rounded, thereby ensuring the accuracy of the root mean square value.

[0096] In another embodiment, a signal processing method further includes: merging the root mean square value of each signal to be processed and storing the merged result in a target memory; and extracting the root mean square value of the signal to be processed from the target memory and transmitting the extracted root mean square value to the target chip.

[0097] In this embodiment, the root mean square value of each signal to be processed needs to be merged and the merged result needs to be stored in the target memory. Alternatively, when an instruction requesting the root mean square value is received, the root mean square value of the signal to be processed is extracted from the target memory and the extracted root mean square value is transmitted to the target chip. The target chip may be a microcontroller unit (MCU) or a central processing unit (CPU), etc. The root mean square value may be transmitted through a network or PCIe. PCIe is a high-speed serial computer expansion bus standard.

[0098] Figure 5 A schematic diagram of the structure of a signal processing system according to an embodiment of the present disclosure is shown. Figure 5 As shown, a processing system includes:

[0099] At least one acquisition module 10, the acquisition module 10 is used to acquire at least one signal to be processed; perform analog-to-digital conversion on each signal to be processed to obtain a digital signal sequence;

[0100] At least one smoothing module 20, the smoothing module 20 is used to store each digital signal sequence into the corresponding first shift register, determine the first average value of the first half of the data in the first shift register, and the second average value of the second half of the data in the first shift register; based on the first average value and the second average value, smooth each digital signal sequence to obtain a smoothed digital signal;

[0101] At least one root mean square calculation module 30 is used to accumulate the square values ​​of each smoothed digital signal to obtain an accumulated digital signal; calculate the third average value of each accumulated digital signal based on a shift operation; perform a square root operation on the third average value based on a successive approximation correction method to obtain a root mean square value of each signal to be processed; the successive approximation correction method can round off the result of the square root operation.

[0102] In one possible implementation mode, the acquisition module 10 includes: an analog-to-digital conversion chip 11, which is used to map the signal to be processed into a digital signal based on the analog-to-digital conversion chip corresponding to each signal to be processed; based on the clock signal and the serial data output pin of the analog-to-digital conversion chip, the digital signal is output as a digital signal sequence; a chip control unit 12, which is used to generate a clock signal and receive the digital signal sequence output by the serial data output pin of the analog-to-digital conversion chip.

[0103] In one embodiment, the smoothing module 20 is further used for: in response to the initial value of the intermediate data of the first shift register being between the first average value and the second average value, determining the initial value as the updated value of the intermediate data; in response to the initial value of the intermediate data of the first shift register not being between the first average value and the second average value, determining the updated value of the intermediate data based on the minimum difference between the initial value of the intermediate data and the first average value and the second average value; shifting the data in the first shift register after the intermediate data is updated forward by one position, re-smoothing the digital signal sequence based on the moved first shift register, and outputting the updated value of the intermediate data obtained after each smoothing process.

[0104] In one embodiment, the smoothing module 20 is further used to: in response to the minimum difference being less than a first threshold, determine the initial value as the value after the intermediate data is updated; in response to the minimum difference being not less than the first threshold, determine the average of the first average value and the second average value as the value after the intermediate data is updated.

[0105] Figure 8 FIG. 4 shows a schematic diagram of the structure of the RMS calculation module in an embodiment of the present disclosure. Figure 8 As shown, the RMS calculation module 30 also includes: a multiplier 31, which is used to perform a square operation on the smoothed digital signal to obtain a squared digital signal; a counter 35, which is used to count the squared digital signal to be accumulated; an adder 32, which is used to accumulate the received squared digital signal in response to the value of the counter 35 being less than or equal to the number of stages of the second shift register 34 to obtain an accumulated digital signal; the second shift register 34 is used to store the accumulated squared digital signal; the adder 32 is also used to add the latest squared digital signal to the latest accumulated digital signal in response to the value of the counter 35 being greater than the number of stages of the second shift register 34; and a subtractor 33, which is used to subtract the first squared digital signal in the second shift register 34 from the added digital signal to obtain the accumulated digital signal.

[0106] In one embodiment, the RMS calculation module 30 further includes: a divider 36 for obtaining a target number of accumulated square values ​​and determining the target number to be 2 to the Mth power; and shifting the accumulated digital signal to the right by M bits to obtain a third average value of the accumulated digital signal.

[0107] In one embodiment, the RMS calculation module 30 also includes: a square root unit 37, which is used to determine that the initial result is 0, and the bit width of the initial result is half of the third average value; setting the value of each bit of the initial result to 1 in turn, and determining the value of each bit of the initial result by the square of the set initial result and the third average value to obtain the square root operation result; determining a first difference between the third average value and the square of the square root operation result, and determining a second difference between the third average value and the square of the square root operation result plus 1; adjusting the square root operation result based on the first difference and the second difference to obtain the RMS value.

[0108] In one embodiment, the square root unit 37 is also used to: set the first bit of the initial result to 1, in response to the square of the initial result after the setting being greater than the third average value, determine that the first bit of the initial result is 0, and in response to the square of the first result being not greater than the third average value, determine that the first bit of the initial result is 1; set the second bit of the initial result whose first bit has been determined to 1, and determine the value of the second bit of the initial result based on the square of the initial result after the setting and the third average value, and iterate in sequence until the values ​​of all bits of the initial result are determined to obtain the square root operation result.

[0109] In one embodiment, the square root unit 37 is further used to: in response to the first difference being greater than the second difference, add 1 to the square root operation result to obtain a root mean square value; in response to the first difference being not greater than the second difference, determine the square root operation result as the root mean square value.

[0110] like Figure 5 As shown, a signal processing system further includes: a storage module 40, which is used to combine the root mean square value of each signal to be processed and store the combined result in a target memory.

[0111] In one embodiment, the storage module 40 includes: a merging unit 41, used to merge the root mean square value of each signal to be processed; a write control unit 42, used to write the merged result into a storage unit 44; the storage unit 44, used to store the merged result; and a read control unit 43, used to read the data in the storage unit 44. The storage unit 44 can be used as a target memory.

[0112] like Figure 5As shown, a signal processing system further includes: a transmission module 50, which is used to transmit the data read by the read control unit 43 to the target chip. The transmission module can transmit the read data based on a network or PCIe.

[0113] According to an embodiment of the present disclosure, the present disclosure further provides an electronic device and a readable storage medium, wherein the electronic device comprises the signal processing system of the present disclosure, and the signal processing system can execute the signal processing method of the present disclosure.

[0114] Fig. 9 A schematic block diagram of an example electronic device 800 that can be used to implement an embodiment of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or required herein.

[0115] like Fig. 9 As shown, the device 800 includes a computing unit 801, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory ROM 802 or a computer program loaded from a storage unit 808 to a random access memory RAM 803. In the RAM 803, various programs and data required for the operation of the device 800 can also be stored. The computing unit 801, the ROM 802, and the RAM 803 are connected to each other via a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804.

[0116] A number of components in the device 800 are connected to the I / O interface 805, including: an input unit 806, such as a keyboard, a mouse, etc.; an output unit 807, such as various types of displays, speakers, etc.; a storage unit 808, such as a disk, an optical disk, etc.; and a communication unit 809, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 809 allows the device 800 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0117] The computing unit 801 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 801 performs the various methods and processes described above, such as a signal processing method. For example, in some embodiments, a signal processing method may be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as a storage unit 808. In some embodiments, part or all of the computer program may be loaded and / or installed on the device 800 via the ROM 802 and / or the communication unit 809. When the computer program is loaded into the RAM 803 and executed by the computing unit 801, one or more steps of a signal processing method described above may be performed. Alternatively, in other embodiments, the computing unit 801 may be configured to perform a signal processing method in any other appropriate manner (e.g., by means of firmware).

[0118] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0119] The program code for implementing the method of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions / operations specified in the flow chart and / or block diagram to be implemented. The program code may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0120] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or device, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0121] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0122] The systems and techniques described herein may be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), and the Internet.

[0123] A computer system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The relationship of client and server is generated by computer programs running on respective computers and having a client-server relationship with each other. The server may be a cloud server, a server of a distributed system, or a server combined with a blockchain.

[0124] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

[0125] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0126] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A signal processing method, characterized in that: The method comprises: Obtain at least one signal to be processed; Performing analog-to-digital conversion on each channel of the signal to be processed to obtain a digital signal sequence; storing each digital signal sequence into a corresponding first shift register, determining a first average value of the first half of the data in the first shift register, and a second average value of the second half of the data in the first shift register; Based on the first average value and the second average value, smoothing is performed on each channel of the digital signal sequence to obtain a smoothed digital signal; Accumulating the square values ​​of the smoothed digital signals of each channel to obtain an accumulated digital signal; Calculate a third average value of each channel of the accumulated digital signal based on a shift operation; Performing a square root operation on the third average value based on a successive approximation correction method to obtain a root mean square value of each channel of the signal to be processed; the successive approximation correction method can round off the result of the square root operation; The step of performing smoothing processing on each digital signal sequence based on the first average value and the second average value to obtain a smoothed digital signal includes: In response to an initial value of the intermediate data of the first shift register being between the first average value and the second average value, determining the initial value as an updated value of the intermediate data; In response to the initial value of the intermediate data of the first shift register not being between the first average value and the second average value, determining an updated value of the intermediate data based on a minimum difference between the initial value of the intermediate data and the first average value and the second average value; Shifting the data in the first shift register after the intermediate data is updated forward by one position, re-smoothing the digital signal sequence based on the first shift register after the shift, and outputting the updated value of the intermediate data obtained after each smoothing process; The step of determining the updated value of the intermediate data based on the initial value of the intermediate data and the minimum difference between the first average value and the second average value includes: In response to the minimum difference being less than a first threshold, determining the initial value as the updated value of the intermediate data; In response to the minimum difference being not less than a first threshold, an average of the first average value and the second average value is determined as the updated value of the intermediate data.

2. The method according to claim 1, characterized in that The step of performing analog-to-digital conversion on each of the signals to be processed to obtain a digital signal sequence includes: Based on the analog-to-digital conversion chip corresponding to each channel of the signal to be processed, mapping the signal to be processed into a digital signal; Based on the clock signal and the serial data output pin of the analog-to-digital conversion chip, the digital signal is output as a digital signal sequence.

3. The method according to claim 1, characterized in that The step of accumulating the square values ​​of the smoothed digital signals of each channel to obtain the accumulated digital signals comprises: Performing a square operation on the smoothed digital signal based on a multiplier to obtain a squared digital signal; Based on the counter, the adder, the subtractor and the second shift register, the squared digital signal is accumulated to obtain the accumulated digital signal.

4. The method according to claim 3, characterized in that The method of accumulating the squared digital signal based on a counter, an adder, a subtractor and a second shift register comprises: Counting the squared digital signal to be accumulated based on the counter; In response to the value of the counter being less than or equal to the number of stages of the second shift register, accumulating the received squared digital signal based on the adder to obtain the accumulated digital signal, and sequentially storing the accumulated squared digital signal in the second shift register; In response to the value of the counter being greater than the number of stages of the second shift register, the latest squared digital signal is added to the latest accumulated digital signal based on the adder, and the first squared digital signal in the second shift register is subtracted from the added digital signal based on the subtractor to obtain the accumulated digital signal.

5. The method according to claim 1, characterized in that The step of calculating the third average value of each channel of the accumulated digital signal based on the shift operation includes: Obtaining a target number of accumulated square values, and determining the target number to be 2 to the Mth power, where M is a positive integer; The accumulated digital signal is shifted rightward by M bits to obtain a third average value of the accumulated digital signal.

6. The method according to claim 1, characterized in that The step of performing a square root operation on the third average value based on the successive approximation correction method to obtain a root mean square value of each channel of the signal to be processed includes: Determine that an initial result is 0, and the bit width of the initial result is half of the third average value; Sequentially set the value of each digit of the initial result to 1, determine the value of each digit of the initial result by the square of the set initial result and the third average value, and obtain a square root operation result; Determine a first difference between the third average value and the square of the square root operation result, and determine a second difference between the third average value and the square of the square root operation result plus 1; The square root operation result is adjusted based on the first difference and the second difference to obtain the root mean square value.

7. The method according to claim 6, characterized in that The step of sequentially setting the value of each bit of the initial result to 1, and determining the value of each bit of the initial result by comparing the square of the initial result after setting with the third average value, includes: Setting the first bit of the initial result to 1, in response to the square of the initial result after setting being greater than the third average value, determining the first bit of the initial result to be 0, and in response to the square of the initial result not being greater than the third average value, determining the first bit of the initial result to be 1; The second bit of the initial result whose first bit value has been determined is set to 1, and the value of the second bit of the initial result is determined based on the square of the set initial result and the size of the third average value, and iterates until the values ​​of all bits of the initial result are determined to obtain the square root operation result.

8. The method according to claim 6, characterized in that The step of adjusting the square root operation result based on the first difference and the second difference to obtain the root mean square value includes: In response to the first difference being greater than the second difference, adding 1 to the square root operation result to obtain the root mean square value; In response to the first difference being not greater than the second difference, the square root operation result is determined as the root mean square value.

9. The method according to claim 1, characterized in that: Also includes: Merging the root mean square values ​​of the signals to be processed in each channel, and storing the merged results in a target memory; and, The root mean square value of the signal to be processed is extracted from the target memory, and the extracted root mean square value is transmitted to the target chip.

10. A signal processing system, characterized in that: The system comprises: At least one acquisition module, the acquisition module is used to acquire at least one signal to be processed; perform analog-to-digital conversion on each signal to be processed to obtain a digital signal sequence; At least one smoothing module, the smoothing module is used to store each digital signal sequence into a corresponding first shift register, determine a first average value of the first half of the data in the first shift register, and a second average value of the second half of the data in the first shift register; based on the first average value and the second average value, smooth each digital signal sequence to obtain a smoothed digital signal; At least one root mean square calculation module, the root mean square calculation module is used to accumulate the square values ​​of each smoothed digital signal to obtain an accumulated digital signal; calculate a third average value of each accumulated digital signal based on a shift operation; perform a square root operation on the third average value based on a successive approximation correction method to obtain a root mean square value of each signal to be processed; the successive approximation correction method can round off the result of the square root operation; Wherein, the smoothing module is also used for: In response to an initial value of the intermediate data of the first shift register being between the first average value and the second average value, determining the initial value as an updated value of the intermediate data; In response to the initial value of the intermediate data of the first shift register not being between the first average value and the second average value, determining an updated value of the intermediate data based on a minimum difference between the initial value of the intermediate data and the first average value and the second average value; Shifting the data in the first shift register after the intermediate data is updated forward by one position, re-smoothing the digital signal sequence based on the first shift register after the shift, and outputting the updated value of the intermediate data obtained after each smoothing process; Wherein, the smoothing module is also used for: In response to the minimum difference being less than a first threshold, determining the initial value as the updated value of the intermediate data; In response to the minimum difference being not less than a first threshold, an average of the first average value and the second average value is determined as the updated value of the intermediate data.

11. The system according to claim 10, characterized in that The acquisition module comprises: An analog-to-digital conversion chip, used for mapping the signal to be processed into a digital signal based on the analog-to-digital conversion chip corresponding to each channel of the signal to be processed; and outputting the digital signal as a digital signal sequence based on a clock signal and a serial data output pin of the analog-to-digital conversion chip; The chip control unit is used to generate the clock signal and receive the digital signal sequence output by the serial data output pin of the analog-to-digital conversion chip.

12. The system according to claim 10, characterized in that The root mean square calculation module is also used for: Performing a square operation on the smoothed digital signal based on a multiplier to obtain a squared digital signal; Based on the counter, the adder, the subtractor and the second shift register, the squared digital signal is accumulated to obtain the accumulated digital signal.

13. The system according to claim 12, characterized in that The root mean square calculation module is also used for: Counting the squared digital signal to be accumulated based on the counter; In response to the value of the counter being less than or equal to the number of stages of the second shift register, accumulating the received squared digital signal based on the adder to obtain the accumulated digital signal, and sequentially storing the accumulated squared digital signal in the second shift register; In response to the value of the counter being greater than the number of stages of the second shift register, the latest squared digital signal is added to the latest accumulated digital signal based on the adder, and the first squared digital signal in the second shift register is subtracted from the added digital signal based on the subtractor to obtain the accumulated digital signal.

14. The system according to claim 10, characterized in that The root mean square calculation module is also used for: Obtaining a target number of accumulated square values, and determining the target number to be 2 to the Mth power, where M is a positive integer; The accumulated digital signal is shifted rightward by M bits to obtain a third average value of the accumulated digital signal.

15. An electronic device, characterized in that: include: The signal processing system according to any one of claims 10 to 14, wherein the signal processing system is capable of executing the signal processing method according to any one of claims 1 to 9.

16. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: The computer instructions are used to enable a computer to execute the signal processing method according to any one of claims 1 to 9.

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