A slope-controllable current driving circuit

Abstract

The application discloses a slope-controllable current driving circuit, which comprises a current-voltage conversion circuit, a voltage-current conversion circuit and a current subtraction circuit; the output end of the current-voltage conversion circuit is connected with the input end of the voltage-current conversion circuit, and the output end of the voltage-current conversion circuit is connected with the input end of the current subtraction circuit. The input current is firstly converted into a voltage square wave signal with a slope proportional to the input current, then the voltage square wave signal is converted into a current square wave signal, and then the current square wave signal is subtracted from a direct current, so that a current driving signal with a minimum output current of zero and a slope proportional to the input current is obtained; and the slope of the current driving signal can be controlled by controlling the size of the input current. The application can be used for a CAN bus transceiver, provides a driving current for the CAN bus transceiver, controls the slope of the bus, and reduces electromagnetic radiation during signal transmission.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, specifically relating to a current driving circuit with controllable slope, which can be used in a CAN bus transceiver to provide driving current for the CAN bus transceiver. Background Technology

[0002] Controller Area Network (CAN) is a low-cost serial communication network used in automotive, industrial automation, and other fields. In system applications, when the CAN bus transmits high-level signals, the rapid changes in the signal generate significant electromagnetic radiation, impacting the system's electromagnetic compatibility (EMC). Reducing the CAN bus slope can decrease electromagnetic interference during signal transmission. Traditional CAN bus drivers provide a fixed current to the bus through switching actions. The rise and fall slopes of this drive current are large, fixed, and uncontrollable, making it impossible to reduce the slope and minimize interference during transmission. Summary of the Invention

[0003] The present invention aims to overcome the problem of large and uncontrollable bus drive current slope in the prior art, and provides a current drive scheme with controllable slope to solve the electromagnetic interference generated by the CAN bus in signal transmission.

[0004] To achieve the above objectives, the present invention adopts the following technical solution:

[0005] This invention provides a current driving circuit with controllable slope, including a current-to-voltage conversion circuit, a voltage-to-current conversion circuit, and a current subtraction circuit;

[0006] The output terminal of the current-to-voltage conversion circuit is connected to the input terminal of the voltage-to-current conversion circuit, and the output terminal of the voltage-to-current conversion circuit is connected to the input terminal of the current subtraction circuit.

[0007] The current-to-voltage conversion circuit is used to convert the input current into a voltage square wave signal;

[0008] The voltage-to-current conversion circuit is used to convert the voltage square wave signal output by the current-to-voltage conversion circuit into a current square wave signal.

[0009] The current subtraction circuit is used to obtain the output current by subtracting the current square wave signal from the reference current, and the slope of the output current is proportional to the input current.

[0010] Optionally, the current-to-voltage conversion circuit includes a first capacitor, a first current mirror, a second current mirror, a third current mirror, a fourth current mirror, a first limiting circuit, a second limiting circuit, a first PMOS transistor, and a first NMOS transistor;

[0011] The first current mirror generates the charging current of the first capacitor, the second current mirror generates the discharging current of the first capacitor, the third current mirror generates the bias current of the first limiting circuit, the fourth current mirror generates the bias current of the second limiting circuit, the first limiting circuit is used to limit the maximum voltage of the first capacitor, the second limiting circuit is used to limit the minimum voltage of the first capacitor, the first PMOS transistor is used to control the first current mirror to charge the first capacitor, and the first NMOS transistor is used to control the second current mirror to discharge the first capacitor.

[0012] The input terminal of the first current mirror is connected to the first input current. The source of the first PMOS transistor is connected to the power supply terminal. The drain of the first PMOS transistor is connected to the first current mirror. The input terminal of the third current mirror is connected to the second input current. The first limiting circuit is connected to the first current mirror, the third current mirror, the second limiting circuit, the first terminal of the first capacitor, and the input terminal of the voltage-to-current conversion circuit. The second limiting circuit is connected to the second current mirror and the fourth current mirror. The third current mirror and the fourth current mirror are connected together. The drain of the first NMOS transistor is connected to the second current mirror. The source of the first NMOS transistor and the second terminal of the first capacitor are both connected to ground. The input terminal of the first limiting circuit is connected to the first reference voltage. The input terminal of the second limiting circuit is connected to the second reference voltage. The gate of the first PMOS transistor is connected to the first control signal. The source of the first NMOS transistor is connected to ground. The gate of the first PMOS transistor is connected to the second control signal.

[0013] Optionally, the first control signal and the second control signal are out of phase.

[0014] Optionally, the first reference voltage is greater than the second reference voltage.

[0015] Optionally, in the current-to-voltage conversion circuit, when the gate of the first PMOS transistor is at a low level, the first current mirror charges the first capacitor, and the voltage of the first capacitor rises until it reaches the second reference voltage. The magnitude of the charging current controls the slope of the capacitor voltage rise. When the gate of the first PMOS transistor is at a high level, the first current mirror stops charging the first capacitor.

[0016] Optionally, in the current-to-voltage conversion circuit, when the gate of the first NMOS transistor is at a high level, the second current mirror discharges the first capacitor, causing the voltage of the first capacitor to drop until it reaches the second reference voltage. The magnitude of the discharge current controls the slope of the capacitor voltage drop. When the gate of the first NMOS transistor is at a low level, the second current mirror stops discharging the first capacitor.

[0017] Optionally, the first current mirror includes a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor. The drain of the second PMOS transistor is connected to the gate of the second PMOS transistor, the gate of the third PMOS transistor, and the gate of the fourth PMOS transistor, respectively. The sources of the second PMOS transistor and the third PMOS transistor are connected to a power supply terminal. The source of the third PMOS transistor is connected to the drain of the first PMOS transistor, and the source of the fourth PMOS transistor is connected to the drain of the first PMOS transistor.

[0018] The second current mirror includes a second NMOS transistor and a third NMOS transistor. The drain of the second NMOS transistor is connected to the gate of the second NMOS transistor, the gate of the third NMOS transistor, and the drain of the third PMOS transistor, respectively. The source of the second NMOS transistor is connected to ground. The source of the third NMOS transistor is connected to the drain of the first NMOS transistor. The source of the third NMOS transistor is also connected to the drain of the first NMOS transistor.

[0019] The third current mirror includes a fifth PMOS transistor, a sixth PMOS transistor, and a seventh PMOS transistor. The drain of the fifth PMOS transistor is connected to the gate of the fifth PMOS transistor, the gate of the sixth PMOS transistor, and the gate of the seventh PMOS transistor, respectively. The source of the fifth PMOS transistor, the source of the sixth PMOS transistor, and the source of the seventh PMOS transistor are all connected to the power supply terminal. The drain of the fifth PMOS transistor is connected to the second input current.

[0020] The fourth current mirror includes a fourth NMOS transistor and a fifth NMOS transistor. The drain of the fourth NMOS transistor is connected to the gate of the fourth NMOS transistor, the gate of the fifth NMOS transistor, and the drain of the sixth PMOS transistor, respectively. The source of the fourth NMOS transistor and the source of the fifth NMOS transistor are both connected to ground.

[0021] The first limiting circuit includes a sixth NMOS transistor and a seventh NMOS transistor. The drain of the sixth NMOS transistor is connected to the gate of the sixth NMOS transistor, the gate of the seventh NMOS transistor, and the drain of the seventh PMOS transistor, respectively. The source of the sixth NMOS transistor is connected to a first reference voltage, and the drain of the seventh NMOS transistor is connected to the drain of the fourth PMOS transistor.

[0022] The second limiting circuit includes an eighth PMOS transistor and a ninth PMOS transistor. The drain of the eighth PMOS transistor is connected to the gate of the eighth PMOS transistor, the gate of the ninth PMOS transistor, and the drain of the fifth NMOS transistor. The source of the eighth PMOS transistor is connected to a second reference voltage. The drain of the ninth PMOS transistor is connected to the drain of the third NMOS transistor. The sources of the seventh NMOS transistor and the ninth PMOS transistor are both connected to the first terminal of the first capacitor.

[0023] Optionally, the voltage-to-current conversion circuit includes a first operational amplifier, a first resistor, an eighth NMOS transistor, a tenth PMOS transistor, and an eleventh PMOS transistor. The non-inverting input of the first operational amplifier is connected to the output of the current-to-voltage conversion circuit. The inverting input of the first operational amplifier is connected to the first terminal of the first resistor and the source of the eighth NMOS transistor. The output of the first operational amplifier is connected to the gate of the eighth NMOS transistor. The second terminal of the first resistor is connected to ground. The drain of the eighth NMOS transistor is connected to the drain, gate, and eleventh PMOS transistor. The sources of the tenth and eleventh PMOS transistors are connected to a power supply terminal. The drain of the eleventh PMOS transistor is connected to the current subtraction circuit.

[0024] Optionally, the current subtraction circuit includes a second operational amplifier, a second resistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a twelfth PMOS transistor, and a thirteenth PMOS transistor. The non-inverting input of the second operational amplifier is connected to the second reference voltage. The inverting input of the second operational amplifier is connected to the first terminal of the second resistor and the source of the ninth NMOS transistor. The second terminal of the second resistor is connected to ground. The output of the second operational amplifier is connected to the gate of the ninth NMOS transistor. The drain of the ninth NMOS transistor is connected to the drain of the twelfth PMOS transistor, the gate of the twelfth PMOS transistor, and the gate of the thirteenth PMOS transistor. The source of the twelfth PMOS transistor and the source of the thirteenth PMOS transistor are both connected to the power supply terminal. The drain of the thirteenth PMOS transistor is connected to the gate of the tenth NMOS transistor, the drain of the tenth NMOS transistor, and the gate of the eleventh NMOS transistor. The drain of the eleventh NMOS transistor is connected to the output terminal of the voltage-to-current conversion circuit, the drain of the twelfth NMOS transistor, the gate of the twelfth NMOS transistor, and the gate of the thirteenth NMOS transistor. The source of the eleventh NMOS transistor, the source of the twelfth NMOS transistor, the source of the twelfth NMOS transistor, and the source of the thirteenth NMOS transistor are all connected to ground. The drain of the thirteenth NMOS transistor is the current square wave output terminal of the slope-controllable current drive circuit.

[0025] Optionally, the rising and falling slopes of the current square wave are proportional to the input current, and the magnitude of the rising and falling slopes of the current square wave can be changed by changing the magnitude of the input current.

[0026] The beneficial effects of this invention are as follows:

[0027] This invention discloses a current drive circuit with controllable slope. By changing the magnitude of the input current, the rising and falling slopes of the output current square wave can be changed, providing the CAN bus as a drive current, thereby realizing slope control of the CAN bus and reducing electromagnetic radiation of the CAN bus. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of a traditional CAN bus and current drive.

[0029] Figure 2 This is a schematic diagram of a current drive circuit with controllable slope according to the present invention.

[0030] Figure 3 This is a schematic diagram of an embodiment of a current drive circuit with controllable slope according to the present invention;

[0031] Figure 4 This is a voltage waveform diagram of the first capacitor in an embodiment of the present invention;

[0032] Figure 5 This is a waveform diagram of the output current Io in an embodiment of the present invention;

[0033] Figure 6 The waveforms of the output current Io corresponding to different input current magnitudes in this embodiment of the invention are shown. Detailed Implementation

[0034] The present invention and its beneficial effects will be further described in detail below with reference to specific embodiments and accompanying drawings. However, the specific embodiments of the present invention are not limited thereto.

[0035] refer to Figure 2 The principle block diagram of the slope-controllable current drive circuit of the present invention. The embodiment of the present invention provides a slope-controllable current drive circuit, including a current-voltage conversion circuit 100, a voltage-current conversion circuit 200, and a current subtraction circuit 300.

[0036] The output terminal of the current-to-voltage conversion circuit 100 is connected to the input terminal of the voltage-to-current conversion circuit 200, and the output terminal of the voltage-to-current conversion circuit 200 is connected to the input terminal of the current subtraction circuit 300.

[0037] The current-to-voltage conversion circuit 100 is used to convert the input current into a voltage square wave signal; wherein the voltage square wave signal has a corresponding slope and limiting, and the slope is proportional to the magnitude of the input current;

[0038] The voltage-to-current conversion circuit 200 is used to convert the voltage square wave signal output by the current-to-voltage conversion circuit 100 into a current square wave signal, and the current square wave signal has a corresponding slope.

[0039] The current subtraction circuit 300 is used to obtain the output current by subtracting the current square wave signal from the reference current, wherein the slope of the output current is proportional to the input current, and the minimum value of the output current is zero.

[0040] refer to Figure 3 In one embodiment, a schematic diagram of the current drive circuit with controllable slope of the present invention is provided to further illustrate the technical solution of the embodiment of the present invention.

[0041] In this embodiment, the current-to-voltage conversion circuit 100 includes a first capacitor C1, a first current mirror 101, a second current mirror 102, a third current mirror 103, a fourth current mirror 104, a first limiting circuit 105, a second limiting circuit 106, a first PMOS transistor P1, a first NMOS transistor N1, a first input current I1, a second input current I2, a first reference voltage VREF1, and a second reference voltage VREF2. The first capacitor C1 is used to store charge and generate voltage. The first current mirror 101 generates the charging current of the first capacitor C1, and the second current mirror 102 generates... The first current mirror 103 generates the discharge current of the first capacitor C1, the third current mirror 103 generates the bias current of the first limiting circuit 105, and the fourth current mirror 104 generates the bias current of the second limiting circuit 106. The first limiting circuit 105 is used to limit the maximum voltage of capacitor C1, and the second limiting circuit 106 is used to limit the minimum voltage of capacitor C1. The first PMOS transistor P1 acts as a switch to control the charging or non-charging of the first capacitor C1 by the first current mirror 101, and the first NMOS transistor N1 acts as a switch to control the discharging or non-discharging of the first capacitor C1 by the second current mirror 102.

[0042] The input terminal of the first current mirror 101 is connected to the first input current I1. The source of the first PMOS transistor P1 is connected to the power supply terminal, and the drain of the first PMOS transistor P1 is connected to the first current mirror 101. The input terminal of the third current mirror 103 is connected to the second input current I2. The first limiting circuit 105 is connected to the first current mirror 101, the third current mirror 103, the second limiting circuit 106, the first terminal of the first capacitor C1, and the input terminal of the voltage-to-current conversion circuit 200. The second limiting circuit 106 is connected to the second current mirror 102 and the fourth current mirror 104. The third current mirror 103 and the fourth current mirror 104 are connected. The drain of the first NMOS transistor N1 is connected to the second current mirror 102. The source of the first NMOS transistor N1 and the second terminal of the first capacitor C1 are both connected to ground. The input terminal of the first limiting circuit 105 is connected to the first reference voltage VREF1. The input terminal of the second limiting circuit 106 is connected to the second reference voltage VREF2. The gate of the first PMOS transistor P1 is connected to the first control signal Ct1. The source of the first NMOS transistor N1 is connected to ground. The gate of the first PMOS transistor P1 is connected to the second control signal Ct2.

[0043] In one embodiment, the source of the first PMOS transistor P1 is connected to the power supply terminal, the gate of the first PMOS transistor P1 is connected to the first control signal, the source of the first NMOS transistor N1 is connected to ground, and the gate of the first NMOS transistor N1 is connected to the second control signal Ct2. The first control signal Ct1 and the second control signal Ct2 are out of phase.

[0044] In one embodiment, the first reference voltage VREF1 is greater than the second reference voltage VREF2.

[0045] In this embodiment, in the current-to-voltage conversion circuit 100, when the gate of the first PMOS transistor P1 is at a low level, the first current mirror 101 charges the first capacitor C1, causing the voltage of the first capacitor C1 to rise until it reaches the first reference voltage VREF1. The magnitude of the charging current controls the voltage rise slope of the capacitor. When the gate of the first PMOS transistor P1 is at a high level, the first current mirror 101 stops charging the first capacitor C1. The voltage rise slope of capacitor C1 is expressed as:

[0046]

[0047] In the formula, K r Let V be the slope of the voltage rise of capacitor C1. cap (t) represents the voltage across capacitor C1, C represents the capacitance of capacitor C1, and I... p This is the charging current of capacitor C1.

[0048] In this embodiment, in the current-to-voltage conversion circuit 100, when the gate of the first NMOS transistor N1 is at a high level, the second current mirror 102 discharges the first capacitor C1, causing the voltage of the first capacitor C1 to drop until it reaches the second reference voltage VREF2. The magnitude of the discharge current controls the slope of the capacitor voltage drop. When the gate of the first NMOS transistor N1 is at a low level, the second current mirror 102 stops discharging the first capacitor C1. The slope of the voltage drop of capacitor C1 is expressed as:

[0049]

[0050] In the formula, K f Let V be the slope of the voltage drop across capacitor C1. cap (t) represents the voltage across capacitor C1, C represents the capacitance of capacitor C1, and I... n This is the discharge current of capacitor C1.

[0051] In one embodiment, the first current mirror 101 includes a second PMOS transistor P2, a third PMOS transistor P3, and a fourth PMOS transistor P4. The drain of the second PMOS transistor P2 is connected to the gate of the second PMOS transistor P2, the gate of the third PMOS transistor P3, the gate of the fourth PMOS transistor P4, and the input current I1. The sources of the second PMOS transistor P2 and the third PMOS transistor P3 are connected to a power supply. The source of the third PMOS transistor P3 is connected to the drain of the first PMOS transistor P1. The second current mirror 102 includes a second NMOS transistor N2 and a third NMOS transistor N3. The drain of the second NMOS transistor N2 is connected to the gate of the second NMOS transistor N2, the gate of the third NMOS transistor N3, and the drain of the third PMOS transistor P3. The source of the second NMOS transistor N2 is connected to ground. The source of the third NMOS transistor N3 is connected to the drain of the first NMOS transistor N1. The third current mirror 103 includes a fifth PMOS transistor P5, a sixth PMOS transistor P6, and a seventh PMOS transistor P7. The drain of the fifth PMOS transistor P5 is connected to the gate of the fifth PMOS transistor P5, the gate of the sixth PMOS transistor P6, and the gate of the seventh PMOS transistor P7. The sources of the fifth PMOS transistor P5, the sixth PMOS transistor P6, and the seventh PMOS transistor P7 are connected to the power supply, and the drain of the seventh PMOS transistor P7 is connected to the input current I2. The fourth current mirror 104 includes a fourth NMOS transistor N4 and a fifth NMOS transistor N5. The drain of the fourth NMOS transistor N4 is connected to the gate of the fourth NMOS transistor N4, the gate of the fifth NMOS transistor N5, and the drain of the sixth PMOS transistor P6. The sources of the fourth NMOS transistor N4 and the fifth NMOS transistor N5 are connected to ground. The first limiting circuit 105 includes a sixth NMOS transistor N6 and a seventh NMOS transistor N7. The drain of the sixth NMOS transistor N6 is connected to its gate, the gate of the seventh NMOS transistor N7, and the drain of the seventh PMOS transistor P7. The source of the sixth NMOS transistor N6 is connected to the first reference voltage VREF1. The second limiting circuit 106 includes an eighth PMOS transistor P8 and a ninth PMOS transistor P9. The drain of the eighth PMOS transistor P8 is connected to its gate, the gate of the ninth PMOS transistor P9, and the drain of the fifth NMOS transistor N5. The source of the eighth PMOS transistor P8 is connected to the second reference voltage. The drain of the ninth PMOS transistor P9 is connected to the drain of the third NMOS transistor N3.

[0052] In one embodiment, the voltage-to-current conversion circuit 200 includes a first operational amplifier A1, a first resistor R1, an eighth NMOS transistor N8, a tenth PMOS transistor P10, and an eleventh PMOS transistor P11. The positive input terminal of the first operational amplifier A1 is connected to the first terminal of the first capacitor C1, the source of the seventh NMOS transistor N7, and the source of the ninth PMOS transistor P9. The negative input terminal of the first operational amplifier A1 is connected to the first terminal of the first resistor R1 and the source of the eighth NMOS transistor N8. The output terminal of the first operational amplifier A1 is connected to the gate of the eighth NMOS transistor N8. The second terminal of the first resistor R1 is connected to ground. The drain of the eighth NMOS transistor N8 is connected to the drain of the tenth PMOS transistor P10, the gate of the tenth PMOS transistor P10, and the gate of the eleventh PMOS transistor P11. The sources of the tenth PMOS transistor P10 and the eleventh PMOS transistor P11 are connected to the power supply terminal.

[0053] In one embodiment, the current subtraction circuit 300 includes a second operational amplifier A2, a second resistor R2, a ninth NMOS transistor N9, a tenth NMOS transistor N10, an eleventh NMOS transistor N11, a twelfth NMOS transistor N12, a thirteenth NMOS transistor N13, a twelfth PMOS transistor P12, and a thirteenth PMOS transistor P13. The positive input terminal of the second operational amplifier A2 is connected to a second reference voltage VREF2, and the negative input terminal of the second operational amplifier A2 is connected to the first terminal of the second resistor R2 and the source of the ninth NMOS transistor N9. The second terminal of the second resistor R2 is connected to ground. The output terminal of the second operational amplifier A2 is connected to the gate of the ninth NMOS transistor N9, and the drain of the ninth NMOS transistor N9 is connected to the drain and gate of the twelfth PMOS transistor P12. The gate of the thirteenth PMOS transistor P13 is connected to the power supply terminal. The source of the twelfth PMOS transistor P12 and the source of the thirteenth PMOS transistor P13 are connected to the power supply terminal. The drain of the thirteenth PMOS transistor P13 is connected to the gate of the tenth NMOS transistor N10, the drain of the tenth NMOS transistor N10, and the gate of the eleventh NMOS transistor N11. The drain of the eleventh NMOS transistor N11 is connected to the drain of the eleventh PMOS transistor N11, the drain of the twelfth NMOS transistor N12, the gate of the twelfth NMOS transistor N12, and the gate of the thirteenth NMOS transistor N13. The source of the eleventh NMOS transistor N11, the source of the twelfth NMOS transistor N12, and the source of the thirteenth NMOS transistor N13 are connected to ground. The drain of the thirteenth NMOS transistor N13 is the current square wave output terminal, and the output current Io is expressed as:

[0054] I o (t)=V cap (t) / R1-V REF2 (t) / R2;

[0055] In the formula, I O (t) represents the output current, V REF2 R1 is the first resistor, R2 is the second resistor, and R1 = R2 = R. (V) cap The maximum value of (t) is V. REF1 The minimum value is V REF2 Therefore I O (t) has a minimum of 0A and a maximum of (V) REF1 -V REF2 ) / RA.

[0056] Current I O The rising slope of (t) is expressed as:

[0057]

[0058] Current I O The descending slope of (t) is expressed as:

[0059]

[0060] From the formula, the rising slope and falling slope of the current square wave are proportional to the input current. By changing the magnitude of the input current, the magnitude of the rising slope and falling slope of the current square wave can be changed.

[0061] In this embodiment, the hot-swap protection circuit is designed and simulated using DB HiTek 0.18um 60V technology, and the components used are 5V devices. Figure 4 This is the voltage waveform of the first capacitor C1 in this embodiment. The capacitance C of the first capacitor C1 is 6pF, the input current I1 is 18uA, the input current I2 is 1uA, the capacitor charging and discharging current is 17.9uA, and the first resistor R1 and the second resistor R2 are 59.63KΩ. Figure 4 In the first capacitor C1, the rising slope of the voltage is 3.00MV / S, and the falling slope is 3.01MV / S. Figure 5 The output current Io waveform has a rising slope of 53.15 A / s and a falling slope of 52.5 A / s, with a minimum current value of 593 nA. Changing the input current I1 to 7.36 uA, 11.27 uA, and 24.96 uA results in the following output current Io: Figure 6 The rising slopes are 21.34 A / s, 34.02 A / s, and 75.50 A / s, respectively, and the falling slopes are 21.04 A / s, 32.99 A / s, and 74.76 A / s, respectively. This demonstrates how the slope of the output current square wave Io can be controlled by changing the magnitude of the input current I1.

[0062] The above are merely preferred embodiments of the present invention. It should be noted that the above preferred embodiments should not be regarded as limitations on the present invention. For those skilled in the art, several equivalent substitutions, improvements and modifications can be made without departing from the spirit and scope of the present invention. These equivalent substitutions, improvements and modifications should also be regarded as the protection scope of the present invention. Here, the embodiments will not be repeated. The protection scope of the present invention should be determined by the scope defined in the claims.

Claims

1. A slope-controllable current driving circuit, characterized by comprising: a current source circuit; a slope control circuit; a current mirror circuit; and a slope control circuit. The current driving circuit comprises a current-voltage conversion circuit, a voltage-current conversion circuit and a current subtraction circuit; The output end of the current-voltage conversion circuit is connected with the input end of the voltage-current conversion circuit, and the output end of the voltage-current conversion circuit is connected with the input end of the current subtraction circuit; The current-voltage conversion circuit is configured to convert an input current into a voltage square wave signal; The voltage-current conversion circuit is configured to convert the voltage square wave signal output by the current-voltage conversion circuit into a current square wave signal; The current subtraction circuit is configured to obtain an output current by taking difference between the current square wave signal and a reference current, and the slope of the output current is proportional to the input current; The current subtraction circuit comprises a second operational amplifier, a second resistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a twelfth PMOS transistor and a thirteenth PMOS transistor, the non-inverting input end of the second operational amplifier is connected with a second reference voltage, the inverting input end of the second operational amplifier is connected with the first end of the second resistor and the source of the ninth NMOS transistor respectively, the second end of the second resistor is connected with the ground, the output end of the second operational amplifier is connected with the gate of the ninth NMOS transistor, the drain of the ninth NMOS transistor is connected with the drain of the twelfth PMOS transistor, the gate of the twelfth PMOS transistor and the gate of the thirteenth PMOS transistor respectively, the source of the twelfth PMOS transistor and the source of the thirteenth PMOS transistor are connected with a power supply end, the drain of the thirteenth PMOS transistor is connected with the gate of the tenth NMOS transistor, the drain of the tenth NMOS transistor and the gate of the eleventh NMOS transistor respectively, the drain of the eleventh NMOS transistor is connected with the output end of the voltage-current conversion circuit, the drain of the twelfth NMOS transistor and the gate of the twelfth NMOS transistor and the gate of the thirteenth NMOS transistor respectively, the source of the eleventh NMOS transistor, the source of the twelfth NMOS transistor, the source of the tenth NMOS transistor and the source of the thirteenth NMOS transistor are connected with the ground, and the drain of the thirteenth NMOS transistor is the current square wave output end of the slope-controllable current driving circuit.

2. The slope-controllable current driving circuit according to claim 1, wherein The current-voltage conversion circuit comprises a first capacitor, a first current mirror, a second current mirror, a third current mirror, a fourth current mirror, a first limiting circuit, a second limiting circuit, a first PMOS transistor and a first NMOS transistor; The first current mirror generates a charging current of the first capacitor, the second current mirror generates a discharging current of the first capacitor, the third current mirror generates a bias current of the first limiting circuit, the fourth current mirror generates a bias current of the second limiting circuit, the first limiting circuit is used for limiting a maximum voltage of the first capacitor, the second limiting circuit is used for limiting a minimum voltage of the first capacitor, the first PMOS transistor is used for controlling the first current mirror to charge the first capacitor, and the first NMOS transistor is used for controlling the second current mirror to discharge the first capacitor. The input end of the first current mirror is connected to a first input current, the source of the first PMOS transistor is connected to a power supply end, the drain of the first PMOS transistor is connected to the first current mirror, the input end of the third current mirror is connected to a second input current, the first limiting circuit is connected with the first current mirror, the third current mirror, the second limiting circuit, a first end of the first capacitor and an input end of the voltage-current conversion circuit respectively, the second limiting circuit is connected with the second current mirror and the fourth current mirror respectively, the third current mirror and the fourth current mirror are connected, the drain of the first NMOS transistor is connected with the second current mirror, the source of the first NMOS transistor and a second end of the first capacitor are both connected with the ground, the input end of the first limiting circuit is connected with a first reference voltage, the input end of the second limiting circuit is connected with a second reference voltage, the gate of the first PMOS transistor is connected with a first control signal, the source of the first NMOS transistor is connected with the ground, and the gate of the first PMOS transistor is connected with a second control signal.

3. The slope-controllable current driving circuit according to claim 2, wherein The first control signal and the second control signal are opposite in phase.

4. The slope-controllable current driving circuit according to claim 2, wherein The first reference voltage is greater than the second reference voltage.

5. The slope-controllable current driving circuit according to claim 2, wherein In the current-voltage conversion circuit, when the gate of the first PMOS transistor is low, the first current mirror charges the first capacitor, the voltage of the first capacitor rises until the second reference voltage is reached, and the size of the charging current controls the voltage rising slope of the capacitor; and when the gate of the first PMOS transistor is high, the first current mirror stops charging the first capacitor.

6. The slope-controllable current driving circuit according to claim 2, wherein In the current-voltage conversion circuit, when the gate of the first NMOS transistor is high, the second current mirror discharges the first capacitor, the voltage of the first capacitor decreases until the second reference voltage is reached, and the size of the discharging current controls the voltage decreasing slope of the capacitor; and when the gate of the first NMOS transistor is low, the second current mirror stops discharging the first capacitor.

7. The slope-controllable current driving circuit according to claim 2, characterized in that: The first current mirror comprises a second PMOS tube, a third PMOS tube and a fourth PMOS tube, the drain of the second PMOS tube is connected to the gate of the second PMOS tube, the gate of the third PMOS tube and the gate of the fourth PMOS tube respectively, the source of the second PMOS tube and the source of the third PMOS tube are connected to a power supply end, the source of the third PMOS tube is connected to the drain of the first PMOS tube, and the source of the fourth PMOS tube is connected to the drain of the first PMOS tube; The second current mirror comprises a second NMOS tube and a third NMOS tube, the drain of the second NMOS tube is connected to the gate of the second NMOS tube, the gate of the third NMOS tube and the drain of the third PMOS tube respectively, the source of the second NMOS tube is connected to the ground, the source of the third NMOS tube is connected to the drain of the first NMOS tube, and the source of the third NMOS tube is connected to the drain of the first NMOS tube; The third current mirror comprises a fifth PMOS tube, a sixth PMOS tube and a seventh PMOS tube, the drain of the fifth PMOS tube is connected to the gate of the fifth PMOS tube, the gate of the sixth PMOS tube and the gate of the seventh PMOS tube respectively, the source of the fifth PMOS tube, the source of the sixth PMOS tube and the source of the seventh PMOS tube are all connected to a power supply end, and the drain of the fifth PMOS tube is connected to a second input current; The fourth current mirror comprises a fourth NMOS tube and a fifth NMOS tube, the drain of the fourth NMOS tube is connected to the gate of the fourth NMOS tube, the gate of the fifth NMOS tube and the drain of the sixth PMOS tube respectively, the source of the fourth NMOS tube and the source of the fifth NMOS tube are all connected to the ground; The first limiting circuit comprises a sixth NMOS tube and a seventh NMOS tube, the drain of the sixth NMOS tube is connected to the gate of the sixth NMOS tube, the gate of the seventh NMOS tube and the drain of the seventh PMOS tube respectively, the source of the sixth NMOS tube is connected to a first reference voltage, the drain of the seventh NMOS tube is connected to the drain of the fourth PMOS tube; The second limiting circuit comprises an eighth PMOS tube and a ninth PMOS tube, the drain of the eighth PMOS tube is connected to the gate of the eighth PMOS tube, the gate of the ninth PMOS tube and the drain of the fifth NMOS tube, the source of the eighth PMOS tube is connected to a second reference voltage, the drain of the ninth PMOS tube is connected to the drain of the third NMOS tube, the source of the seventh NMOS tube and the source of the ninth PMOS tube are both connected to the first end of the first capacitor.

8. The slope-controllable current driving circuit according to claim 1, wherein The voltage current conversion circuit includes a first operational amplifier, a first resistor, an eighth NMOS tube, a tenth PMOS tube and an eleventh PMOS tube, the non-inverting input end of the first operational amplifier is connected with the output end of the current voltage conversion circuit, the inverting input end of the first operational amplifier is connected with the first end of the first resistor and the source of the eighth NMOS tube respectively, the output end of the first operational amplifier is connected with the gate of the eighth NMOS tube, the second end of the first resistor is connected with the ground, the drain of the eighth NMOS tube is connected with the drain of the tenth PMOS tube, the gate of the tenth PMOS tube and the gate of the eleventh PMOS tube, the source of the tenth PMOS tube and the source of the eleventh PMOS tube are connected with the power supply end, and the drain of the eleventh PMOS tube is connected with the current subtraction circuit.

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