Data read control method and memory storage device

Abstract

The present application provides a data read control method and a memory storage device, which can improve the construction quality and efficiency of a sequential mapping table and improve the performance of the memory storage device. The data read control method is used in a rewritable non-volatile memory module. The data read control method includes: receiving a read instruction and a corresponding first logical address interval; determining whether a first sequential mapping table corresponding to the first logical address interval exists according to a state table; if the first sequential mapping table exists, performing a read operation according to the first sequential mapping table; and if the first sequential mapping table does not exist, performing the read operation according to a logical-to-physical address mapping table, wherein the first sequential mapping table is different from the logical-to-physical address mapping table.

Description

TECHNICAL FIELD

[0001] The present application relates to a storage technology field, and more particularly, to a data read control method and a memory storage device. BACKGROUND

[0002] Smartphones, tablet computers and personal computers have grown rapidly in recent years, resulting in a rapid increase in consumer demand for storage media. Rewritable non-volatile memory modules (e.g., flash memory) are very suitable for being built into various portable multimedia devices exemplified above due to their data non-volatility, power saving, small size, and no mechanical structure.

[0003] Generally speaking, one or more mapping tables are established and maintained in a memory storage device to record the mapping relationship between physical addresses and logical addresses. When a host system wants to read data or write data from a rewritable non-volatile memory module, a memory management circuit (e.g., a memory controller) can, for example, look up a mapping table to obtain the physical address corresponding to the logical address to perform a data access operation on the rewritable non-volatile memory module. In a memory storage device, the lookup or search of a mapping table is usually a time-consuming and energy-consuming operation.

[0004] How to optimize the operation of looking up a mapping table is a technical problem that needs to be solved urgently. SUMMARY

[0005] An example embodiment of the present application provides a data read control method and a memory storage device, which can improve the performance of the memory storage device.

[0006] An example embodiment of the present application provides a data read control method for a rewritable non-volatile memory module. The data read control method includes: receiving a read instruction and a first logical address interval corresponding to the read instruction; determining whether a first sequential mapping table corresponding to the first logical address interval exists according to a state table; if the first sequential mapping table exists, performing a read operation according to the first sequential mapping table; and if the first sequential mapping table does not exist, performing the read operation according to a logical-to-physical address mapping table, wherein the first sequential mapping table is different from the logical-to-physical address mapping table.

[0007] In an example embodiment of the present disclosure, the data read control method further comprises: constructing the state table; and constructing a plurality of sequential mapping tables, wherein the state table comprises a plurality of state identifiers, the plurality of state identifiers respectively correspond to a plurality of logical address intervals, each of the state identifiers is used to represent whether there is a sequential mapping table corresponding to the logical address interval corresponding thereto, and the plurality of sequential mapping tables comprises the first sequential mapping table and the plurality of logical address intervals comprises the first logical address interval.

[0008] In an example embodiment of the present disclosure, the data read control method further comprises: detecting that a trigger condition is reached when a plurality of read operations are performed, then traversing the state table to query a plurality of continuous segments; determining whether the plurality of continuous segments satisfy a preset condition; if yes, arranging the plurality of continuous segments from large to small, and copying a second sequential mapping table corresponding to a first number of continuous segments in the plurality of continuous segments to a sequential mapping buffer memory, wherein the plurality of sequential mapping tables comprises the second sequential mapping table.

[0009] In an example embodiment of the present disclosure, the step of determining whether the plurality of continuous segments satisfy the preset condition comprises: determining whether the number of the plurality of continuous segments is in a preset interval; if the number is in the preset interval, determining whether the total number of state identifiers in the plurality of continuous segments is greater than a third number; if yes, determining that the plurality of continuous segments satisfy the preset condition.

[0010] In an example embodiment of the present disclosure, the step of determining whether the plurality of continuous segments satisfy the preset condition further comprises: if the number is not in the preset interval, determining whether the number is greater than a preset number; if the number is greater than the preset number, determining whether the total number of state identifiers in a second number of continuous segments with more state identifiers in the plurality of continuous segments is greater than the third number; if yes, determining that the plurality of continuous segments satisfy the preset condition.

[0011] In an example embodiment of the present disclosure, the trigger condition is that the number of the plurality of read operations is greater than a preset value or the data amount of read data corresponding to the plurality of read operations is greater than a preset data amount.

[0012] In an example embodiment of the present disclosure, a state identifier belonging to a first logical value in the plurality of state identifiers is used to represent that there is the sequential mapping table corresponding to the logical address interval corresponding thereto, and a state identifier belonging to a second logical value in the plurality of state identifiers is used to represent that there is no sequential mapping table corresponding to the logical address interval corresponding thereto.

[0013] In an example embodiment of the present application, each of the plurality of consecutive segments includes a consecutive status indicator, and the consecutive status indicator is at least two adjacent status indicators of the plurality of status indicators, wherein the at least two adjacent status indicators are both the first logical value.

[0014] In an example embodiment of the present application, the step of traversing the status table to query the plurality of consecutive segments includes, if the status indicator belonging to the second logical value is queried, not querying the subsequent fourth number of status indicators.

[0015] In an example embodiment of the present application, the fourth number is associated with a logical address interval corresponding to a consecutive write operation.

[0016] In an example embodiment of the present application, the step of arranging the plurality of consecutive segments from large to small includes arranging the plurality of consecutive segments from large to small according to the number of status indicators included therein.

[0017] An example embodiment of the present application further provides a memory storage device including a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit includes a sequential mapping buffer memory. The connection interface unit is used to be coupled to a host system. The memory control circuit unit is used to receive a read instruction and a corresponding first logical address interval. The memory control circuit unit is further used to determine whether a first sequential mapping table corresponding to the first logical address interval exists according to a status table. If the first sequential mapping table exists, the memory control circuit unit is further used to perform a read operation according to the first sequential mapping table. If the first sequential mapping table does not exist, the memory control circuit unit is further used to perform the read operation according to a logical-to-physical address mapping table, wherein the first sequential mapping table is different from the logical-to-physical address mapping table.

[0018] In an example embodiment of the present application, the memory control circuit unit is further used to construct the status table and a plurality of sequential mapping tables, wherein the status table includes a plurality of status indicators, the plurality of status indicators respectively correspond to a plurality of logical address intervals, each of the status indicators is used to represent whether a sequential mapping table corresponding to the logical address interval corresponding thereto exists, and the plurality of sequential mapping tables include the first sequential mapping table and the plurality of logical address intervals include the first logical address interval.

[0019] In an example embodiment of the present disclosure, the memory control circuit unit is further configured to detect that a trigger condition is reached when performing a plurality of read operations. The memory control circuit unit is further configured to traverse the state table to query a plurality of consecutive segments. The memory control circuit unit is further configured to determine whether the plurality of consecutive segments satisfy a preset condition. If so, the memory control circuit unit is further configured to arrange the plurality of consecutive segments from large to small, and copy a second order mapping table corresponding to a first number of consecutive segments in the plurality of consecutive segments to an order mapping buffer memory, wherein the plurality of order mapping tables include the second order mapping table.

[0020] In an example embodiment of the present disclosure, the memory control circuit unit is further configured to determine whether the number of the plurality of consecutive segments is in a preset interval. If the number is in the preset interval, the memory control circuit unit is further configured to determine whether a total number of state identifiers in the plurality of consecutive segments is greater than a third number. If so, the memory control circuit unit is further configured to determine that the plurality of consecutive segments satisfy the preset condition.

[0021] In an example embodiment of the present disclosure, wherein if the number is not in the preset interval, the memory control circuit unit is further configured to determine whether the number is greater than a preset number. If the number is greater than the preset number, the memory control circuit unit is further configured to determine whether a total number of state identifiers in a second number of consecutive segments having more state identifiers in the plurality of consecutive segments is greater than the third number. If so, the memory control circuit unit is further configured to determine that the plurality of consecutive segments satisfy the preset condition.

[0022] In an example embodiment of the present disclosure, wherein if the state identifier belonging to the second logical value is queried, the memory control circuit unit is further configured to not query a fourth number of subsequent state identifiers.

[0023] In an example embodiment of the present disclosure, the memory control circuit unit is further configured to arrange the plurality of consecutive segments from large to small according to a number of state identifiers included therein.

[0024] Based on the above, the present disclosure provides a data read control method and a memory storage device. The management mechanism for order mapping tables can be optimized based on the continuity of a state table (i.e., a plurality of consecutive segments in the state table), and read operations are performed according to the order mapping tables, so as to reduce the time required for loading the mapping tables, thereby improving the efficiency of the memory storage device.

[0025] In order to make the above features and advantages of the present disclosure more apparent, specific examples are described below in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device shown in accordance with an example embodiment of the present invention;

[0027] Figure 2 is a schematic diagram of a host system, a memory storage device, and an I / O device shown in accordance with an example embodiment of the present invention;

[0028] Figure 3 is a schematic diagram of a host system and a memory storage device shown in accordance with an example embodiment of the present invention;

[0029] Figure 4 is a schematic diagram of a memory storage device shown in accordance with an example embodiment of the present invention;

[0030] Figure 5 is a schematic diagram of a memory control circuit unit shown in accordance with an example embodiment of the present invention;

[0031] Figure 6 is a schematic diagram of a management rewritable non-volatile memory module shown in accordance with an example embodiment of the present invention;

[0032] Figure 7 is a schematic diagram of a state table and a sequence mapping table shown in accordance with an example embodiment of the present invention;

[0033] Figure 8 is a flowchart of a data read control method shown in accordance with an example embodiment of the present invention;

[0034] Figure 9 is a flowchart of a data read control method shown in accordance with an example embodiment of the present invention. DETAILED DESCRIPTION

[0035] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

[0036] Generally speaking, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module and a controller (also referred to as a control circuit). The memory storage device can be used with a host system so that the host system can write data to or read data from the memory storage device.

[0037] Figure 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device shown in accordance with an example embodiment of the present invention;Figure 2 is a schematic diagram of a host system, a memory storage device, and an I / O device shown in accordance with an example embodiment of the present application.

[0038] Referring to Figure 1 and Figure 2 , the host system 11 can include a processor 111, a random access memory (RAM) 112, a read only memory (ROM) 113, and a data transfer interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transfer interface 114 can be coupled to a system bus 110.

[0039] In an example embodiment, the host system 11 can be coupled to the memory storage device 10 through the data transfer interface 114. For example, the host system 11 can store data to or read data from the memory storage device 10 via the data transfer interface 114. In addition, the host system 11 can be coupled to the I / O device 12 through the system bus 110. For example, the host system 11 can transmit an output signal to or receive an input signal from the I / O device 12 via the system bus 110.

[0040] In an example embodiment, the processor 111, the random access memory 112, the read only memory 113, and the data transfer interface 114 can be disposed on a motherboard 20 of the host system 11. The number of the data transfer interface 114 can be one or more. Through the data transfer interface 114, the motherboard 20 can be coupled to the memory storage device 10 via a wired or wireless manner.

[0041] In an example embodiment, the memory storage device 10 can be, for example, a flash drive 201, a memory card 202, a solid state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 can be, for example, a near field communication (NFC) memory storage device, a wireless fidelity (WiFi) memory storage device, a Bluetooth memory storage device, or a Bluetooth low energy memory storage device (e.g., iBeacon), or the like memory storage device based on various wireless communication technologies. In addition, the motherboard 20 can also be coupled to various I / O devices, such as a global positioning system (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, and the like, through the system bus 110. For example, in an example embodiment, the motherboard 20 can access the wireless memory storage device 204 through the wireless transmission device 207.

[0042] In an example embodiment, the host system 11 is a computer system. In an example embodiment, the host system 11 can be any system that can substantially cooperate with the memory storage device to store data. In an example embodiment, the host system 11 is an in-vehicle system. In an example embodiment, the memory storage device 10 and the host system 11 can respectively comprise a memory storage device 30 and a host system 31 as shown in Figure 3

[0043] Figure 3 A schematic diagram of a host system and a memory storage device according to an example embodiment of the present application.

[0044] Referring to Figure 3 , the memory storage device 30 can be used in cooperation with the host system 31 to store data. For example, the host system 31 can be a digital camera, a camcorder, a communication device, an audio player, a video player, or a tablet computer, or the like system. For example, the memory storage device 30 can be various non-volatile memory storage devices, such as a secure digital (SD) card 32, a compact flash (CF) card 33, or an embedded storage device 34, used by the host system 31. The embedded storage device 34 includes various types of embedded storage devices that directly couple memory modules to a substrate of the host system, such as an embedded multi media card (eMMC) 341 and / or an embedded multi chip package (eMCP) storage device 342. ​

[0045] Figure 4 is a schematic diagram of a memory storage device shown in accordance with an example embodiment of the present application.

[0046] Referring to Figure 4 , the memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable non-volatile memory module 43.

[0047] The connection interface unit 41 is used to couple the memory storage device 10 to a host system 11. The memory storage device 10 can communicate with the host system 11 via the connection interface unit 41. In an example embodiment, the connection interface unit 41 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. In an example embodiment, the connection interface unit 41 can also be compliant with the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards. The connection interface unit 41 can be packaged in a chip with the memory control circuit unit 42, or the connection interface unit 41 can be disposed off-chip from the chip containing the memory control circuit unit 42.

[0048] The memory control circuit unit 42 is coupled to the connection interface unit 41 and the rewritable nonvolatile memory module 43. The memory control circuit unit 42 is used to execute a plurality of logic gates or control instructions implemented in a hardware type or a firmware type and perform operations such as writing, reading, and erasing data in the rewritable nonvolatile memory module 43 according to instructions of the host system 11.

[0049] The rewritable nonvolatile memory module 43 is used to store data written by the host system 11. The rewritable nonvolatile memory module 43 can include a single level cell (SLC) NAND type flash memory module (i.e., a flash memory module in which one storage cell can store one bit), a multi level cell (MLC) NAND type flash memory module (i.e., a flash memory module in which one storage cell can store two bits), a triple level cell (TLC) NAND type flash memory module (i.e., a flash memory module in which one storage cell can store three bits), a quad level cell (QLC) NAND type flash memory module (i.e., a flash memory module in which one storage cell can store four bits), other flash memory modules, or other memory modules with the same characteristics.

[0050] Each storage cell in the rewritable nonvolatile memory module 43 stores one or more bits by changing a voltage (hereinafter also referred to as a threshold voltage). Specifically, there is a charge trapping layer between a control gate and a channel of each storage cell. By applying a write voltage to the control gate, the amount of electrons of the charge trapping layer can be changed, thereby changing the threshold voltage of the storage cell. This operation of changing the threshold voltage of the storage cell is also referred to as "writing data to the storage cell" or "programming the storage cell". With the change in the threshold voltage, each storage cell in the rewritable nonvolatile memory module 43 has a plurality of storage states. By applying a read voltage, it can be determined which storage state a storage cell belongs to, thereby obtaining one or more bits stored in the storage cell.

[0051] In an example embodiment, the memory cells of the rewritable nonvolatile memory module 43 can constitute a plurality of physical program units, and the physical program units can constitute a plurality of physical units. Specifically, the memory cells on the same word line can form one or more physical program units. If each memory cell can store more than two bits, the physical program units on the same word line can be classified into at least lower physical program units and upper physical program units. For example, the least significant bit (LSB) of a memory cell belongs to a lower physical program unit, and the most significant bit (MSB) of a memory cell belongs to an upper physical program unit. Generally, in an MLC NAND type flash memory, the write speed of a lower physical program unit is greater than that of an upper physical program unit, and / or the reliability of a lower physical program unit is higher than that of an upper physical program unit.

[0052] In an example embodiment, a physical program unit is the smallest unit of programming. That is, a physical program unit is the smallest unit of writing data. For example, a physical program unit can be a physical page or a physical sector. If a physical program unit is a physical page, the physical program units can include a data bit area and a redundancy bit area. The data bit area contains a plurality of physical sectors for storing user data, and the redundancy bit area is for storing system data (e.g., management data such as error correction codes). In the present example embodiment, the data bit area contains 32 physical sectors, and the size of one physical sector is 512 bytes (B). However, in other example embodiments, the data bit area can contain 8, 16, or a greater or smaller number of physical sectors, and the size of each physical sector can be greater or smaller. On the other hand, a physical unit is the smallest unit of erasing. That is, each physical unit contains a minimum number of memory cells that are erased together. For example, a physical unit is a physical block.

[0053] Figure 5 FIG. 1 is a schematic diagram of a memory control circuit unit according to an example embodiment of the present application.

[0054] Referring to Figure 5 , the memory control circuit unit 42 includes a memory management circuit 51, a host interface 52, and a memory interface 53.

[0055] The memory management circuit 51 is used to control the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has a plurality of control instructions, and these control instructions are executed to perform data write, read and erase operations, etc. when the memory storage device 10 is in operation. The following description of the operation of the memory management circuit 51 is equivalent to the description of the operation of the memory control circuit unit 42.

[0056] In an exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in firmware. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are burned into the read-only memory. When the memory storage device 10 is in operation, these control instructions are executed by the microprocessor unit to perform data write, read and erase operations, etc.

[0057] In an exemplary embodiment, the control instructions of the memory management circuit 51 can also be stored in code form in a specific area (e.g., a system area in the memory module for storing system data) of the rewritable non-volatile memory module 43. In addition, the memory management circuit 51 has a microprocessor unit (not shown), a read-only memory (not shown) and a random access memory (not shown). In particular, the read-only memory has a boot code, and when the memory control circuit unit 42 is enabled, the microprocessor unit first executes the boot code to load the control instructions stored in the rewritable non-volatile memory module 43 into the random access memory of the memory management circuit 51. Then, the microprocessor unit executes these control instructions to perform data write, read and erase operations, etc.

[0058] In an example embodiment, the control instructions of the memory management circuit 51 can also be implemented in a hardware type. For example, the memory management circuit 51 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory write circuit, the memory read circuit, the memory erase circuit, and the data processing circuit are coupled to the microcontroller. The memory cell management circuit is used to manage the memory cells or the groups of memory cells of the rewritable non-volatile memory module 43. The memory write circuit is used to issue a write instruction sequence to the rewritable non-volatile memory module 43 to write data into the rewritable non-volatile memory module 43. The memory read circuit is used to issue a read instruction sequence to the rewritable non-volatile memory module 43 to read data from the rewritable non-volatile memory module 43. The memory erase circuit is used to issue an erase instruction sequence to the rewritable non-volatile memory module 43 to erase data from the rewritable non-volatile memory module 43. The data processing circuit is used to process the data to be written into the rewritable non-volatile memory module 43 and the data read from the rewritable non-volatile memory module 43. The write instruction sequence, the read instruction sequence, and the erase instruction sequence can each include one or more codes or instruction codes and are used to instruct the rewritable non-volatile memory module 43 to perform corresponding write, read, and erase operations, etc. In an example embodiment, the memory management circuit 51 can also issue other types of instruction sequences to the rewritable non-volatile memory module 43 to instruct to perform corresponding operations.

[0059] The host interface 52 is coupled to the memory management circuit 51. The memory management circuit 51 can communicate with the host system 11 through the host interface 52. The host interface 52 can be used to receive and identify the instructions and data transmitted by the host system 11. For example, the instructions and data transmitted by the host system 11 can be transmitted to the memory management circuit 51 through the host interface 52. In addition, the memory management circuit 51 can transmit data to the host system 11 through the host interface 52. In the present example embodiment, the host interface 52 is compatible with the PCI Express standard. However, it must be understood that the present application is not limited thereto, and the host interface 52 can also be compatible with the SATA standard, the PATA standard, the IEEE 1394 standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard, or other suitable data transmission standards.

[0060] The memory interface 53 is coupled to the memory management circuit 51 and is used to access the rewritable non-volatile memory module 43. For example, the memory management circuit 51 can access the rewritable non-volatile memory module 43 through the memory interface 53. That is, data intended to be written to the rewritable non-volatile memory module 43 is converted into a format acceptable to the rewritable non-volatile memory module 43 via the memory interface 53. Specifically, if the memory management circuit 51 wants to access the rewritable non-volatile memory module 43, the memory interface 53 transmits a corresponding instruction sequence. For example, the instruction sequence can include a write instruction sequence indicating write data, a read instruction sequence indicating read data, an erase instruction sequence indicating erase data, and corresponding instruction sequences to indicate various memory operations (e.g., change read voltage level or perform garbage collection operation, etc.). The instruction sequence is generated, for example, by the memory management circuit 51 and transmitted to the rewritable non-volatile memory module 43 through the memory interface 53. The instruction sequence can include one or more signals, or data on a bus. The signals or data can include instruction codes or codes. For example, in a read instruction sequence, the identification code of the read, memory address, etc. information is included.

[0061] In an example embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 54, a buffer memory 55, a power management circuit 56, and a sequence mapping buffer memory 57.

[0062] The error checking and correction circuit 54 is coupled to the memory management circuit 51 and is used to perform error checking and correction operations to ensure the correctness of data. Specifically, when the memory management circuit 51 receives a write instruction from the host system 11, the error checking and correction circuit 54 generates a corresponding error correcting code (ECC) and / or error detecting code (EDC) for the data corresponding to the write instruction, and the memory management circuit 51 writes the data corresponding to the write instruction and the corresponding error correcting code and / or error detecting code into the rewritable non-volatile memory module 43. Then, when the memory management circuit 51 reads data from the rewritable non-volatile memory module 43, the error correcting code and / or error detecting code corresponding to the data is also read, and the error checking and correction circuit 54 performs error checking and correction operations on the read data according to the error correcting code and / or error detecting code.

[0063] Buffer memory 55 is coupled to memory management circuit 51 and is used to temporarily store data. Power management circuit 56 is coupled to memory management circuit 51 and is used to control the power supply of memory storage device 10. Sequential mapping buffer memory 57 is coupled to memory management circuit 51 and is used to store sequential mapping table.

[0064] In one exemplary embodiment, Figure 4 The rewritable non-volatile memory module 43 may include a flash memory module. In one exemplary embodiment, Figure 4 The memory control circuit unit 42 may include a flash memory controller. In one exemplary embodiment, Figure 5 The memory management circuit 51 may include a flash memory management circuit.

[0065] Figure 6 This is a schematic diagram illustrating the management of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention.

[0066] Please refer to Figure 6 The memory management circuit 51 can logically group the physical units 610(0) to 610(B) in the rewritable non-volatile memory module 43 into the storage area 601 and the spare area 602. A physical unit refers to a virtual block (VB). A virtual block may include multiple physical units. For example, a virtual block may contain one or more physical units.

[0067] Entity units 610(0) to 610(A) in storage area 601 are used to store user data (e.g., from...) Figure 1 (User data of host system 11). For example, entity units 610(0) to 610(A) in storage area 601 can store valid and invalid data. Entity units 610(A+1) to 610(B) in free area 602 do not store data (e.g., valid data). For example, if an entity unit does not store valid data, this entity unit can be associated (or added) to free area 602. In addition, entity units in free area 602 (or entity units that do not store valid data) can be erased. When new data is written, one or more entity units can be retrieved from free area 602 to store this new data. In an exemplary embodiment, free area 602 is also referred to as a free pool.

[0068] The memory management circuit 51 can configure logic units 612(0) to 612(C) to map physical units 610(0) to 610(A) in memory area 601. In an exemplary embodiment, each logic unit corresponds to a logical address. For example, a logical address may include one or more logical block addresses (LBAs) or other logical management units.

[0069] It should be noted that a logical unit can be mapped to one or more entity units. If an entity unit is currently mapped to a logical unit, it means that the data stored in this entity unit currently contains valid data. Conversely, if an entity unit is not currently mapped to any logical unit, it means that the data stored in this entity unit currently does not contain any valid data.

[0070] The memory management circuit 51 can record management data (also known as logic-to-entity mapping information) describing the mapping relationship between logical units and physical units in at least one logic-to-entity mapping table. When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 51 can perform data access operations on the memory storage device 10 according to the information in this logic-to-entity mapping table.

[0071] Figure 7 This is a schematic diagram of a state table and a sequence mapping table according to an exemplary embodiment of the present invention.

[0072] Please refer to Figure 7 The memory management circuit 51 can record management information describing the mapping relationship between logical address ranges and physical address ranges in a sequential mapping table, and construct a status table (PTE) to manage the sequential mapping table. In an exemplary embodiment, the status table PTE may include, for example, multiple (e.g., 512) status identifiers, and each status identifier corresponds to a logical address range. For example, each status identifier corresponds to a logical address range of size 4kB. For example, the logical address range includes the addresses of multiple logical units. For example, the physical address range includes the addresses of multiple physical units.

[0073] In an example embodiment, each state flag is used to indicate whether there is a sequential mapping table corresponding to the logical address interval to which it corresponds. Specifically, the plurality of state flags can respectively belong to a first logical value (e.g., logical value 1) or a second logical value (e.g., logical value 0). For example, a state flag belonging to the logical value 1 is used to indicate that its corresponding logical address interval has been mapped to one or more physical address intervals. That is, a state flag belonging to the logical value 1 is used to indicate that there is a sequential mapping table corresponding to the logical address interval to which it corresponds. For example, a state flag belonging to the logical value 0 is used to indicate that its corresponding logical address interval has not been mapped to a physical address interval. That is, a state flag belonging to the logical value 0 is used to indicate that there is no sequential mapping table corresponding to the logical address interval to which it corresponds.

[0074] In an example embodiment, the memory management circuit 51 can perform a read operation on the memory storage 10 according to the sequential mapping table or the logical-to-physical mapping table described above. Specifically, when the host system 11 desires to read data from the memory storage 10, the memory management circuit 51 can receive a read instruction and its corresponding logical address interval (also referred to as a first logical address interval). The memory management circuit 51 can determine whether there is a sequential mapping table (also referred to as a first sequential mapping table) corresponding to the first logical address interval according to the state table PTE.

[0075] In an example embodiment, assume that the first logical address interval corresponds to the 5th state flag in the state table PTE. As shown in FIG. 5, the 5th state flag belongs to the first logical value (i.e., logical value 1), which indicates that there is a first sequential mapping table Ml corresponding to the first logical address interval. Accordingly, the memory management circuit 51 can perform the read operation according to the first sequential mapping table Ml. Figure 7

[0076] Specifically, the sequential mapping table Ml includes, but is not limited to, a start logical address Addr-l, a length L, and a start physical address Addr-phy. The start logical address Addr-l is the start address of the logical address interval included by the sequential mapping table Ml. The length L is the length of the logical address interval included by the sequential mapping table Ml. The start physical address Addr-phy is the start address of the physical address interval corresponding to the logical address interval. As shown in FIG. 5, the start logical address Addr-l is the same as the first logical address interval, and the start physical address Addr-phy is the start address of the physical address interval corresponding to the first logical address interval. Figure 7 ​As shown, the starting logical address Addr-l is 4 and the length L is 3. Since the first logical address interval corresponds to the 5th state identifier in the state table PTE (i.e., the first logical address interval is the 5th logical address interval represented by the state table PTE) and the starting logical address Addr-l is 4 (i.e., the starting address of the logical address interval included by the sequential mapping table Ml is the starting address of the 4th logical address interval), the memory management circuit 51 can calculate the difference (also referred to as the offset) between the starting address (i.e., the starting address of the 4th logical address interval) and the starting address of the logical address interval currently requested (i.e., the 5th logical address interval) as 1 (i.e., the length of 1 logical address interval). Then, the memory management circuit 51 can obtain the physical address of the physical address interval to which the first logical address interval is mapped according to the starting physical address Addr-phy, the length L and the offset, and complete the read operation accordingly.

[0077] In an example embodiment, it is assumed that the first logical address interval corresponds to the 4th state identifier in the state table PTE. As shown, the 4th state identifier belongs to the second logical value (i.e., the logical value 0), i.e., representing that there is no first sequential mapping table corresponding to the first logical address interval. Therefore, the memory management circuit 51 needs to perform the read operation according to the logical-to-physical mapping table described above. Figure 7

[0078] It is noted that, since the logical-to-physical mapping table is used to record the mapping relationship between each logical unit and the physical unit, and the sequential mapping table only includes the following information: the starting physical address Addr-phy, the length L and the starting physical address Addr-phy, and only these information can be used to represent the mapping relationship between the logical address interval and the physical address interval, therefore, compared with the sequential mapping table, the logical-to-physical mapping table needs to occupy more storage space. Further, the loading time of the logical-to-physical mapping table is also longer than the loading time of the sequential mapping table.

[0079] It is worth mentioning that, if the write data from the host system 11 is discontinuous data, a logical unit corresponding to the write data can be mapped to multiple physical units. In this case, when the host system 11 wants to read the data belonging to this logical unit, the memory management circuit 51 needs to load different logical-to-physical mapping tables multiple times to perform the read operation, which will cause the read speed to be slow, seriously affecting the performance of the memory storage device 10.

[0080] Accordingly, the memory management circuit 51 of the present application can determine to use the logical-to-physical mapping table or the sequential mapping table to perform the read operation through the state table PTE, which can accelerate the execution efficiency of the read operation, thereby improving the performance of the memory storage device 10. ​

[0081] Figure 8 is a flowchart of a data read control method shown according to an example embodiment of the present application.

[0082] Referring to Figure 8 In step S801, the memory management circuit 51 detects that a trigger condition is reached when performing a plurality of read operations. In an example embodiment, the read operations can be, for example, consecutive read operations or random read operations. In an example embodiment, the trigger condition is that the number of read operations is greater than a preset value. In an example embodiment, the trigger condition is that the data amount of read data corresponding to the plurality of read operations is greater than a preset data amount. The values of the preset value and the preset data amount can be designed according to actual needs, and the present application is not limited thereto.

[0083] In step S802, the memory management circuit 51 can traverse the state table PTE to query a plurality of consecutive segments. In an example embodiment, the memory management circuit 51 can check a plurality of state identifiers in the state table PTE to query a plurality of consecutive segments. Specifically, each consecutive segment includes consecutive state identifiers, and the consecutive state identifiers are at least two adjacent state identifiers in the plurality of state identifiers in the state table PTE, wherein the at least two adjacent state identifiers are both the first logic value (i.e., logic value 1). For example, as shown in Figure 7 the first three state identifiers in the state table PTE are all logic value 1, so the three state identifiers are a consecutive segment.

[0084] In an example embodiment, when the memory management circuit 51 queries a state identifier belonging to the second logic value (i.e., logic value 0), the memory management circuit 51 can not query the subsequent fourth number (for example, 64) of state identifiers. In an example embodiment, the fourth number is associated with a logical address interval corresponding to the consecutive write operation.

[0085] Generally, the logical address interval corresponding to the consecutive write operation is in units of 512kB, so in the process of the memory management circuit 51 finding the consecutive segment, the finding unit needs to be less than 512kB (for example, 256kB) each time. Therefore, the fourth number can be defined as 256kB (i.e., 64 state identifiers).

[0086] For example, as shown in Figure 7As shown, the fourth state identifier in the state table PTE is identified as a logical value 0, and the memory management circuit 51 can not query the 64 state identifiers after the fourth state identifier. Further, the fourth state identifier is identified as a logical value 0, which means that there is no sequential mapping table corresponding to the logical address interval corresponding to the fourth state identifier. In other words, the logical address interval corresponding to the fourth state identifier is not mapped to a physical address interval, and therefore the logical address intervals corresponding to the 64 state identifiers after the fourth state identifier should be mapped to discontinuous physical addresses. In other words, the 64 state identifiers have a small probability of having a continuous segment, and therefore the 64 state identifiers can be omitted to quickly query the next continuous segment and improve the traversal speed of the state table PTE.

[0087] After traversing the state table PTE, the memory management circuit 51 can successively determine whether the plurality of continuous segments satisfy a predetermined condition. For example, the memory management circuit 51 can successively perform step 803 and / or step 803 to determine whether the plurality of continuous segments satisfy the predetermined condition. For example, the memory management circuit 51 can successively perform step 803 and / or step 807 and / or step 807 to determine whether the plurality of continuous segments satisfy the predetermined condition.

[0088] In step S803, the memory management circuit 51 can determine whether the number of the plurality of continuous segments is within a predetermined interval. In an example embodiment, the predetermined interval can be, for example, 4 to 8. The range of the predetermined interval can be designed according to actual needs, and the present application is not limited thereto. If the number of the plurality of continuous segments is within the predetermined interval, step S804 is entered. Otherwise, if the number of the plurality of continuous segments is not within the predetermined interval, step S807 is entered.

[0089] In step S804, the memory management circuit 51 can determine whether the total number of state identifiers in the plurality of continuous segments is greater than a third number (for example, 128, which is 512kB).

[0090] In an example embodiment, assuming that the number of the plurality of continuous segments is 8, the memory management circuit 51 can determine whether the total number of state identifiers in the 8 continuous segments is greater than 128. The value of the third number can be designed according to actual needs, and the present application is not limited thereto.

[0091] If the total number of state identifiers in the plurality of continuous segments is not greater than 128, the data read control method of the present application is ended. Figure 8 Specifically, when the total number of state identifiers in the plurality of continuous segments is not greater than 128, it means that the state table PTE is highly random, and the benefit of using a sequential mapping table to record the mapping relationship between the logical address interval and the physical address interval is limited. Therefore, if the total number of state identifiers in the plurality of continuous segments is not greater than 128, the data read control method of the present application is ended. Figure 8the data read control method, and the state table PTE is no longer used. Specifically, when the number of the plurality of consecutive segments is not greater than 4, it indicates that the state table PTE is highly random state, and thus the state table PTE is no longer used.

[0092] On the contrary, if the total number of the state identifiers in the 8 consecutive segments is greater than 128, step S805 is entered.

[0093] In step S805, the memory management circuit 51 can determine that the plurality of consecutive segments satisfy a preset condition.

[0094] In step S806, the memory management circuit 51 can arrange the plurality of consecutive segments from large to small, and copy a sequential mapping table (also referred to as a second sequential mapping table) corresponding to the first number (for example, the first 4) of consecutive segments in the plurality of consecutive segments to the sequential mapping buffer memory 57. In an example embodiment, the memory management circuit 51 can arrange the plurality of consecutive segments from large to small according to the number of state identifiers included therein. Then, the memory management circuit 51 can copy the second sequential mapping table corresponding to the first 4 consecutive segments having the most state identifiers in the state table PTE to the sequential mapping buffer memory 57. Accordingly, the memory management circuit 51 can construct a high-quality (for example, corresponding to a plurality of logical address intervals) sequential mapping table according to all the sequential mapping tables corresponding to the first 4 consecutive segments, thereby improving the performance of the memory storage device 10.

[0095] Accordingly, the memory management circuit 51 can read the data that can be required in advance into the buffer memory 55 according to the information in all the sequential mapping tables corresponding to the first 4 consecutive segments, so as to improve the performance of the memory storage device 10. In addition, the method of copying the first 4 consecutive segments to the sequential mapping buffer memory 57 can avoid the time of loading the sequential mapping table when performing the subsequent data access operation, and can reduce the situation of loading different logical to physical mapping tables multiple times, so as to improve the data access speed of the memory storage device 10.

[0096] On the other hand, if the number of the plurality of consecutive segments is not in the preset interval (that is, 4 to 8), in step S807, the memory management circuit 51 can determine whether the number of the plurality of consecutive segments is greater than a preset number (for example, 4). The value of the preset number can be designed according to actual needs, and the present application is not limited thereto. If the number of the plurality of consecutive segments is not greater than 4, the process ends. Figure 8 the data read control method, and the state table PTE is no longer used. Specifically, when the number of the plurality of consecutive segments is not greater than 4, it indicates that the state table PTE is highly random state, and thus the state table PTE is no longer used.

[0097] On the contrary, if the number of the plurality of consecutive segments is greater than 4, step S808 is entered.

[0098] In step S808, the memory management circuit 51 can determine whether the total number of state identifiers in the second number (e.g., the first 8) of consecutive segments having more state identifiers among the plurality of consecutive segments is greater than a third number (i.e., 128). In an example embodiment, assuming that the number of consecutive segments is 10, the memory management circuit 51 can select the first 8 consecutive segments having more state identifiers from the 10 consecutive segments, and determine whether the total number of state identifiers in the first 8 consecutive segments is greater than 128. If the total number of nodes in the first 8 consecutive segments is not greater than 128, it indicates that the state table PTE is highly random, and the method of data read control ends. Figure 8 The state table PTE is no longer used.

[0099] On the contrary, if the total number of state identifiers in the first 8 consecutive segments is greater than 128, the memory management circuit 51 can successively complete steps S805 and S806. The implementation details of steps S805 and S806 have been described above, and are not repeated here.

[0100] According to the above, the memory management circuit 51 can optimize the management mechanism for the sequential mapping table based on the continuity of the state table PTE to construct a high-quality (e.g., corresponding to a plurality of logical address intervals) sequential mapping table, thereby improving the performance of the memory storage device 10.

[0101] Figure 9 is a flowchart of a memory management method according to an example embodiment of the present application. Please refer to Figure 9 In step S901, a read instruction and its corresponding first logical address interval are received. In step S902, it is determined whether a first sequential mapping table corresponding to the first logical address interval exists according to the state table. In step S903, if the first sequential mapping table exists, a read operation is performed according to the first sequential mapping table. In step S904, if the first sequential mapping table does not exist, a read operation is performed according to a logical-to-physical address mapping table, wherein the first sequential mapping table is different from the logical-to-physical address mapping table.

[0102] However, Figure 9 The implementation details of each step in have been described above, and are not repeated here. It is noted that Figure 9 Each step in can be implemented as a plurality of program codes or circuits, and the present application is not limited thereto. In addition, Figure 9 The method of can be used in combination with the above embodiments, or can be used alone, and the present application is not limited thereto.

[0103] In summary, the data read control method and the memory storage device of the exemplary embodiments of the present application can optimize the management mechanism for the sequential mapping table based on the continuity of the state table, and can accelerate the execution efficiency of the read operation by using the sequential mapping table to perform the read operation, thereby improving the performance of the memory storage device 10.

[0104] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A data read control method, characterized by, A data read control method for a rewritable non-volatile memory module, the data read control method comprising: constructing a state table and a plurality of sequential mapping tables, wherein the state table comprises a plurality of state identifiers, each of the plurality of state identifiers corresponding to a logical address interval, each of the state identifiers is used to represent whether there is a sequential mapping table corresponding to the logical address interval to which the state identifier corresponds, a state identifier of the plurality of state identifiers belonging to a first logical value is used to represent that there is the sequential mapping table corresponding to the logical address interval to which the state identifier corresponds, and a state identifier of the plurality of state identifiers belonging to a second logical value is used to represent that there is not the sequential mapping table corresponding to the logical address interval to which the state identifier corresponds; receiving a read instruction and a first logical address interval corresponding to the read instruction, wherein the plurality of logical address intervals comprises the first logical address interval; determining whether there is a first sequential mapping table corresponding to the first logical address interval according to the state table, wherein the plurality of sequential mapping tables comprises the first sequential mapping table; if the first sequential mapping table exists, performing a read operation according to the first sequential mapping table; if the first sequential mapping table does not exist, performing the read operation according to a logical-to-physical address mapping table, wherein the first sequential mapping table is different from the logical-to-physical address mapping table; if a trigger condition is detected when a plurality of read operations are performed, traversing the state table to query a plurality of continuous segments, wherein each of the continuous segments comprises continuous state identifiers, and the continuous state identifiers are at least two adjacent state identifiers of the plurality of state identifiers, and the at least two adjacent state identifiers are the first logical value; determining whether the plurality of continuous segments satisfy a preset condition; if yes, arranging the plurality of continuous segments from large to small, and copying a second sequential mapping table corresponding to a first number of continuous segments of the plurality of continuous segments to a sequential mapping buffer memory, wherein the plurality of sequential mapping tables comprises the second sequential mapping table.

2. The data read control method of claim 1, wherein the step of determining whether the plurality of continuous segments satisfy the preset condition comprises: determining whether a number of the plurality of continuous segments is in a preset interval; if the number is in the preset interval, determining whether a total number of state identifiers in the plurality of continuous segments is greater than a third number; if yes, determining that the plurality of continuous segments satisfy the preset condition.

3. The data read control method of claim 2, wherein the step of determining whether the plurality of continuous segments satisfy the preset condition further comprises: if the number is not in the preset interval, determining whether the number is greater than a preset number; if the number is greater than the preset number, determining whether a total number of state identifiers in a second number of continuous segments of the plurality of continuous segments, which include more state identifiers, is greater than the third number; if yes, determining that the plurality of continuous segments satisfy the preset condition.

4. The data read control method of claim 1, wherein the trigger condition is that a number of the plurality of read operations is greater than a preset value or a data amount of read data corresponding to the plurality of read operations is greater than a preset data amount.

5. The data read control method of claim 1, wherein the step of traversing the state table to query the plurality of consecutive segments comprises: if a state identifier belonging to the second logical value is queried, not querying a subsequent fourth number of state identifiers.

6. The data read control method of claim 5, wherein the fourth number is associated with a logical address interval corresponding to a sequential write operation.

7. The data read control method of claim 1, wherein the step of arranging the plurality of consecutive segments from large to small comprises: arranging the plurality of consecutive segments from large to small according to a number of state identifiers included therein.

8. A memory storage device, characterized by, comprises: a connection interface unit coupled to a host system; a rewritable non-volatile memory module; and a memory control circuit unit coupled to the connection interface unit and the rewritable non-volatile memory module and comprising a sequential mapping buffer memory, wherein the memory control circuit unit is configured to: construct a state table and a plurality of sequential mapping tables, wherein the state table comprises a plurality of state identifiers, the plurality of state identifiers respectively corresponding to a plurality of logical address intervals, each of the state identifiers is used to represent whether a sequential mapping table corresponding to the logical address interval to which the state identifier corresponds exists, a state identifier belonging to a first logical value among the plurality of state identifiers is used to represent that the sequential mapping table corresponding to the logical address interval to which the state identifier corresponds exists, and a state identifier belonging to a second logical value among the plurality of state identifiers is used to represent that the sequential mapping table corresponding to the logical address interval to which the state identifier corresponds does not exist; receive a read instruction and a first logical address interval corresponding thereto, wherein the plurality of logical address intervals comprises the first logical address interval; determine whether a first sequential mapping table corresponding to the first logical address interval exists according to the state table, wherein the plurality of sequential mapping tables comprises the first sequential mapping table; if the first sequential mapping table exists, perform a read operation according to the first sequential mapping table; if the first sequential mapping table does not exist, perform the read operation according to a logical-to-physical address mapping table, wherein the first sequential mapping table is different from the logical-to-physical address mapping table; detect that a trigger condition is reached when performing a plurality of read operations, then traverse the state table to query a plurality of consecutive segments, each of the consecutive segments comprises consecutive state identifiers, and the consecutive state identifiers are at least two adjacent state identifiers among the plurality of state identifiers, wherein the at least two adjacent state identifiers are both the first logical value; determine whether the plurality of consecutive segments satisfy a preset condition; if yes, arrange the plurality of consecutive segments from large to small, and copy a second sequential mapping table corresponding to a first number of consecutive segments among the plurality of consecutive segments to the sequential mapping buffer memory, wherein the plurality of sequential mapping tables comprises the second sequential mapping table.

9. The memory storage device of claim 8, wherein the memory control circuit unit is further configured to: determine whether a number of the plurality of consecutive segments is located in a preset interval; if the number is in the preset interval, determining whether a total number of state identifiers in the plurality of continuous segments is greater than a third number; if yes, determining that the plurality of continuous segments satisfy the preset condition.

10. The memory storage device of claim 9, wherein the memory control circuitry is further configured to: if the number is not in the preset interval, determining whether the number is greater than a preset number; if the number is greater than the preset number, determining whether a total number of state identifiers in a second number of continuous segments of the plurality of continuous segments that include more state identifiers is greater than the third number; if yes, determining that the plurality of continuous segments satisfy the preset condition.

11. The memory storage device of claim 8, wherein the trigger condition is that the number of the plurality of read operations is greater than a preset value or an amount of data corresponding to read data of the plurality of read operations is greater than a preset data amount.

12. The memory storage device of claim 8, wherein the memory control circuitry is further configured to: if the state identifier belonging to the second logic value is found, not querying a fourth number of subsequent state identifiers.

13. The memory storage device of claim 12, wherein the fourth number is associated with a logic address interval corresponding to a continuous write operation.

14. The memory storage device of claim 8, wherein the memory control circuitry is further configured to: arranging the plurality of continuous segments in descending order according to the number of state identifiers included therein.

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