A high-speed data interaction method and device of an inkjet printer and a storage medium

Abstract

The application discloses a high-speed data interaction method and device of an inkjet printer and a storage medium, and the method comprises the following steps: S1, a data buffer is arranged between a transmission channel of an FPGA and an MCU; S2, the MCU initializes the state of the data buffer; S3, the MCU acquires a data block from a printing task queue and transmits the data block to the data buffer; S4, the MCU sends a write completion signal to the FPGA through a control line; S5, after the FPGA receives the write completion signal, the FPGA reads data from the data buffer for processing; and S6, after reading is completed, the FPGA feeds back a read completion signal to the MCU through the control line, so as to prepare for the next data exchange. The application introduces high-speed DRAM as a data buffer and optimizes the data transmission architecture between the MCU and the FPGA, effectively solves the bandwidth bottleneck problem of a traditional data bus, and greatly improves the overall system response speed and printing efficiency of the digital inkjet printer.

Description

Technical Field

[0001] This invention relates to the field of printer technology, and in particular to a high-speed data interaction method, device and storage medium for inkjet printers. Background Technology

[0002] In modern digital inkjet printer systems, data exchange between a microcontroller unit (MCU) and a field-programmable gate array (FPGA) is crucial for achieving efficient printing. However, with the continuous enhancement of printer functionality and the increase in printing speed, the data transmission requirements between the MCU and FPGA are also constantly increasing. In this process, traditional data bus architectures typically face the following problems:

[0003] Bandwidth bottleneck: Existing bus architectures frequently experience insufficient bandwidth during frequent data transmissions. Because the MCU and FPGA require high-speed transmission of large amounts of data, traditional bus bandwidth cannot meet this demand, resulting in low data transmission rates and impacting the overall performance of the printer.

[0004] Data transmission rate mismatch: There are differences in data processing capabilities and operating frequencies between MCUs and FPGAs. Traditional bus connection architectures are prone to data congestion or transmission delays due to data rate mismatch, which can lead to poor data flow during printing and affect printing efficiency.

[0005] Low system response speed: Due to the limitations of the bus architecture, under high-load printing tasks, the problems of data transmission delay and rate mismatch become more and more serious, resulting in a decrease in the printer's system response speed, which affects user experience and production efficiency.

[0006] These technical limitations severely restrict the performance and application scope of digital inkjet printers, especially in scenarios requiring high-speed, large-data-volume transmission, where traditional architectures can no longer meet the demands of efficient printing. Therefore, there is an urgent need for a new data exchange architecture that can improve data transmission rates, alleviate bandwidth bottlenecks, and reduce system latency to enhance the overall performance and printing efficiency of digital inkjet printers. Summary of the Invention

[0007] In order to solve the above-mentioned technical problems, the present invention provides a high-speed data interaction method, device and storage medium for inkjet printers.

[0008] The technical solution of this invention is implemented as follows:

[0009] A high-speed data interaction method for inkjet printers is as follows:

[0010] S1, Set up a data buffer between the transmission channels of the FPGA and the MCU;

[0011] S2, MCU initializes the state of the data buffer;

[0012] S3, the MCU retrieves a data block from the print task queue and transfers the data block to the data buffer;

[0013] S4. After the transmission in step S3 is completed, the MCU sends a write completion signal to the FPGA via the control line.

[0014] S5, after the FPGA receives the write completion signal, it reads data from the data buffer for processing;

[0015] S6. After the read is completed, the FPGA sends a read completion signal back to the MCU via the control line to prepare for the next data exchange.

[0016] Preferably, the data buffer is a high-speed DRAM, and the FPGA and MCU interact with the DRAM through a complex number of control lines.

[0017] Preferably, the control lines of the complex number specifically include read / write enable lines, address lines, and data lines.

[0018] Preferably, a synchronization circuit is added between the MCU and the FPGA, specifically a bistable trigger to construct a synchronizer, with the control signal from the MCU as the input of the synchronizer, and the clock signal of the synchronizer matching the system clock of the FPGA.

[0019] Preferably, in step S2, the MCU initializes the state of the data buffer, specifically by clearing the memory space in the data buffer.

[0020] Preferably, the data buffer further includes the following data processing steps:

[0021] L1: The MCU reads the DRAM status and sends data information to the DRAM. After the DRAM confirms that it is ready, the MCU starts sending data blocks.

[0022] L2: After the MCU finishes sending the data block, it sends information to the DRAM to confirm that the transmission was complete.

[0023] L3, the MCU triggers the synchronization circuit, the FPGA sends a request signal to the DRAM, and after the DRAM confirms that it is ready, it starts sending data to the FPGA;

[0024] The DRAM state includes read and write states, which specifically refers to determining whether the current read and write requirements can be met in the DRAM's storage cells.

[0025] The DRAM is also equipped with multiple levels of cache, namely a level 1 cache, a level 2 cache, and a level 3 cache. The level 1 and level 2 caches are read and write areas, and the level 3 cache is a data transmission area. Data interaction between the level 1 and level 2 caches is transmitted through the level 3 cache.

[0026] A device for high-speed data interaction of an inkjet printer includes at least one processor, at least one memory, and computer program instructions stored in the memory, wherein the method for high-speed data interaction of the inkjet printer is implemented when the computer program instructions are executed by the processor.

[0027] A storage medium storing computer program instructions, characterized in that a method for high-speed data interaction of the inkjet printer is implemented when the computer program instructions are executed by a processor.

[0028] This invention effectively solves the bandwidth bottleneck problem of traditional data buses by introducing high-speed DRAM as a data buffer and optimizing the data transmission architecture between the MCU and FPGA. This significantly improves the overall system response speed and printing efficiency of digital inkjet printers. By adopting control line multiplexing technology, it ensures that data exchange between the MCU and FPGA can be carried out efficiently and synchronously, significantly reducing data transmission latency, improving the continuity of data flow and the smoothness of the printing process. Through the efficient data exchange mechanism and improved real-time processing capabilities, the printer can better control ink output and printing accuracy, thereby improving the quality of print output and meeting high-end printing needs. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of a high-speed data interaction method for an inkjet printer according to the present invention. Detailed Implementation

[0030] To further illustrate the technical means and effects adopted by the present invention to achieve its intended purpose, exemplary embodiments will be described in detail below, examples of which are illustrated in the accompanying drawings. In the following description relating to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of methods and systems consistent with some aspects of this application as detailed in the appended claims.

[0031] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0032] Example 1

[0033] like Figure 1 The high-speed data interaction method for an inkjet printer according to the present invention is as follows:

[0034] S1 sets up a data buffer between the transmission channels of the FPGA and MCU, which serves as a key hub for data interaction between the two, thereby improving the stability and efficiency of data transmission.

[0035] Preferably, the data buffer is a high-speed DRAM, and the FPGA and MCU interact with the DRAM via multiple control lines; a high-frequency, low-latency DRAM module is used as an intermediate cache. The capacity of the DRAM should be selected according to the printer's data processing requirements, typically between 256MB and 2GB, which can effectively alleviate the bottleneck problem that may be caused by the difference in data transmission rate between the FPGA and MCU, creating a good environment for stable data transmission. Through reasonable hardware connection and circuit design, it is ensured that the DRAM can be accurately connected to the data transmission link between the FPGA and MCU, making it the core hub for data interaction between the two, thereby significantly improving the stability and efficiency of the entire data transmission system.

[0036] S2, MCU initializes the data buffer state. The MCU performs an initialization operation on the data buffer, the core step of which is to thoroughly clear the memory space in the data buffer. During the initialization process, the MCU first performs a full scan of the memory addresses of the data buffer, resetting the content of each memory unit to a preset initial value, usually set to zero or a specific invalid data marker. This operation can effectively clear any historical data, random noise data, or erroneous data generated by system anomalies that may remain in the buffer, minimizing the risk of data transmission errors.

[0037] In step S3, the MCU retrieves a data block from the print task queue and transfers it to the data buffer. The MCU reads the DRAM status and interacts with the DRAM via a specific communication protocol and control signals to obtain the DRAM's current operating status information, including memory cell occupancy and data write readiness status. Only after the DRAM confirms it is ready—that is, has sufficient storage space and its internal circuitry is in a stable writable state—does the MCU officially initiate the data block transmission process. After the data block transmission is complete, the MCU sends another message to the DRAM to explicitly inform it that the data has been completely transmitted. This confirmation message helps the DRAM perform internal data management and status updates, such as marking data storage locations and updating memory cell occupancy information, providing accurate metadata support for subsequent data reading and processing.

[0038] S4. After the transmission in step S3 is completed, the MCU sends a write completion signal to the FPGA via the control line. When the data is successfully transmitted to the data buffer, the MCU sends a write completion signal to the FPGA via the control line. This control line, as an important communication line between the FPGA and the MCU, is responsible for transmitting various control signals and status information. The write completion signal, as a crucial trigger signal, ensures accurate and timely transmission, effectively coordinating the working rhythm of the FPGA and the MCU, notifying the FPGA that the data buffer is ready to be read, thereby triggering subsequent data reading operations on the FPGA, ensuring the continuity and efficiency of the data interaction process.

[0039] S5. After receiving the write completion signal, the FPGA reads data from the data buffer for processing. After receiving the write completion signal from the MCU, the FPGA starts the process of reading data from the data buffer for subsequent processing.

[0040] Before reading data, the FPGA must first send a request signal to the DRAM. This request signal contains specific address information, data volume information, and control instructions for the read operation required by the FPGA. After receiving the request signal from the FPGA, the DRAM first parses and verifies the request information to confirm its legality and validity. Subsequently, the DRAM checks its own operating status and the readiness of the memory cells. Only after confirming that everything is ready will it begin to transmit data to the FPGA according to its requirements. Throughout this process, data is transmitted through carefully designed data lines and interfaces to ensure high-speed and stable data transmission.

[0041] S6. After reading is complete, the FPGA sends a read completion signal to the MCU via the control line to prepare for the next data exchange. This feedback signal serves as a crucial end marker for this data exchange, promptly informing the MCU that the FPGA has successfully acquired the data and completed the relevant processing operations, and that the data buffer is ready to receive new data. This feedback mechanism helps establish a stable data interaction cycle, ensuring continuous and efficient data exchange between the FPGA and the MCU.

[0042] Preferably, the complex control lines specifically include read / write enable lines, address lines, and data lines. The read / write enable line, as a key control signal line for data read / write operations, determines the data transmission direction and operation type based on its level state. When the read / write enable line is in a specific level combination, it can trigger DRAM read or write operations respectively, ensuring data is transmitted at the correct time and in the correct manner. The address lines are responsible for determining the specific storage or read location of data in the DRAM. By sending precise address encoding information on the address lines, the MCU or FPGA can accurately locate specific memory cells in the DRAM, realizing point-to-point read / write operations. The width of the address lines is closely related to the DRAM's storage capacity and addressing mode. A reasonable design of the number of address lines can optimize data transmission efficiency and speed while meeting storage requirements. The data lines bear the actual data transmission task, and their width determines the parallelism and data volume of each data transmission. Wider data lines can transmit more data bits in the same clock cycle, thus significantly improving the data transmission rate. During data transmission, the data lines need to have good electrical characteristics and signal integrity to ensure accurate data transmission and avoid data errors caused by signal interference or attenuation.

[0043] Preferably, a synchronization circuit is added between the MCU and the FPGA, specifically a bistable trigger to construct a synchronizer, with the control signal from the MCU as the input of the synchronizer, and the clock signal of the synchronizer matching the system clock of the FPGA.

[0044] Preferably, in step S2, the MCU initializes the state of the data buffer, specifically by clearing the memory space in the data buffer.

[0045] Preferably, the data buffer further includes the following data processing steps:

[0046] L1: The MCU reads the DRAM status and sends data information to the DRAM. After the DRAM confirms that it is ready, the MCU starts sending data blocks.

[0047] L2: After the MCU finishes sending the data block, it sends information to the DRAM to confirm that the transmission was complete.

[0048] L3, the MCU triggers the synchronization circuit, the FPGA sends a request signal to the DRAM, and after the DRAM confirms that it is ready, it starts sending data to the FPGA;

[0049] The DRAM state includes read and write states, which specifically refers to determining whether the current read and write requirements can be met in the DRAM's storage cells.

[0050] The DRAM also includes multiple levels of cache: Level 1, Level 2, and Level 3 caches. Level 1 and Level 2 caches are for reading and writing, while Level 3 cache is for data transfer. Data exchange between Level 1 and Level 2 caches is handled through Level 3 cache. Level 1 and Level 2 caches, as read / write areas, handle the primary data read / write functions. Level 1 cache typically has a small capacity but extremely high access speed, designed to quickly respond to data read / write requests from the FPGA or MCU, storing the most frequently used data or data blocks about to be processed. Level 2 cache has a relatively large capacity and a slightly lower speed than Level 1 cache, used to cache data overflowing from Level 1 cache due to capacity limitations or less urgent data, balancing storage and access efficiency. Level 3 cache, as the data transfer area, is responsible for data exchange between Level 1 and Level 2 caches. When Level 1 cache needs to exchange data with Level 2 cache, the data is first transferred to Level 3 cache, and then forwarded by Level 3 cache to the target cache. This multi-level caching structure can effectively optimize the data storage and transmission process. Through hierarchical management and dynamic allocation of cached data, it can improve the efficiency and speed of data processing and reduce the latency and performance loss that may be caused by frequent direct access to DRAM storage units.

[0051] Preferably, in the DRAM data processing, read / write tasks are categorized according to their impact on the real-time performance and performance of the printing system. For example, data reading tasks related to real-time printhead control (such as printhead current position, ink level monitoring data reading, etc.) can be classified as high-priority real-time tasks because these data directly affect the continuity and quality of printing; while some read / write tasks used for background print job management or non-critical configuration data can be classified as low-priority tasks. When a task is in the waiting queue, its priority is recalculated periodically (e.g., every 10 milliseconds) according to the above formula. The priority is also updated promptly when a new task is added or the task status changes (e.g., the amount of data increases or the waiting time increases). This ensures that high-priority tasks are processed at the appropriate time, preventing low-priority tasks from occupying resources for extended periods and causing delays in high-priority tasks.

[0052] The MCU continuously monitors the status of the print task queue, including the number of tasks, task priorities, and the amount of data for each task. When multiple tasks exist in the queue and the data for subsequent tasks is ready (e.g., data received from the network has reached a certain amount or local data parsing is complete), the timing for pre-writing is evaluated. For example, if there are three print tasks in the queue, and the data for the second task has been fully received in the local buffer, while the first task is transferring data to DRAM and has transferred more than 50%, pre-writing the data for the second task can be considered, analyzing the task priority distribution. If a high-priority task is about to complete and a low-priority task has a large amount of data, pre-writing the low-priority task should be prioritized during the final stage of the high-priority task, so that the processing of the low-priority task can be quickly switched after the high-priority task is completed, reducing the overall task switching time. For example, if a high-priority text print task is about to end, while a low-priority image print task has a large amount of data, the image print task's data can be pre-written to DRAM during the last few lines of data transmission in the text print task. The system's resource utilization is monitored in real time, including CPU utilization, data bus bandwidth utilization, and DRAM free space. A pre-write operation is triggered when system resource utilization is relatively low, such as CPU utilization below 60%, data bus bandwidth utilization below 70%, and DRAM free space greater than 1.5 times the amount of data to be pre-written. This ensures that the pre-write operation does not compete for resources with other ongoing critical tasks, avoiding system performance degradation and considering data transmission stability. If there are no errors or delays in the current data transmission, and the system clock signal is stable and not subject to external interference, then a pre-write operation can be performed if resource conditions are met. For example, by monitoring the error check code of the data transmission (such as the CRC check result), if multiple consecutive check results are correct and the system clock jitter is within the allowable range, pre-write can be initiated.

[0053] Preferred,

[0054] The amount of data to be prewritten is dynamically adjusted based on the available space in the DRAM. First, the current free space size of the DRAM is obtained. Then, a prewrite ratio is determined based on the system load and the urgency of subsequent tasks. For example, if the DRAM free space is 500MB, the system load is light, and the subsequent tasks are of medium priority, the prewrite ratio can be set to 0.3, resulting in 150MB of data to be prewritten. However, to ensure that there is still enough space in the DRAM after prewriting for other tasks (such as FPGA data read operations), 20%-30% of the free space is generally reserved as a buffer.

[0055] Consider the integrity of data blocks. Prewrite data in complete blocks whenever possible, avoiding splitting a data block across multiple prewrite operations. For example, if printed data is organized as pixel rows of an image or paragraphs of text, each prewrite should ensure a complete pixel row or paragraph. This reduces the processing complexity for the FPGA during subsequent data reading and improves data processing efficiency.

[0056] Frequency control

[0057] Set a minimum time interval threshold, such as 10 milliseconds, and ensure that there is at least this threshold interval between two pre-write operations. This prevents excessive pre-write operations from causing excessive consumption of system resources and data transmission chaos. Adjust this threshold according to the urgency of the task and the size of the data. For urgent tasks with small data volumes, the threshold time can be shortened appropriately, but it should not be lower than the minimum value that allows the system to operate stably, such as 5 milliseconds; for non-urgent tasks with large data volumes, the threshold time can be extended to 20 milliseconds or even longer.

[0058] Frequency control is implemented based on the data transmission rate. If the current data transmission rate is high, indicating sufficient system bandwidth resources, the pre-write frequency can be appropriately increased, provided other conditions are met. Conversely, if the data transmission rate is slow, the pre-write frequency should be reduced to ensure overall system stability. For example, when the data transmission rate is higher than 100MB / s, the pre-write frequency can be once every 8 milliseconds; when the transmission rate is lower than 50MB / s, the pre-write frequency is adjusted to once every 15 milliseconds.

[0059] Error handling and recovery

[0060] During the pre-write process, each data block undergoes error checking, such as using CRC or ECC checksums. If an error is detected, the pre-write operation is immediately stopped, and the data block is marked as faulty. Simultaneously, the decision to perform data recovery operations is made based on the type and severity of the error. For correctable errors, such as single-bit errors that ECC can handle, an attempt can be made to correct the error in place before continuing the pre-write operation. For uncorrectable errors, such as severely corrupted data blocks, the data block needs to be retrieved again, possibly by downloading it from the network or reading it from local storage, before the pre-write operation is performed again.

[0061] Establish an error logging mechanism to record error information occurring during the pre-write process, including error type, time of occurrence, and location of the erroneous data block. Regularly analyze these error logs to optimize parameter settings and data processing flow for the pre-write operation, improving its reliability and stability. For example, if a specific type of task frequently encounters errors during pre-write, it may be a data format conversion issue; optimize the data format conversion module for that task to reduce the probability of errors.

[0062] A device for high-speed data interaction of an inkjet printer includes at least one processor, at least one memory, and computer program instructions stored in the memory, wherein the method for high-speed data interaction of the inkjet printer is implemented when the computer program instructions are executed by the processor.

[0063] A storage medium storing computer program instructions, characterized in that a method for high-speed data interaction of the inkjet printer is implemented when the computer program instructions are executed by a processor.

[0064] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A high-speed data interaction method for an inkjet printer, characterized in that, Includes the following steps: S1 sets up a data buffer between the transmission channels of the FPGA and MCU, which serves as a key hub for data interaction between the two, thereby improving the stability and efficiency of data transmission. The data buffer is specifically a high-speed DRAM. The FPGA and MCU interact with the DRAM through multiple control lines. A high-frequency, low-latency DRAM module is used as an intermediate cache. The capacity of the DRAM should be selected according to the printer's data processing requirements, between 256MB and 2GB, to ensure that the DRAM can access the data transmission link between the FPGA and the MCU. S2, MCU initializes the state of the data buffer. The core step of the MCU initialization operation is to thoroughly clear the memory space in the data buffer. During the initialization process, the MCU first performs a full scan of the memory address of the data buffer and resets the content of each memory unit to a preset initial value, usually set to zero or a specific invalid data mark. S3, the MCU retrieves a data block from the print task queue and transmits the data block to the data buffer. The MCU reads the DRAM status and interacts with the DRAM through a specific communication protocol and control signals to obtain the current working status information of the DRAM, including the occupancy of the memory cells and the readiness status for data writing. After confirming that the DRAM is ready, the MCU starts the data block sending process. After the data block is sent, the MCU sends information to the DRAM again. This information is used to clearly inform the DRAM that the data has been completely sent. S4. After the transmission in step S3 is completed, the MCU sends a write completion signal to the FPGA through the control line. When the data is successfully transmitted to the data buffer, the MCU sends a write completion signal to the FPGA through the control line. This control line is an important communication line between the FPGA and the MCU, responsible for transmitting various control signals and status information. The write completion signal is a key trigger signal. Its accurate and timely transmission can effectively coordinate the working rhythm of the FPGA and the MCU, notify the FPGA that the data buffer is ready to be read, thereby triggering the subsequent data reading operation of the FPGA, ensuring the continuity and efficiency of the data interaction process. S5. After receiving the write completion signal, the FPGA reads data from the data buffer for processing. After receiving the write completion signal from the MCU, the FPGA starts the process of reading data from the data buffer for subsequent processing. Before reading data, the FPGA needs to send a request signal to the DRAM. This request signal contains the specific address information, data volume information, and control instructions for the read operation of the data required by the FPGA. After receiving the request signal from the FPGA, the DRAM first parses and verifies the request information to confirm the legality and validity of the request. Then, the DRAM checks its own working status and the readiness of the storage unit. After confirming that it is ready, it transmits the data to the FPGA according to the requirements of the FPGA. S6. After the data reading is completed, the FPGA sends a read completion signal back to the MCU via the control line to prepare for the next data exchange. In step S2, the MCU initializes the state of the data buffer, specifically by clearing the memory space in the data buffer. The data buffer also includes the following data processing steps: L1: The MCU reads the DRAM status and sends data information to the DRAM. After the DRAM confirms that it is ready, the MCU starts sending data blocks. L2: After the MCU finishes sending the data block, it sends information to the DRAM to confirm that the transmission was complete. L3, the MCU triggers the synchronization circuit, the FPGA sends a request signal to the DRAM, and after the DRAM confirms that it is ready, it starts sending data to the FPGA; The DRAM state includes read and write states, which specifically refers to determining whether the current read and write requirements can be met in the DRAM's storage cells. The DRAM is further equipped with multiple levels of cache, namely a level 1 cache, a level 2 cache, and a level 3 cache. The level 1 and level 2 caches are read / write areas, while the level 3 cache is a data transmission area. Data exchange between the level 1 and level 2 caches is transmitted through the level 3 cache. The level 1 and level 2 caches, as read / write areas, undertake the main data read / write functions. The level 1 cache has a small capacity but extremely high access speed, quickly responding to data read / write requests from the FPGA or MCU, and storing the most frequently used data or data blocks that are about to be processed. The level 2 cache has a relatively large capacity but a lower speed than the level 1 cache. It is used to cache data that overflows from the level 1 cache due to capacity limitations or relatively non-urgent data, in order to balance data storage and access efficiency. The level 3 cache, as a data transmission area, is responsible for data exchange and transmission between the level 1 and level 2 caches. When the level 1 cache needs to exchange data with the level 2 cache, the data is first transmitted to the level 3 cache, and then forwarded by the level 3 cache to the target cache. In the data processing of the DRAM, read and write tasks are classified according to their impact on the real-time performance and performance of the printing system. Data reading tasks related to the real-time control of the printhead are classified as high-priority real-time tasks, while read and write tasks used for background print task management or non-critical configuration data are classified as low-priority tasks. Read and write tasks are classified according to their impact on the real-time performance and performance of the printing system. Data reading tasks related to real-time printhead control are classified as high-priority real-time tasks, while read and write tasks used for background print task management or non-critical configuration data are classified as low-priority tasks. The priority is also updated in a timely manner when a new task is added or the task status changes. The MCU continuously monitors the status of the print task queue, including the number of tasks, task priorities, and the data volume of each task. When there are multiple tasks in the queue and the data for subsequent tasks is ready, it begins to evaluate the timing of pre-writing. If there are three print tasks in the queue, and the data for the second task has been completely received in the local buffer, while the first task is transferring data to DRAM and has transferred more than 50%, then the data for the second task is pre-written. The MCU analyzes the task priority distribution. If a high-priority task is about to complete and a low-priority task has a large data volume, the low-priority task is pre-written first during the final stage of the high-priority task. This allows for a quick switch to the low-priority task after the high-priority task is completed, reducing overall task switching time. If a high-priority text print task is about to finish, while a low-priority image print task has a large data volume, the image print task's data is pre-written to DRAM when the last line of data is being transferred from the text print task. The MCU also monitors system resource utilization in real time, including CPU utilization, data bus bandwidth utilization, and DRAM free space. When system resource utilization is relatively low (i.e., CPU utilization below 60%, data bus bandwidth utilization below 70%, and DRAM free space is low), the MCU will pre-write the data. When the free space is greater than 1.5 times the amount of data to be prewritten, the prewrite operation is triggered. If there are no errors or delays in the current data transmission, and the system clock signal is stable and not affected by external interference, then the prewrite operation is performed if the resource conditions are met. By monitoring the error check code of the data transmission, if the check result is correct and the jitter of the system clock is within the allowable range, the prewrite can be started. The amount of data to be prewritten is dynamically adjusted based on the free space of DRAM. First, the current free space size of DRAM is obtained. Then, a prewrite ratio coefficient is determined based on the system load and the urgency of subsequent tasks. However, it is necessary to ensure that there is still enough space in DRAM after prewriting for other tasks to run normally. 20% - 30% of the free space is reserved as a buffer. If the printed data is organized in the form of pixel lines of images or paragraphs of text, each prewrite ensures that it is a complete pixel line or paragraph. Set a minimum time interval threshold. There must be at least this threshold time interval between two pre-write operations. Adjust this threshold according to the urgency of the task and the amount of data. For urgent tasks with small data volume, shorten the threshold time appropriately, but it cannot be lower than the minimum value that the system can run stably. For non-urgent tasks with large data volume, extend the threshold time to 20 milliseconds or more. Frequency control is implemented based on the data transfer rate. If the current data transfer rate is high, the pre-write frequency is increased; conversely, if the data transfer rate is slow, the pre-write frequency is decreased to ensure the overall stability of the system. When the data transfer rate is higher than 100MB / s, the pre-write frequency is once every 8 milliseconds; when the data transfer rate is lower than 50MB / s, the pre-write frequency is adjusted to once every 15 milliseconds. During the pre-write process, each data block undergoes error checking using either CRC or ECC check. If an error is detected, the pre-write operation is immediately stopped, and the data block is marked as faulty. Simultaneously, based on the type and severity of the error, a decision is made regarding whether to perform data recovery. For correctable errors, an attempt is made to correct the error in place before continuing the pre-write process. For uncorrectable errors, the data is re-downloaded from the network or re-read from local storage before the pre-write operation is performed again. Establish an error logging mechanism to record error information that occurs during the pre-write process, including error type, time of error occurrence, and location of the erroneous data block. Analyze the error logs periodically to optimize parameter settings and data processing flow for the pre-write operation, thereby improving its reliability and stability. If multiple errors are found during pre-write, optimize the data format conversion module for that task to reduce the probability of errors.

2. The high-speed data interaction method for an inkjet printer according to claim 1, characterized in that, A synchronization circuit is added between the MCU and the FPGA. Specifically, a synchronizer is constructed by using bistable triggers. The control signal from the MCU is used as the input of the synchronizer, and the clock signal of the synchronizer is matched with the system clock of the FPGA.

3. A device for high-speed data interaction of an inkjet printer, comprising at least one processor, at least one memory, and computer program instructions stored in the memory, wherein the computer program instructions, when executed by the processor, implement the method described in any one of claims 1-2.

4. A storage medium storing computer program instructions thereon, characterized in that, When computer program instructions are executed by a processor, the method described in any one of claims 1-2 is implemented.

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