Method and device for improving stability of FPGA code stream data

Abstract

The invention discloses a method and a device for improving the stability of FPGA code stream data, which can reduce the condition of error of the code stream data, reduce the harm of code stream error to the FPGA, and are relatively simple in application condition and relatively low in hardware requirement. The method comprises the following steps: (1) splitting code stream data into N data blocks with the length of M according to requirements; (2) a check value is calculated according to each data block, the check value of the first data block is calculated from an initial value FFFFFFF, and then the check value of each data block is obtained through continuous calculation on the basis of the check value calculated from the previous data block; (3) placing the verification value behind the calculated data block; (4) during FPGA verification, the verification value is compared with the verification value calculated by the current configuration data, the verification value is discarded after comparison is completed, and the verification value behind each data block is used for verifying all data from the initial data block to the current data block.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a method for improving the stability of FPGA code stream data, and a device for improving the stability of FPGA code stream data. Background Art

[0002] With the rapid development of chip technology, the scale of field programmable gate arrays (FPGA) continues to expand, and internal resources continue to be enriched. The unique programmable characteristics of SRAM-type FPGA chips have higher flexibility and higher performance than single-chip microcomputers, and can complete higher-demand tasks in many application scenarios.

[0003] There are two steps for FPGA chips to work as expected. First, the FPGA EDA tool synthesizes the user circuit, lays out the wiring, and generates a bit stream file (code stream file) that the FPGA can recognize. Second, the user configures the data of the bit stream file into the FPGA through the FPGA configuration IO port. Only the correct code stream file can make the FPGA work properly. Therefore, as long as there is a problem with the code stream data, the FPGA is likely to fail to work.

[0004] There are many ways to configure the bitstream of FPGA chips. Taking Xilinx as an example, it supports passive serial, passive parallel, active serial, active parallel, j1tag, spi master and other configuration methods. For the spi mst configuration mode, an external flash is generally connected. In some cases, the flash may be erased by mistake, causing part of the bitstream data to become FF or other values ​​unrelated to the bitstream. In other modes, it may also be due to virtual connection or environmental interference, causing part of the bitstream data to become FF. The current bitstream format is CRAM address + all CRAM data, and BRAM address + all BRAM data, followed by a CRC check. If the above situation occurs, FF or irrelevant values ​​will appear in the bitstream. In worse cases, the content of the FPGA's CRAM data will mostly be FF or unknown values, which may cause great harm to the FPGA hardware or even a short circuit.

[0005] When FPGA is in plateau, low orbit, or space, SRAM FPGA will have single event upset (SEU), which will cause unexpected situations in user circuits. Therefore, FPGA needs error correction (ECC, Error Correction Code) circuit or refresh (by configuring the original bit stream data at intervals of the interface to ensure that the bit stream data is constantly updated) to correct the SEU errors. The most common SEU is implemented based on Hamming code, which supports up to 2 bits of detection and 1 bit of correction. If it exceeds this, it cannot detect and correct errors. Summary of the invention

[0006] In order to overcome the defects of the prior art, the technical problem to be solved by the present invention is to provide a method for improving the stability of FPGA code stream data, which can reduce the occurrence of errors in code stream data and reduce the harm of code stream errors to FPGA. The application conditions are relatively simple and the hardware requirements are low.

[0007] The technical solution of the present invention is: the method for improving the stability of FPGA code stream data comprises the following steps: (1) Split the code stream data into N data blocks of length M according to the requirements; (2) Calculate the checksum for each data block. The checksum for the first data block is calculated starting from the initial value FFFFFFFF. The checksum for each subsequent data block is calculated based on the checksum calculated for the previous data block. (3) Put the checksum value after the calculated data block; (4) When the FPGA is verified, the verification value is compared with the verification value calculated from the current configuration data and discarded after the comparison is completed. The verification value after each data block is a verification of all data from the initial data block to the current data block.

[0008] The beneficial technical effects of the present invention are as follows: 1. The method described in the present invention can effectively avoid problems such as high current and circuit caused by the writing of a large range of unexpected data into the hardware circuit: In the present invention, each data block will have an independent address. If unexpected data appears, it is very likely that the address will also be modified, so that the remaining part will not be recognized. Secondly, there will be a CRC check before every two data blocks. If an error occurs, a CRC error will also be reported, thereby preventing subsequent erroneous data from being written into the FPGA.

[0009] 2. The splitting described in the present invention is very flexible: the splitting of the code stream in the present invention is not fixed. For any scale, it only needs to be split according to the corresponding situation. No complex algorithm is used to limit the splitting. The CRC check commonly used in FPGA is also used.

[0010] 3. The supplement to ECC described in the present invention: The method in the present invention adds block CRC to perform verification on the basis of traditional Hamming code, thereby reducing the situation where ECC cannot detect errors.

[0011] 4. The method of the present invention is simple to implement: the method of the present invention is only based on splitting CRAM data and adding block CRC to achieve data stability, and the algorithm is simple.

[0012] A device for improving the stability of FPGA code stream data is also provided, comprising: A code stream data splitting module, which is configured to split the code stream data into N data blocks of length M according to requirements; A calculation module is configured to calculate a checksum value for each data block. The checksum value for the first data block is calculated starting from an initial value of FFFFFFFF. The checksum value for each subsequent data block is calculated based on the checksum value calculated for the previous data block. A placement module configured to place the checksum after the calculated data block; The check module, when its configuration is used to check the FPGA, compares the check value with the check value calculated by the current configuration data, and discards it after the comparison is completed. The check value after each data block is the check of all data from the initial data block to the current data block. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 The process of generating code stream in the prior art is shown.

[0014] Figure 2 A flow chart of a method for improving FPGA code stream data stability according to the present invention is shown. DETAILED DESCRIPTION

[0015] In the process of FPGA generating configuration code stream, address + data length + data of corresponding length are generally used to read and write FPGA registers. Figure 1 As shown, the corresponding CRAM and BRAM data are generated according to the user circuit, and then the two parts of data are added with the corresponding addresses of CRAM and BRAM respectively, and finally combined with the user settings to form the final code stream. If encryption is required, it only needs to be encrypted based on the final code stream. In the above case, there will be a problem. As long as the FPGA recognizes the address of the CRAM and the corresponding data length, if an error occurs somewhere in the data, all data starting from the error will be configured into the FPGA.

[0016] exist Figure 2In the present invention, the CRAM data is split into N blocks of M-length data according to different requirements, and then whether to add CRC check in two blocks of data according to the requirements, and these are combined into a new CRAM data stream with a structure of address + M length + M-length data + (CRC address + length 1 + check value) address + M length + M-length data + (CRC address + length 1 + check value)... In this way, in the first case, the CRAM data becomes FF from somewhere, and at most only M-length erroneous data will be configured, because the FPGA will not recognize the address of the next block, and the harm caused is also relatively controllable; in the second case, the CRAM data is flipped from the interference received part, and the CRC between blocks can detect the problem, and it will not cause too much unexpected data to be configured.

[0017] Specifically, the method for improving the stability of FPGA code stream data includes the following steps: (1) Split the code stream data into N data blocks of length M according to the requirements; (2) Calculate the checksum for each data block. The checksum for the first data block is calculated starting from the initial value FFFFFFFF. The checksum for each subsequent data block is calculated based on the checksum calculated for the previous data block. (3) Put the checksum value after the calculated data block; (4) When the FPGA is verified, the verification value is compared with the verification value calculated from the current configuration data and discarded after the comparison is completed. The verification value after each data block is a verification of all data from the initial data block to the current data block.

[0018] The beneficial technical effects of the present invention are as follows: 1. The method described in the present invention can effectively avoid problems such as high current and circuit caused by the writing of a large range of unexpected data into the hardware circuit: In the present invention, each data block will have an independent address. If unexpected data appears, it is very likely that the address will also be modified, so that the remaining part will not be recognized. Secondly, there will be a CRC check before every two data blocks. If an error occurs, a CRC error will also be reported, thereby preventing subsequent erroneous data from being written into the FPGA.

[0019] 2. The splitting described in the present invention is very flexible: the splitting of the code stream in the present invention is not fixed. For any scale, it only needs to be split according to the corresponding situation. No complex algorithm is used to limit the splitting. The CRC check commonly used in FPGA is also used.

[0020] 3. The supplement to ECC described in the present invention: The method in the present invention adds block CRC to perform verification on the basis of traditional Hamming code, thereby reducing the situation where ECC cannot detect errors.

[0021] 4. The method of the present invention is simple to implement: the method of the present invention is only based on splitting CRAM data and adding block CRC to achieve data stability, and the algorithm is simple.

[0022] Preferably, in step (1), when stability check is required, each data block is set to 10-99 words. However, in this case, more blocks will be split, and the CRC check value that needs to be added later will increase, which will increase the size of the code stream.

[0023] Preferably, in step (1), when the code stream size is required, the number of splits is set to 1-9. This will increase the amount of data much less, and errors can be detected more quickly, preventing more erroneous data from being written.

[0024] Preferably, the code stream data in step (1) is CRAM data.

[0025] Preferably, the code stream data in step (1) is ECC data. This method is also applicable to ECC calculation. In the ECC of FPGA, all data will not be subjected to ECC calculation only once, but will be split into multiple identical blocks according to the hardware circuit, and ECC will be performed one by one in sequence. This is consistent with the first step of this method. Traditionally, when using Hamming code for ECC, more than 2 bits will not be detected (other algorithms also have the same method). According to the second step of this method, the check value of each ECC block can be calculated (including the check bit also participating in CRC), and the CRC is placed in BRAM during coding. BRAM turns on its own ECC function to ensure that the block check value in BRAM remains unchanged to the greatest extent. The check value of this data block is calculated at the same time during the ECC detection and error correction process. Finally, after error correction, it is compared with the CRC in BRAM. If it is consistent, it proves that there is no problem with local error detection and error correction. Then, the corrected data is rewritten into FPGA. If it is inconsistent, ECC is stopped and reported to the user, proving that an error of more than 2 bits has occurred.

[0026] This method is basically software processing. Except for the ECC part, it does not require high hardware. It only processes the bitstream data format and is more convenient to use. Compared with the basic bitstream, the CRC check based on the number of blocks is added, which can detect bitstream errors and attacks earlier. The corresponding processing can be added to the hardware, and the FPGA has a more comprehensive check on the bitstream.

[0027] Alternatively, in step (2), if the CRC of each block is independent of the CRC of the previous block, each CRC is calculated starting from the initial value FFFFFFFF. In this way, if any block of data is lost, it will not affect the configuration of the next block because the check values ​​are unrelated to each other.

[0028] In the step (3), taking CRC32 as an example, CRC can be placed between blocks. FPGA only needs to compare the check value with the check value calculated by the current configuration data. After the comparison, it can be discarded and does not need to be stored. The check value after each block is a check of all data from the initial block to the current block. The CRC just calculated can also be used as part of the key of the next data block. The following is an encryption method based on the combination of rolling keys and this method. The key is more complex and more difficult to crack. Taking AES128-ECB as an example, the check value of the first block is used as part of the key of the second encrypted block. Normally, the rolling key will put all the 128-bit keys of the second segment in the first segment. As long as someone knows where the 128 bits are, it may be cracked. Based on this method, only 96 bits need to be put in, and the remaining 32 bits are the check value of the first segment. For the traditional rolling key, if part of the code stream is modified, as long as the key part is not modified, it will not affect the normal decryption of the next segment; for the encryption method described in this method, as long as any 1 bit is modified, the CRC of the corresponding block changes, and the key used to decrypt the next block will also change, so that the subsequent decryption fails. Therefore, it is safer than the ordinary one.

[0029] Those skilled in the art can understand that all or part of the steps in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes the steps of the above-mentioned embodiment method, and the storage medium can be: ROM / RAM, disk, optical disk, memory card, etc. Therefore, corresponding to the method of the present invention, the present invention also includes a device for improving the stability of FPGA code stream data, which is usually represented in the form of functional modules corresponding to the steps of the method. The device includes: A code stream data splitting module, which is configured to split the code stream data into N data blocks of length M according to requirements; A calculation module is configured to calculate a checksum value for each data block. The checksum value for the first data block is calculated starting from an initial value of FFFFFFFF. The checksum value for each subsequent data block is calculated based on the checksum value calculated for the previous data block. A placement module configured to place the checksum after the calculated data block; The check module, when its configuration is used to check the FPGA, compares the check value with the check value calculated by the current configuration data, and discards it after the comparison is completed. The check value after each data block is the check of all data from the initial data block to the current data block.

[0030] Preferably, in the code stream data splitting module, when data checking for stability is required, each data block is set to 10-99 words.

[0031] Preferably, in the code stream data splitting module, when the code stream size is required, the number of splits is set to 1-9.

[0032] Preferably, in the code stream data splitting module, the code stream data is CRAM data.

[0033] Preferably, in the code stream data splitting module, the code stream data is ECC data.

[0034] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Any simple modification, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention are still within the protection scope of the technical solution of the present invention.

Claims

1. A method for improving the stability of FPGA code stream data, characterized in that: It includes the following steps: (1) Split the code stream data into N data blocks of length M according to the requirements; (2) Calculate the checksum for each data block. The checksum for the first data block is calculated starting from the initial value FFFFFFFF. The checksum for each subsequent data block is calculated based on the checksum calculated for the previous data block. (3) Put the checksum value after the calculated data block; (4) When the FPGA is verified, the verification value is compared with the verification value calculated from the current configuration data and discarded after the comparison is completed. The verification value after each data block is a verification of all data from the initial data block to the current data block.

2. The method for improving the stability of FPGA code stream data according to claim 1, characterized in that: In the step (1), when data checking for stability is required, each data block is set to 10-99 words.

3. The method for improving the stability of FPGA code stream data according to claim 1, characterized in that: In the step (1), when the bitstream size is required, the number of splits is set to 1-9.

4. The method for improving the stability of FPGA code stream data according to any one of claims 1 to 3, characterized in that: The code stream data in step (1) is CRAM data.

5. The method for improving the stability of FPGA code stream data according to claim 1, characterized in that: The code stream data in step (1) is ECC data.

6. A device for improving the stability of FPGA code stream data, the device being used to execute the method according to claim 1, characterized in that: The device includes: A code stream data splitting module, which is configured to split the code stream data into N data blocks of length M according to requirements; A calculation module is configured to calculate a checksum value for each data block. The checksum value for the first data block is calculated starting from an initial value of FFFFFFFF. The checksum value for each subsequent data block is calculated based on the checksum value calculated for the previous data block. A placement module configured to place the checksum after the calculated data block; The check module, when its configuration is used to check the FPGA, compares the check value with the check value calculated by the current configuration data, and discards it after the comparison is completed. The check value after each data block is the check of all data from the initial data block to the current data block.

7. The device for improving the stability of FPGA code stream data according to claim 6, characterized in that: In the code stream data splitting module, when data checking for stability is required, each data block is set to 10-99 words.

8. The device for improving the stability of FPGA code stream data according to claim 6, characterized in that: In the code stream data splitting module, when the code stream size is required, the number of splits is set to 1-9.

9. The device for improving the stability of FPGA code stream data according to any one of claims 6 to 8, characterized in that: In the code stream data splitting module, the code stream data is CRAM data.

10. The device for improving FPGA code stream data stability according to claim 6, characterized in that: In the code stream data splitting module, the code stream data is ECC data.

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