Signal quality evaluation method based on edge sampling value

Abstract

The invention relates to chip design, in particular to a signal quality evaluation method based on an edge sampling value, and the method comprises the steps: receiving data information and edge information output by a high-speed serial-parallel transceiver SERDES through a signal quality evaluation module; searching various code patterns representing different frequencies according to the data information; edge sampling values corresponding to all code patterns are obtained from the edge information, and the number of the edge sampling values corresponding to various code patterns is counted; calculating a quality factor according to the number of the edge sampling values corresponding to each code pattern; determining the quality of a filtered analog signal output by an analog front end (AFE) in a high-speed serial-parallel transceiver SERDES according to the quality factor; according to the technical scheme provided by the invention, the defect that the quality of the filtered analog signal output by the analog front end (AFE) in a high-speed serial-parallel transceiver SERDES is difficult to effectively quantify and evaluate in the prior art can be effectively overcome.

Description

Technical Field

[0001] The invention relates to chip design, and in particular to a signal quality evaluation method based on edge sampling values. Background Art

[0002] The receiving end structure of the existing high-speed serial-parallel transceiver SERDES is as follows Fig.11 As shown, the analog front end AFE (AnalogFrontEnd) is responsible for filtering and shaping the input analog signal, and then sending it to the sampler SLICER for sampling and quantization to obtain a logic signal (binary 0 and 1), and then sending it to the clock data recovery CDR (Clock Data Recovery) for processing. The clock data recovery CDR is responsible for recovering the data and clock, and sending the clock as a sampling clock to the sampler SLICER for sampling data. Finally, the clock data recovery CDR outputs data information and edge information to the subsequent circuit for processing.

[0003] During the receiving process, the clock data recovery (CDR) will dynamically adjust the phase of the sampling clock according to the situation so that the sampling clock phase is always close to the optimal sampling phase. The principle is as follows: Figures 12 to 15 As shown:

[0004] S1 and S3 are data sampling ( Fig.11 The source of data information), S2 is edge sampling ( Fig.11 The source of the mid-edge information);

[0005] Fig.12 The situation that occurs in is S1≠S3 and S2=S3, indicating that the sampling clock phase is lagging behind. At this time, the clock data recovery CDR needs to advance the sampling clock phase;

[0006] Fig.13 The situation that occurs in is S1≠S3 and S2=S1, indicating that the sampling clock phase is ahead. At this time, the clock data recovery CDR needs to delay the sampling clock phase;

[0007] Fig.14 The situation that occurs in is S1=S3, indicating that the signal has no flip. At this time, the clock data recovery CDR needs to maintain the sampling clock phase;

[0008] Fig.15 What is described in FIG. 1 is that after multiple sampling clock phase adjustments, the clock data recovery CDR finally finds the optimal sampling phase.

[0009] Due to the influence of jitter, Figures 12 to 15The situations described in the previous section will continue to occur, and the clock data recovery (CDR) needs to dynamically adjust the phase of the sampling clock according to the situation, in order to ensure that the initial phase of the sampling clock is always close to the optimal sampling phase.

[0010] The receiving end of the high-speed serial-to-parallel transceiver SERDES needs to ensure that the data is correctly received under a certain bit error rate requirement, in which the ability of the analog front end AFE to filter and shape the input analog signal plays a crucial role. How to evaluate the quality of the filtered analog signal output by the analog front end AFE, there is currently a lack of an intuitive and easy-to-implement mechanism. Summary of the invention

[0011] 1. Technical issues to be solved

[0012] In view of the above-mentioned shortcomings of the prior art, the present invention provides a signal quality evaluation method based on edge sampling values, which can effectively overcome the defect of the prior art that it is difficult to effectively quantify and evaluate the quality of the filtered analog signal output by the analog front end AFE in the high-speed serial-to-parallel transceiver SERDES.

[0013] (II) Technical solution

[0014] To achieve the above objectives, the present invention is implemented through the following technical solutions:

[0015] A signal quality assessment method based on edge sampling values ​​comprises the following steps:

[0016] S1, using the signal quality evaluation module to receive data information and edge information output by the high-speed serial-to-parallel transceiver SERDES;

[0017] S2. Searching for various code types representing different frequencies according to the data information;

[0018] S3, obtaining edge sampling values ​​corresponding to all code types from the edge information, and counting the number of edge sampling values ​​corresponding to each code type;

[0019] S4, calculating the quality factor according to the number of edge sampling values ​​corresponding to each type of code;

[0020] S5. Determine the quality of the filtered analog signal output by the analog front end AFE in the high-speed serial-to-parallel transceiver SERDES according to the quality factor.

[0021] Preferably, in S2, various code types representing different frequencies are searched according to the data information, including:

[0022] Search for a preset number of binary patterns that represent high frequencies: 010, 101;

[0023] Searching for a preset number of binary codes representing sub-high frequencies: 0110, 1001;

[0024] Search for a preset number of binary codes representing the intermediate frequency: 01110, 10001;

[0025] Search for a preset number of binary codes representing the second lowest frequency: 011110, 100001;

[0026] Search for a preset number of binary patterns that represent low frequencies: 0111110, 1000001.

[0027] Preferably, in S3, edge sampling values ​​corresponding to all code types are obtained from the edge information, and the number of edge sampling values ​​corresponding to each type of code type is counted, including:

[0028] S31, obtaining edge sampling values ​​corresponding to all code patterns from the edge information, that is, binary 0 or 1;

[0029] S32, counting the number of 0s and 1s corresponding to various code types, and recording them as CNTH0 and CNTH1, CNTSH0 and CNTSH1, CNTM0 and CNTM1, CNTSL0 and CNTSL1, CNTL0 and CNTL1 respectively;

[0030] Among them, CNTH0 and CNTH1 are the number of 0 and 1 corresponding to the binary code representing the high frequency, CNTSH0 and CNTSH1 are the number of 0 and 1 corresponding to the binary code representing the second high frequency, CNTM0 and CNTM1 are the number of 0 and 1 corresponding to the binary code representing the medium frequency, CNTSL0 and CNTSL1 are the number of 0 and 1 corresponding to the binary code representing the second low frequency, and CNTL0 and CNTL1 are the number of 0 and 1 corresponding to the binary code representing the low frequency;

[0031] The sum of the number of 0s and 1s corresponding to each type of code is equal to the number of each type of code.

[0032] Preferably, for CNTH0 and CNTH1 representing the number of 0 and 1 corresponding to the binary code type 010 representing high frequency:

[0033] When the phase of the sampling clock dynamically adjusted by the clock data recovery (CDR) in the high-speed serial-to-parallel transceiver SERDES is at the optimal sampling phase, the probability of 0 and 1 appearing is equal;

[0034] When the phase of the sampling clock dynamically adjusted by the clock data recovery CDR in the high-speed serial-to-parallel transceiver SERDES is ahead of the optimal sampling phase, the probability of 1 appearing is greater than the probability of 0 appearing, and the statistical result is CNTH1>CNTH0;

[0035] When the phase of the sampling clock dynamically adjusted by the clock data recovery CDR in the high-speed serial-to-parallel transceiver SERDES lags behind the optimal sampling phase, the probability of 0 appearing is greater than the probability of 1 appearing, and the statistical result is CNTH0>CNTH1.

[0036] Preferably, in S4, the quality factor is calculated according to the number of edge sampling values ​​corresponding to each type of code pattern, including:

[0037] S41, calculate the maximum value FOM_MAX of the quality factor FOM, the maximum value FOM_MAX of the quality factor FOM is the sum of the number of various types of code:

[0038] FOM_MAX=(CNTH0+CNTH1)+(CNTSH0+CNTSH1)+(CNTM0+CNTM1)+(CNTSL0+CNTSL1)+(CNTL0+CNTL1);

[0039] S42. Calculate the quality factor FOM:

[0040] FOM=FOM_MAX-|CNTH0-CNTH1|-|CNTSH0-CNTSH1|-|CNTM0-CNTM1|-|CNTSL0-CNTSL1|-|CNTL0-CNTL1|.

[0041] Preferably, determining the quality of the filtered analog signal output by the analog front end AFE in the high-speed serial-to-parallel transceiver SERDES according to the quality factor in S5 includes:

[0042] According to the calculation formula of quality factor FOM in S42:

[0043] When the difference between the number of 0s and 1s corresponding to each type of code is smaller, the quality factor FOM is larger, which means that the quality of the filtered analog signal output by the analog front end AFE in the high-speed serial-parallel transceiver SERDES is better;

[0044] When the difference between the number of 0s and 1s corresponding to each type of code is larger, the quality factor FOM is smaller, which means that the quality of the filtered analog signal output by the analog front end AFE in the high-speed serial-to-parallel transceiver SERDES is worse.

[0045] (III) Beneficial effects

[0046] Compared with the prior art, the signal quality evaluation method based on edge sampling values ​​provided by the present invention only adds a signal quality evaluation module to the receiving end circuit of the existing high-speed serial-to-parallel transceiver SERDES. From the hardware structure point of view, the modification is small and easy to implement. At the same time, by calculating the quality factor FOM, it can realize the effective quantitative evaluation of the quality of the filtered analog signal output by the analog front end AFE in the high-speed serial-to-parallel transceiver SERDES. The quality factor FOM can intuitively reflect the quality of the signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0048] Figure 1 It is a schematic diagram of the process of the present invention;

[0049] Figure 2 It is a schematic diagram of the hardware structure of the present invention;

[0050] Figures 3 to 7 A schematic diagram of binary code types representing different frequencies in the present invention;

[0051] Figures 8 to 10 This is a schematic diagram of edge sampling of the binary code type 010 representing high frequency in the present invention;

[0052] Fig.11 The schematic diagram of the receiving end structure of the existing high-speed serial-parallel transceiver SERDES is as follows:

[0053] Figures 12 to 15 Schematic diagram for dynamically adjusting the phase of the sampling clock for clock data recovery (CDR). DETAILED DESCRIPTION

[0054] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0055] A signal quality assessment method based on edge sampling values, such as Figure 1 As shown, S1, using the signal quality assessment module (such as Figure 2As shown in FIG. 1 , the device receives data information and edge information output by a high-speed serial-to-parallel transceiver SERDES.

[0056] S2. Search for various code types representing different frequencies based on data information, including:

[0057] Search for a preset number (number is configurable) of binary patterns that represent high frequencies, such as Figure 3 Shown: 010, 101;

[0058] Search for a preset number of binary patterns representing sub-high frequencies, such as Figure 4 Shown: 0110, 1001;

[0059] Search for a preset number of binary patterns that represent the intermediate frequency, such as Figure 5 As shown: 01110, 10001;

[0060] Search for a preset number of binary patterns representing sub-low frequencies, such as Figure 6 As shown: 011110, 100001;

[0061] Search for a preset number of binary patterns that represent low frequencies, such as Figure 7 Shown: 0111110, 1000001.

[0062] S3. Obtain edge sampling values ​​corresponding to all code types from the edge information, and count the number of edge sampling values ​​corresponding to each code type, specifically including:

[0063] S31, obtain edge sampling values ​​corresponding to all code types from edge information (such as Figures 8 to 10 The edge sampling value at the position indicated by each arrow in the figure is binary 0 or 1;

[0064] S32, counting the number of 0s and 1s corresponding to various code types, and recording them as CNTH0 and CNTH1, CNTSH0 and CNTSH1, CNTM0 and CNTM1, CNTSL0 and CNTSL1, CNTL0 and CNTL1 respectively;

[0065] Among them, CNTH0 and CNTH1 are the number of 0 and 1 corresponding to the binary code representing the high frequency, CNTSH0 and CNTSH1 are the number of 0 and 1 corresponding to the binary code representing the second high frequency, CNTM0 and CNTM1 are the number of 0 and 1 corresponding to the binary code representing the medium frequency, CNTSL0 and CNTSL1 are the number of 0 and 1 corresponding to the binary code representing the second low frequency, and CNTL0 and CNTL1 are the number of 0 and 1 corresponding to the binary code representing the low frequency;

[0066] The sum of the number of 0s and 1s corresponding to each type of code is equal to the number of each type of code.

[0067] The following uses CNTH0 and CNTH1, which represent the number of 0s and 1s corresponding to the binary code 010 representing high frequency, as an example to illustrate the influence of the phase of the sampling clock dynamically adjusted by the clock data recovery CDR on edge sampling:

[0068] like Figure 8 As shown, when the phase of the sampling clock dynamically adjusted by the clock data recovery CDR in the high-speed serial-to-parallel transceiver SERDES is at the optimal sampling phase, the probability of 0 and 1 appearing is equal;

[0069] like Fig. 9 As shown, when the phase of the sampling clock dynamically adjusted by the clock data recovery CDR in the high-speed serial-to-parallel transceiver SERDES is ahead of the optimal sampling phase, the probability of 1 appearing is greater than the probability of 0 appearing, and the statistical result is CNTH1>CNTH0;

[0070] like Fig.10 As shown, when the phase of the sampling clock dynamically adjusted by the clock data recovery CDR in the high-speed serial-to-parallel transceiver SERDES lags behind the optimal sampling phase, the probability of 0 appearing is greater than the probability of 1 appearing, and the statistical result is CNTH0>CNTH1.

[0071] S4. Calculate the quality factor according to the number of edge sampling values ​​corresponding to each type of code, including:

[0072] S41, calculate the maximum value FOM_MAX of the quality factor FOM, the maximum value FOM_MAX of the quality factor FOM is the sum of the number of various types of code:

[0073] FOM_MAX=(CNTH0+CNTH1)+(CNTSH0+CNTSH1)+(CNTM0+CNTM1)+(CNTSL0+CNTSL1)+(CNTL0+CNTL1);

[0074] S42. Calculate the quality factor FOM:

[0075] FOM=FOM_MAX-|CNTH0-CNTH1|-|CNTSH0-CNTSH1|-|CNTM0-CNTM1|-|CNTSL0-CNTSL1|-|CNTL0-CNTL1|.

[0076] S5. Determine the quality of the filtered analog signal output by the analog front end AFE in the high-speed serial-to-parallel transceiver SERDES according to the quality factor, specifically including:

[0077] According to the calculation formula of quality factor FOM in S42:

[0078] When the difference between the number of 0s and 1s corresponding to each type of code is smaller, the quality factor FOM is larger, which means that the quality of the filtered analog signal output by the analog front end AFE in the high-speed serial-parallel transceiver SERDES is better;

[0079] When the difference between the number of 0s and 1s corresponding to each type of code is larger, the quality factor FOM is smaller, which means that the quality of the filtered analog signal output by the analog front end AFE in the high-speed serial-to-parallel transceiver SERDES is worse.

[0080] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements will not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A signal quality assessment method based on edge sampling values, characterized in that: The following steps are involved: S1, using the signal quality evaluation module to receive data information and edge information output by the high-speed serial-to-parallel transceiver SERDES; S2. Searching for various code types representing different frequencies according to the data information; S3, obtaining edge sampling values ​​corresponding to all code types from the edge information, and counting the number of edge sampling values ​​corresponding to each code type; S4, calculating the quality factor according to the number of edge sampling values ​​corresponding to each type of code; S5. Determine the quality of the filtered analog signal output by the analog front end AFE in the high-speed serial-to-parallel transceiver SERDES according to the quality factor.

2. The signal quality assessment method based on edge sampling values ​​according to claim 1, characterized in that: S2 searches for various code types representing different frequencies based on data information, including: Search for a preset number of binary patterns that represent high frequencies: 010, 101; Searching for a preset number of binary codes representing sub-high frequencies: 0110, 1001; Search for a preset number of binary codes representing the intermediate frequency: 01110, 10001; Search for a preset number of binary codes representing the second lowest frequency: 011110, 100001; Search for a preset number of binary patterns that represent low frequencies: 0111110, 1000001.

3. The signal quality assessment method based on edge sampling values ​​according to claim 2, characterized in that: In S3, edge sampling values ​​corresponding to all code types are obtained from the edge information, and the number of edge sampling values ​​corresponding to each code type is counted, including: S31, obtaining edge sampling values ​​corresponding to all code patterns from the edge information, that is, binary 0 or 1; S32, counting the number of 0s and 1s corresponding to various code types, and recording them as CNTH0 and CNTH1, CNTSH0 and CNTSH1, CNTM0 and CNTM1, CNTSL0 and CNTSL1, CNTL0 and CNTL1 respectively; Among them, CNTH0 and CNTH1 are the number of 0 and 1 corresponding to the binary code representing the high frequency, CNTSH0 and CNTSH1 are the number of 0 and 1 corresponding to the binary code representing the second high frequency, CNTM0 and CNTM1 are the number of 0 and 1 corresponding to the binary code representing the medium frequency, CNTSL0 and CNTSL1 are the number of 0 and 1 corresponding to the binary code representing the second low frequency, and CNTL0 and CNTL1 are the number of 0 and 1 corresponding to the binary code representing the low frequency; The sum of the number of 0s and 1s corresponding to each type of code is equal to the number of each type of code.

4. The signal quality assessment method based on edge sampling values ​​according to claim 3 is characterized in that: For CNTH0 and CNTH1, which represent the number of 0 and 1 corresponding to the binary code 010 representing high frequency: When the phase of the sampling clock dynamically adjusted by the clock data recovery (CDR) in the high-speed serial-to-parallel transceiver SERDES is at the optimal sampling phase, the probability of 0 and 1 appearing is equal; When the phase of the sampling clock dynamically adjusted by the clock data recovery CDR in the high-speed serial-to-parallel transceiver SERDES is ahead of the optimal sampling phase, the probability of 1 appearing is greater than the probability of 0 appearing, and the statistical result is CNTH1>CNTH0; When the phase of the sampling clock dynamically adjusted by the clock data recovery CDR in the high-speed serial-to-parallel transceiver SERDES lags behind the optimal sampling phase, the probability of 0 appearing is greater than the probability of 1 appearing, and the statistical result is CNTH0>CNTH1.

5. The signal quality assessment method based on edge sampling values ​​according to claim 3 is characterized in that: In S4, the quality factor is calculated according to the number of edge sampling values ​​corresponding to each type of code, including: S41, calculate the maximum value FOM_MAX of the quality factor FOM, the maximum value FOM_MAX of the quality factor FOM is the sum of the number of various types of code: FOM_MAX=(CNTH0+CNTH1)+(CNTSH0+CNTSH1)+(CNTM0+CNTM1)+(CNTSL0+CNTSL1)+(CNTL0+CNTL1); S42. Calculate the quality factor FOM: FOM=FOM_MAX-|CNTH0-CNTH1|-|CNTSH0-CNTSH1|-|CNTM0-CNTM1|-|CNTSL0-CNTSL1|-|CNTL0-CNTL1|.

6. The signal quality assessment method based on edge sampling values ​​according to claim 5, characterized in that: In S5, the quality of the filtered analog signal output by the analog front end AFE in the high-speed serial-to-parallel transceiver SERDES is determined according to the quality factor, including: According to the calculation formula of quality factor FOM in S42: When the difference between the number of 0s and 1s corresponding to each type of code is smaller, the quality factor FOM is larger, which means that the quality of the filtered analog signal output by the analog front end AFE in the high-speed serial-parallel transceiver SERDES is better; When the difference between the number of 0s and 1s corresponding to each type of code is larger, the quality factor FOM is smaller, which means that the quality of the filtered analog signal output by the analog front end AFE in the high-speed serial-to-parallel transceiver SERDES is worse.

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