Verification method for integrating module verification and system verification

Abstract

The invention discloses a verification method for integrating module verification and system verification, which comprises the following steps of: a, selecting at least one module from a plurality of composition modules of a system, establishing an independent verification environment for each selected module, and writing a test case; b, performing independent simulation verification on each module according to a coverage rate requirement; c, integrating each module and the corresponding verification environment into a system verification environment; and d, performing simulation verification on each function of the system. According to the method, in the project verification process, parallel verification can be carried out between a single module and a system, the verification work efficiency is further improved, and the mutual influence between verification workers is reduced.

Description

Technical Field

[0001] The present invention relates to the field of digital verification, and more specifically to a verification method integrating module verification and system verification. Background Art

[0002] With the development of integrated circuit technology and the expansion of market demand, the functions and scale of circuits are becoming larger and more complex. In order to ensure the correctness of the circuit and the normal implementation of the function, the compilation and simulation time required for verification on the system will also increase significantly.

[0003] In the actual verification process, we often encounter such a phenomenon: the functions of one or several modules are not complex, and there are relatively few functional points that need to be verified. At the same time, these modules do not have many complex applications in the normal operation of the actual chip. However, in order to ensure the verification coverage and accuracy, the verification process has to include them in the system and set different parameters for them to perform simulation verification on the system. At the same time, the system where these modules are located is very large, and the simulation and compilation time are very long. The actual verification results only cover a small part of the verification that is not very important.

[0004] Combined with the specific practical application situation, this processing method has an obvious and large imbalance between time investment and results. Therefore, this processing method is undoubtedly extremely inefficient and unreasonable, which has a great negative impact on the progress of the project and adds more burden to the verification personnel.

[0005] Therefore, it is necessary to provide an improved verification method that can perform simulation verification on some specific modules separately and integrate module verification and system verification to overcome the above-mentioned defects. Summary of the invention

[0006] The purpose of the present invention is to provide a verification method that integrates module verification and system verification. During the verification process of a project, the method of the present invention can perform parallel verification between a single module and the system, further improving the efficiency of the verification work and reducing the mutual influence between the work of the verification staff.

[0007] To achieve the above-mentioned purpose, the present invention provides a verification method integrating module verification and system verification, which comprises the following steps: a. selecting at least one module from a plurality of component modules of the system, establishing an independent verification environment for each selected module and writing test cases; b. performing independent simulation verification on each module according to coverage requirements; c. integrating each module and its corresponding verification environment into the system verification environment; d. performing simulation verification on each function of the system.

[0008] Preferably, before step a, the method further includes the step of: selecting all modules in the system that meet the requirements according to the set requirements.

[0009] Preferably, the setting requirement is that the number of interconnections between a single module and other modules is less than or equal to 3, and the input signal sources of other modules are the same module.

[0010] Preferably, the coverage includes code coverage, condition coverage, state machine coverage and flip coverage.

[0011] Preferably, the coverage ratio is required to be greater than 80%.

[0012] Preferably, in step d, the system verification environment calls all functions and test cases in the verification environment corresponding to a single module as needed.

[0013] Compared with the prior art, the verification method of integrated module verification and system verification of the present invention can perform simulation verification separately for each module that meets the requirements selected from the constituent modules of the system. Therefore, independent verification can be performed first when the system verification environment has not yet been built or the system process still has problems and cannot be fully implemented. The parallel verification method further improves the efficiency of the verification work and reduces the mutual influence between the work of relevant personnel. In addition, in the scheme of the present invention, after the individual module and its verification environment are integrated into the system, all test cases and functions of the individual module and its verification environment can also be called in the system verification environment, so that in the later stage of the project when time and resources are relatively sufficient, all test cases and functions of the individual module can also be verified in the system verification environment, further ensuring the normal implementation and verification of the functions of each module on the system. The scheme of the present invention performs separate verification on each module that meets the requirements, so that the same set of process methods can be used to build the verification environment for different modules in different projects, which improves the convenience of verification and has high portability.

[0014] The present invention will become more apparent from the following description taken in conjunction with the accompanying drawings, which are used to illustrate embodiments of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 The flowchart of the verification method of the present invention is an integrated module verification and system verification. DETAILED DESCRIPTION

[0016] The embodiments of the present invention are now described with reference to the accompanying drawings, in which similar element numbers represent similar elements. As described above, the present invention provides a verification method that integrates module verification and system verification. During the verification process of a project, the method of the present invention can perform parallel verification between a single module and a system, further improving the efficiency of the verification work and reducing the mutual influence between the work of verification staff.

[0017] Please refer to Figure 1 , Figure 1 FIG. 1 is a flow chart of the verification method for integrated module verification and system verification of the present invention. Figure 1 As shown, the verification method of integrated module verification and system verification of the present invention comprises the following steps:

[0018] Step S001, select at least one module from multiple modules constituting the system, establish an independent verification environment for each selected module and write test cases; in this step, select a number of modules suitable for independent simulation verification from the multiple modules constituting the system, wherein, as described in the background technology, the functions of the modules involved in the present invention are not complicated and the functional points that need to be verified are relatively few, that is, the selected modules need to meet the set requirements, and not all modules can be subjected to the independent simulation verification of the present invention; specifically, the set requirements are that the number of interconnections between a single module and other modules is less than or equal to 3, and the input signal source of other modules is the same module, also That is, the number of other templates connected to a selected module cannot exceed 3, and the input signals of these modules all come from the same module; for example, module A is only connected to modules B and C (the number of interconnections between module A and other modules is less than 3), and the input signals of modules B and C all come from module D (module D is not connected to module A), and module A is the module that meets the set requirements and can be selected for independent simulation verification; in the present invention, it is specifically set that the selected module needs to meet the above set requirements, mainly to avoid other modules with complex functions or structures being selected, but their functions may not be fully verified during the independent simulation verification process, thereby affecting the verification results of the entire system. And then establish an independent verification environment for each module and write test cases, so that these selected modules can be completely independent of other modules for simulation verification, and thus do not take up the time of system verification, thereby improving the efficiency of system verification.

[0019] Step S002, perform independent simulation verification on each module according to the coverage requirement; in this step, the coverage of the independent simulation verification of each module includes code coverage, condition coverage, state machine coverage and flip coverage; wherein, it can be seen from the above step S001 that each selected module, although its overall structure and function are relatively simple, is still part of the system and also needs to be connected to other modules (the number of connections is less than or equal to 3), so the coverage of a single module cannot be 100% for sure, but in order to cooperate with the integrity of the whole system fax verification, in the present invention, the coverage requirement is greater than 80%, that is, when a single module is simulated and verified, the coverage involved is greater than 80%. The code coverage, condition coverage, state machine coverage and flip coverage must be greater than 80% to ensure the comprehensiveness of the simulation verification process of a single module and that the subsequent simulation verification process of the module in the system does not affect the verification result of the entire system; wherein, the simulation verification process of each module is the same as other fax verifications and will not be described in detail here; in addition, the verification environment of a single module will not compile other files and modules in the system during the simulation verification, thereby ensuring the independence of its simulation verification. Therefore, when the system verification environment has not been completed or the system flow still has problems and cannot be fully run through, independent verification is performed first. The parallel verification method of the present invention further improves the efficiency of the verification work and reduces the mutual constraints between the work of relevant personnel.

[0020] Step S003, integrating each module and its corresponding verification environment into the system verification environment; in the above steps, each module selected as required has been simulated and verified separately. In this step, each module that has completed independent simulation verification and its corresponding verification environment are integrated into the system verification environment, which not only assists in completing the assembly and setup of the entire system, but also assists in the subsequent simulation and verification of the entire system.

[0021] Step S004, simulate and verify each function of the system; in this step, the assembly setting of the system will be completed, so that the corresponding simulation verification can be carried out on each function of the entire system, and the system verification environment can call all functions and test cases in the verification environment corresponding to a single module as needed, so that various functions of the module can also be verified in the system verification environment, ensuring that the reproduction of the actual chip test situation can be achieved; all test cases and functions of the separate module verification environment can also be called in the system verification environment, and when time and resources are relatively sufficient in the later stage of the project, all test cases and functions of the separate module verification environment can also be verified in the system verification environment, ensuring the normal implementation and verification of the module functions on the system.

[0022] To sum up, the verification method of integrated module verification and system verification of the present invention, since each selected individual module can be directly simulated and verified independently of the system verification environment, independent verification can be carried out first when the system verification environment has not yet been built or the system process still has problems and cannot be fully implemented. The parallel verification method further improves the efficiency of the verification work and reduces the mutual influence between the work of related personnel; in addition, in the scheme of the present invention, all test cases and functions of the individual module and its verification environment can also be called in the system verification environment, so that in the later stage of the project when time and resources are relatively sufficient, all test cases and functions of the individual module can also be verified in the system verification environment, further ensuring the normal implementation and verification of the functions of each module on the system; the scheme of the present invention verifies each module that meets the requirements separately, so that the same set of process methods can be used to build the verification environment for different modules in different projects, so that the convenience of verification is improved and the portability is very high.

[0023] The present invention has been described above in conjunction with the best embodiments, but the present invention is not limited to the embodiments disclosed above, but should cover various modifications and equivalent combinations based on the essence of the present invention.

Claims

1. A verification method integrating module verification and system verification, characterized in that: The steps include: a. Select at least one module from the multiple components of the system, establish an independent verification environment for each selected module and write test cases; b. Perform independent simulation verification on each module according to the coverage requirements; c. Integrate each module and its corresponding verification environment into the system verification environment; d. Perform simulation verification on each function of the system.

2. The verification method for integrated module verification and system verification as claimed in claim 1, characterized in that: Before step a, the method further comprises the following steps: According to the set requirements, select all modules in the system that meet the requirements.

3. The verification method for integrated module verification and system verification as claimed in claim 2, characterized in that: The setting requirement is that the number of interconnections between a single module and other modules is less than or equal to 3, and the input signal sources of other modules are the same module.

4. The verification method for integrated module verification and system verification as claimed in claim 1, characterized in that: The coverage includes code coverage, condition coverage, state machine coverage and flip coverage.

5. The verification method for integrated module verification and system verification as claimed in claim 4, characterized in that: The coverage is required to be greater than 80%.

6. The verification method for integrated module verification and system verification as claimed in claim 1, characterized in that: In step d, the system verification environment calls all functions and test cases in the verification environment corresponding to a single module as needed.

Images