Data transmission efficiency improvement method and device, equipment and storage medium

Abstract

The invention provides a data transmission efficiency improving method and device, equipment and a storage medium, and the method comprises the steps: carrying out the equipment recognition and address space mapping of expansion card equipment connected with a PCIe interface on a GPU, and obtaining GPU data transmission configuration information; according to the configuration information, carrying out storage space division and transmission channel establishment on the expansion card equipment to obtain a GPU data transmission channel configuration result; scheduling and distributing the GPU data to be transmitted based on the configuration result and a preset CUDA (Compute Unified Device Architecture) shared storage mechanism to obtain a data transmission execution scheme; and starting, controlling, monitoring in real time and dynamically adjusting the transmission process of the data to be transmitted according to the execution scheme and a preset RAID (Redundant Array of Independent Disks) disk array. According to the method, the expansion card equipment and the RAID disk array are introduced, and a CUDA shared storage mechanism is combined, so that the available storage space of the GPU is effectively expanded, the data transmission process is optimized, the data transmission efficiency when the GPU processes a large-scale data set is remarkably improved, and meanwhile, relatively low hardware cost is kept.

Description

Technical Field

[0001] The present invention relates to the field of graphics processors, and in particular to a method, device, equipment and storage medium for improving data transmission efficiency. Background Art

[0002] With the rapid development of big data and artificial intelligence technologies, the application of graphics processing units (GPUs) in the field of high-performance computing continues to expand. Currently, the computing efficiency of GPUs is largely limited by their data transmission capabilities. Traditional GPU data transmission methods mainly rely on PCIe interfaces and high-bandwidth memory (HBM).

[0003] In the prior art, GPUs exchange data with external storage devices through PCIe interfaces and use built-in HBM for high-speed data caching. However, this approach has a major drawback: when processing ultra-large-scale data sets, the HBM capacity built into the GPU is often insufficient to meet data processing requirements, resulting in frequent data exchanges, which significantly reduces data transmission efficiency and overall computing performance.

[0004] Although this problem can be alleviated by increasing HBM capacity, this method is costly and difficult to flexibly respond to data processing needs of different scales. Therefore, how to effectively improve the data transmission efficiency of GPU without significantly increasing hardware costs has become a technical problem that needs to be solved urgently. Summary of the invention

[0005] The main purpose of the present invention is to solve the technical problem that the existing GPU built-in high-bandwidth memory capacity is insufficient, resulting in low data transmission efficiency; A first aspect of the present invention provides a method for improving data transmission efficiency, the method comprising: Perform device identification and address space mapping on the expansion card device connected to the PCIe interface on the GPU to obtain GPU data transmission configuration information; According to the GPU data transmission configuration information, the expansion card device is subjected to storage space division and transmission channel establishment processing to obtain a GPU data transmission channel configuration result; Based on the GPU data transmission channel configuration result and the preset CUDA shared storage mechanism, the GPU data to be transmitted is scheduled and allocated to obtain a data transmission execution plan; According to the data transmission execution scheme and the preset RAID disk array, the data transmission process of the data to be transmitted is started and controlled, and the transmission status of the data to be transmitted is monitored and dynamically adjusted in real time during the transmission process.

[0006] Optionally, in a first implementation of the first aspect of the present invention, performing device identification and address space mapping processing on an expansion card device connected to a PCIe interface on a GPU to obtain GPU data transmission configuration information includes: Connect the expansion card device through the PCIe interface on the GPU, and perform VID / DID reading and BDF structure scanning processing on the expansion card device to obtain a device identification code; According to the device identification code, the storage space size detection process is performed on the expansion card device through the BAR register of the configuration space in the PCIe interface to obtain available storage space information; The CPU performs address range allocation processing on the expansion card device according to the storage space information to obtain GPU data transmission configuration information.

[0007] Optionally, in a second implementation of the first aspect of the present invention, the performing storage space size detection processing on the expansion card device through a BAR register of a configuration space in a PCIe interface according to the device identification code to obtain the available storage space information includes: According to the device identification code, a configuration address register of the PCIe interface is set to obtain an access address for accessing a configuration space of the expansion card device; Based on the access address, write all 1s to the BAR register in the configuration space of the expansion card device to obtain the initial state value of the BAR register; Reading the BAR register of the initial state value to obtain a register return value containing unmodifiable bit information; Calculate the storage space size of the expansion card device according to the unmodifiable bit information in the register return value to obtain the storage capacity value of the expansion card device; Based on the storage capacity value and the attribute bit information in the register return value, the storage space type and access characteristics of the expansion card device are identified to obtain available storage space information including storage space size, type and access attributes.

[0008] Optionally, in a third implementation of the first aspect of the present invention, performing storage space division and transmission channel establishment processing on the expansion card device according to the GPU data transmission configuration information to obtain a GPU data transmission channel configuration result includes: Controlling the root complex of the PCIe interface through the CPU to divide the storage space of the expansion card device into a running capacity area and a cache area according to the GPU data transmission configuration information, so as to obtain a storage area division result of GPU operation; Setting the BME bit and the MSE bit in the configuration space of the expansion card device through the command register of the root complex to obtain a basic configuration that allows DMA requests and controller register access; According to the storage area division result and the basic configuration, a data transmission channel between the kernel function of the GPU and each storage area is established, and the physical parameters, bandwidth allocation and priority of the data transmission channel are set to obtain the GPU data transmission channel configuration result.

[0009] Optionally, in a fourth implementation of the first aspect of the present invention, the scheduling and allocation processing of the GPU data to be transmitted based on the GPU data transmission channel configuration result and the preset CUDA shared storage mechanism to obtain the data transmission execution plan includes: In the kernel function of the GPU, a preset shared keyword is used to declare the expansion card device, and the HBM expansion firmware check process is performed on the program version in the expansion card device to obtain an extension declaration; According to the extended declaration and the GPU data transmission channel configuration result, the access frequency, data size and correlation analysis and processing of the data to be transmitted are performed to obtain data feature information; Based on the data characteristic information, the data to be transmitted is allocated between the high-bandwidth memory and the storage space of the expansion card device to obtain a data allocation plan; According to the data allocation scheme and the GPU data transmission channel configuration result, the transmission channel and transmission priority of each data block are selected and processed to obtain the data transmission execution scheme including the data block source address, target address, transmission channel and transmission priority.

[0010] Optionally, in a fifth implementation of the first aspect of the present invention, the use of a preset shared keyword in the kernel function of the GPU to declare the expansion card device, and performing an HBM expansion firmware check on the program version in the expansion card device, to obtain the extended declaration includes: Preprocessing the kernel function code of the GPU to obtain a code segment of a shared keyword, and inserting a device identification code of the expansion card device into the code segment to obtain a shared memory declaration statement of the extended memory; Performing syntax parsing on the shared memory declaration statement to obtain a parameter list including the storage space size of the expansion card device; According to the parameter list, the HBM firmware version of the expansion card device is detected, and based on the HBM firmware version, the extended shared memory declaration statement is conditionally compiled to obtain the extended declaration of the expansion card device adapted to the HBM firmware version.

[0011] Optionally, in a sixth implementation of the first aspect of the present invention, starting and controlling the data transmission process of the data to be transmitted according to the data transmission execution scheme and the preset RAID disk array, and monitoring and dynamically adjusting the transmission status of the data to be transmitted in real time during the transmission process includes: According to the data transmission execution scheme, the data transmission path between the transmission channel and the RAID disk array is configured and processed to obtain a high-speed data transmission path; Through the high-speed data transmission path, the DMA controller is parameterized and the transmission buffer is prepared to obtain a data transmission initialization configuration; Based on the data transmission initialization configuration, a transmission process of the data to be transmitted from the source address to the target address is started through the PCIe interface to obtain a data transmission execution state; Performing real-time monitoring and processing on the transmission rate, delay and error rate in the data transmission execution state to obtain transmission performance indicators; According to the transmission performance index, the transmission task allocation and channel priority are dynamically adjusted in combination with RAID disk array technology to obtain an optimized data transmission strategy; Based on the optimized data transmission strategy, the occupancy of the receiving end buffer is analyzed and processed to obtain adaptive flow control parameters, and the data transmission rate is adjusted according to the adaptive flow control parameters.

[0012] A second aspect of the present invention provides a device for improving data transmission efficiency, the device for improving data transmission efficiency comprising: The device initialization module is used to perform device identification and address space mapping processing on the expansion card device connected to the PCIe interface on the GPU to obtain GPU data transmission configuration information; A channel configuration module is used to perform storage space division and transmission channel establishment processing on the expansion card device according to the GPU data transmission configuration information to obtain a GPU data transmission channel configuration result; A data scheduling module is used to schedule and allocate the data to be transmitted of the GPU based on the GPU data transmission channel configuration result and the preset CUDA shared storage mechanism to obtain a data transmission execution plan; The transmission control module is used to start and control the data transmission process of the data to be transmitted according to the data transmission execution plan and the preset RAID disk array, and to monitor and dynamically adjust the transmission status of the data to be transmitted in real time during the transmission process.

[0013] The third aspect of the present invention provides a device for improving data transmission efficiency, comprising: a memory and at least one processor, wherein instructions are stored in the memory, and the memory and the at least one processor are interconnected via lines; the at least one processor calls the instructions in the memory so that the data transmission efficiency improvement device executes the steps of the above-mentioned data transmission efficiency improvement method.

[0014] A fourth aspect of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium stores instructions, which, when executed on a computer, enable the computer to execute the steps of the above-mentioned method for improving data transmission efficiency.

[0015] The above-mentioned data transmission efficiency improvement method, device, equipment and storage medium obtain GPU data transmission configuration information by performing device identification and address space mapping on the expansion card device connected to the PCIe interface on the GPU; according to the configuration information, the storage space of the expansion card device is divided and the transmission channel is established to obtain the GPU data transmission channel configuration result; based on the configuration result and the preset CUDA shared storage mechanism, the GPU data to be transmitted is scheduled and allocated to obtain the data transmission execution plan; according to the execution plan and the preset RAID disk array, the transmission process of the data to be transmitted is started, controlled, monitored in real time and dynamically adjusted. The present invention effectively expands the available storage space of the GPU, optimizes the data transmission process, and significantly improves the data transmission efficiency of the GPU when processing large-scale data sets by introducing the expansion card device and the RAID disk array, combined with the CUDA shared storage mechanism, while maintaining a low hardware cost.

[0016] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention are realized and obtained by the structures particularly pointed out in the description, claims and drawings.

[0017] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A schematic diagram of a first embodiment of a method for improving data transmission efficiency in an embodiment of the present invention; Figure 2 A schematic diagram of an embodiment of a device for improving data transmission efficiency in an embodiment of the present invention; Figure 3 Schematic diagram of an embodiment of a device for improving data transmission efficiency in an embodiment of the present invention. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0020] The terms "including" and "having" and any variations thereof mentioned in the embodiments of the present invention are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device end including a series of steps or units is not limited to the listed steps or units, but may optionally include other steps or units that are not listed, or may optionally include other steps or units that are inherent to these processes, methods, products or device ends.

[0021] To facilitate understanding of this embodiment, a method for improving data transmission efficiency disclosed in an embodiment of the present invention is first described in detail. Figure 1 As shown, the method comprises the following steps: 101. Perform device identification and address space mapping processing on the expansion card device connected to the PCIe interface on the GPU to obtain GPU data transmission configuration information; In one embodiment of the present invention, the device identification and address space mapping processing of the expansion card device connected to the PCIe interface on the GPU to obtain the GPU data transmission configuration information includes: connecting the expansion card device through the PCIe interface on the GPU, and performing VID / DID reading and BDF structure scanning processing on the expansion card device to obtain a device identification code; according to the device identification code, performing storage space size detection processing on the expansion card device through the BAR register of the configuration space in the PCIe interface to obtain available storage space information; and performing address range allocation processing on the expansion card device according to the storage space information by the CPU to obtain the GPU data transmission configuration information.

[0022] Specifically, the expansion card device is first physically connected through the PCIe interface on the GPU to establish a hardware-level communication foundation. Subsequently, the device enumeration process is automatically triggered to read the VID / DID and scan the BDF structure of the expansion card device. The VID / DID reading operation is implemented by accessing the configuration space of the device. Specifically, the Configuration Address Register is set at the 0xCF8 address of the I / O space to determine the BDF combination to be accessed, and then the actual reading operation is performed at the 0xCFC address. This process obtains the vendor ID and device ID of the expansion card device, which are essential for the correct identification and subsequent configuration of the device. At the same time, the BDF structure of the device is also scanned, that is, the unique identifier of each PCIe device node is determined by the combination of the bus number, device number and function number. This process is led by the root complex in the PCIe architecture, and the identification and management of PCIe devices are completed under the control of the CPU. Through these operations, a detailed device identification code is obtained, which contains the identity information of the device and its position in the PCIe topology.

[0023] Specifically, after obtaining the device identification code, the storage space size detection process is performed on the expansion card device through the BAR register of the configuration space in the PCIe interface. This process first involves accessing the configuration space of the expansion card device, which contains various configuration information of the device, among which the BAR register is a key component. The BAR register is written with all 1s, which is a standard mechanism defined in the PCIe specification for determining the size of the memory space required by the device. After writing all 1s, the return value of the BAR register is read. Since some bits of the BAR register are read-only, the size of the storage space required by the device can be known by observing which bits remain unchanged. For example, if the lower 12 bits do not change, it means that the device requires 4KB of space. In addition, the lower bits of the BAR register also contain some attribute information, such as whether the storage space is memory space or I / O space, whether it supports prefetching and other features. How to access the device's storage space will be determined based on these features. Through this process, available storage space information including space size and access characteristics is obtained, which is crucial for subsequent memory allocation and data transmission.

[0024] Finally, the CPU allocates the address range for the expansion card device according to the acquired storage space information. This process is achieved by setting the BAR register in the PCIe configuration space. The CPU will allocate a continuous address range in the address space to the expansion card device according to the storage space required by the expansion card device. This address range will be written into the BAR register, thereby establishing a mapping relationship between the physical address and the device storage space. In PCIe, due to the existence of the root complex, when the CPU needs to read the data of the PCIe device, it will first let the root complex read the data from the PCIe device to the CPU memory, and then the CPU will read the data from the memory. Conversely, when the CPU needs to write data to the device, it also writes the data to the memory first, and then writes it to the PCIe device through the root complex. This memory-mapped I / O method enables the CPU to access the device's storage space like accessing memory, greatly simplifying the data transmission process. Through this address range allocation process, the complete GPU data transmission configuration information is obtained, which includes important parameters such as device identification information, storage capacity information, address mapping relationship, and access characteristics. These configuration information lays the foundation for the subsequent GPU data transmission process, ensuring the correctness and efficiency of data transmission.

[0025] Further, the storage space size detection process is performed on the expansion card device through the BAR register of the configuration space in the PCIe interface according to the device identification code to obtain the available storage space information, including: setting the configuration address register of the PCIe interface according to the device identification code to obtain the access address for accessing the configuration space of the expansion card device; based on the access address, writing all 1s to the BAR register in the configuration space of the expansion card device to obtain the initial state value of the BAR register; reading the BAR register of the initial state value to obtain a register return value containing unmodifiable bit information; calculating the storage space size of the expansion card device according to the unmodifiable bit information in the register return value to obtain the storage capacity value of the expansion card device; identifying the storage space type and access characteristics of the expansion card device based on the storage capacity value and the attribute bit information in the register return value to obtain the available storage space information containing the storage space size, type and access attributes.

[0026] Specifically, first set the configuration address register of the PCIe interface according to the device identification code. Use the 0xCF8 address of the I / O space to set the Configuration Address Register. This 32-bit register is divided into multiple fields, including an 8-bit bus number, a 5-bit device number, a 3-bit function number, and an 8-bit register offset. Write the bus number, device number, and function number contained in the device identification code into the corresponding fields respectively, and set the register offset to 0 (because we want to access the BAR register, which is located at the beginning of the configuration space). In addition, the highest bit of the register is set to 1 to enable configuration access. Through this setting, the specific access address for accessing the configuration space of the expansion card device is obtained.

[0027] Specifically, after obtaining the access address, the BAR (Base Address Register) register in the expansion card device configuration space is written with all 1s. This operation is performed through the 0xCFC address of the I / O space. Specifically, 0xFFFFFFFF (for 32-bit BAR) or 0xFFFFFFFFFFFFFFFF (for 64-bit BAR) is written to the 0xCFC address. This write operation does not actually change the value of the BAR register, but is used to detect the size of the memory space required by the device. After the write is completed, the value of the BAR register is read to obtain the initial state value of the BAR register. The BAR register of this initial state value is read, also performed through the 0xCFC address. The read operation returns a 32-bit or 64-bit value, which contains the unmodifiable bit information. In the BAR register, some bits are read-only. These bits remain unchanged in the previous all-1 write operation, and they are unmodifiable bits. The position and number of these unmodifiable bits directly reflect the size and type of memory space requested by the device.

[0028] Specifically, based on the obtained register return value, the storage space size of the expansion card device is calculated. This calculation process first determines the position of the lowest unmodifiable bit. For example, if the lower 12 bits in the return value are unmodifiable (i.e., they remain 1), and the 13th bit becomes 0, this means that the device requires 2^12 = 4KB of memory space. If the lower 16 bits are all 1, then the device requires 2^16 = 64KB of space. This value is determined by bit operations and bit counting operations. For 64-bit BARs, the values ​​of two 32-bit registers need to be considered at the same time. In this way, the storage space size required by the expansion card device is accurately calculated to obtain the storage capacity value of the expansion card device. Based on the storage capacity value and the attribute bit information in the register return value, the storage space type and access characteristics of the expansion card device are identified. The lower bits (usually the lowest 4 bits) of the BAR register contain important attribute information. In addition, the case of multiple BAR registers needs to be considered. PCIe devices may have up to 6 32-bit BARs or 3 64-bit BARs. It is necessary to traverse all BAR registers and perform the above size detection and attribute identification process for each valid BAR. Through the above steps, a comprehensive available storage space information is finally obtained, which contains the storage space size, type and access attributes corresponding to each BAR. This information is organized into a data structure, which contains detailed information such as the starting address, size, type (memory or I / O), whether it is a 64-bit address, whether it can be prefetched, etc. of each BAR. This data structure will be used for subsequent memory allocation, address mapping, data transfer and access optimization operations.

[0029] 102. According to the GPU data transmission configuration information, perform storage space division and transmission channel establishment processing on the expansion card device to obtain a GPU data transmission channel configuration result; In one embodiment of the present invention, the storage space division and transmission channel establishment processing of the expansion card device according to the GPU data transmission configuration information to obtain the GPU data transmission channel configuration result includes: controlling the root complex of the PCIe interface through the CPU to divide the storage space of the expansion card device into a running capacity area and a cache area according to the GPU data transmission configuration information to obtain the storage area division result of the GPU operation; setting the BME bit and the MSE bit in the configuration space of the expansion card device through the command register of the root complex to obtain the basic configuration allowing DMA requests and controller register access; establishing the data transmission channel between the kernel function of the GPU and each storage area according to the storage area division result and the basic configuration, and setting the physical parameters, bandwidth allocation and priority of the data transmission channel to obtain the GPU data transmission channel configuration result.

[0030] Specifically, the CPU first controls the root complex of the PCIe interface to divide the storage space of the expansion card device according to the GPU data transmission configuration information. Specifically, the CPU sends instructions to the root complex to instruct how to divide the storage space of the expansion card device. As the core component connecting the CPU and PCIe devices in the PCIe architecture, the root complex is responsible for performing this division operation. During the division process, the total storage space of the expansion card device is divided into two main areas: the running capacity area and the cache area. Usually, 2TB of the total capacity of 4TB is divided into the running capacity area, and the remaining 2TB is used as the cache area. This division is achieved by setting the corresponding address range registers in the root complex. The root complex writes these divided address ranges into the PCIe configuration space, thereby completing the space division at the hardware level. Specifically, the root complex sets two sets of address range registers, one for defining the starting address and size of the running capacity area, and the other for defining the starting address and size of the cache area. The setting of these registers ensures that subsequent memory access requests can be correctly routed to the corresponding storage area. The division process also includes the setting of access rights and attributes for each area. For example, the running capacity area can be set to be readable and writable, while the cache area can be set to be readable only or have special cache attributes. These settings are recorded in the storage area partition result, which contains detailed information such as the starting address, size, and access attributes of each area. This partition result provides the necessary parameters for the subsequent establishment of data transmission channels.

[0031] Specifically, after the storage space is divided, the BME (Bus Master Enable) bit and the MSE (Memory Space Enable) bit in the configuration space of the expansion card device are set through the command register of the root complex. This step is to enable certain key functions of the expansion card device. Specifically, the root complex writes specific values ​​to the configuration space of the expansion card device to set these two bits. The setting of the BME bit allows the expansion card device to become a bus master, which means that it can actively initiate DMA (direct memory access) requests. When the BME bit is set to 1, the expansion card device obtains the ability to initiate read and write requests to the host memory, which is essential for efficient data transfer. The setting of the MSE bit allows access to the memory space of the expansion card device. When the MSE bit is set to 1, the memory mapping registers of the expansion card device can be read and written, which is very important for controlling and configuring device functions. After the two bits are set, the basic configuration that allows DMA requests and controller register access is obtained. This configuration lays the foundation for subsequent data transfer operations, ensuring that the expansion card device can actively participate in the data transfer process and its internal registers can be correctly accessed and controlled. Finally, based on the previously obtained storage area division results and basic configuration, we start to establish data transmission channels between the GPU kernel function and each storage area. This process involves establishing logical connections inside the GPU to associate the GPU kernel function with different storage areas of the expansion card device. Specifically, independent data transmission channels are created for each storage area (running capacity area and cache area). These channels use PCIe differential signal pairs for data transmission, and each channel has its own independent transmission instruction management mechanism.

[0032] Specifically, in the process of establishing these channels, it is also necessary to set the physical parameters, bandwidth allocation and priority of each channel. Physical parameters include the bit width and operating frequency of the channel, which determine the basic transmission capacity of the channel. Bandwidth allocation involves how to allocate available PCIe bandwidth among multiple channels to ensure that each channel can obtain sufficient resources to meet its transmission needs. Priority setting is used to handle scheduling problems when multiple transmission requests arrive at the same time, and high-priority channels will receive priority processing. These settings are integrated into a complete GPU data transmission channel configuration result. This result contains detailed information for each channel, such as physical parameters, bandwidth allocation, priority, etc. In addition, the configuration result also includes the mapping relationship between channels and storage areas to ensure that data can be correctly routed to the target storage area.

[0033] 103. Based on the GPU data transmission channel configuration result and the preset CUDA shared storage mechanism, the GPU data to be transmitted is scheduled and allocated to obtain a data transmission execution plan; In one embodiment of the present invention, the scheduling and allocation processing of the data to be transmitted of the GPU based on the GPU data transmission channel configuration result and the preset CUDA shared storage mechanism to obtain the data transmission execution plan includes: using a preset shared keyword in the kernel function of the GPU to declare the expansion card device, and performing HBM expansion firmware check processing on the program version in the expansion card device to obtain an extended declaration; according to the extended declaration and the GPU data transmission channel configuration result, performing access frequency, data size and correlation analysis processing on the data to be transmitted to obtain data feature information; based on the data feature information, allocating the data to be transmitted between the high bandwidth memory and the storage space of the expansion card device to obtain a data allocation plan; according to the data allocation plan and the GPU data transmission channel configuration result, selecting the transmission channel and transmission priority of each data block to obtain the data transmission execution plan including the source address, target address, transmission channel and transmission priority of the data block.

[0034] Specifically, first, the expansion card device is declared in the kernel function of the GPU using the preset shared keyword. Specifically, in the CUDA programming model, the __shared__ keyword is used to declare shared memory. In this solution, this keyword is extended to declare the expansion card device. This declaration process includes specifying the identifier of the expansion card, determining the size of the shared storage space and other parameters. Next, the HBM expansion firmware check process is performed on the program version in the expansion card device. This step is to ensure that the firmware version of the expansion card device is compatible with the current HBM expansion solution. The check process obtains the firmware version information by reading the specific registers of the expansion card device, and then compares it with the preset compatible version list. If the versions match, the expansion card device will be marked as available; if not, an error will be recorded and the device may be disabled or the firmware will be updated. The results of these two steps are combined into an extended declaration, which contains the identifier of the expansion card device, the size of the shared storage space, the firmware version information, etc.

[0035] Specifically, next, according to the extension declaration and the GPU data transfer channel configuration results, the data to be transferred is analyzed in depth. This analysis process mainly considers three aspects: access frequency, data size and relevance. Access frequency analysis involves counting the number of times and time intervals each data block is accessed, which is usually achieved by inserting counters or timestamps in the GPU kernel function. Data size analysis directly calculates the number of bytes of each data block, which is crucial for determining the most suitable storage location. Relevance analysis considers the dependencies between data blocks, which requires building a data dependency graph to record which data blocks are often accessed or processed together. The results of this analysis process are integrated into a complete data feature information. This information is a complex data structure that contains the access frequency statistics, size information, and relevance scores of each data block with other data blocks. These feature information provides a key basis for subsequent data allocation decisions. Based on the obtained data feature information, the data to be transferred is allocated and processed between the storage space of the high bandwidth memory (HBM) and the expansion card device. This allocation process uses an optimization algorithm, which can be based on a greedy strategy or a dynamic programming method. The algorithm considers the access frequency, size, and relevance of each data block, as well as the storage characteristics of the HBM and expansion card devices (such as capacity, access speed, etc.). Generally speaking, data blocks with high access frequency will be allocated to the HBM first because HBM has a higher access speed. Larger data blocks may be allocated to expansion card devices because expansion cards usually provide larger storage capacity. Data blocks with high relevance will be allocated to the same storage area as much as possible to reduce data transmission overhead. The allocation process also needs to consider load balancing to ensure that neither the HBM is overloaded nor the storage space of the expansion card device is idle. The result of this allocation process is a detailed data allocation plan that specifies where each data block should be stored (specific storage area of ​​the HBM or expansion card device). This plan can be a mapping table that maps data block IDs to specific storage locations.

[0036] Specifically, finally, according to the data allocation scheme and the GPU data transmission channel configuration results, the transmission channel and transmission priority of each data block are selected. This step takes into account the storage location of the data block (according to the allocation scheme) and the available transmission channels (according to the channel configuration results). The most suitable transmission channel will be selected for each data block, taking into account factors such as the bandwidth of the channel, the current load, etc. At the same time, the transmission priority will be assigned according to the importance of the data block (which may be based on the access frequency or the role in the calculation). The result of this selection process is a complete data transmission execution plan. This plan contains detailed transmission information for each data block, including the source address (current storage location), the destination address (the new location determined by the allocation scheme), the selected transmission channel, and the assigned transmission priority. This execution plan provides comprehensive guidance for subsequent actual data transmission operations, ensuring the efficiency and controllability of the data transmission process.

[0037] Furthermore, the use of a preset shared keyword in the kernel function of the GPU to declare the expansion card device, and performing HBM expansion firmware check processing on the program version in the expansion card device to obtain an extended declaration includes: preprocessing the kernel function code of the GPU to obtain a code segment of the shared keyword, and inserting the device identification code of the expansion card device into the code segment to obtain a shared memory declaration statement of the extended memory; performing syntax parsing processing on the shared memory declaration statement to obtain a parameter list including the storage space size of the expansion card device; detecting the HBM firmware version of the expansion card device according to the parameter list, and based on the HBM firmware version, conditionally compiling the extended shared memory declaration statement to obtain an extended declaration of the expansion card device adapted to the HBM firmware version.

[0038] Specifically, the kernel code of the GPU is first preprocessed to identify and extract code segments with the shared keyword. This preprocessing step uses the preprocessor of the CUDA compiler to perform a preliminary analysis of the source code. The preprocessor scans the entire kernel code and identifies all statements that use the __shared__ keyword. These statements are usually used to declare variables in shared memory. After identifying these code segments, the device identification code of the expansion card device is inserted into these code segments. The device identification code is a unique identifier used to distinguish different expansion card devices. The insertion process needs to consider the correctness of CUDA syntax to ensure that the inserted code still complies with the CUDA programming specification. The inserted code segment forms a shared memory declaration statement for the extended memory. This declaration statement not only contains the original shared memory declaration, but also contains specific information about the expansion card device. Next, the generated shared memory declaration statement is parsed. This step uses the syntax analyzer of the CUDA compiler to perform in-depth analysis of the declaration statement. The syntax analyzer builds an abstract syntax tree (AST) to represent the structure and relationship of these declarations. During the analysis process, special attention is paid to parameter information related to storage space, such as the size of the storage space, alignment requirements, etc. Through this syntax parsing process, a parameter list containing the storage space size of the expansion card device is extracted. This parameter list is a structured data set that contains detailed information about each shared memory declaration, especially the storage space size of the expansion card device. This size information is crucial for subsequent memory allocation and management because it determines the specific capacity of the additional storage space that can be used.

[0039] After obtaining the parameter list, the HBM firmware version of the expansion card device is detected. This detection process is completed by reading specific registers of the expansion card device. A specific command is sent to the expansion card device to request it to return the current firmware version information. This version information usually contains the major version number, minor version number, and revision number, which are used to accurately identify the specific version of the firmware. Obtaining firmware version information is very important to ensure compatibility and functional correctness. Different versions of HBM firmware may support different functions or have different performance characteristics. Therefore, it is necessary to decide how to optimally use the resources of the expansion card device based on the detected firmware version. Based on the detected HBM firmware version, the extended shared memory declaration statement is conditionally compiled. Conditional compilation is a technology that selectively includes or excludes code segments according to specific conditions during compilation. In this scenario, different compilation strategies are selected according to different firmware versions. Specifically, preprocessing instructions (such as #ifdef, #ifndef, #endif, etc.) are used to wrap different code segments. Each code segment corresponds to one or more specific firmware versions. For example, for version 1.0 of the firmware, one memory layout may be used, while for version 2.0 of the firmware, another more efficient memory layout may be used. This conditional compilation process ensures that the generated code can maximize the use of features supported by the current firmware version while maintaining compatibility with different firmware versions. The processed code will be able to adapt to different versions of HBM firmware, thereby improving flexibility and scalability. Finally, through this conditional compilation process, an extended declaration of the expansion card device adapted to a specific HBM firmware version is obtained. This extended declaration is an optimized code segment that contains the identification information of the expansion card device, the size of the storage space, and the memory access and management code optimized for a specific firmware version.

[0040] 104. According to the data transmission execution plan and the preset RAID disk array, the data transmission process of the data to be transmitted is started and controlled, and the transmission status of the data to be transmitted is monitored and dynamically adjusted in real time during the transmission process.

[0041] In one embodiment of the present invention, the data transmission process of the data to be transmitted is started and controlled according to the data transmission execution scheme and the preset RAID disk array, and the transmission status of the data to be transmitted is monitored in real time and dynamically adjusted during the transmission process, including: according to the data transmission execution scheme, the data transmission path between the transmission channel and the RAID disk array is configured to obtain a high-speed data transmission path; through the high-speed data transmission path, the DMA controller is parameterized and the transmission buffer is prepared to obtain a data transmission initialization configuration; based on the data transmission initialization configuration, the transmission process of the data to be transmitted from the source address to the target address is started through the PCIe interface to obtain a data transmission execution status; the transmission rate, delay and error rate in the data transmission execution status are monitored in real time to obtain a transmission performance index; according to the transmission performance index, the transmission task allocation and channel priority are dynamically adjusted in combination with the RAID disk array technology to obtain an optimized data transmission strategy; based on the optimized data transmission strategy, the receiving end buffer occupancy is analyzed to obtain an adaptive flow control parameter, and the data sending rate is adjusted according to the adaptive flow control parameter.

[0042] Specifically, the implementation process of the technical solution first configures the data transmission path between the transmission channel and the RAID disk array according to the data transmission execution plan. This step involves setting the transmission parameters of the PCIe interface to fully utilize the high-speed transmission capabilities of the RAID disk array. Specifically, PCIe Gen 3.0x4 or PCIe Gen4.0x4 channels will be configured, which can provide 3.938GB / s and 7.877GB / s of data transmission capabilities respectively. Combined with RAID disk array technology, the data transmission capacity can be increased to a high-speed transmission mode of 15.754GB / s. This configuration process includes setting the registers of the PCIe controller, determining the data packet size, and optimizing the transmission queue depth to establish a high-speed data transmission path.

[0043] Specifically, after establishing a high-speed data transmission path, the DMA controller is parameterized and the transmission buffer is prepared through this path. The parameter setting of the DMA controller includes configuring the source address and destination address registers, setting the transmission data size, and defining the transmission direction (from memory to device or from device to memory). At the same time, transmission buffers are prepared in the host memory and RAID disk array respectively. The size and location of these buffers are optimized to maximize data throughput and minimize transmission latency. The result of these settings and preparations is a complete data transmission initialization configuration, which lays the foundation for subsequent efficient data transmission. Based on this data transmission initialization configuration, the transmission process of the data to be transmitted from the source address to the destination address is started through the PCIe interface. The startup process includes sending a command to start the transmission to the DMA controller and activating the data transmission mechanism of the PCIe interface. The timestamp of the start of the transmission is recorded, and various indicators during the transmission process, such as the amount of data transferred and the current transmission rate, are continuously monitored. This information constitutes the data transmission execution status, which provides a real-time snapshot of the transmission process.

[0044] Specifically, as data transmission proceeds, the transmission rate, delay, and error rate in the data transmission execution state are monitored in real time. This monitoring process uses the performance counters and error detection mechanisms of the PCIe interface to regularly collect transmission performance data. The transmission rate is obtained by calculating the amount of data successfully transmitted per unit time, and the delay is determined by measuring the time from the sending to the receiving of the data packet. The error rate is calculated based on the number of CRC check failures and the frequency of retransmission requests. These data are integrated into a set of comprehensive transmission performance indicators, which reflect the efficiency and reliability of current data transmission. Based on these transmission performance indicators, the transmission task allocation and channel priority are dynamically adjusted in combination with RAID disk array technology. If the performance of a transmission channel is detected to be degraded, the transmission task will be reallocated to transfer part of the data to the channel with better performance. At the same time, the priority of each channel will be adjusted to ensure that critical data can be transmitted first. The characteristics of the RAID disk array are fully utilized. For example, in RAID 0 mode, the data striping strategy will be optimized to maximize the parallel transmission efficiency. The result of these adjustments is an optimized data transmission strategy that can dynamically adjust the transmission configuration according to real-time performance.

[0045] Specifically, finally, based on the optimized data transmission strategy, the receiving end buffer occupancy is analyzed and processed. This analysis process includes monitoring the fill rate of the receiving buffer, the data processing speed, and the possible buffer overflow risk. Through these analyses, a set of adaptive flow control parameters are obtained, which reflect the receiving end's ability to process data and the current load status. According to these adaptive flow control parameters, the data sending rate is adjusted in real time. If the receiving end buffer is close to saturation, the sending rate will be reduced to prevent data loss; conversely, if the buffer is relatively empty, the sending rate will be increased to improve transmission efficiency.

[0046] In this embodiment, the expansion card device connected to the PCIe interface on the GPU is identified and the address space is mapped to obtain the GPU data transmission configuration information; according to the configuration information, the storage space of the expansion card device is divided and the transmission channel is established to obtain the GPU data transmission channel configuration result; based on the configuration result and the preset CUDA shared storage mechanism, the GPU data to be transmitted is scheduled and allocated to obtain the data transmission execution plan; according to the execution plan and the preset RAID disk array, the transmission process of the data to be transmitted is started, controlled, monitored in real time and dynamically adjusted. The present invention effectively expands the available storage space of the GPU, optimizes the data transmission process, and significantly improves the data transmission efficiency of the GPU when processing large-scale data sets, while maintaining a low hardware cost.

[0047] The above describes the method for improving the data transmission efficiency in the embodiment of the present invention. The following describes the device for improving the data transmission efficiency in the embodiment of the present invention. Figure 2 , an embodiment of a device for improving data transmission efficiency in an embodiment of the present invention includes: The device initialization module 201 is used to perform device identification and address space mapping processing on the expansion card device connected to the PCIe interface on the GPU to obtain GPU data transmission configuration information; A channel configuration module 202 is used to perform storage space division and transmission channel establishment processing on the expansion card device according to the GPU data transmission configuration information to obtain a GPU data transmission channel configuration result; The data scheduling module 203 is used to schedule and allocate the data to be transmitted of the GPU based on the GPU data transmission channel configuration result and the preset CUDA shared storage mechanism to obtain a data transmission execution plan; The transmission control module 204 is used to start and control the data transmission process of the data to be transmitted according to the data transmission execution plan and the preset RAID disk array, and to monitor and dynamically adjust the transmission status of the data to be transmitted in real time during the transmission process.

[0048] In an embodiment of the present invention, the data transmission efficiency improvement device runs the above-mentioned data transmission efficiency improvement method, and the data transmission efficiency improvement device obtains GPU data transmission configuration information by performing device identification and address space mapping on the expansion card device connected to the PCIe interface on the GPU; according to the configuration information, the storage space of the expansion card device is divided and the transmission channel is established to obtain the GPU data transmission channel configuration result; based on the configuration result and the preset CUDA shared storage mechanism, the GPU data to be transmitted is scheduled and allocated to obtain the data transmission execution plan; according to the execution plan and the preset RAID disk array, the transmission process of the data to be transmitted is started, controlled, monitored in real time and dynamically adjusted. The present invention effectively expands the available storage space of the GPU, optimizes the data transmission process, and significantly improves the data transmission efficiency of the GPU when processing large-scale data sets by introducing the expansion card device and the RAID disk array, combined with the CUDA shared storage mechanism, while maintaining a low hardware cost.

[0049] above Figure 2 The data transmission efficiency improvement device in the embodiment of the present invention is described in detail from the perspective of modular functional entities, and the data transmission efficiency improvement device in the embodiment of the present invention is described in detail from the perspective of hardware processing.

[0050] Figure 3 3 is a schematic diagram of the structure of a data transmission efficiency improvement device provided by an embodiment of the present invention. The data transmission efficiency improvement device 300 may have relatively large differences due to different configurations or performances, and may include one or more processors (central processing units, CPU) 310 and memory 320, and one or more storage media 330 (for example, one or more mass storage device terminals) storing application programs 333 or data 332. Among them, the memory 320 and the storage medium 330 can be short-term storage or permanent storage. The program stored in the storage medium 330 may include one or more modules (not shown in the figure), and each module may include a series of instruction operations in the data transmission efficiency improvement device 300. Furthermore, the processor 310 can be configured to communicate with the storage medium 330, and execute a series of instruction operations in the storage medium 330 on the data transmission efficiency improvement device 300 to implement the steps of the above-mentioned data transmission efficiency improvement method.

[0051] The data transmission efficiency improvement device 300 may also include one or more power supplies 340, one or more wired or wireless network interfaces 350, one or more input and output interfaces 360, and / or one or more operating systems 331, such as Windows Server, Mac OS X, Unix, Linux, FreeBSD, etc. Those skilled in the art will appreciate that Figure 3 The structure of the data transmission efficiency improvement device shown does not constitute a limitation on the data transmission efficiency improvement device provided by the present invention, and may include more or fewer components than shown in the figure, or a combination of certain components, or a different arrangement of components.

[0052] The present invention also provides a computer-readable storage medium, which may be a non-volatile computer-readable storage medium or a volatile computer-readable storage medium. Instructions are stored in the computer-readable storage medium. When the instructions are executed on a computer, the computer executes the steps of the method for improving data transmission efficiency.

[0053] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the above-described system, device, or unit can refer to the corresponding process in the aforementioned method embodiment and will not be repeated here.

[0054] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art or the whole or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program code.

[0055] As described above, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features thereof may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for improving data transmission efficiency, characterized in that: The method for improving data transmission efficiency comprises: Perform device identification and address space mapping on the expansion card device connected to the PCIe interface on the GPU to obtain GPU data transmission configuration information; According to the GPU data transmission configuration information, the expansion card device is subjected to storage space division and transmission channel establishment processing to obtain a GPU data transmission channel configuration result; Based on the GPU data transmission channel configuration result and the preset CUDA shared storage mechanism, the GPU data to be transmitted is scheduled and allocated to obtain a data transmission execution plan; According to the data transmission execution scheme and the preset RAID disk array, the data transmission process of the data to be transmitted is started and controlled, and the transmission status of the data to be transmitted is monitored and dynamically adjusted in real time during the transmission process.

2. The method for improving data transmission efficiency according to claim 1, characterized in that: The device identification and address space mapping process of the expansion card device connected to the PCIe interface on the GPU to obtain the GPU data transmission configuration information includes: Connect the expansion card device through the PCIe interface on the GPU, and perform VID / DID reading and BDF structure scanning processing on the expansion card device to obtain a device identification code; According to the device identification code, the storage space size detection process is performed on the expansion card device through the BAR register of the configuration space in the PCIe interface to obtain available storage space information; The CPU performs address range allocation processing on the expansion card device according to the storage space information to obtain GPU data transmission configuration information.

3. The method for improving data transmission efficiency according to claim 2, characterized in that: The process of performing storage space size detection on the expansion card device through the BAR register of the configuration space in the PCIe interface according to the device identification code to obtain the available storage space information includes: According to the device identification code, a configuration address register of the PCIe interface is set to obtain an access address for accessing a configuration space of the expansion card device; Based on the access address, write all 1s to the BAR register in the configuration space of the expansion card device to obtain the initial state value of the BAR register; Reading the BAR register of the initial state value to obtain a register return value containing unmodifiable bit information; Calculate the storage space size of the expansion card device according to the unmodifiable bit information in the register return value to obtain the storage capacity value of the expansion card device; Based on the storage capacity value and the attribute bit information in the register return value, the storage space type and access characteristics of the expansion card device are identified to obtain available storage space information including storage space size, type and access attributes.

4. The method for improving data transmission efficiency according to claim 1, characterized in that: The step of performing storage space division and transmission channel establishment processing on the expansion card device according to the GPU data transmission configuration information to obtain the GPU data transmission channel configuration result includes: Controlling the root complex of the PCIe interface through the CPU to divide the storage space of the expansion card device into a running capacity area and a cache area according to the GPU data transmission configuration information, so as to obtain a storage area division result of GPU operation; Setting the BME bit and the MSE bit in the configuration space of the expansion card device through the command register of the root complex to obtain a basic configuration that allows DMA requests and controller register access; According to the storage area division result and the basic configuration, a data transmission channel between the kernel function of the GPU and each storage area is established, and the physical parameters, bandwidth allocation and priority of the data transmission channel are set to obtain the GPU data transmission channel configuration result.

5. The method for improving data transmission efficiency according to claim 1, characterized in that: The step of scheduling and allocating the data to be transmitted on the GPU based on the GPU data transmission channel configuration result and the preset CUDA shared storage mechanism to obtain the data transmission execution plan includes: In the kernel function of the GPU, a preset shared keyword is used to declare the expansion card device, and the HBM expansion firmware check process is performed on the program version in the expansion card device to obtain an extension declaration; According to the extended declaration and the GPU data transmission channel configuration result, the access frequency, data size and correlation analysis and processing of the data to be transmitted are performed to obtain data feature information; Based on the data characteristic information, the data to be transmitted is allocated between the high-bandwidth memory and the storage space of the expansion card device to obtain a data allocation plan; According to the data allocation scheme and the GPU data transmission channel configuration result, the transmission channel and transmission priority of each data block are selected and processed to obtain the data transmission execution scheme including the data block source address, target address, transmission channel and transmission priority.

6. The method for improving data transmission efficiency according to claim 5, characterized in that: The expansion card device is declared using a preset shared keyword in the kernel function of the GPU, and the HBM expansion firmware check is performed on the program version in the expansion card device to obtain an extended declaration including: Preprocessing the kernel function code of the GPU to obtain a code segment of a shared keyword, and inserting a device identification code of the expansion card device into the code segment to obtain a shared memory declaration statement of the extended memory; Performing syntax parsing on the shared memory declaration statement to obtain a parameter list including the storage space size of the expansion card device; According to the parameter list, the HBM firmware version of the expansion card device is detected, and based on the HBM firmware version, the extended shared memory declaration statement is conditionally compiled to obtain the extended declaration of the expansion card device adapted to the HBM firmware version.

7. The method for improving data transmission efficiency according to claim 1, characterized in that: The method of starting and controlling the data transmission process of the data to be transmitted according to the data transmission execution scheme and the preset RAID disk array, and monitoring and dynamically adjusting the transmission status of the data to be transmitted in real time during the transmission process includes: According to the data transmission execution scheme, a data transmission path between a transmission channel and a RAID disk array is configured and processed to obtain a high-speed data transmission path; Through the high-speed data transmission path, the DMA controller is parameterized and the transmission buffer is prepared to obtain a data transmission initialization configuration; Based on the data transmission initialization configuration, a transmission process of the data to be transmitted from the source address to the target address is started through the PCIe interface to obtain a data transmission execution state; Performing real-time monitoring and processing on the transmission rate, delay and error rate in the data transmission execution state to obtain transmission performance indicators; According to the transmission performance index, the transmission task allocation and channel priority are dynamically adjusted in combination with RAID disk array technology to obtain an optimized data transmission strategy; Based on the optimized data transmission strategy, the occupancy of the receiving end buffer is analyzed and processed to obtain adaptive flow control parameters, and the data transmission rate is adjusted according to the adaptive flow control parameters.

8. A device for improving data transmission efficiency, characterized in that: The data transmission efficiency improving device comprises: The device initialization module is used to perform device identification and address space mapping processing on the expansion card device connected to the PCIe interface on the GPU to obtain GPU data transmission configuration information; A channel configuration module is used to perform storage space division and transmission channel establishment processing on the expansion card device according to the GPU data transmission configuration information to obtain a GPU data transmission channel configuration result; A data scheduling module is used to schedule and allocate the data to be transmitted of the GPU based on the GPU data transmission channel configuration result and the preset CUDA shared storage mechanism to obtain a data transmission execution plan; The transmission control module is used to start and control the data transmission process of the data to be transmitted according to the data transmission execution plan and the preset RAID disk array, and to monitor and dynamically adjust the transmission status of the data to be transmitted in real time during the transmission process.

9. A device for improving data transmission efficiency, characterized in that: The data transmission efficiency improvement device comprises: a memory and at least one processor, wherein instructions are stored in the memory; The at least one processor calls the instruction in the memory so that the data transmission efficiency improvement device executes the steps of the data transmission efficiency improvement method as described in any one of claims 1-7.

10. A computer-readable storage medium having instructions stored thereon, characterized in that: When the instructions are executed by the processor, the steps of the method for improving data transmission efficiency as described in any one of claims 1 to 7 are implemented.

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