Communication interface multiplexing method and system in multi-bare-core operation environment

Abstract

The invention discloses a communication interface multiplexing method and system in a multi-bare-core operation environment. According to the method, a shared data space is developed in a multi-core CPU memory, sending and receiving descriptors and handle information of a network communication interface are stored, and control over the same communication interface by multiple cores is achieved. Shared variables are stored in a shared data space for inter-core coordination of a data ready state. In a sending scene, multiple cores respond to synchronous interruption, data are prepared and synchronized through a shared variable, and the data are uniformly sent by the last core. And during receiving, the specified core checks and notifies other cores that the message arrives, and each core processes the message according to the provided address. According to the method, multi-core multiplexing of a single communication interface is effectively realized, hardware circuit switching is avoided, and data transmission consistency and system efficiency are ensured.

Description

Technical Field

[0001] The present invention belongs to the field of communication, and in particular relates to a communication interface multiplexing method and system in a multi-bare core operating environment. Background Art

[0002] In the current power system, due to the existence of large amounts of data and complex calculations, it is difficult for a single-core CPU to meet the requirements of real-time performance and reliability. The application of multi-core CPUs and multi-processor board devices can greatly improve the processing power and reliability of the system. By assigning tasks to multiple processors or boards, parallel processing of tasks is achieved, which improves the system processing speed. In addition, when a processor or board fails, other processors or boards can continue to work, thereby ensuring the reliability of the system.

[0003] Bare core refers to a program that runs directly on the hardware without operating system support. In embedded systems, bare core programs are usually used to implement specific hardware control or real-time processing tasks. In order to meet the real-time requirements of relay protection devices, relay protection devices often use bare core programs to implement their protection functions to ensure that the faulty part can be quickly and accurately cut off when a fault occurs in the power system.

[0004] In the multi-core and multi-board type devices of the power system, the communication interface is the key part to realize the data transmission between the multi-core boards. The use of efficient communication protocols and interface technologies can ensure the real-time and reliability of data transmission. Considering the limited number of high-speed interfaces of multi-core processors, a single communication link is often used between the multi-core board and other boards to realize data interaction between the multi-core board and other boards.

[0005] In the prior art, there are two solutions for data interaction between multi-core boards and other boards that can meet basic requirements: (1) When a multi-core board communicates with other boards through a single communication link, the multi-core bare-core board only starts one core, and the other cores are in a dormant or idle state; (2) When a multi-core board communicates with other boards through a single communication link, a certain core is used as a data proxy, and the proxy core receives data between boards and distributes it to other cores; the data sent by non-proxy cores is summarized by the proxy core and then sent to other boards by the proxy core.

[0006] However, although solution (1) is simple to implement, it only runs one core, and the performance of other cores is idle, which greatly wastes the performance of multi-core CPUs. In solution (2), when a multi-core board communicates with other boards through a single communication link, a certain core needs to be used as a data proxy. The proxy core needs to deploy complex management tasks, which increases the operating burden of the proxy core, greatly weakens the advantages of multiple bare cores and multiple boards, and fails to give full play to the performance of hardware equipment. Summary of the invention

[0007] Purpose of the invention: In order to solve the problem that cores are idle when a multi-core board communicates with other boards through a single communication link and a certain core needs to be used for data proxy, the present invention provides a communication interface multiplexing method and system in a multi-bare-core operating environment, so that multiple cores (hosts) on a multi-bare-core board can reuse a single communication link at the same time.

[0008] Technical solution: In the first aspect, a communication interface multiplexing method in a multi-bare core operating environment comprises the following steps:

[0009] A shared data space is opened in the memory of the multi-core CPU for storing a send descriptor, a receive descriptor and related handle information associated with the network communication interface, so that multiple cores can control the same network communication interface controller;

[0010] Register shared variables in the shared data space to allow multiple cores to determine whether the data is ready to be sent or received.

[0011] In the sending scenario, multiple cores respond to synchronous interrupts and prepare to send data in their respective interrupt tasks. Multiple cores judge the data preparation status of other cores through shared variables. The last core that is ready sends the data of all cores to other boards through the network communication interface controller. After completing the interrupt task, any core decides whether to send data directly or return according to the data ready flags of other cores.

[0012] In the receiving scenario, multiple cores respond to synchronous interrupts. When the interrupt starts, the designated core checks whether there are network communication messages sent by other boards. If so, the starting address of the received message buffer is notified to other cores through the shared data space, and the received messages are processed; other cores process the network communication messages from other boards in the interrupt according to the starting address of the message buffer provided by the shared data space.

[0013] Furthermore, the information stored in the shared data space includes: for the sending scenario, it includes: network communication interface status, sending buffer, sending descriptor, sending sequence number, and sending preparation completion flag; for the receiving scenario, it includes: network communication interface status, receiving buffer, receiving descriptor, receiving sequence number, and receiving data flag.

[0014] Furthermore, in the sending scenario, the multi-core specific processing flow is as follows:

[0015] Specify a core configuration delay flag among multiple cores;

[0016] At the start of the synchronous interrupt response function, each core clears the send preparation completion flag of the core, and then after executing its own application task, checks whether the send preparation completion flag of other cores in the shared data space is set:

[0017] (a) If the send preparation completion flags of other cores are all set, it means that other cores are ready to send data to other boards. At this time, this core will package its own and other cores' data and send them to other boards through the data communication interface;

[0018] (b) If the send ready flag of any core in other cores is not set, it means that there is a core that is not ready to send data to other boards at present, and it is called an unready core. Then this core will first set its own send ready flag and check whether the delay flag is configured for this core. If the delay flag is configured, it will check whether the send ready flag of the unready core is set after a specified delay time. If it is set, execute the steps in (a). If it is not set, the unready core will package the data after completing the task and send the data to other boards through the network communication interface. The core will complete the interrupt task and exit the interrupt task function. If the delay flag is not configured for this core, the interrupt task will be completed and the interrupt task function will be exited after the send ready flag of this core is set.

[0019] Furthermore, under the receiving scenario, the multi-core specific processing flow is as follows:

[0020] A designated core in the multi-core checks whether there are network communication messages sent by other boards at the beginning of the interruption. If there are, the starting address of the received message buffer is stored in the shared data space, and the received data flag is set. The designated core then processes the received network communication messages of other boards;

[0021] The other cores in the multi-core query whether the receive data flag is set within a period of time when the interrupt starts. If it is set, they obtain the starting address of the receive message buffer from the shared data space, process the network communication messages received from other boards, and finally clear the receive data flag; if the receive data flag is still not set when the query time expires, it is considered that there are no other board network communication messages that need to be processed in this interrupt.

[0022] In a second aspect, a communication interface multiplexing system in a multi-bare core operating environment includes:

[0023] A shared data space building module is used to open a shared data space in the memory of the multi-core CPU for storing a send descriptor, a receive descriptor and related handle information associated with the network communication interface, so that multiple cores can control the same network communication interface controller;

[0024] The shared variable registration module is used to register shared variables in the shared data space, so that multiple cores can judge whether the data is ready to be sent or received.

[0025] The sending logic control block is used to realize multiple cores responding to synchronous interrupts in the sending scenario and preparing to send data in their respective interrupt tasks. Multiple cores judge the data preparation status of other cores through shared variables. The last core that is ready sends the data of all cores to other boards through the network communication interface controller. After completing the interrupt task, any core decides whether to send data directly or return according to the data ready flag of other cores.

[0026] The receiving logic control module is used to realize multiple cores responding to synchronous interrupts in the receiving scenario. The designated core checks whether there are network communication messages sent by other boards at the beginning of the interrupt. If so, the starting address of the received message buffer is notified to other cores through the shared data space, and the received messages are processed; other cores process the network communication messages from other boards in the interrupt according to the starting address of the message buffer provided by the shared data space.

[0027] In a third aspect, a multi-core CPU is provided, wherein multiple cores realize message interaction with other boards by reusing the same communication interface, a shared data space is opened in the memory of the multi-core CPU for storing a sending descriptor, a receiving descriptor and related handle information associated with a network communication interface, so that multiple cores can control the same network communication interface controller; a shared variable is stored in the shared data space for the multiple cores to mutually judge whether sending data is ready and receiving data is ready;

[0028] In the sending scenario, multiple cores respond to synchronous interrupts and prepare to send data in their respective interrupt tasks. Multiple cores judge the data preparation status of other cores through shared variables. The last core that is ready sends the data of all cores to other boards through the network communication interface controller. After completing the interrupt task, any core decides whether to send data directly or return according to the data ready flags of other cores.

[0029] In the receiving scenario, multiple cores respond to synchronous interrupts. When the interrupt starts, the designated core checks whether there are network communication messages sent by other boards. If so, the starting address of the received message buffer is notified to other cores through the shared data space, and the received messages are processed; other cores process the network communication messages from other boards in the interrupt according to the starting address of the message buffer provided by the shared data space.

[0030] A fourth aspect provides a computing device, comprising the multi-core CPU described in the third aspect.

[0031] In a fifth aspect, a computer device comprises one or more processors; a memory; and one or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by the one or more processors, and when the programs are executed by the processors, the steps of the communication interface multiplexing method in a multi-bare core operating environment as described in the first aspect are implemented.

[0032] In a sixth aspect, a computer storage medium stores a computer program thereon, characterized in that when the computer program is executed by a processor, the steps of the communication interface multiplexing method in a multi-bare-core operating environment as described in the first aspect are implemented.

[0033] Beneficial effects: In the present invention, a multi-core CPU can reuse the same communication interface to exchange data with other boards, without going through a data proxy or switching hardware circuits, and functional decoupling is achieved between multiple cores, ensuring consistency of data transmission and system efficiency. At the same time, the design of the bus board and the system is simplified, and the reliability of the system is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a flow chart of a communication interface multiplexing method in a multi-bare core operating environment;

[0035] Figure 2 Sending flow chart for core 1 in dual-core CPU scenario;

[0036] Figure 3 Sending flow chart for core 2 in dual-core CPU scenario;

[0037] Figure 4 This is the receiving flow chart of core 1 in the dual-core CPU scenario;

[0038] Figure 5 This is the receiving flow chart of core 2 in the dual-core CPU scenario;

[0039] Figure 6 This is a typical application scenario diagram of the present invention. DETAILED DESCRIPTION

[0040] The technical solutions in the embodiments of the present invention will be described clearly and completely below with reference to the accompanying drawings.

[0041] Reference Figure 1 The present invention provides a communication interface multiplexing method in a multi-bare core operating environment, comprising the following steps:

[0042] Step S102: Opening a shared data space in the memory of the multi-core CPU for storing a send descriptor, a receive descriptor and related handle information associated with the network communication interface, so that multiple cores can control the same network communication interface controller;

[0043] Step S104: registering a shared variable in a shared data space, so that multiple cores can mutually judge whether the sending data is ready and whether the receiving data is ready;

[0044] Step S106: In the sending scenario, multiple cores respond to synchronous interrupts and prepare to send data in their respective interrupt tasks. Multiple cores judge the data preparation status of other cores through shared variables. The last core that is ready sends the data of all cores to other boards through the network communication interface controller. After completing the interrupt task, any core decides whether to send data directly or return according to the data ready flags of other cores.

[0045] Step S108: In the receiving scenario, multiple cores respond to synchronous interrupts, and the designated core checks whether there are network communication messages sent by other boards at the beginning of the interrupt. If so, the starting address of the received message buffer is notified to other cores through the shared data space, and the received messages are processed; other cores process the network communication messages from other boards in the interrupt according to the starting address of the message buffer provided by the shared data space.

[0046] In step 106, the present invention avoids conflicts in which multiple cores are set at the same time by specifying the delay query function of the core. Specifically, a core is arbitrarily specified among multiple cores to configure a delay flag for it; for each core, at the start time of the synchronous interrupt response function, the sending preparation completion flag of the core is cleared, and then after executing its own application task, the sending preparation completion flag of other cores in the shared data space is checked to see whether it is set:

[0047] (a) If the send preparation completion flags of other cores are all set, it means that other cores are ready to send data to other boards. At this time, this core will package its own and other cores' data and send them to other boards through the data communication interface;

[0048] (b) If the send ready flag of any core in other cores is not set, it means that there is a core that is not ready to send data to other boards at present, and it is called an unready core. Then this core will first set its own send ready flag and check whether the delay flag is configured for this core. If the delay flag is configured, it will check whether the send ready flag of the unready core is set after a specified delay time. If it is set, execute the steps in (a). If it is not set, the unready core will package the data after completing the task and send the data to other boards through the network communication interface. The core will complete the interrupt task and exit the interrupt task function. If the delay flag is not configured for this core, the interrupt task will be completed and the interrupt task function will be exited after the send ready flag of this core is set.

[0049] In step 108 of the present invention, the designated core in the multi-core executes the setting of the received data flag. When the interrupt starts, the designated core checks whether there are network communication messages sent by other boards. If there are, the starting address of the received message buffer is stored in the shared data space, and the received data flag is set. The designated core then processes the received network communication messages from other boards;

[0050] The other cores in the multi-core query whether the receive data flag is set within a period of time when the interrupt starts. If it is set, they obtain the starting address of the receive message buffer from the shared data space, process the network communication messages received from other boards, and finally clear the receive data flag; if the receive data flag is still not set when the query time expires, it is considered that there are no other board network communication messages that need to be processed in this interrupt.

[0051] Taking the dual-core as an example, the communication interface selects GMAC (Gigabit Media Access Controller). The dual-core reuses the same communication interface to send data to other boards. The process is as follows:

[0052] (a) A shared data space is created to store the GMAC transmit descriptor (Transmit Descriptor, abbreviated as transmit BD) and GMAC handle information (which stores information such as the GMAC transmit sequence number), so that both cores can control the GMAC controller.

[0053] (b) Register the dual-core shared variable in the shared data space, which is used by the dual-core to determine whether the data sent by the other core is ready.

[0054] (c) The dual cores respond to synchronous interrupts and prepare the data that the core needs to send to other boards in the interrupt task.

[0055] (d) The two cores each determine whether the other core is ready, and the core that prepares the data later sends the dual-core data to other boards through GMAC. After completing its own interrupt task, any core in the two cores chooses whether to send data directly or return according to the data ready flag of the other core, eliminating the invalid waiting time. The core that prepares the data later sends the data according to the interrupt beat, without the need for hardware circuit switching, so that multiple cores can use the same communication interface to send data to other boards.

[0056] The dual cores reuse the same communication interface to receive messages sent by other boards. The process is as follows:

[0057] (i) A shared data space is created to store the GMAC receive descriptor (Receive Descriptor, abbreviated as receive BD) and GMAC handle information (which stores information such as the GMAC receive sequence number), so that both cores can receive GMAC messages.

[0058] (ii) Registering a shared variable in the shared data space so that other cores can determine whether core 1 is in a ready state to receive data.

[0059] (iii) Dual cores respond to synchronous interrupts. Core 1 checks whether there are GMAC messages sent by other boards at the beginning of the interrupt. If there are messages, the start address of the received message buffer is notified to other cores through the shared data area, eliminating the need to copy the received message to the shared area. Core 1 processes the GMAC messages received from other boards during the interrupt.

[0060] (iv) Other cores process the GMAC messages sent by other boards in the interrupt according to the starting address of the message buffer area provided by core 1. This enables multiple cores to multiplex the same communication interface to receive messages sent by other boards, while ensuring data consistency.

[0061] Specifically, for the sending scenario, the GMAC usage status, sending BD, sending sequence number, multi-core data preparation completion flag and other contents required for sending the GMAC message are stored in the shared data area, as shown in Table 1. Both cores can obtain them, thereby achieving the purpose of both cores being able to send GMAC messages.

[0062] Table 1 The contents of the transmission stored in the shared data space

[0063]

[0064] In dual-core, specify to execute delayed query on core 1. The sending process of core 1 is as follows Figure 2 As shown, at the start of the multi-core synchronous interrupt response function, core 1 first clears the core 1 data ready flag READY_C1. Clearing means writing the value of the address where the flag is located to 0, which means writing the value of the address READY_C1 to 0. Then, after executing its own application task, core 1 checks whether the shared data area core 2 data ready flag READY_C2 is set. Setting means writing the value of the address where the flag is located to 1, which means checking whether the address value of READY_C2 is 1):

[0065] (a) If the READY_C2 flag is set, core 2 is ready to send data to other boards. At this time, core 1 packages the data of itself and core 2 and sends it to other boards through GMAC.

[0066] (b) If the READY_C2 flag is not set, it means that core 2 is not ready to send data to other boards. Core 1 first sets the data preparation completion flag READY_C1 of its own core. In order to avoid missing messages when both cores complete data preparation at the same time, core 1 delays for 1 microsecond and then checks whether READY_C2 is set. If it is set, execute the steps in (a); if it is not set, it means that core 1 has completed data preparation before core 2. After completion, core 2 will package the data and send the data to other boards through GMAC. Core 1 completes the interrupt task and exits the interrupt task function.

[0067] As shown in Table 1, each core has its own corresponding send buffer, BUF_C1 and BUF_C2, etc., which are also stored in the shared data area. Both cores can obtain and know the corresponding location. The packet is assembled by the core that completes the preparation work later, and the data of all core send buffers are spliced ​​together in the order of core numbers (core 1 data in front, core 2 data in the back).

[0068] The sending process of core 2 is as follows Figure 3 As shown. In the header of the multi-core synchronous interrupt response function, core 2 first clears the core 2 data preparation completion flag READY_C2. After core 2 completes the application task, it checks whether the shared data area core 1 data preparation completion flag READY_C1 is set:

[0069] (1) If the READY_C1 flag is set, core 1 is ready to send data to other boards. Core 2 packages the data of core 2 and core 1 and sends it to other boards through GMAC.

[0070] (b) If the READY_C1 flag is not set, that is, core 1 is not yet ready to send data to other boards, the core 2 data preparation completion flag READY_C2 is set, and core 2 completes the interrupt task and exits the interrupt task function.

[0071] The above describes the detailed process of the dual-core multiplexing communication interface. For 3 cores or more, the principle of the sending process for core 1 and core 2 remains unchanged. Core 1 and core 2 need to query whether core 3 is completed (i.e., READY_C3, etc.) or not. Core 3, etc. also need to query the data preparation completion flag of core 1 and core 2. Finally, the core that prepares the data last assembles the packets and sends them to all cores.

[0072] For the receiving scenario, the GMAC usage status, receiving BD, receiving sequence number, receiving data flag and other contents required for GMAC message reception are stored in the shared data area, as shown in Table 2. This achieves the purpose of both cores being able to receive GMAC messages.

[0073] Table 2 Received content stored in shared data space

[0074]

[0075]

[0076] In the dual cores, core 1 is designated to set the received data flag. The receiving process of core 1 is as follows: Figure 4 As shown. When the interrupt starts, core 1 checks whether there is a GMAC message sent by other boards. If so, the starting address of the received message buffer is stored in the shared data area (i.e., shared data space), and the received data flag is set. Core 1 then processes the GMAC messages received from other boards. The receiving process of core 2 is as follows Figure 5 As shown: Core 2 queries whether the received data flag is set at the beginning of the interrupt, until the query exceeds the set time. If the received data flag is set, the start address of the received message buffer is obtained from the shared data area, and the GMAC message received from other boards is processed, and finally the received data flag is cleared; if the received data flag is not set when the query time expires, it is considered that there is no GMAC message from other boards that needs to be processed in this interrupt.

[0077] For 3 cores and above, the receiving process is exactly the same as that of core 2. Core 3 and others query whether the received data flag is set at the beginning of the interrupt until the query exceeds the set time. If the received data flag is set, the starting address of the received message buffer is obtained from the shared data area, and the GMAC messages received from other boards are processed, and finally the received data flag is cleared; if the received data flag is not queried before the query timeout, it is considered that there are no GMAC messages from other boards that need to be processed in this interrupt.

[0078] Figure 6 A typical application scenario of the present invention is shown, where multi-core processing boards directly exchange data through the processor GMAC, without the need for FPGA to implement channel multiplexing, thereby reducing costs.

[0079] Based on the same technical concept as the method embodiment, the present invention also provides a communication interface multiplexing system in a multi-bare core operating environment, including:

[0080] A shared data space building module is used to open a shared data space in the memory of the multi-core CPU for storing a send descriptor, a receive descriptor and related handle information associated with the network communication interface, so that multiple cores can control the same network communication interface controller;

[0081] The shared variable registration module is used to register shared variables in the shared data space, so that multiple cores can judge whether the data is ready to be sent or received.

[0082] The sending logic control block is used to realize multiple cores responding to synchronous interrupts in the sending scenario and preparing to send data in their respective interrupt tasks. Multiple cores judge the data preparation status of other cores through shared variables. The last core that is ready sends the data of all cores to other boards through the network communication interface controller. After completing the interrupt task, any core decides whether to send data directly or return according to the data ready flag of other cores.

[0083] The receiving logic control module is used to realize multiple cores responding to synchronous interrupts in the receiving scenario. The designated core checks whether there are network communication messages sent by other boards at the beginning of the interrupt. If so, the starting address of the received message buffer is notified to other cores through the shared data space, and the received messages are processed; other cores process the network communication messages from other boards in the interrupt according to the starting address of the message buffer provided by the shared data space.

[0084] The present invention also provides a multi-core CPU, wherein multiple cores realize message interaction with other boards by reusing the same communication interface, a shared data space is opened in the memory of the multi-core CPU for storing a sending descriptor, a receiving descriptor and related handle information associated with the network communication interface, so that multiple cores can control the same network communication interface controller; a shared variable is stored in the shared data space for the multiple cores to mutually judge whether the sending data is ready and whether the receiving data is ready;

[0085] In the sending scenario, multiple cores respond to synchronous interrupts and prepare to send data in their respective interrupt tasks. Multiple cores judge the data preparation status of other cores through shared variables. The last core that is ready sends the data of all cores to other boards through the network communication interface controller. After completing the interrupt task, any core decides whether to send data directly or return according to the data ready flags of other cores.

[0086] In the receiving scenario, multiple cores respond to synchronous interrupts. When the interrupt starts, the designated core checks whether there are network communication messages sent by other boards. If so, the starting address of the received message buffer is notified to other cores through the shared data space, and the received messages are processed; other cores process the network communication messages from other boards in the interrupt according to the starting address of the message buffer provided by the shared data space.

[0087] The present invention also provides a computing device, which includes the multi-core CPU.

[0088] The present invention also provides a computer device, which includes one or more processors; a memory; and one or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by the one or more processors, and when the programs are executed by the processors, the steps of the communication interface multiplexing method in a multi-bare core operating environment are implemented.

[0089] The present invention also provides a computer storage medium on which a computer program is stored, characterized in that when the computer program is executed by a processor, the steps of the communication interface multiplexing method in a multi-bare core operating environment are implemented.

[0090] It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, devices (systems), computer equipment or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0091] The present invention is described with reference to a flowchart of a method according to an embodiment of the present invention. It should be understood that each process in the flowchart and a combination of processes in the flowchart can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the process in the flowchart. Figure 1 A device that specifies functions in a process or multiple processes.

[0092] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A function specified in a process or multiple processes.

[0093] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 The steps of a specified function in a process or multiple processes.

Claims

1. A communication interface multiplexing method in a multi-bare core operating environment, characterized in that: The following steps are involved: A shared data space is opened in the memory of the multi-core CPU for storing a send descriptor, a receive descriptor and related handle information associated with the network communication interface, so that multiple cores can control the same network communication interface controller; Register shared variables in the shared data space to allow multiple cores to determine whether the data is ready to be sent or received. In the sending scenario, multiple cores respond to synchronous interrupts and prepare to send data in their respective interrupt tasks. Multiple cores judge the data preparation status of other cores through shared variables. The last core that is ready sends the data of all cores to other boards through the network communication interface controller. After completing the interrupt task, any core decides whether to send data directly or return according to the data ready flags of other cores. In the receiving scenario, multiple cores respond to synchronous interrupts. When the interrupt starts, the designated core checks whether there are network communication messages sent by other boards. If so, the starting address of the received message buffer is notified to other cores through the shared data space, and the received messages are processed; other cores process the network communication messages from other boards in the interrupt according to the starting address of the message buffer provided by the shared data space.

2. The method according to claim 1, characterized in that The information stored in the shared data space includes: for the sending scenario, it includes: network communication interface status, sending buffer, sending descriptor, sending sequence number, and sending preparation completion flag; for the receiving scenario, it includes: network communication interface status, receiving buffer, receiving descriptor, receiving sequence number, and receiving data flag.

3. The method according to claim 2, characterized in that In the sending scenario, the specific multi-core processing flow is as follows: Specify a core configuration delay flag among multiple cores; At the start of the synchronous interrupt response function, each core clears the send preparation completion flag of the core, and then after executing its own application task, checks whether the send preparation completion flag of other cores in the shared data space is set: (a) If the send preparation completion flags of other cores are all set, it means that other cores are ready to send data to other boards. At this time, this core will package its own and other cores' data and send them to other boards through the data communication interface; (b) If the send ready flag of any core in other cores is not set, it means that there is a core that is not ready to send data to other boards at present, and it is called an unready core. Then this core will first set its own send ready flag and check whether the delay flag is configured for this core. If the delay flag is configured, it will check whether the send ready flag of the unready core is set after a specified delay time. If it is set, execute the steps in (a). If it is not set, the unready core will package the data after completing the task and send the data to other boards through the network communication interface. The core will complete the interrupt task and exit the interrupt task function. If the delay flag is not configured for this core, the interrupt task will be completed and the interrupt task function will be exited after the send ready flag of this core is set.

4. The method according to claim 2, characterized in that: In the receiving scenario, the multi-core specific processing flow is as follows: A designated core in the multi-core checks whether there are network communication messages sent by other boards at the beginning of the interruption. If there are, the starting address of the received message buffer is stored in the shared data space, and the received data flag is set. The designated core then processes the received network communication messages of other boards; The other cores in the multi-core query whether the receive data flag is set within a period of time when the interrupt starts. If it is set, they obtain the starting address of the receive message buffer from the shared data space, process the network communication messages received from other boards, and finally clear the receive data flag; if the receive data flag is still not set when the query time expires, it is considered that there are no other board network communication messages that need to be processed in this interrupt.

5. The method according to claim 1, characterized in that The network communication interface is the GMAC interface.

6. A communication interface multiplexing system in a multi-bare core operating environment, characterized in that: include: A shared data space building module is used to open a shared data space in the memory of the multi-core CPU for storing a send descriptor, a receive descriptor and related handle information associated with the network communication interface, so that multiple cores can control the same network communication interface controller; The shared variable registration module is used to register shared variables in the shared data space, so that multiple cores can judge whether the data is ready to be sent or received. The sending logic control block is used to realize multiple cores responding to synchronous interrupts in the sending scenario and preparing to send data in their respective interrupt tasks. Multiple cores judge the data preparation status of other cores through shared variables. The last core that is ready sends the data of all cores to other boards through the network communication interface controller. After completing the interrupt task, any core decides whether to send data directly or return according to the data ready flag of other cores. The receiving logic control module is used to realize multiple cores responding to synchronous interrupts in the receiving scenario. The designated core checks whether there are network communication messages sent by other boards at the beginning of the interrupt. If so, the starting address of the received message buffer is notified to other cores through the shared data space, and the received messages are processed; other cores process the network communication messages from other boards in the interrupt according to the starting address of the message buffer provided by the shared data space.

7. A multi-core CPU, characterized in that: Multiple cores realize message interaction with other boards by reusing the same communication interface. A shared data space is opened in the memory of the multi-core CPU for storing the sending descriptor, receiving descriptor and related handle information associated with the network communication interface, so that multiple cores can control the same network communication interface controller; shared variables are stored in the shared data space for the multiple cores to judge whether the sending data is ready and whether the receiving data is ready; In the sending scenario, multiple cores respond to synchronous interrupts and prepare to send data in their respective interrupt tasks. Multiple cores judge the data preparation status of other cores through shared variables. The last core that is ready sends the data of all cores to other boards through the network communication interface controller. After completing the interrupt task, any core decides whether to send data directly or return according to the data ready flags of other cores. In the receiving scenario, multiple cores respond to synchronous interrupts. When the interrupt starts, the designated core checks whether there are network communication messages sent by other boards. If so, the starting address of the received message buffer is notified to other cores through the shared data space, and the received messages are processed; other cores process the network communication messages from other boards in the interrupt according to the starting address of the message buffer provided by the shared data space.

8. A computing device, characterized in that: The device comprises the multi-core CPU as claimed in claim 7.

9. A computer storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by the processor, the steps of the communication interface multiplexing method in a multi-bare-core operating environment as described in any one of claims 1-5 are implemented.

10. A computer device, characterized in that: include: one or more processors; Memory; And one or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by the one or more processors, and when the programs are executed by the processors, the steps of the communication interface multiplexing method in a multi-bare-core operating environment as described in any one of claims 1-5 are implemented.

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