One-dimensional Gaussian fitting IP core based on FPGA and implementation method thereof

Abstract

The invention discloses a one-dimensional Gaussian fitting IP (intellectual property) core based on an FPGA (field programmable gate array) and an implementation method thereof. The invention relates to the technical field of network communication, and discloses an FPGA-based one-dimensional Gaussian fitting IP core, which comprises a communication interface, an input conversion module, a filling cache module, a fitting parameter solving module and an output conversion module, the communication interface comprises an AXI-Stream interface and an AXI-Lite interface; the IP soft core can be directly used in an FPGA or an embedded system comprising the FPGA, the application requirement of a high-speed and small-sized computing device is met, the IP soft core is directly embedded in design, a designer does not need to carry out development and design for one-dimensional Gaussian fitting, the development cost is reduced, and the period is shortened.

Description

Technical Field

[0001] The present invention relates to the technical field of network communication, and in particular to a one-dimensional Gaussian fitting IP core based on FPGA and an implementation method thereof. Background Art

[0002] At present, the development and implementation of one-dimensional Gaussian fitting algorithms are mostly carried out on microcontroller units (MCU), digital signal processors (DSP), and central processing units (CPU). When processing one-dimensional Gaussian fitting algorithms, microcontrollers and digital signal processors often cannot meet the needs of high-speed data processing due to their own architecture and resource limitations, which greatly limits the wide application and in-depth development of one-dimensional Gaussian fitting technology in fields with strict requirements on real-time performance and response speed. The central processing unit has powerful general computing capabilities and can use software algorithms to achieve accurate and rapid modeling of one-dimensional Gaussian fitting. However, the CPU has inherent disadvantages in miniaturization, and it is difficult to integrate the CPU-based Gaussian fitting processing system into small devices or embedded systems with strict requirements on volume and power consumption. At present, there is no general one-dimensional Gaussian fitting intellectual property (IP) soft core, and technicians need to spend a lot of time designing algorithms according to specific hardware when using Gaussian fitting scenarios. Therefore, it is necessary to propose a one-dimensional Gaussian fitting IP core based on FPGA and its implementation method to solve the above problems. Summary of the invention

[0003] The present invention provides a one-dimensional Gaussian fitting IP core based on FPGA and an implementation method thereof, so as to solve the problem that the CPU has inherent disadvantages in miniaturization and it is difficult to integrate the CPU-based Gaussian fitting processing system into a small device or embedded system with strict requirements on volume, power consumption, etc.

[0004] In a first aspect, the present invention provides a one-dimensional Gaussian fitting IP core based on FPGA, comprising: a communication interface, an input conversion module, a filling cache module, a fitting parameter solving module and an output conversion module; the communication interface comprises an AXI-Stream interface and an AXI-Lite interface;

[0005] The AXI-Stream interface is used to receive data to be fitted;

[0006] The input conversion module is used to convert the format of the data input by the AXI-Stream interface and send the converted data to the filling cache module;

[0007] The filling cache module is used to fill the Vandermonde matrix A and the matrix Y used to fit the quadratic polynomial using the least squares method according to the set number of fitting bits, and send the data to the fitting parameter solving module;

[0008] The fitting parameter solving module is used to receive the Vandermonde matrix A and the matrix Y filled by the filling cache module, calculate the fitting straight line parameters using the least squares method, obtain the mean, standard deviation, and peak height parameters of the one-dimensional Gaussian fitting through the conversion formula, and send the parameters to the output conversion module after the calculation is completed;

[0009] The output conversion module is used to confirm the parameters calculated by the fitting parameter solving module, convert the confirmed parameters into a format according to a set data format, and then output them;

[0010] The AXI-Lite interface is used to output the data output by the output conversion module and is responsible for the communication interaction between the IP core and the processor.

[0011] Furthermore, the input format of the input conversion module is configured as a floating point or fixed point decimal format.

[0012] Furthermore, the input conversion module is used to convert the data to be calculated input by the AXI-Stream interface into floating-point numbers, and obtain the X-axis coordinate x(n) and Y-axis coordinate y(n) of the data to be fitted in the Cartesian coordinate system, where n=0, 1, ..., m-1, and m is the number of fitting bits; and send the converted data to the filling cache module.

[0013] Furthermore, the number of fitting bits m is configured as any integer between 10 and 30, and the number of fitting bits determines the shapes of matrices involved in calculation in the filling cache module and the fitting parameter solving module.

[0014] Furthermore, the filling cache module is used to fill the Vandermonde matrix A and the matrix Y used for fitting the quadratic polynomial using the least squares method according to the set fitting bit number m, and send the data to the fitting parameter solving module;

[0015] The Vandermonde matrix A is:

[0016] ;

[0017] Where x0, x1, ..., x m-1 is the X-axis coordinate x(n) of the data to be fitted. The matrix Y is:

[0018] ;

[0019] Where y0, y1, ..., y m-1 is the Y-axis coordinate y(n) of the data to be fitted. ,ln ,··· It means taking the logarithm of each term of the input y(n).

[0020] Furthermore, the fitting parameter solving module is used to:

[0021] Calculate the Vandermonde matrix passed to the fill cache module The transposed matrix of ;

[0022] Calculate the parameters of the fitted line using the least squares method , t=0, 1, 2; parallel computing and , and After all calculations are completed, multiply them to get (t) , , where is the transposed matrix Directly multiply the matrix Y of the filling cache module input fitting parameter solution module; First, transpose the matrix Vandermonde matrix Multiply, then judge Is the determinant value 0? If If the determinant value is 0, the exception flag position is 1, such as If the determinant value is not 1, then Take the inverse matrix and calculate ;

[0023] The fitting parameters are obtained by parallel calculation through the following conversion formula:

[0024] ;

[0025] In the formula, , , This corresponds to fitting the coefficients of a quadratic polynomial function using the least squares method. is the mean of the one-dimensional Gaussian fit, is the standard deviation, h is the peak height parameter;

[0026] To determine the output data, When the determinant value is not 0, the output value is the calculated one-dimensional Gaussian fitting parameter. The determinant value is 0, and the output one-dimensional Gaussian fitting parameters are replaced by three identical set numbers.

[0027] Furthermore, the output format of the output conversion module is configured as a floating point or fixed point decimal format.

[0028] In a second aspect, the present invention provides a method for implementing the above-mentioned one-dimensional Gaussian fitting IP core based on FPGA, comprising:

[0029] The FIFO module sequentially caches the data to be fitted and transmits the data to be fitted to the peak-finding module; the peak-finding module locates the maximum value of the data to be fitted, and takes a continuous data segment with the maximum value as the middle position and a length that is consistent with the number of fitting bits configured in the one-dimensional Gaussian fitting IP core, and streams the continuous data to the one-dimensional Gaussian fitting IP core based on FPGA, and the one-dimensional Gaussian fitting IP core based on FPGA uses the data to perform one-dimensional Gaussian fitting and outputs the mean value of the one-dimensional Gaussian fitting. , Standard Deviation , peak height parameter h.

[0030] The present invention has the following beneficial effects: a one-dimensional Gaussian fitting IP core based on FPGA and its implementation method of the present invention can be directly used in FPGA or an embedded system containing FPGA to realize the application requirements of high-speed and miniaturized computing devices, directly embedded in the design, without the need for designers to develop and design for one-dimensional Gaussian fitting, thereby reducing development costs and shortening cycles. The IP core of the present invention can be developed using the HLS tool, and the C / C++ code can be first converted into hardware description language codes such as Verliog / VHDL, and then the converted hardware description language codes can be integrated into a specific circuit. All configuration information can be put into a header file and configured and modified in the form of parameters, which is more convenient and quick. It supports the setting of the number of fitting bits, input data format, and output data format of one-dimensional Gaussian fitting, and is flexible and convenient for specific application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solution of the present invention, the drawings required for use in the embodiments are briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0032] Figure 1 This is an architecture diagram of an FPGA-based one-dimensional Gaussian fitting IP core of the present invention.

[0033] Figure 2 The present invention is a schematic diagram of a method for implementing a one-dimensional Gaussian fitting IP core based on FPGA. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described in conjunction with the specific embodiments of the present invention and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. The technical solutions provided by the embodiments of the present invention are described in detail below in conjunction with the drawings.

[0035] The present invention implements a one-dimensional Gaussian fitting algorithm on a field programmable gate array (FPGA). By utilizing the editability and parallelism of FPGA devices, high-speed one-dimensional Gaussian fitting calculation can be realized. At the same time, a high-level synthesis (Xilinx HLS) tool is used to generate an FPGA IP soft core. The IP soft core can be configured according to specific devices and can be integrated into various embedded systems to meet the needs of miniaturization. In addition, it is designed as a general FPGA IP soft core, and designers do not need to develop and design one-dimensional Gaussian fitting, saving project development time. The present invention aims to develop a one-dimensional Gaussian fitting IP core based on FPGA using the HLS tool, which can realize high-speed calculation, miniaturized application, and one-dimensional Gaussian fitting that can be configured and used on FPGA. At the same time, a method for using this IP core to realize one-dimensional Gaussian fitting is provided.

[0036] See also Figure 1 The present invention provides a one-dimensional Gaussian fitting IP core based on FPGA, comprising: a communication interface, an input conversion module, a filling cache module, a fitting parameter solving module and an output conversion module; the communication interface comprises an Advanced eXtensible Interface-Stream (AXI-Stream) interface and an Advanced eXtensible Interface Lite (AXI-Lite) interface.

[0037] One-dimensional Gaussian fitting calculations may face burst data transmission. A large amount of input data exceeds the processing capacity of the one-dimensional Gaussian fitting IP core. The input communication bus needs to have the ability to cache data and transmit at high speed. At the same time, because the envelope of the data to be calculated by one-dimensional Gaussian fitting meets the characteristics of the Gaussian bell shape, the input calculation data needs to be passed in sequentially and does not need to be read by address. The AXI-Stream interface adopts an advanced asynchronous first-in-first-out (FIFO) buffer mechanism, which can meet the needs of the IP core to transmit output data.

[0038] Among them, the AXI-Stream interface is used to receive the data to be fitted;

[0039] The input conversion module is used to convert the format of the data input by the AXI-Stream interface and send the converted data to the filling cache module. Specifically, the input format of the input conversion module is configured as a floating point or fixed point decimal format. For example, the input conversion module is used to convert the data to be calculated input by the AXI-Stream interface into floating point numbers, and obtain the X-axis coordinate x(n) and Y-axis coordinate y(n) of the data to be fitted in the converted Cartesian coordinate system, n=0,1,...,m-1, m is the number of fitting bits; the converted data is sent to the filling cache module.

[0040] The filling cache module is used to fill the Vandermonde matrix A and the matrix Y used to fit the quadratic polynomial using the least squares method according to the set fitting bit number, and send the data to the fitting parameter solving module.

[0041] Specifically, the filling cache module fills the Vandermonde matrix A and the matrix Y used for fitting the quadratic polynomial using the least squares method according to the set fitting bit number m, and sends the data to the fitting parameter solving module;

[0042] The Vandermonde matrix A is:

[0043] ;

[0044] Where x0, x1, ..., x m-1 is the X-axis coordinate x(n) of the data to be fitted. The matrix Y is:

[0045] ;

[0046] Where y0, y1, ..., y m-1 is the Y-axis coordinate y(n) of the data to be fitted. ,ln ,··· It means taking the logarithm of each term of the input y(n).

[0047] The fitting parameter solving module is used to receive the Vandermonde matrix A and matrix Y filled by the filling buffer module, calculate the fitting line parameters using the least square method, obtain the mean, standard deviation, and peak height parameters of the one-dimensional Gaussian fitting through the conversion formula, and send the parameters to the output conversion module after the calculation is completed. The number of fitting bits m is configured as any integer from 10 to 30, and the number of fitting bits determines the shape of the matrices involved in the calculation in the filling buffer module and the fitting parameter solving module.

[0048] Specifically, the fitting parameter solving module is used to:

[0049] Calculate the Vandermonde matrix passed to the fill cache module The transposed matrix of ;

[0050] Calculate the parameters of the fitted line using the least squares method , t=0, 1, 2; parallel computing and , and After all calculations are completed, multiply them to get (t); , where is the transposed matrix Directly multiply the matrix Y of the filling cache module input fitting parameter solution module; First, transpose the matrix Vandermonde matrix Multiply, then judge Is the determinant value 0? If If the determinant value is 0, the exception flag position is 1, such as If the determinant value is not 1, then Take the inverse matrix and calculate ;

[0051] The fitting parameters are obtained by parallel calculation through the following conversion formula:

[0052] ;

[0053] In the formula, , , This corresponds to fitting the coefficients of a quadratic polynomial function using the least squares method. is the mean of the one-dimensional Gaussian fit, is the standard deviation, h is the peak height parameter;

[0054] To determine the output data, When the determinant value is not 0, the output value is the calculated one-dimensional Gaussian fitting parameter. The determinant value is 0, and the output one-dimensional Gaussian fitting parameters are replaced by three identical set numbers.

[0055] The output conversion module is used to confirm the parameters calculated by the fitting parameter solving module, convert the confirmed parameters according to the set data format and then output them. Specifically, the output format of the output conversion module is configured as a floating point or fixed point decimal format.

[0056] The AXI-Lite interface is used to output the data output by the output conversion module and is responsible for the communication interaction between the IP core and the processor.

[0057] The FPGA-based one-dimensional Gaussian fitting IP core of the present invention is provided in the form of a soft core, which can be deployed on any FPGA platform, facilitating rapid updating and iteration of products.

[0058] The present invention also provides a method for implementing the above one-dimensional Gaussian fitting IP core based on FPGA, including:

[0059] The FIFO module sequentially caches the data to be fitted and transmits the data to be fitted to the peak-finding module; the peak-finding module locates the maximum value of the data to be fitted, and takes a continuous data segment with the maximum value as the middle position and a length that is consistent with the number of fitting bits configured in the one-dimensional Gaussian fitting IP core, and streams the continuous data to the one-dimensional Gaussian fitting IP core based on FPGA. The one-dimensional Gaussian fitting IP core based on FPGA uses the data to perform one-dimensional Gaussian fitting and outputs the mean value of the one-dimensional Gaussian fitting. , Standard Deviation , peak height parameter h.

[0060] Use case description: Use the FPGA-based one-dimensional Gaussian fitting IP core provided by the present invention to implement one-dimensional Gaussian fitting.

[0061] In order to better illustrate the technical solution of the present invention, the principle of the present invention is first briefly deduced and explained.

[0062] The formula for fitting a quadratic polynomial to m input data using the least squares method is:

[0063] ; (1)

[0064] (1) Where: is the calculation result of the quadratic polynomial of m input data fitted by the least squares method; m is the number of fitting bits, which can be configured as an integer between 10 and 30; the input data to be fitted is ( , ),( , ),···,( , ), Coordinates and Input coordinates alternately to find the Parameters, t=0, 1, 2, can fit a quadratic polynomial.

[0065] The following definitions are given:

[0066] ; (2)

[0067] ; (3)

[0068] ; (4)

[0069] The A matrix is ​​the Vandermonde matrix calculated by inputting the x-coordinate of the data to be fitted. Matrix is ​​the fitting parameter matrix, and Y is the matrix consisting of the y-coordinates of the data to be fitted.

[0070] The following equations are derived from (2), (3), and (4):

[0071] ; (5)

[0072] Solve the parameter matrix from the normal equations , multiply (3) by matrix:

[0073] ; (6)

[0074] in The matrix is ​​the transpose of the A matrix. At this time, solve the fitting parameter matrix in equation (1): , then solve equation (6) Solution:

[0075] ; (7)

[0076] The standard one-dimensional Gaussian bell function expression is:

[0077] ; (8)

[0078] Where x and y are the X-axis and Y-axis coordinates in the Cartesian coordinate system, μ is the mean of the one-dimensional Gaussian fit, σ is the standard deviation of the one-dimensional Gaussian fit, and h is the peak height parameter of the one-dimensional Gaussian fit. Take the logarithm of the left and right sides of formula (8):

[0079] ; (9)

[0080] Comparing formula (9) with formula (1), we can obtain:

[0081] ; (10)

[0082] From equation (11), we can get the one-dimensional Gaussian clock function parameters and fitting parameter matrix: The conversion formula between elements:

[0083] ; (11)

[0084] In summary, we can get the method of calculating one-dimensional Gaussian fitting using the least squares method:

[0085] Enter m coordinate data in the Cartesian coordinate system to be fitted ( , ),( , ),···,( , ).

[0086] Fill the matrix A according to formula (2), and After taking the logarithm of the coordinates, fill the matrix Y according to formula (4).

[0087] Calculate the fitting parameter matrix according to formula (7): .

[0088] According to the conversion formula (11), the mean of the one-dimensional Gaussian fitting is calculated , standard deviation of one-dimensional Gaussian fit , the peak height parameter h of the one-dimensional Gaussian fit.

[0089] In order to further improve the speed of IP core fitting function, equation (7) is decomposed and parallelized. and After both parts are calculated, they are multiplied to get . Some calculations will transpose the matrix Directly multiply with the filling matrix Y; The calculation part is to first and Multiply and then judge Whether the determinant value is 0, if the determinant value is 0, the exception flag position is 1, if the determinant value is not 1, then calculate , that is, The calculation of the inverse matrix in formula (7) is Reversible, otherwise the calculation result is unreliable. It is necessary to set the exception flag to indicate whether the calculation result is reliable. When the flag is 1, the calculation result output by the IP core this time is a fixed exception value. If the flag is not 1, the calculation result output by the IP core this time is the calculated value.

[0090] The specific steps to generate an IP core are as follows:

[0091] Set the top-level configuration parameters of the IP core and the top-level input and output interface. The configuration parameters include device, clock, etc. The input and output interface includes clock, reset, interface register, interface bit width, etc.

[0092] Set the number of fitting bits m, input format and output format of one-dimensional Gaussian fitting. The setting of the number of fitting bits is determined according to the device resources and fitting accuracy, and the input and output formats are determined according to the specific communication protocol.

[0093] Finally, it should be noted that the IP core of the present invention can be developed using high-level synthesis, i.e., the HLS tool, which is faster, more efficient, and more flexible than the traditional development using hardware description language. For one-dimensional Gaussian fitting with different fitting bits, input formats, and output formats, rapid configuration can be achieved by simply changing the design parameters.

[0094] In summary, the IP core of the present invention relies on the design characteristics of its own algorithm and combines the advantages of the HLS tool to make the IP core have extremely high applicability, flexibility and configurability, and can meet the needs of high-speed calculation of one-dimensional Gaussian fitting in FPGA and embedded systems.

[0095] The above-described embodiments of the present invention do not limit the protection scope of the present invention.

Claims

1. A one-dimensional Gaussian fitting IP core based on FPGA, characterized in that: include: A communication interface, an input conversion module, a filling cache module, a fitting parameter solving module and an output conversion module; the communication interface includes an AXI-Stream interface and an AXI-Lite interface; The AXI-Stream interface is used to receive data to be fitted; The input conversion module is used to convert the format of the data input by the AXI-Stream interface and send the converted data to the filling cache module; The filling cache module is used to fill the Vandermonde matrix A and the matrix Y used to fit the quadratic polynomial using the least squares method according to the set number of fitting bits, and send the data to the fitting parameter solving module; The fitting parameter solving module is used to receive the Vandermonde matrix A and the matrix Y filled by the filling cache module, calculate the fitting straight line parameters using the least squares method, obtain the mean, standard deviation, and peak height parameters of the one-dimensional Gaussian fitting through the conversion formula, and send the parameters to the output conversion module after the calculation is completed; The output conversion module is used to confirm the parameters calculated by the fitting parameter solving module, convert the confirmed parameters into a format according to a set data format, and then output them; The AXI-Lite interface is used to output the data output by the output conversion module and is responsible for the communication interaction between the IP core and the processor.

2. The one-dimensional Gaussian fitting IP core based on FPGA as claimed in claim 1, characterized in that: The input format of the input conversion module is configured as a floating point or fixed point decimal format.

3. The one-dimensional Gaussian fitting IP core based on FPGA as claimed in claim 2, characterized in that: The input conversion module is used to convert the data to be calculated input by the AXI-Stream interface into floating-point numbers, obtain the X-axis coordinate x(n) and Y-axis coordinate y(n) of the data to be fitted in the Cartesian coordinate system, n=0, 1, ..., m-1, m is the number of fitting bits; and send the converted data to the filling cache module.

4. The one-dimensional Gaussian fitting IP core based on FPGA as claimed in claim 1, characterized in that: The number of fitting bits m is configured as any integer between 10 and 30, and the number of fitting bits determines the shapes of matrices involved in calculation in the filling cache module and the fitting parameter solving module.

5. The one-dimensional Gaussian fitting IP core based on FPGA as claimed in claim 1, characterized in that: The filling cache module is used to fill the Vandermonde matrix A and the matrix Y used to fit the quadratic polynomial using the least squares method according to the set fitting bit number m, and send the data to the fitting parameter solving module; The Vandermonde matrix A is: ; Where x0, x1, ..., x m-1 is the X-axis coordinate x(n) of the data to be fitted; The matrix Y is: ; Where y0, y1, ..., y m-1 is the Y-axis coordinate y(n) of the data to be fitted; where ln ,ln ,··· It means taking the logarithm of each term of the input y(n).

6. The one-dimensional Gaussian fitting IP core based on FPGA as claimed in claim 1, characterized in that: The fitting parameter solving module is used for: Calculate the Vandermonde matrix passed to the fill cache module The transposed matrix of ; Calculate the parameters of the fitted line using the least squares method (t), t=0, 1, 2; parallel calculation and , and After all calculations are completed, multiply them to get (t); , where is the transposed matrix Directly multiply the matrix Y of the filling cache module input fitting parameter solution module; First, transpose the matrix Vandermonde matrix Multiply, then judge Whether the determinant value is 0, if If the determinant value is 0, the exception flag position is 1, such as If the determinant value is not 1, then Take the inverse matrix and calculate ; The fitting parameters are obtained by parallel calculation through the following conversion formula: ; In the formula, , , This corresponds to fitting the coefficients of a quadratic polynomial function using the least squares method. is the mean of the one-dimensional Gaussian fit, is the standard deviation of the one-dimensional Gaussian fit, and h is the peak height parameter of the one-dimensional Gaussian fit; To determine the output data, When the determinant value is not 0, the output value is the calculated one-dimensional Gaussian fitting parameter. The determinant value is 0, and the output one-dimensional Gaussian fitting parameters are replaced by three identical set numbers.

7. The one-dimensional Gaussian fitting IP core based on FPGA as claimed in claim 1, characterized in that: The output format of the output conversion module is configured as a floating point or fixed point decimal format.

8. A method for implementing the one-dimensional Gaussian fitting IP core based on FPGA as claimed in any one of claims 1 to 7, characterized in that: include: The FIFO module sequentially caches the data to be fitted and transmits the data to be fitted to the peak-finding module; the peak-finding module locates the maximum value of the data to be fitted, and takes a continuous data segment with the maximum value as the middle position and a length that is consistent with the number of fitting bits configured in the one-dimensional Gaussian fitting IP core, and streams the continuous data to the one-dimensional Gaussian fitting IP core based on FPGA, and the one-dimensional Gaussian fitting IP core based on FPGA uses the data to perform one-dimensional Gaussian fitting and outputs the mean value of the one-dimensional Gaussian fitting. , Standard Deviation , peak height parameter h.

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