Parallel optimization method for static timing analysis of FPGA (Field Programmable Gate Array)

Abstract

The invention belongs to the field of electronic design automation and static time sequence analysis, particularly relates to a parallel optimization method for FPGA static time sequence analysis, and aims to solve the problems of low calculation efficiency and long compiling time of static time sequence analysis in the prior art. The method comprises the following steps: performing memory layout optimization on a time sequence diagram and time sequence constraints according to a built FPGA-oriented STA data structure; task decomposition is carried out, calculation tasks of nodes and edges of each hierarchy are allocated to a plurality of parallel kernels to be executed in parallel, and single CPU threads are allocated to different hierarchies to be executed in sequence; during execution, traversing the time sequence diagram, and marking to-be-updated nodes and edges; and obtaining effective arrival time and effective demand time of the nodes through bidirectional traversal calculation, determining a key path in FPGA (Field Programmable Gate Array) time sequence static analysis, and generating a parallel optimization report of the FPGA static time sequence analysis. According to the method, the calculation efficiency in static time sequence analysis is improved, and the compiling time is shortened.

Description

Technical Field

[0001] The invention belongs to the field of electronic design automation and static timing analysis, and in particular relates to a parallel optimization method for FPGA static timing analysis. Background Art

[0002] With the rapid growth of integrated circuit design scale, especially in the field of FPGA, the increase of design complexity and timing constraints makes static timing analysis (STA) a key design verification link. STA is a core tool for evaluating whether the digital circuit design meets the timing requirements. It is widely used in the layout and routing process of FPGA to ensure that the circuit runs correctly within the predetermined clock cycle. However, with the increase of design scale and the diversification of clock domains and timing angles, the computational complexity of STA has also increased significantly, which in turn leads to the extension of FPGA compilation time.

[0003] At present, traditional STA mostly relies on single-threaded CPU processing. In complex FPGA designs, single-threaded processing can no longer meet the needs of fast verification, resulting in low analysis efficiency. In addition, although the parallel computing capabilities of GPUs are superior in certain computationally intensive tasks, in STA tasks, due to the bottleneck of data transmission, GPUs have not fully exerted their potential advantages. Specifically, the data format conversion between the CPU and GPU is cumbersome, and the data copy time between the main memory and the video memory is long, which often offsets the acceleration effect of GPU kernel computing. STA tasks are highly data-dependent and require frequent data access and synchronization, which makes GPUs inefficient in processing these tasks.

[0004] Therefore, although some existing methods try to use GPU to accelerate static timing analysis and show the advantages of GPU in kernel computing speed, the overall performance improvement is limited due to the limitations of data transmission and synchronization overhead. At the same time, making full use of the parallel computing capabilities of multi-core CPUs and combining some of the computing advantages of GPUs to avoid the overhead of frequent data transmission between different storage units has become a more promising direction for accelerating STA.

[0005] Therefore, how to effectively utilize the parallel computing capabilities of multi-core CPUs and combine the computing advantages of GPUs to optimize the processing flow of STA and reduce the data synchronization and transmission overhead in timing analysis has become an important challenge in the field of electronic design automation (EDA). By improving the operating efficiency of STA, the time for FPGA design verification can be significantly shortened and the quality of design optimization can be further improved. Summary of the invention

[0006] In order to solve the above problems in the prior art, that is, to solve the problems of low calculation efficiency and long compilation time of static timing analysis in the prior art, especially the inefficiency of single-thread CPU processing in complex FPGA design and the limited performance improvement of GPU parallel computing due to data transmission bottleneck, the first aspect of the present invention proposes a parallel optimization method for FPGA static timing analysis, which includes:

[0007] Step S1, obtaining a timing diagram and timing constraints of FPGA static timing analysis; performing memory layout optimization on the timing diagram and the timing constraints according to the constructed FPGA-oriented STA data structure; the timing diagram includes nodes, edges, delay models, and timing analysis results;

[0008] Step S2, performing task decomposition on the timing graph after memory layout optimization, after decomposition, assigning the computational tasks of nodes and edges within each level to multiple parallel cores for parallel execution, and assigning single CPU threads to different levels for sequential execution; the parallel cores include CPU cores and GPU cores;

[0009] Step S3, when executed, traverse the time sequence graph through a preset traversal strategy, and mark the nodes and edges to be updated; the preset traversal strategy includes full update and incremental update;

[0010] Step S4, combined with the parallel computing strategy, obtains the effective arrival time of the node and the effective demand time of the node through bidirectional traversal calculation; determines the critical path in the FPGA timing static analysis according to the effective arrival time of the node and the effective demand time of the node, and then generates a parallel optimization report for the FPGA static timing analysis.

[0011] In some preferred implementations, the memory layout of the timing diagram and timing constraints is optimized according to the constructed FPGA-oriented STA data structure, and the method is as follows:

[0012] The structure of the timing graph is optimized to a hierarchical structure, wherein the data of the timing graph is stored in an array structure and only static node information and edge information are stored;

[0013] When the timing graph is stored, the timing graph is stored as a timing graph in which the directed timing graph is stored as a bidirectional edge.

[0014] In some preferred implementations, after the memory layout is optimized but before the task decomposition, the steps of timing diagram verification and hierarchical query are also included:

[0015] The data is initialized and accessed for verification based on the hierarchical traversal order of the timing graph after memory layout optimization to ensure that the data access order during traversal is consistent with the storage order in memory.

[0016] In some preferred implementations, the timing diagram after memory layout optimization is subjected to task decomposition, and the method is as follows:

[0017] Obtaining nodes to be processed in the timing diagram after memory layout optimization, allocating parallel kernel parameters, and performing task decomposition on the timing diagram after memory layout optimization using relevant function libraries; the relevant function libraries include TBB and CUDA;

[0018] Perform task decomposition on the timing diagram after memory layout optimization, including fine-grained task decomposition and coarse-grained task decomposition;

[0019] The fine-grained tasks are decomposed into: dividing each level of the timing graph after the memory layout is optimized into different fine-grained tasks, and assigning the computational tasks of the nodes and edges of each level to multiple parallel cores for parallel execution; the fine-grained tasks include arrival time pre-traversal, arrival time traversal, demand time pre-traversal, demand time traversal, relaxation update and state reset;

[0020] The coarse-grained task is decomposed into: different levels of the timing graph after the memory layout is optimized are executed in sequence by a single CPU thread.

[0021] In some preferred implementations, the full update is: each call uses a serial traversal method to completely reanalyze the timing diagram; the full update is used to initialize the build and reset phases;

[0022] The incremental update is as follows: in the previous round of traversal, invalid edges and nodes to be updated are marked; when traversing the arrival time and demand time, only the nodes marked as to be updated are traversed, and the nodes that need to be added to the update queue are determined based on the invalid edges; the relaxation value of the modified node is calculated and updated; the modified node is a node whose relaxation value in the update queue changes during the traversal calculation; the incremental update is used in the parallel calculation stage.

[0023] In some preferred implementations, the effective arrival time of a node is obtained by:

[0024] Step S411, initializing the arrival time of all input pins based on the timing constraints;

[0025] Step S412, adding the delay time of each edge to the source node arrival time of the edge to calculate the arrival time of the edge;

[0026] Step S413, calculating the maximum setup time or the minimum hold time of all input edge arrival times at each downstream node, and storing it as the node arrival time;

[0027] Step S414, determine whether step S3 is incrementally updated, if not, loop through steps S412-S413 until valid arrival times of all nodes are obtained, otherwise, loop through steps S412-S413 until valid arrival times of nodes in the update queue are obtained.

[0028] In some preferred implementations, the effective demand time of all nodes is obtained by:

[0029] Step S421, initializing the time required by all output pins according to the timing constraints;

[0030] Step S422, subtract the sink node demand time of each edge from the delay time of the edge to calculate the edge demand time;

[0031] Step S423, calculating the minimum setup time or the maximum hold time of all input edge demand times at each upstream node, and storing it as the node demand time;

[0032] Step S424, determine whether step S3 is incrementally updated, if not, loop through steps S422-S423 until valid demand times of all nodes are obtained, otherwise, loop through steps S422-S423 until valid demand times of nodes in the update queue are obtained.

[0033] In some preferred implementations, when calculating the effective arrival time of all nodes or the effective demand time of all nodes, a parallel computing strategy is used for parallel execution:

[0034] By hierarchical calculation, the timing diagram is processed one level at a time. Two parallel kernel clusters are allocated in each level, one of which is responsible for piecewise addition and the other is responsible for piecewise maximum reduction.

[0035] The processing process of the parallel kernel cluster responsible for the segmented addition is as follows: parallelization enables each kernel in the parallel kernel cluster to be assigned an edge, perform an edge calculation once, and obtain the edge arrival time or edge demand time;

[0036] The processing process of the parallel kernel cluster responsible for segmented maximization reduction is as follows: each parallel kernel in the parallel kernel cluster is assigned to a sink node of the current layer, traverses the arrival time or demand time of all edges related to the sink node, and performs a maximization reduction operation to obtain the final arrival time or demand time.

[0037] In some preferred implementations, the critical path in the FPGA timing static analysis is determined based on the effective arrival time of all nodes and the effective demand time of all nodes, and the method is as follows:

[0038] The difference between the effective arrival time and the effective demand time of all nodes in each path is calculated, and the path corresponding to zero or the smallest difference is taken as the critical path.

[0039] In some preferred implementations, a parallel optimization report for FPGA static timing analysis is generated by extracting parameter value records of all intermediate links and generating a readable parallel optimization report for FPGA static timing analysis after all critical path calculations are completed in parallel.

[0040] Beneficial effects of the present invention:

[0041] The present invention optimizes memory access efficiency, reduces synchronization overhead, improves concurrency performance, increases the parallel computing efficiency of FPGA static timing analysis by several times, shortens compilation time, and significantly improves the timing analysis performance in ultra-large-scale FPGA designs, which can better meet the requirements for efficient timing analysis in modern FPGA designs.

[0042] 1) The present invention ensures that the nodes and edges of each layer are stored continuously in the memory by constructing a hierarchical memory layout, matching the access order during traversal, and reducing the probability of cache failure. Through such an optimized memory layout, the efficiency of kernel data access is improved, especially in multi-core parallel processing, each kernel can quickly obtain the required data, further speeding up the process of timing analysis. Compared with the prior art, the memory layout of the present invention is more targeted and can significantly improve the data access speed during the timing analysis process;

[0043] 2) The present invention adopts a parallel processing method without explicit synchronization, avoiding the inter-thread synchronization overhead caused by lock operations in traditional methods. By allocating tasks in a fine-grained manner, each thread is only responsible for the calculation of independent nodes and edges, avoiding the situation where multiple threads compete for the same data, thereby further improving concurrency performance. Compared with existing parallel algorithms that rely on lock mechanisms, the solution of the present invention can more effectively utilize multi-core resources and improve the efficiency of parallel execution;

[0044] 3) Existing static timing analysis methods usually rely on single-threaded or limited parallel computing, resulting in low efficiency when facing complex FPGA designs. The present invention greatly improves the utilization of multi-core CPUs and GPUs through the strategy of intra-layer parallel processing and inter-layer sequential execution of timing graphs. Nodes and edge tasks in each layer are executed by multiple parallel cores, which reduces the waiting time for calculations and gives full play to the parallel computing capabilities of modern multi-core processors. Compared with the existing technology, the overall computing efficiency of FPGA static timing analysis has been improved by 2.9 times, especially in ultra-large-scale FPGA designs;

[0045] 4) The present invention calculates the maximum arrival time and the minimum required time of the node through forward and backward traversal respectively, and compares and determines the critical path, thereby ensuring the accuracy of timing analysis. Compared with the existing single CPU thread or partial parallel scheme, the present invention combines parallel computing with sequential execution to ensure the balance between intra-layer parallelism and inter-layer dependency, which can not only speed up the calculation, but also avoid the problem of data inconsistency caused by concurrency, thereby improving the overall accuracy of timing analysis. In addition, the combination of inter-layer sequential execution makes this method more flexible when dealing with complex FPGA designs;

[0046] 5) As the complexity of FPGA design increases, the performance bottleneck of existing technologies in large-scale design becomes increasingly obvious. The present invention can effectively meet the timing analysis requirements in complex FPGA designs by performing fine-grained parallelism within the hierarchy and coarse-grained sequential execution between layers, greatly shortening the analysis time. Compared with traditional methods, the timing analysis performance of the present invention in large-scale FPGA design is improved by more than several times, which can better meet the requirements for efficient timing analysis in modern FPGA design. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings.

[0048] Figure 1 It is a flow chart of a parallel optimization method for FPGA static timing analysis according to an embodiment of the present invention;

[0049] Figure 2 It is a simplified flow chart of a parallel optimization method for FPGA static timing analysis according to an embodiment of the present invention;

[0050] Figure 3 It is a schematic diagram of critical path parallel computing of an embodiment of the present invention. DETAILED DESCRIPTION

[0051] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution in the embodiment of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiment is a part of the embodiment of the present invention, not all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0052] The present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the relevant invention, rather than to limit the invention. It is also necessary to explain that, for ease of description, only the parts related to the relevant invention are shown in the accompanying drawings.

[0053] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application may be combined with each other.

[0054] A parallel optimization method for FPGA static timing analysis according to a first embodiment of the present invention is as follows: Figure 1 As shown, the following steps are included:

[0055] Step S1, obtaining a timing diagram and timing constraints of FPGA static timing analysis; performing memory layout optimization on the timing diagram and the timing constraints according to the constructed FPGA-oriented STA data structure; the timing diagram includes nodes, edges, delay models, and timing analysis results;

[0056] Step S2, performing task decomposition on the timing graph after memory layout optimization, after decomposition, assigning the computational tasks of nodes and edges within each level to multiple parallel cores for parallel execution, and assigning single CPU threads to different levels for sequential execution; the parallel cores include CPU cores and GPU cores;

[0057] Step S3, when executed, traverse the time sequence graph through a preset traversal strategy, and mark the nodes and edges to be updated; the preset traversal strategy includes full update and incremental update;

[0058] Step S4, combined with the parallel computing strategy, obtains the effective arrival time of the node and the effective demand time of the node through bidirectional traversal calculation; determines the critical path in the FPGA timing static analysis according to the effective arrival time of the node and the effective demand time of the node, and then generates a parallel optimization report for the FPGA static timing analysis.

[0059] In order to more clearly illustrate the parallel optimization method for FPGA static timing analysis of the present invention, the following is combined with the attached Figure 2 Each step in an embodiment of the method of the present invention is described in detail.

[0060] The present invention aims to optimize the processing flow of STA by making full use of the parallel computing power of multi-core CPUs and combining the computing advantages of GPUs, reduce the overhead of data synchronization and transmission, thereby significantly improving the speed of static timing analysis, shortening the time of FPGA design verification, and further improving the quality and efficiency of design optimization. The details are as follows:

[0061] Step S1, obtaining a timing diagram and timing constraints of FPGA static timing analysis; performing memory layout optimization on the timing diagram and the timing constraints according to the constructed FPGA-oriented STA data structure;

[0062] In this embodiment, the specific process of performing memory layout optimization is as follows:

[0063] Step S101, the STA data structure for FPGA includes two parts: constructing an FPGA timing diagram and a timing constraint (i.e., the STA data structure includes a timing diagram data structure and a timing constraint data structure). The timing diagram part includes nodes (including node types, source nodes, and sink nodes), edges (including edge types, input and output edges), delay models (including maximum and minimum delays, setup time, hold time, etc. of edges) and timing analysis results (including but not limited to data arrival time, data demand time, clock start and clock capture time, and offset time of setup time and hold time). The timing constraint part includes but is not limited to constants, maximum input and output constraints, minimum input and output constraints, setup time constraints, and hold time constraints. The corresponding operations of the data structure include but are not limited to addition, deletion, modification, verification, and remapping. The optimized data structure of the timing diagram and timing constraints is also oriented to parallel kernels (parallel kernels include CPU kernels and GPU kernels): Taking CPU kernels and GPU kernels as examples, the data structure not only optimizes memory access efficiency, but also takes into account the needs of CPU and GPU parallel computing. By adopting a unified memory format, the timing diagram and timing constraint data structure can support direct access and calculation by both the CPU and GPU, avoiding the bottleneck caused by traditional data transmission. This design greatly improves the efficiency of parallel computing and ensures the collaborative work of the CPU and GPU during the timing analysis process.

[0064] Step S102, the data of the timing graph is stored and established in the form of an array structure, that is, all data of a specific field (such as node type, edge type, etc.) is kept in a continuous memory, which can enable memory sorting optimization, greatly improve cache behavior, and improve the efficiency of data access. The structure of the timing graph is stored and established in a hierarchical manner, that is, all nodes and edges are stored according to the topological hierarchy, ensuring that the node and edge data of the same layer are continuously distributed in the memory block. This memory layout optimization not only improves the cache hit rate of the CPU, but also enables the GPU kernel to process these data efficiently. In the parallel computing process, the GPU kernel can directly access these continuously stored data, and accelerate the execution of timing analysis by executing batch computing tasks (such as edge delay calculation, parallel traversal of node arrival time, etc.). In particular, the GPU can process a large number of computing tasks on nodes and edges in parallel, and fully utilize the large-scale parallel computing capabilities of the GPU in the traversal and relaxation update of the timing graph. This design greatly reduces the overhead of data transmission, because the GPU can directly access the optimized data structure stored in the memory, avoiding frequent data copying and conversion. The node storage includes but is not limited to information such as node type, arrival time, required time, etc., and the edge storage includes but is not limited to information such as delay, starting node and ending node. The GPU core can perform parallel processing through an efficient memory access mode without performing complex memory remapping operations. The timing graph is a directed graph during the establishment process, but is actually stored as a bidirectional edge, which can greatly simplify the forward or backward traversal operations in the subsequent links of the timing graph, allowing the GPU to perform these tasks with minimal delay and higher throughput. The data structure of the timing graph only stores static connection information and node information. Other dynamic information (edge ​​delay, node arrival time or required time, etc.) is stored separately to support dynamic updates and reading in parallel computing. The addition of the GPU core makes parallel processing within the layer more efficient, and also ensures the balanced distribution of computing load when processing large-scale designs, further improving the efficiency of overall timing analysis. Because most behaviors operating on the timing graph only require read-only access to the timing graph, the GPU can give full play to its advantages and handle a large number of computing tasks without interfering with the use of other computing resources.

[0065] Step S103: Timing constraints store all timing constraints applied during timing analysis, such as setup constraints, hold constraints, maximum and minimum input constraints, maximum and minimum output constraints, setup clock constraints, hold clock constraints, early source delays, late source delays, etc. These constraint data are uniformly stored in memory for efficient access and processing. In the parallel computing process, the GPU kernel can directly process these constraints and perform parallel traversal and updates together with other data of the timing diagram (such as arrival time and demand time).

[0066] Step S104: parse the timing diagram and timing constraint information of the FPGA netlist and constraint files (including but not limited to .eblif files and .sdc files), perform memory layout optimization according to the steps of building the data structure, and perform timing diagram verification and hierarchical query to ensure the correctness and hierarchical structure of the timing diagram. The timing diagram verification and hierarchical query are to perform initialization access verification on the data according to the hierarchical traversal order of the timing diagram, to ensure that the data access order during traversal is consistent with the storage order in the memory, thereby reducing the probability of cache failure and improving processing performance.

[0067] Step S2, the timing graph after memory layout optimization is task-decomposed. After decomposition, the computational tasks of nodes and edges within each level are assigned to multiple parallel cores for execution, and different levels are assigned to a single CPU thread for sequential execution; specifically, the computational tasks of nodes and edges within each level are calculated by multiple parallel cores, including CPU cores and GPU cores. This design ensures full utilization of CPU and GPU computing resources, especially when processing large-scale timing analysis tasks, which can speed up computing and avoid idle resources.

[0068] In this embodiment, task decomposition includes two parts: fine-grained task allocation and coarse-grained task allocation.

[0069] Fine-grained task allocation is to divide each level of the timing graph after memory layout optimization into six fine-grained tasks, namely, arrival time pre-traversal, arrival time traversal, demand time pre-traversal, demand time traversal, relaxation update and state reset. These six main tasks are executed in parallel by the GPU core, because they involve a large number of node traversals and calculations, and the GPU can handle these parallel computing tasks efficiently. Specifically, the GPU core can process data of multiple nodes and edges at the same time through efficient parallel computing capabilities, thereby significantly improving the computing speed, while the remaining operations involving conditional judgment, recursion and large-scale call access operations, scheduling and synchronization use the CPU core.

[0070] Each parallel kernel is responsible for calculating all nodes or edges within the layer, avoiding data competition between threads and improving computing efficiency. The arrival time pre-traversal is to traverse the starting node and perform a pre-traversal (i.e., set the constraints of the starting node) to set the arrival time of the starting point. The arrival time traversal is to traverse all nodes in the timing graph and calculate the arrival time of the nodes step by step. The demand time pre-traversal is to traverse the logic output nodes and set the demand time of these nodes (i.e., the time constraints of the logic output). The demand time traversal is to traverse backward from the logic output to the starting point step by step to calculate the demand time of the node. The relaxation update is to traverse the relaxation values ​​of all nodes for timing optimization. The state reset is to reset the state of the nodes and edges to prepare for the next task analysis.

[0071] Coarse-grained task allocation means that different levels of the timing graph after memory layout optimization are executed sequentially by a single CPU thread. The nodes and edges of each layer depend on the calculation results of the previous layer. This is because the CPU core has great advantages in executing tasks with strong dependencies. When calculating the critical path of the timing graph, it is necessary to gradually transfer and process the calculation results of the previous layer. Therefore, the sequential execution between levels avoids cross-level data dependency problems and ensures the correctness of the overall timing analysis.

[0072] The specific process is as follows: before traversal, initialization and node preparation are performed, that is, all nodes are prepared in advance, and the nodes to be processed are recorded. Then, appropriate parallel kernel parameters are allocated (in this embodiment, the CPU is set to use 20 CPU cores and the GPU is set to use 512 GPU cores), and the relevant function library (TBB and CUDA are preferably used in this embodiment, but not limited to TBB and CUDA) is used to execute the above task decomposition strategy in the timing diagram after the memory layout optimization is completed.

[0073] Step S3, when executed, traverse the time sequence graph through a preset traversal strategy, and mark the nodes and edges to be updated; the preset traversal strategy includes full update and incremental update;

[0074] In this embodiment, the traversal strategy includes two parts: full update and incremental update. The full update means that each call uses a serial traversal method to completely re-analyze the timing graph, which is mainly used in the initialization construction and reset phases. The incremental update refers to incrementally analyzing the timing graph, which is mainly used in the parallel traversal calculation phase. Incremental updates can be used to process invalid nodes in advance and mark those nodes and edges that need to be updated. This ensures that when entering the bidirectional traversal, only the parts that need to be updated will be calculated, rather than indiscriminately calculating the entire graph, thereby improving computing efficiency and reducing unnecessary time and resource consumption.

[0075] The specific process of the incremental update strategy is: 1. Edge invalidation and node preparation: First, the invalid edges in the previous round of traversal are recorded, and which nodes need to be updated again are marked. 2. Incremental arrival time and demand time traversal: Only traverse the nodes marked as needing to be updated, and decide which nodes need to be added to the update queue based on the invalid edges. 3. Relaxation update: Calculate the relaxation value of the modified nodes (that is, the update queue includes all nodes that need to be recalculated. These nodes may be directly marked or derived through dependencies. For example, if an edge is invalidated, the nodes connected to this edge need to be recalculated. When the update is actually executed, the nodes in the update queue will be traversed and recalculated in turn. During the recalculation process, the relaxation values ​​of some nodes may change. These nodes are "modified nodes". Therefore, the "modified nodes" are dynamically determined. They are some of the nodes in the update queue that are recalculated in the actual calculation, that is, the modified nodes are the nodes whose relaxation values ​​in the update queue change during the traversal calculation). The above process can reduce unnecessary node updates and more efficiently handle small changes in the timing graph without completely re-traversing the entire graph each time, thereby speeding up the STA analysis time.

[0076] During the incremental update process, the timing diagram is executed according to the coarse-grained and fine-grained task allocation in step S2 to ensure that the dependencies between layers do not cause data competition and synchronization problems.

[0077] Step S4, combined with the parallel computing strategy, obtains the effective arrival time of the node and the effective demand time of the node through bidirectional traversal calculation; determines the critical path in the FPGA timing static analysis according to the effective arrival time of the node and the effective demand time of the node, and then generates a parallel optimization report for the FPGA static timing analysis.

[0078] In this embodiment, the bidirectional traversal calculation is to perform two stages of forward traversal and reverse traversal successively in the critical path calculation process. In the forward (first) traversal, the timing diagram is traversed from the input pin point to the output pin point, the arrival time is calculated, and the following operations are performed:

[0079] Step S411, initializing the arrival time of all input pins (usually 0) based on the timing constraint;

[0080] Step S412, adding the delay time of each edge to the source node arrival time of the edge to calculate the arrival time of the edge;

[0081] Step S413, calculating the maximum setup time or the minimum hold time of all input edge arrival times at each downstream node, and storing it as the node arrival time;

[0082] Step S414, determine whether step S3 is incrementally updated, if not, loop through steps S412-S413 until valid arrival times of all nodes are obtained, otherwise, loop through steps S412-S413 until valid arrival times of nodes in the update queue are obtained.

[0083] In the backward (second) traversal, the timing diagram is traversed backwards from the output pins to the input pin points, performing the following operations:

[0084] Step S421, initializing the time required for all output pins according to the timing constraints (usually establishing a target clock cycle for analysis);

[0085] Step S422, subtract the sink node demand time of each edge from the delay time of the edge to calculate the edge demand time;

[0086] Step S423, at each upstream node, calculate the minimum setup time or maximum hold time of all input edge demand times (i.e., the demand time and arrival time each include setup time and hold time, the setup time is the minimum value that needs to be met, and the hold time is the maximum value that needs to be met. Finally, the maximum and minimum values ​​of the demand time, and the maximum and minimum values ​​of the arrival time are stored, which is equivalent to the minimum demand time, the maximum demand time, the minimum arrival time, and the maximum arrival time), and store it as the node demand time;

[0087] Step S424, determine whether step S3 is incrementally updated, if not, loop through steps S422-S423 until valid demand times of all nodes are obtained, otherwise, loop through steps S422-S423 until valid demand times of nodes in the update queue are obtained.

[0088] When calculating the required time or the arrival time, the timing diagram is processed by hierarchical calculation, one level is processed each time, and the processing is performed by allocating the processing to two parallel kernel clusters (GPU is used in this embodiment) for implementation. Each parallel kernel cluster has a certain number of parallel kernels (determined according to the actual scale of the circuit, and is set to 512 in this embodiment), such as Figure 3As shown. The first parallel kernel cluster is responsible for piecewise addition. In this step, each parallel kernel is assigned an edge and calculates the arrival time of the edge, see formula (1), or the demand time (the formula is not given here). The specific calculation method is to add the arrival time of the source node of the previous layer to the delay time of the edge of this layer. This operation is parallelized so that each kernel in the parallel kernel cluster performs an edge calculation once. The second parallel kernel cluster is responsible for piecewise maximum reduction. In this step, each parallel kernel is assigned a sink node of the current layer. The kernel will traverse the arrival time (or demand time) of all edges related to the sink node and perform a maximum reduction operation on it (see formula (2)) to obtain the final arrival time (or demand time) of the sink node. This strategy makes full use of the parallel computing power of all remaining available parallel kernels. By parallelizing the calculation of the edge arrival time (or demand time), the calculation amount of each edge is basically the same, so the load is well balanced. This strategy also ensures the merging and cache optimization of memory access, thereby improving the overall processing efficiency and significantly accelerating the static timing analysis process.

[0089]

[0090]

[0091]

[0092] Among them, EAT represents the arrival time of the edge, SO represents the arrival time of the source node, ED represents the delay time of the edge, SIAT represents the arrival time of the sink node, l represents the number of layers, n represents the number of nodes in the current layer, and k represents the number of nodes in the current layer. e Indicates the number of edges connected to the current k-th node.

[0093] By comparing the arrival time and the required time, the critical path in the FPGA static timing analysis is determined. The path corresponding to the critical path is the path where the difference between the arrival time and the required time is zero or the smallest. The method for calculating the critical path is: slack value = arrival time - required time. If the slack value is negative, it means that the timing of the path does not meet the requirements and is a potential timing problem. The critical path is the path with zero or negative slack values, which determines the slowest timing of the system.

[0094] After parallel computing completes all critical path calculations, the parameter values ​​of all intermediate links (in this embodiment, there are the maximum and minimum values, medians and average values ​​of the time in the six fine-grained tasks, the acceleration ratio of each task time, the critical path calculation time, etc.) are recorded and extracted to generate a readable parallel optimization report for FPGA static timing analysis. This report can provide analysis of setup time and hold time, and generate a worst path report; it can analyze optimization contents such as arrival time, demand time, relaxation, and report information on unconstrained nodes, so that users can compare the detailed results of static timing analysis after parallel optimization, and help them intuitively understand the timing status of different paths in the timing diagram, thereby optimizing and improving the design.

[0095] A parallel optimization system for FPGA static timing analysis according to a second embodiment of the present invention comprises:

[0096] A memory layout optimization module is configured to obtain a timing diagram and timing constraints of FPGA static timing analysis; and perform memory layout optimization on the timing diagram and the timing constraints according to a constructed FPGA-oriented STA data structure;

[0097] The task decomposition module is configured to perform task decomposition on the timing graph after memory layout optimization. After decomposition, the computation tasks of nodes and edges at each level are assigned to multiple CPU cores for parallel execution, and different levels are assigned to single CPU threads for sequential execution.

[0098] The traversal module is configured to traverse the timing graph during execution; the traversal strategies include full update and incremental update;

[0099] The static timing analysis module is configured to combine the parallel computing strategy to obtain the effective arrival time of the node and the effective demand time of the node through bidirectional traversal calculation; according to the effective arrival time of the node and the effective demand time of the node, the critical path in the FPGA timing static analysis is determined, and then a parallel optimization report for the FPGA static timing analysis is generated.

[0100] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process and related instructions of the system described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0101] It should be noted that the above embodiment provides a parallel optimization system for FPGA static timing analysis, which is only illustrated by the division of the above functional modules. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the modules or steps in the embodiments of the present invention can be decomposed or combined. For example, the modules in the above embodiments can be combined into one module, or further divided into multiple sub-modules to complete all or part of the functions described above. The names of the modules and steps involved in the embodiments of the present invention are only for distinguishing the modules or steps, and are not regarded as improper limitations of the present invention.

[0102] An electronic device according to the third embodiment of the present invention comprises: at least one processor; and a memory communicatively connected to at least one of the processors; wherein the memory stores instructions executable by the processor, and the instructions are used to be executed by the processor to implement the above-mentioned parallel optimization method for FPGA static timing analysis.

[0103] A computer-readable storage medium according to a fourth embodiment of the present invention stores computer instructions, and the computer instructions are used to be executed by the computer to implement the above-mentioned parallel optimization method for FPGA static timing analysis.

[0104] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process and related instructions of the electronic device and computer-readable storage medium described above can refer to the corresponding process in the aforementioned method example and will not be repeated here.

[0105] Those skilled in the art should be able to appreciate that the modules and method steps of each example described in conjunction with the embodiments disclosed herein can be implemented with electronic hardware, computer software or a combination of the two, and the programs corresponding to the software modules and method steps can be placed in random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the technical field. In order to clearly illustrate the interchangeability of electronic hardware and software, the composition and steps of each example have been generally described in the above description according to the function. Whether these functions are performed in electronic hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.

[0106] The terms "first", "second", etc. are used to distinguish similar objects rather than to describe or indicate a particular order or sequence.

[0107] The term "comprise" or any other similar term is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus / device that includes a list of elements includes not only those elements but also other elements not expressly listed, or also includes elements inherent to such process, method, article, or apparatus / device.

[0108] So far, the technical solutions of the present invention have been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, it is easy for those skilled in the art to understand that the protection scope of the present invention is obviously not limited to these specific embodiments. Without departing from the principle of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will fall within the protection scope of the present invention.

Claims

1. A parallel optimization method for FPGA static timing analysis, characterized in that: The method comprises the following steps: Step S1, obtaining a timing diagram and timing constraints of FPGA static timing analysis; performing memory layout optimization on the timing diagram and the timing constraints according to the constructed FPGA-oriented STA data structure; the timing diagram includes nodes, edges, delay models, and timing analysis results; Step S2, performing task decomposition on the timing graph after memory layout optimization, after decomposition, assigning the computational tasks of nodes and edges within each level to multiple parallel cores for parallel execution, and assigning single CPU threads to different levels for sequential execution; the parallel cores include CPU cores and GPU cores; Step S3, when executed, traverse the time sequence graph through a preset traversal strategy, and mark the nodes and edges to be updated; the preset traversal strategy includes full update and incremental update; Step S4, combined with the parallel computing strategy, obtains the effective arrival time of the node and the effective demand time of the node through bidirectional traversal calculation; determines the critical path in the FPGA timing static analysis according to the effective arrival time of the node and the effective demand time of the node, and then generates a parallel optimization report for the FPGA static timing analysis.

2. A parallel optimization method for FPGA static timing analysis according to claim 1, characterized in that: The memory layout of the timing diagram and timing constraints is optimized according to the constructed FPGA-oriented STA data structure, and the method is as follows: The structure of the timing graph is optimized to a hierarchical structure, wherein the data of the timing graph is stored in an array structure and only static node information and edge information are stored; When the timing graph is stored, the timing graph is stored as a timing graph in which the directed timing graph is stored as a bidirectional edge.

3. A parallel optimization method for FPGA static timing analysis according to claim 2, characterized in that: After memory layout optimization and before task decomposition, the following steps are also included: timing diagram verification and hierarchical query: The data is initialized and accessed for verification based on the hierarchical traversal order of the timing graph after memory layout optimization to ensure that the data access order during traversal is consistent with the storage order in memory.

4. A parallel optimization method for FPGA static timing analysis according to claim 3, characterized in that: The task decomposition of the timing diagram after memory layout optimization is performed as follows: Obtaining nodes to be processed in the timing diagram after memory layout optimization, allocating parallel kernel parameters, and performing task decomposition on the timing diagram after memory layout optimization using relevant function libraries; the relevant function libraries include TBB and CUDA; Perform task decomposition on the timing diagram after memory layout optimization, including fine-grained task decomposition and coarse-grained task decomposition; The fine-grained tasks are decomposed into: dividing each level of the timing graph after the memory layout is optimized into different fine-grained tasks, and assigning the computational tasks of the nodes and edges of each level to multiple parallel cores for parallel execution; the fine-grained tasks include arrival time pre-traversal, arrival time traversal, demand time pre-traversal, demand time traversal, relaxation update and state reset; The coarse-grained task is decomposed into: different levels of the timing graph after the memory layout is optimized are executed in sequence by a single CPU thread.

5. The parallel optimization method for FPGA static timing analysis according to claim 1, characterized in that: The full update is: each call uses a serial traversal method to completely re-analyze the timing diagram; the full update is used to initialize the construction and reset phases; The incremental update is as follows: in the last round of traversal, invalid edges and nodes to be updated are marked; When traversing the arrival time and demand time, only the nodes marked as to be updated are traversed, and the nodes that need to be added to the update queue are determined based on the invalid edges; the slack values ​​of the modified nodes are calculated and updated; The modified node is a node whose relaxation value in the update queue changes during traversal calculation; the incremental update is used in the parallel calculation stage.

6. The parallel optimization method for FPGA static timing analysis according to claim 5, characterized in that: Get the effective arrival time of a node by: Step S411, initializing the arrival time of all input pins based on the timing constraints; Step S412, adding the delay time of each edge to the source node arrival time of the edge to calculate the arrival time of the edge; Step S413, calculating the maximum setup time or the minimum hold time of all input edge arrival times at each downstream node, and storing it as the node arrival time; Step S414, determine whether step S3 is incrementally updated, if not, loop through steps S412-S413 until valid arrival times of all nodes are obtained, otherwise, loop through steps S412-S413 until valid arrival times of nodes in the update queue are obtained.

7. A parallel optimization method for FPGA static timing analysis according to claim 6, characterized in that: Get the effective demand time of a node by: Step S421, initializing the time required by all output pins according to the timing constraints; Step S422, subtract the sink node demand time of each edge from the delay time of the edge to calculate the edge demand time; Step S423, calculating the minimum setup time or the maximum hold time of all input edge demand times at each upstream node, and storing it as the node demand time; Step S424, determine whether step S3 is incrementally updated, if not, loop through steps S422-S423 until valid demand times of all nodes are obtained, otherwise, loop through steps S422-S423 until valid demand times of nodes in the update queue are obtained.

8. The parallel optimization method for FPGA static timing analysis according to claim 7, characterized in that: When calculating the effective arrival time of all nodes or the effective demand time of all nodes, a parallel computing strategy is used for parallel execution: By hierarchical calculation, the timing diagram is processed one level at a time. Two parallel kernel clusters are allocated in each level, one of which is responsible for piecewise addition and the other is responsible for piecewise maximum reduction. The processing process of the parallel kernel cluster responsible for the segmented addition is as follows: parallelization enables each kernel in the parallel kernel cluster to be assigned an edge, perform an edge calculation once, and obtain the edge arrival time or edge demand time; The processing process of the parallel kernel cluster responsible for segmented maximization reduction is as follows: each parallel kernel in the parallel kernel cluster is assigned to a sink node of the current layer, traverses the arrival time or demand time of all edges related to the sink node, and performs a maximization reduction operation to obtain the final arrival time or demand time.

9. A parallel optimization method for FPGA static timing analysis according to claim 8, characterized in that: According to the effective arrival time of all nodes and the effective demand time of all nodes, the critical path in the static analysis of FPGA timing is determined as follows: The difference between the effective arrival time and the effective demand time of all nodes in each path is calculated, and the path corresponding to zero or the smallest difference is taken as the critical path.

10. The parallel optimization method for FPGA static timing analysis according to claim 9, characterized in that: Generate a parallel optimization report for FPGA static timing analysis by: After parallel computing completes all critical path calculations, the parameter value records of all intermediate links are extracted and a readable parallel optimization report for FPGA static timing analysis is generated.

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