AI-assisted time sequence report analysis method

Abstract

The invention discloses an AI-assisted time sequence report analysis method, and belongs to the technical field of integrated circuit design automation. The method comprises the following steps: acquiring a static time sequence analysis report; analyzing the report through an analysis rule base, and extracting structured information of a time sequence path; performing hierarchical grouping on the plurality of analyzed time sequence paths according to time sequence grouping, clock domains and violation types to generate time sequence statistical characteristics; and identifying a key path according to the time sequence statistical characteristics, and outputting a structured analysis result and an optimization suggestion. Through automatic analysis and intelligent analysis, the time sequence debugging efficiency is remarkably improved, dependence on experience of engineers is reduced, and the method is suitable for time sequence convergence scenes of large-scale integrated circuit design.

Description

Technical Field

[0001] This invention relates to the fields of integrated circuit design automation (EDA) and artificial intelligence-aided design technology, specifically to a method for automatic parsing and critical path identification of static timing analysis (STA) reports based on artificial intelligence algorithms. Background Technology

[0002] In modern large-scale integrated circuit design, static timing analysis is a crucial step in verifying whether a chip meets target frequencies and timing constraints. EDA tools typically generate numerous timing reports after synthesis or place-and-route, describing the delays, margins, and constraints of various timing paths. As chip size continues to increase, the number of timing paths grows exponentially, resulting in massive timing report files with complex path types and timing groups.

[0003] The current industry-standard time series analysis methods mainly rely on manual analysis by engineers. The typical process includes: using static time series analysis tools to generate a timing report, engineers manually reading and screening the report content, judging which paths are critical paths or potential risk paths based on experience, comparing different versions of the report, and manually inferring the causes of time series changes. This existing technical solution has the following disadvantages: (1) it is highly dependent on engineers' experience, and different engineers may have different analysis results for the same report; (2) the analysis efficiency is low, the iteration cycle is long, and it is difficult to support high-frequency design iterations; (3) it is difficult to systematically track the causes of time series changes; and (4) it lacks structured summaries and decision support. Summary of the Invention

[0004] The purpose of this invention is to provide an AI-assisted time series report analysis method that can quickly identify critical paths and assist engineers in making time series optimization decisions by automatically parsing, grouping, comparing and summarizing time series information, thereby significantly improving the efficiency of time series analysis and debugging.

[0005] To achieve the above objectives, the present invention provides an AI-assisted time series report analysis method, comprising the following steps.

[0006] Step 1: Automatic parsing of timing reports;

[0007] Obtain the static timing analysis report of the integrated circuit design. Parse the static timing analysis report using a parsing rule base to extract structured information about the timing paths. The parsing rule base includes an EDA report terminology normalization dictionary, and the structured information includes path slack, clock period, path delay, start cell, end cell, and the corresponding timing group.

[0008] Specifically, the parsing process includes: identifying different ways of expressing the same timing indicator in static timing analysis reports generated by different EDA tools or different design stages, and uniformly mapping the different expressions. The timing indicator includes at least cell delay and net delay. Based on regular expressions and semantic analysis, the structured information is extracted from the non-standardized typesetting report. The extracted structured data is then subjected to integrity verification and missing field completion.

[0009] The above analysis process solves the problem of inconsistent timing report formats generated by different EDA tools, different process nodes, and different design stages, and realizes the structured analysis of non-standardized reports.

[0010] Step 2: Intelligent grouping of time-series paths; The parsed multiple timing paths are hierarchically grouped according to timing grouping, clock domain, and violation type, generating timing statistical characteristics for each group. The timing statistical characteristics include at least worst-case negative margin (WNS) and total negative margin (TNS), and may also include violation path percentage, cell delay percentage, average path delay, and path delay distribution range.

[0011] In a preferred embodiment, the hierarchical grouping by time sequence, clock domain, and violation type is implemented based on a graph neural network (GNN). By constructing a path association model, the hierarchical grouping is automatically performed by time sequence, clock domain, and violation type, outputting the time sequence statistical features of each dimension.

[0012] By using multi-dimensional intelligent grouping, the problem of the inability of manual systems to systematically count tens of thousands of time-series paths is solved, and the time-series health of each time-series group can be quickly identified.

[0013] Step 3: Multi-version time series comparison and root cause tracing; Obtain static timing analysis reports for at least two design versions, compare and analyze the timing paths of different versions, and detect changes in timing metrics. Through difference analysis, quantify and locate the root causes of timing changes, including changes in path topology, changes in cell delays, or changes in constraints. Generate a structured comparison report containing a multi-version timing comparison table and root cause classification.

[0014] Through multi-version comparison and difference analysis, automatic tracking and root cause quantitative analysis of temporal changes between versions are achieved, which can quantify the contribution of each factor to temporal deterioration.

[0015] Step 4: Critical path identification; Critical paths are identified based on the aforementioned temporal statistical features. Specifically, delay correlation analysis is performed on multiple temporal paths within the same temporal group. This delay correlation analysis is based on the similarity of the unit delay change rates of the multiple paths. When the unit delay change rates of multiple paths all exceed a set threshold, the multiple paths are identified as a critical path cluster with consistent delay change trends, where the set threshold is a preset value. The critical path cluster is used to indicate the execution targets of batch optimization operations.

[0016] Delay correlation analysis can identify critical path clusters with highly consistent delay change trends in the same time series grouping, enabling batch optimization and improving optimization efficiency by more than 5 times.

[0017] Step 5: Predicting Potential Risk Paths; Historical iteration data of time-series paths is acquired, and potential violation path judgment rules are constructed based on this data. Specifically, based on the statistical correlation between path features and violation results in the historical iteration data, thresholds for each feature are set as judgment rules. These judgment rules at least include identifying potential risk paths based on path margin, unit delay growth rate, and time-series group load changes. Based on these judgment rules, potential risk paths that are not currently in violation but are predicted to potentially violate in future iterations are identified, and warning information is output.

[0018] By constructing judgment rules based on historical data, we can identify potential risk paths that are not currently in violation but may become critical paths in the future, thus enabling proactive early warning of time-series issues.

[0019] Step Six: Time Series Analysis Knowledge Graph; A time-series analysis knowledge graph is generated, which stores the relationships between path features, root causes of violations, optimization schemes, and optimization effects. When the features of a newly identified time-series path match the path features in the knowledge graph, the corresponding optimization scheme is output. Here, "matching" means that the new path's path type, unit type, delay ratio structure, and other features are the same as or highly similar to the path features stored in the knowledge graph.

[0020] By leveraging knowledge graphs to accumulate experience in time-series analysis across projects and versions, we can achieve intelligent recommendations for optimization solutions and avoid engineers repeating trial and error.

[0021] Step 7: Time-series health score; The time health score of the time series group is calculated. The time health score is calculated based on at least two of the following indicators: worst negative margin, violation path ratio, total negative margin, unit delay ratio, and path delay distribution standard deviation of the time series group, wherein the worst negative margin has the highest weight.

[0022] Through multi-dimensional composite scoring, it provides a comprehensive health assessment based on time-series grouping, helping engineers quickly locate problematic modules.

[0023] Step 8: Root cause unit localization; The cell delay ratio and interconnect delay ratio of the timing path are quantitatively analyzed. Based on the rate of change of the cell delay ratio and the change of interconnect delay, a comprehensive judgment is made to locate the root cell causing the timing violation.

[0024] By quantifying the contribution of changes in cell delay and interconnect delay, the specific cell causing the timing violation can be accurately located.

[0025] Step 9: Output the structured analysis results.

[0026] Output structured time series analysis results and optimization suggestions, including at least one of the following: critical path list, time series grouping statistics summary table, multi-version time series comparison table, and time series constraint impact table.

[0027] Structured summary reports provide engineers with clear and actionable support for time-series optimization decisions.

[0028] In summary, compared with existing technical solutions that rely on engineers manually analyzing timing reports, this invention has the following advantages: (1) Achieve automation and intelligence in STA report analysis: The algorithm automatically parses and processes timing reports, reducing the workload of manual reading and screening. The analysis task that would take 3 days to complete manually can be completed in just 10 minutes by the algorithm.

[0029] (2) Significantly improve timing debugging efficiency: Quickly identify critical paths and the causes of timing changes, and accelerate design iteration speed. Through batch optimization of critical path clusters, optimization efficiency is improved by more than 5 times.

[0030] (3) Reduce reliance on engineers’ personal experience: Transform the empirical analysis process into an algorithmic flow to improve the consistency and reproducibility of the analysis results.

[0031] (4) Provide structured decision support: Provide clear and actionable references for time series optimization through summary reports and optimization suggestions.

[0032] (5) Suitable for complex, large-scale designs: It can handle complex chip designs with a large number of timing paths and multiple timing groups, and is suitable for advanced process node applications.

[0033] (6) Achieve proactive early warning: By predicting potential risk paths, identify potential future violations in advance and achieve proactive management of time-series issues.

[0034] (7) Accumulate design experience: Through knowledge graphs, systematically accumulate time series analysis experience across projects and versions to avoid repeated trial and error. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein: Figure 1 This is a flowchart illustrating the AI-assisted time series report analysis method provided by the present invention. Detailed Implementation

[0036] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0037] The terms "first," "second," etc., used in this specification are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class, without limiting the number of objects; for example, the first object can be one or more. Furthermore, in the specification, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0038] Please see Figure 1 As shown, this invention provides an AI-assisted time series report analysis method, including: Step S1: Obtain the static timing analysis report of the integrated circuit design; Step S2: The static timing analysis report is parsed using a parsing rule base to extract structured information of the timing path. The parsing rule base includes an EDA report terminology normalization dictionary. The structured information includes path margin, clock cycle, path delay, starting unit, ending unit, and the timing group to which it belongs. Step S3: The parsed multiple timing paths are hierarchically grouped according to timing group, clock domain and violation type, and the timing statistical characteristics of each group are generated. The timing statistical characteristics include at least the worst negative margin and the total negative margin. Step S4: Identify the critical path based on the time-series statistical features, and output structured time-series analysis results and optimization suggestions.

[0039] In step S3, the hierarchical grouping by timing, clock domain, and violation type is implemented based on a graph neural network.

[0040] Furthermore, the time-series statistical characteristics also include the proportion of violation paths, the proportion of unit delays, the average path delay, and the path delay distribution range.

[0041] Step S2, parsing through the rule base, further includes: Identify different ways of expressing the same timing metric in static timing analysis reports generated by different EDA tools or different design stages, and perform a unified mapping on the different ways of expressing the timing metric, which includes at least cell delay and interconnect delay. Based on regular expressions and semantic analysis, the structured information is extracted from reports with non-standardized typesetting. Perform integrity checks and fill in missing fields on the extracted structured data.

[0042] The AI-assisted time series report analysis method provided by this invention also includes: Obtain static timing analysis reports for at least two design versions; Compare and analyze the timing paths of different versions to detect changes in timing metrics; Through difference analysis, the root causes of time series changes are quantified and located, including changes in path topology, changes in unit delay, or changes in constraints. Generate a structured comparison report containing multiple version time series comparison tables and root cause classifications.

[0043] In step S4, identifying the critical path includes: Delay correlation analysis is performed on multiple time-series paths within the same time-series group, and the delay correlation analysis is based on the similarity of the unit delay change rate of the multiple paths. When the unit delay change rate of multiple paths all exceeds a set threshold, the multiple paths are identified as a cluster of critical paths with consistent delay change trends. The critical path cluster is used to indicate the execution objects of batch optimization operations.

[0044] The output includes structured time series analysis results and optimization suggestions, including: Generate a time-series analysis knowledge graph, which is used to store the relationships between path features, root causes of violations, optimization schemes, and optimization effects; When the features of a newly identified temporal path match the path features in the knowledge graph, the corresponding optimization scheme is output.

[0045] The AI-assisted time series report analysis method provided by this invention also includes: Obtain historical iteration data of the time-series path; Based on the historical iterative data, a potential violation path judgment rule is constructed. The judgment rule includes at least identifying potential risk paths based on path margin, unit delay growth rate, and time-series grouped load changes. Based on the judgment rules, identify potential risk paths that are not currently in violation but are predicted to be in violation in future iterations, and output warning information.

[0046] The AI-assisted time series report analysis method provided by the present invention further includes: calculating the time series health score of the time series group, wherein the time series health score is calculated based on at least two of the following indicators: the worst negative margin, the proportion of violation paths, the total negative margin, the proportion of unit delay, and the standard deviation of path delay distribution of the time series group, wherein the worst negative margin has the highest weight.

[0047] The AI-assisted timing report analysis method provided by this invention further includes: quantitatively analyzing the cell delay ratio and interconnect delay ratio of the timing path, making a comprehensive judgment based on the rate of change of the cell delay ratio and the change of interconnect delay, and locating the root cause cell that causes the timing violation.

[0048] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in further detail below.

[0049] Example 1: Time Series Comparison Analysis Before and After Design Iteration This embodiment uses a 5nm process system-on-a-chip (SoC) design as an example to illustrate the application of the present invention in timing analysis between two design iterations (version V1 and version V2).

[0050] 1. Automatic parsing of time series reports; The algorithm retrieves static timing analysis reports for versions V1 and V2. It then parses the reports using a parsing rule base, which includes an EDA report terminology normalization dictionary to identify and uniformly map different expressions. For example, it uniformly maps "Net Delay" and "Interconnect Delay" to "interconnect delay," and "Setup S" and "Setup Slack" to "setup time margin."

[0051] Based on regular expressions and semantic analysis, the algorithm extracts structured information from non-standardized typesetting reports, including path slack, clock period, path delay, starting unit, ending unit, and the corresponding time series group. After integrity verification, all data fields are complete, and the unit is uniformly set to picoseconds (ps).

[0052] 2. Intelligent grouping of time-series paths; The algorithm stratifies the parsed timing paths into hierarchical groups based on timing sequence, clock domain, and violation type. In this embodiment, a path association model is constructed based on a graph neural network (GNN) to perform cluster analysis on the paths under the Core_CPU0 timing group.

[0053] The generated grouped time-series statistical features include: Worst Negative Margin (WNS): -5.0ps for version V1, -8.2ps for version V2; Total negative margin (TNS): -5.0ps for version V1, -8.2ps for version V2; Percentage of violations: V1 version 0.008% (only 1 path), V2 version 0.008% (still the same path); Unit latency percentage: 54.4% for version V1 and 57.6% for version V2; Average path latency: 817.5ps ​​for version V1 and 828ps for version V2 (an increase of 1.28%). Path delay distribution range: The overall distribution in version V2 has shifted to the right, showing a worsening trend.

[0054] Through the above intelligent grouping and statistical feature calculation, the timing health status of the Core_CPU0 group was quickly identified as deteriorating, with WNS deteriorating by 3.2ps and TNS synchronization deteriorating by 3.2ps, and core violations concentrated in the P001 path.

[0055] 3. Multi-version time series comparison and root cause tracing; The algorithm compares and analyzes the timing paths of versions V1 and V2. The refined comparison results for a single path are shown in Table 1. Table 1. Comparison Results of Single-Path Refinement

[0056] Through differential analysis, the algorithm quantifies and locates the root causes of time-series variations: Factors excluded: The P001 path topology remained unchanged, the clock cycle was not adjusted (still 800ps), and the interconnect delay actually decreased, thus ruling out timing degradation caused by topology changes, clock constraints, and routing delays. The root cause: The latency of the AND2_X10 unit in the P001 path increased from 120ps to 215ps, directly causing the unit latency ratio of the entire path to rise from 60% to 70.5%, which is the only core reason for the deterioration of Slack.

[0057] Through multi-version comparison and difference analysis, the root cause of timing degradation was accurately located as increased latency of specific cells, rather than topology changes or constraint adjustments.

[0058] 4. Critical path identification; The algorithm performs latency correlation analysis on timing paths within the Core_CPU0 group, judging based on the similarity of the unit latency change rate of multiple paths. The analysis results show that the unit latency change rate of path P001 is +79.2% (increasing from 120ps to 215ps), while the unit latency change rates of other paths in this group are all within 5%, showing a significant difference. Therefore, P001 is identified as an independent critical path, rather than a critical path cluster.

[0059] By using delay correlation analysis, the core violation paths can be accurately identified, avoiding ineffective analysis of non-critical paths.

[0060] 5. Root unit localization; The algorithm quantifies the proportion of cell delay and interconnect delay in path P001. The results show that the cell delay increased by 112.5 ps (+22.06%), and although the interconnect delay decreased by 134.5 ps (-39.6%), it still could not offset the significant increase in cell delay. Based on the rate of change of the cell delay proportion (+10.5%), and combined with the change in interconnect delay, the algorithm identifies cell AND2_X10 as the root cause of the timing violation.

[0061] By comprehensively judging cell delay and interconnect delay, the root cause cell can be accurately located.

[0062] 6. Output of time-series analysis knowledge graph and optimization scheme; The algorithm generates a time-series analysis knowledge graph, storing the relationships between path features, violation root causes, optimization schemes, and optimization effects. Based on knowledge graph matching, when the path type, unit type, delay ratio structure, and other features of a new path are the same as or highly similar to the path features stored in the knowledge graph, the algorithm outputs the corresponding optimization scheme. In this embodiment, the algorithm outputs optimization schemes, as shown in Table 2: Table 2 Algorithm Output Optimization Scheme

[0063] Through intelligent matching based on knowledge graphs, engineers are provided with feasible optimization solutions and expected performance assessments, avoiding manual trial and error.

[0064] 7. Time-series health score and structured results output; The algorithm calculates the timing health score for the Core_CPU0 group. This score is calculated based on a composite of worst-case negative margin (WNS), violation path percentage, total negative margin (TNS), cell latency percentage, and path latency distribution standard deviation, with the worst-case negative margin having the highest weight.

[0065] In this embodiment, the health score of the Core_CPU0 group is 62 / 100, indicating that the group has significant timing risks.

[0066] The algorithm outputs structured time series analysis results, including: Critical Path List: Detailed information about path P001 (starting cell, ending cell, Slack, cell latency percentage, interconnect latency percentage, etc.); Timing Group Statistics Summary Table: Total number of paths, number of violation paths, WNS, TNS, average Slack, and latency distribution range for Core_CPU0 group; Multi-version time series comparison table: WNS / TNS changes, number of critical paths added or removed, and root cause classification between V1 and V2 versions; Timing Constraint Impact Table: Evaluate the impact of constraint adjustments on timing (no constraint changes in this embodiment).

[0067] Structured summary reports provide engineers with clear and actionable support for time-series optimization decisions.

[0068] Example 2: Prediction of Potential Risk Paths This embodiment uses the multiple iterations of a 5nm SoC design as an example to illustrate the potential risk path prediction function of the present invention.

[0069] 1. Acquisition of historical iteration data; The algorithm acquires historical iteration data of timing paths from multiple design versions, including indicators such as path margin (Slack), cell delay growth rate, and timing group load changes for each path in each iteration, as well as label data indicating whether the path ultimately becomes an illegal path.

[0070] 2. Construction of rules for identifying potential violation paths; Based on historical iteration data, the algorithm constructs rules for judging potential violation paths. Specifically, based on the statistical correlation between path features and violation results in historical iteration data, thresholds for each feature are set as judgment rules. In this embodiment, the judgment rules include: the current path margin is positive (Slack>0), but the unit latency growth rate exceeds 15%, and the load of the time-series group to which it belongs continues to increase (the number of paths increases or the logical complexity increases).

[0071] 3. Identification of potential risk paths; The algorithm inputs the timing path characteristics of the current design version (V3) into the judgment rules. It identifies that the current Slack of path P036 is +1.2ps (positive value), but its cell latency growth rate reaches 18%, and the DDR timing packet load to which it belongs has increased by 12% compared to the previous version. Therefore, path P036 is marked as a potential risk path, and a warning message is output.

[0072] 4. Verification of prediction results; In the subsequent placement and routing iteration (V4), the Slack of the P036 path deteriorated to -2.5ps, becoming an actual violation path, thus validating the effectiveness of the prediction.

[0073] By predicting potential risk paths, we can proactively warn of time-series problems and avoid reactive analysis after problems occur.

[0074] Example 3: Critical Path Cluster Identification and Batch Optimization This embodiment uses a CPU core design as an example to illustrate the critical path cluster identification function of the present invention.

[0075] 1. Delayed correlation analysis; The algorithm performs latency correlation analysis on multiple timing paths within the Core_CPU0 timing group, and makes judgments based on the similarity of the unit latency change rates of multiple paths. The analysis found that the unit latency change rates of paths P001, P015, and P028 are 22%, 21%, and 23%, respectively, all exceeding the preset threshold of 20%, and the latency change trends are highly consistent.

[0076] 2. Critical path cluster identification; The algorithm identifies P001, P015, and P028 as critical path clusters and outputs the analysis results.

[0077] 3. Batch optimization; Engineers performed batch optimization on this critical path cluster, uniformly replacing the common AND2_X10 units in the paths with the AND2_X8 version. After optimization, the Slack of all three paths returned to positive values, and the optimization efficiency was improved by more than 5 times compared to analyzing each path individually.

[0078] By identifying critical path clusters, batch optimization can be achieved, significantly improving optimization efficiency.

[0079] Example 4: Calculation and Output of Time-Series Health Score This embodiment 4 details the calculation method of time series health score, the output format of the score result, and its application effect in time series analysis.

[0080] 1. Core principles of time-series health assessment; The time series health score is a composite index ranging from 0 to 100, used to comprehensively reflect the time series risk of time series groups (such as Core_CPU0). This score is a weighted sum of normalized time series indicators from multiple dimensions, where the worst-case negative margin (…) is the most significant factor. The weight of ) is the highest, and it is also combined with the proportion of violation paths and the total negative margin ( The evaluation is based on a comprehensive assessment of factors such as unit delay percentage and path delay distribution standard deviation. Weight allocation can be flexibly adjusted according to the design stage and process node. In this embodiment, the weight allocation is as follows: The weight is 0.4, and the weights of the other four indicators are each 0.15.

[0081] 2. Calculation method for normalized scores of each indicator; The formulas for calculating the normalized scores of each indicator are as follows: (1) Worst-case negative margin ( )Score; The worst-case margin reflects the severity of the most serious single-point violation in the group. The closer to 0, the higher the score. The normalized score is calculated using the following formula: ; in, This represents the actual measured value (a negative value indicates a violation). Defined for the project Threshold (e.g., -0.5ns). When The score is 0 when the value equals the threshold. A score of 100 is awarded when the value is 0.

[0082] (2) Score based on the percentage of violations; The percentage of violation paths reflects the breadth of the timing problems in this group; the fewer the violation paths, the higher the score. The normalized score is calculated using the following formula: ; in, This represents the number of violation paths within the group. This represents the total number of paths within a group. 100 points are awarded when there are no violation paths, and 0 points are awarded when all paths are violation paths.

[0083] (3) Total negative margin ( )Score; Total margin reflects the overall cumulative severity of violations in that group. The closer to 0, the higher the score. The normalized score is calculated using the following formula: ; in, These are actual measured values. Defined for the project Threshold (e.g., -1000ns). When The score is 0 when the value equals the threshold. A score of 100 is awarded when the value is 0.

[0084] (4) Score based on the percentage of unit delay; The unit latency percentage reflects the proportion of unit latency in the critical path within a group to the total latency. A lower unit latency percentage indicates greater room for interconnect latency optimization and a higher score. The normalized score calculation formula is as follows: ; in, The percentage of average unit latency on the critical path within the group. The target unit latency percentage (e.g., 60%). The threshold is the percentage of latency in the warning unit (e.g., 90%). A score of 100 is given when the percentage of latency in the unit is lower than the target value, and a score of 0 is given when it is higher than the warning value.

[0085] (5) Standard deviation score of path delay distribution; The standard deviation of the path delay distribution reflects the concentration of path delays within a group. A smaller standard deviation indicates a more concentrated path delay distribution, better temporal convergence, and a higher score. The formula for calculating the normalized score is: ; in, The standard deviation of the critical path delay within the group. The target standard deviation is (e.g., 0.2 ns). The warning standard deviation is given (e.g., 1.0 ns). A score of 100 is given when the standard deviation is below the target value, and a score of 0 is given when it is above the warning value.

[0086] 3. Calculation of the total score for temporal health status; The weighted sum of the normalized scores of each indicator yields the comprehensive health score for the time-series grouping: ; in, ,and Weight The maximum weight is assigned. In this embodiment, the weight allocation is as follows: , , , , .

[0087] 4. Example calculation; Taking the Core_CPU0 group in Example 1 as an example, the actual values ​​of each indicator and the calculation of the normalized score are shown in Table 3 below: Table 3. Actual values ​​and normalized scores of each indicator.

[0088] The total score is calculated by weighted summation: Score=0.4×40+0.15×80+0.15×40+0.15×50+0.15×50=16+12+6+7.5+7.5=49; The group scored 49 points, which is considered a high-risk level, consistent with the actual timeline.

[0089] 5. Scoring results output and visualization; The algorithm outputs structured time-series health scores, including a module-level summary table and a detailed score composition table for each module.

[0090] (1) Module-level summary, as shown in Table 4: Table 4 Module-level Summary Table

[0091] (2) The detailed scoring structure of a single module (taking Core_CPU0 as an example) is shown in Table 5: Table 5 Detailed Scoring Composition for a Single Module

[0092] (3) Definition and interpretation of scoring intervals The algorithm automatically classifies time-series risk levels based on health scores, as specifically defined in Table 6 below: Table 6 Definition of Time-Series Risk Levels

[0093] 6. Application effects; By using time-series health scores, engineers can quickly complete the following tasks: Quickly identify high-risk modules: Through the module-level summary table, DDR_Phy and Core_CPU0 can be clearly identified as high-risk modules that require priority allocation and optimization of resources; Problem identification dimensions: A detailed scoring table for each module allows for analysis of the scores across all dimensions. For example, Core_CPU0... and The low scores (all 40 points) indicate that this module has serious and cumulative violations and should be addressed as a priority. The worst path; Allocate optimization resources reasonably: Based on optimization priority, allocate optimization resources to high-risk modules first, and avoid wasting optimization time on healthy modules; Track optimization results: After optimization iteration, the health score is recalculated, and the optimization effect can be intuitively evaluated through the changes in the score.

[0094] By using multi-dimensional composite scoring, it provides a comprehensive health assessment of time series groups, helping engineers quickly locate problematic modules, identify problem dimensions, and rationally allocate and optimize resources, significantly improving the efficiency and accuracy of time series analysis.

[0095] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An AI-assisted time-series report analysis method, characterized in that, include: Step S1: Obtain the static timing analysis report of the integrated circuit design; Step S2: The static timing analysis report is parsed using a parsing rule base to extract structured information of the timing path. The parsing rule base includes an EDA report terminology normalization dictionary. The structured information includes path margin, clock cycle, path delay, starting unit, ending unit, and the timing group to which it belongs. Step S3: The parsed multiple timing paths are hierarchically grouped according to timing group, clock domain and violation type, and the timing statistical characteristics of each group are generated. The timing statistical characteristics include at least the worst negative margin and the total negative margin. Step S4: Identify the critical path based on the time-series statistical features, and output structured time-series analysis results and optimization suggestions.

2. The AI-assisted time-series report analysis method according to claim 1, characterized in that, In step S3, the hierarchical grouping by timing, clock domain, and violation type is implemented based on a graph neural network.

3. The AI-assisted time-series report analysis method according to claim 1, characterized in that, Step S2, parsing through the rule base, further includes: Identify different ways of expressing the same timing metric in static timing analysis reports generated by different EDA tools or different design stages, and perform a unified mapping on the different ways of expressing the timing metric, which includes at least cell delay and interconnect delay. Based on regular expressions and semantic analysis, the structured information is extracted from reports with non-standardized typesetting. Perform integrity checks and fill in missing fields on the extracted structured data.

4. The AI-assisted time-series report analysis method according to claim 1, characterized in that, In step S3, the time-series statistical features also include the proportion of violation paths, the proportion of unit delays, the average path delay, and the path delay distribution range.

5. The AI-assisted time-series report analysis method according to claim 1, characterized in that, Also includes: Obtain static timing analysis reports for at least two design versions; Compare and analyze the timing paths of different versions to detect changes in timing metrics; Through difference analysis, the root causes of time series changes are quantified and located, including changes in path topology, changes in unit delay, or changes in constraints. Generate a structured comparison report containing multiple version time series comparison tables and root cause classifications.

6. The AI-assisted time-series report analysis method according to claim 1, characterized in that, In step S4, identifying the critical path includes: Delay correlation analysis is performed on multiple time-series paths within the same time-series group, and the delay correlation analysis is based on the similarity of the unit delay change rate of the multiple paths. When the unit delay change rate of multiple paths all exceeds a set threshold, the multiple paths are identified as a cluster of critical paths with consistent delay change trends. The critical path cluster is used to indicate the execution objects of batch optimization operations.

7. The AI-assisted time-series report analysis method according to claim 1, characterized in that, Also includes: Obtain historical iteration data of the time-series path; Based on the historical iterative data, a potential violation path judgment rule is constructed. The judgment rule includes at least identifying potential risk paths based on path margin, unit delay growth rate, and time-series grouped load changes. Based on the judgment rules, identify potential risk paths that are not currently in violation but are predicted to be in violation in future iterations, and output warning information.

8. The AI-assisted time-series report analysis method according to claim 1, characterized in that, In step S4, the structured time series analysis results and optimization suggestions are output, including: Generate a time-series analysis knowledge graph, which is used to store the relationships between path features, root causes of violations, optimization schemes, and optimization effects; When the features of a newly identified temporal path match the path features in the knowledge graph, the corresponding optimization scheme is output.

9. The AI-assisted time-series report analysis method according to claim 1, characterized in that, Also includes: The time health score of the time series group is calculated. The time health score is calculated based on at least two of the following indicators: worst negative margin, violation path ratio, total negative margin, unit delay ratio, and path delay distribution standard deviation of the time series group, wherein the worst negative margin has the highest weight.

10. The AI-assisted time-series report analysis method according to claim 1, characterized in that, Also includes: The cell delay ratio and interconnect delay ratio of the timing path are quantitatively analyzed. Based on the rate of change of the cell delay ratio and the change of interconnect delay, a comprehensive judgment is made to locate the root cell causing the timing violation.

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