A method and apparatus for fast repair of time violation in static timing analysis

Abstract

The application relates to the field of integrated circuit design and verification technology, and discloses a fast repairing method and device for establishing time violation in static timing analysis. The method comprises the following steps: obtaining a static timing analysis report; extracting a target timing path according to the static timing analysis report; calculating a plurality of types of redundancy values of each module passed through by the target timing path; calculating a redundancy value set of a data path of the target timing path and a redundancy value subset corresponding to each module according to the redundancy values of the modules corresponding to the target timing path; determining a repairing sequence of each module according to the redundancy values of the modules corresponding to the target timing path; analyzing each module according to the redundancy value set and the redundancy value subset of each module in sequence to determine a repairing scheme of each module; and obtaining a repairing strategy of the target timing path according to the repairing schemes of the modules passed through by the target timing path. The application provides an efficient solution for an early stage of time repairing.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design and verification technology, and specifically to a rapid repair method and apparatus for establishing timing violations in static timing analysis. Background Technology

[0002] With the continuous application of large-scale and very large-scale integrated circuits, process dimensions are constantly shrinking, and mainstream processes have reached the nanometer scale. This presents greater challenges to integrated circuit chip design. Establishing good timing closure is crucial for chip performance and stability during the design process. However, timing violations can occur due to factors such as inappropriate standard cell selection, improper placement and routing, inadequate logic optimization, and algorithmic discrepancies between different tools. Setup time violations are a specific type of timing violation, which can lead to data sampling errors or degraded circuit performance.

[0003] Existing setup time repair tools offer relatively accurate solutions for accelerating timing compliance in designs nearing timing convergence. However, their repair capabilities are primarily limited to adjustments at the standard cell level, such as adjusting the threshold voltage of standard cells, changing their size, inserting or removing buffers, and implementing high fan-out decomposition. For deeper placement and routing issues, such as verbose logic levels, circuitous paths, illogical standard cell placement, crosstalk between interconnects, and clock tree skew, these tools cannot provide effective risk warnings or direct remediation strategies. Therefore, existing setup time repair tools are more suitable for the later stages of timing convergence than for the earlier stages.

[0004] Addressing the aforementioned layout and wiring deficiencies still relies heavily on engineers' experience. However, due to varying levels of engineer qualifications, the solutions they provide are sometimes not the most efficient or economical. As design scale increases dramatically, the time required to manually develop corrective solutions is growing longer, significantly increasing project development time. Summary of the Invention

[0005] In view of this, the present invention provides a method and apparatus for rapid repair of setup time violations in static timing analysis, which can effectively identify and resolve setup time violations in the early stage of timing convergence, and also reduces the need for human intervention and significantly reduces the risk of human error.

[0006] In a first aspect, the present invention provides a rapid repair method for establishment time violations in static timing analysis, comprising: obtaining a static timing analysis report; extracting a target timing path based on the static timing analysis report, wherein the target timing path has establishment time violations and a target timing path passes through at least one module; calculating multiple types of redundancy values ​​for each module passed through by the target timing path; calculating a set of redundancy values ​​for the data path of the target timing path and a subset of redundancy values ​​corresponding to each module based on the redundancy values ​​of each module corresponding to the target timing path; determining the repair order of each module based on the redundancy values ​​of each module corresponding to the target timing path; analyzing each module sequentially according to the repair order of the modules, based on the set of redundancy values ​​and the subset of redundancy values ​​of each module, and determining a repair scheme for each module; and obtaining a repair strategy for the target timing path based on the repair schemes of each module passed through by the target timing path.

[0007] The rapid repair method for establishment time violations in static timing analysis provided by this invention obtains a static timing analysis report, identifies target timing paths with establishment time violations, calculates the redundancy values ​​of each module traversed by the target timing path to quantify the influence of each module in the timing path, and determines the repair order by calculating the redundancy values ​​of each module based on the redundancy value set and the redundancy value subset of each module. This prevents the occurrence of establishment time violations in the early stage of timing convergence, forming a systematic repair process. Each module is analyzed and repaired sequentially according to the repair order. By comprehensively considering the redundancy values ​​and repair schemes of each module, a globally optimal repair strategy is formulated. The automated calculation and repair process reduces the need for manual intervention.

[0008] In one optional implementation, after the steps of calculating the redundancy set of the data path of the target timing path and the redundancy subset corresponding to each module based on the redundancy values ​​of each module corresponding to the target timing path, and before the step of determining the repair order of each module based on the redundancy values ​​of each module corresponding to the target timing path, the method includes: calculating the clock tree skew value of the target timing path; determining the redundancy sum of the target timing path based on the sum of each element in the redundancy set of the data path of the target timing path; if the redundancy sum is greater than or equal to a first preset violation value, executing the step of determining the repair order of each module based on the redundancy values ​​of each module corresponding to the target timing path; if the redundancy sum is less than the first preset violation value, and the sum of the redundancy sum and a preset multiple of the clock tree skew value is greater than the first preset violation value, determining the repair strategy of the target timing path based on the engineering operations corresponding to each element in the redundancy set of the target timing path and the repair strategy of the clock tree skew value; if the redundancy sum is less than the first preset violation value, and the sum of the redundancy sum and a preset multiple of the clock tree skew value is less than the first preset violation value, sending the target timing path to the target user.

[0009] The fast repair method for establishing timing violations in static timing analysis provided in this invention calculates the clock tree skew value of the target timing path to understand the delay differences of clock signals on the path. Clock tree skew is one of the key factors affecting timing convergence. Therefore, accurately assessing the skew value helps to identify and solve potential problems in the design phase. By calculating the redundancy sum of the target timing path, the additional resources available for repair or optimization on the path can be evaluated. This helps determine whether it is possible to solve timing problems by adjusting redundant resources without more complex redesign or adding additional hardware resources. Based on the relationship between the redundancy sum and the clock tree skew value, this process can intelligently select repair strategies. For example, if the redundancy value is greater than or equal to the first preset violation value, the repair order can be determined based on the redundancy value of each module, prioritizing the modules with the most redundant resources to improve repair efficiency and success rate. If the redundant resources are insufficient but close to the first preset violation value, and considering the impact of clock tree skew, a comprehensive repair plan can be formulated by comprehensively considering the engineering operations corresponding to the redundancy value and the clock tree skew repair strategy. If the redundant resources are severely insufficient, even considering the clock tree skew repair strategy, the requirements cannot be met. This process will promptly send the target timing path information to the target user, helping the user to understand the problems in the design in a timely manner and take further measures to solve these problems.

[0010] In one optional implementation, calculating the clock tree skew value of the target timing path includes: determining a first delay based on the sum of the delays of each standard cell and each interconnect along the clock path during transmission; determining a second delay based on the sum of the delays of each standard cell and each interconnect along the clock path during reception; if the clock is an imperfect clock and the first delay is greater than the second delay, then determining the clock tree skew value of the target timing path based on the difference between the first delay and the second delay; if the clock is an ideal clock, or if the clock is an imperfect clock and the first delay is less than or equal to the second delay, then determining the clock tree skew value of the target timing path as 0.

[0011] The fast repair method for establishing timing violations in static timing analysis provided by this invention can accurately evaluate the clock tree skew value of the target timing path by considering the delay difference between the transmit and receive clock paths, as well as the ideal and non-ideal states of the clock. When the clock is non-ideal and the delay difference is large, the clock tree skew value can be automatically adjusted to adapt to the actual situation. By setting the skew value, the ideal clock or favorable delay difference can be handled, simplifying the design process.

[0012] In one optional implementation, the redundancy value includes one or more of the following: logic level redundancy value, standard cell delay redundancy value, interconnect crosstalk delay redundancy value, and path detour redundancy value.

[0013] The fast repair method for establishing timing violations in static timing analysis provided by this invention can better cope with performance fluctuations caused by external factors such as process changes and temperature changes by considering the redundancy values ​​of logic levels and standard cell delays. By considering the redundancy values ​​of interconnect crosstalk delays and path detours, the signal transmission path and performance can be optimized, signal loss and interference can be reduced, and signal integrity and stability can be improved.

[0014] In one optional implementation, the step of calculating the logic level redundancy value of any module in the target timing path includes: extracting the number of levels of standard cells in the data path of the target timing path in the module, and a third delay, the third delay being determined based on the sum of the standard cell delay and the interconnect delay of the data path of the target timing path; determining the typical value of the standard cell delay based on the median of the set of all standard cell delay information in the static timing analysis report; determining the typical value of the sum of the delays of standard cells and interconnects based on the ratio of the delay of standard cells to the delay of interconnects, and the typical value of the delay of standard cells; calculating the ideal maximum number of levels for each module based on the typical value of the sum of the delays of standard cells and interconnects in the module, and the third delay; if the number of levels of standard cells is greater than the ideal maximum number of levels, then calculating the logic level redundancy value based on the number of levels of standard cells, the ideal maximum number of levels, the ratio of the delay of standard cells to the delay of interconnects, and the third delay; if the number of levels of standard cells is less than or equal to the ideal maximum number of levels, then determining the logic level redundancy value as 0.

[0015] The fast repair method for establishing timing violations in static timing analysis provided by this invention can accurately assess the delay of the target timing path by calculating the sum of the delays of standard cells and interconnects, and considering the delay ratio and typical values, thereby improving the accuracy of timing analysis. By calculating the ideal maximum level and logic level redundancy value, the timing performance of the circuit can be better understood, and the design can be optimized as needed to meet performance requirements.

[0016] In one optional implementation, the step of calculating the standard cell delay redundancy value of any module in the target timing path includes: extracting the delay of each standard cell in the module; calculating the standard cell delay redundancy value based on the delay of each standard cell in the module and a typical value of the standard cell delay; if the calculated standard cell delay redundancy value is greater than a set delay redundancy value, then the calculated standard cell delay redundancy value is determined as the standard cell delay redundancy value; if the calculated standard cell delay redundancy value is less than or equal to the set delay redundancy value, then the standard cell delay redundancy value is determined to be 0.

[0017] The fast repair method for establishing timing violations in static timing analysis provided in this embodiment of the invention ensures that the delay of each standard cell is within the preset safety limit by setting an upper limit for acceptable delay and calculating the delay redundancy value of the standard cell, thereby improving the stability, reliability and performance of the circuit. For standard cells with large delay redundancy values, manual optimization design is required.

[0018] In one optional implementation, the step of calculating the path detour redundancy value of any module in the target timing path includes: extracting the standard unit string length of the module, the sum of the distances between any two adjacent standard units, and a fourth delay. The standard unit string length is the Manhattan distance between the adjacent starting standard unit position and the ending standard unit position of the module's standard unit string. The sum of the distances between any two adjacent standard units in the standard unit string is the sum of the Manhattan distances between any two adjacent standard units between the starting and ending standard unit positions. The fourth delay is the sum of the delays of all standard units in the standard unit string and the delay of the interconnect. The standard unit string of the module is a continuous string of standard units on the data path of the target timing path in the module. If any... If the sum of the distances between adjacent standard units is less than a set distance, the path detour redundancy value is set to 0. If the sum of the distances between any adjacent standard units in a standard unit string is greater than or equal to a set distance, and the ratio of the sum of the distances between any adjacent standard units to the length of the standard unit string is greater than a set ratio, the path detour redundancy value of the standard unit string is calculated based on the sum of the distances between any adjacent standard units in the standard unit string and the length of the standard unit string. If the sum of the distances between any adjacent standard units in a standard unit string is greater than a set distance, and the ratio of the sum of the distances between any adjacent standard units to the length of the standard unit string is less than or equal to a set ratio, the path detour redundancy value of the standard unit string is set to 0. The path detour redundancy value of the module is determined based on the sum of the path detour redundancy values ​​of each standard unit string in the module.

[0019] The fast repair method for establishing timing violations in static timing analysis provided in this embodiment of the invention accurately evaluates the impact of path detours on circuit timing performance by considering factors such as the length of the standard cell string, the sum of the distances between any adjacent standard cells, and delay, thereby improving the accuracy of timing analysis. For standard cell strings with large path detour redundancy values, manual optimization of layout and routing is required to reduce unnecessary detours.

[0020] In one optional implementation, the redundancy value set of the data path of the target time-series path and the redundancy value subset corresponding to each module are calculated based on the redundancy values ​​of each module. This includes: the redundancy value subset of the module includes a first weighted value corresponding to each type of redundancy value of the module, and a second weighted value of the redundancy value is obtained by weighting the redundancy value according to the type of redundancy value; the redundancy value set of the target time-series path includes a second weighted value corresponding to each type of redundancy value, and the second weighted value of the redundancy value is obtained by summing the first weighted values ​​of the redundancy value in each module.

[0021] The fast repair method for establishing time violations in static timing analysis provided in this embodiment of the invention accurately evaluates the impact of different types of redundancy values ​​on the overall performance of the target timing path by introducing weighted values.

[0022] In one optional implementation, the repair order of each module is determined based on the redundancy values ​​of each module corresponding to the target time-series path, including: establishing a redundancy value sequence for each module based on various types of redundancy values, where one column represents a type of redundancy value; performing column operations on the redundancy value sequence for each module and summing the column elements to obtain the sum of the column elements; weighting the sum of the column elements in the redundancy value sequence to obtain the evaluation sequence for each module; establishing an evaluation matrix for the target time-series path based on the evaluation sequence for each module; processing the evaluation matrix using the entropy weight method to obtain the evaluation score of each module in the target time-series path; and determining the repair order of each module based on the evaluation score of each module.

[0023] The fast repair method for establishing timing violations in static timing analysis provided by this invention uses the entropy weight method to process the evaluation matrix, objectively determine the weight of each redundancy value type, avoid the bias caused by subjective weighting, improve the objectivity of the evaluation, and can prioritize the repair order determined by the evaluation score, thereby more effectively improving the performance and stability of the overall circuit.

[0024] In one optional implementation, following the repair order of modules, each module is analyzed sequentially based on the set of redundant values ​​and the subset of redundant values ​​for each module to determine the repair scheme for each module. This includes: sequentially traversing the sum of all elements in the subset of redundant values ​​for each module according to the repair order, and comparing the sum of all elements in the subset of redundant values ​​with a second preset violation value; if the sum of all elements in the subset of redundant values ​​for the current module is greater than the second preset violation value, stopping the traversal, and performing a greedy algorithm on the redundant subset of the current module to determine the amount of redundancy elimination for each type of redundant value in the current module, so as to reduce the redundancy of each type of redundant value. The sum of the eliminated values ​​is greater than the second preset violation value and less than the third preset violation value. For each module, the sum of all elements in the redundant value subset of the previous module is subtracted from the current second preset violation value to obtain the updated second preset violation value. The sum of all elements in the redundant value subset of the previous module is subtracted from the current third preset violation value to obtain the updated third preset violation value. Based on the engineering operations corresponding to the elimination amount of various redundant values ​​in the current module, and the engineering operations corresponding to all elements in the redundant value subsets of all previously traversed modules, the repair scheme for each module is determined.

[0025] The fast repair method for establishing time violations in static timing analysis provided by this invention uses a greedy algorithm to process the redundant subset of the current module, which can accurately control the amount of various redundant values ​​eliminated, ensuring that over-optimization is not performed while eliminating redundancy. The preset violation value is dynamically updated during the traversal process, and subsequent judgments can be made based on the eliminated redundant values, ensuring the accuracy and effectiveness of the entire repair process. By comprehensively considering the amount of redundant value elimination and the corresponding engineering operations of the current module and all previously traversed modules, a more comprehensive and optimized repair strategy can be formulated.

[0026] Secondly, the present invention provides an apparatus for rapid repair of establishment time violations in static timing analysis, comprising: an acquisition module for acquiring a static timing analysis report; an extraction module for extracting a target timing path based on the static timing analysis report, wherein the target timing path has establishment time violations and a target timing path passes through at least one module; a redundancy value calculation module for calculating multiple types of redundancy values ​​of each module passed through by the target timing path; a redundancy value set calculation module for calculating the redundancy value set of the data path of the target timing path and the redundancy value subset corresponding to each module based on the redundancy values ​​of each module corresponding to the target timing path; a repair order determination module for determining the repair order of each module based on the redundancy values ​​of each module corresponding to the target timing path; a repair scheme determination module for analyzing each module sequentially according to the repair order of the modules, based on the redundancy value set and the redundancy value subset of each module, and determining the repair scheme of each module; and a repair strategy determination module for obtaining the repair strategy of the target timing path based on the repair scheme of each module passed through by the target timing path.

[0027] Thirdly, the present invention provides a computer device, comprising: a memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the computer instructions to perform the fast repair method for establishing timing violations in static timing analysis as described in the first aspect or any corresponding embodiment.

[0028] Fourthly, the present invention provides a computer-readable storage medium storing computer instructions for causing a computer to execute the fast repair method for establishing timing violations in static timing analysis of the first aspect or any corresponding embodiment described above. Attached Figure Description

[0029] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0030] Figure 1 This is a flowchart illustrating a fast repair method for establishing timing violations in static timing analysis according to an embodiment of the present invention.

[0031] Figure 2 This is a flowchart illustrating a fast repair method for establishing timing violations in another static timing analysis according to an embodiment of the present invention.

[0032] Figure 3 This is a flowchart illustrating a fast repair method for establishing timing violations in another static timing analysis according to an embodiment of the present invention.

[0033] Figure 4 This is a flowchart illustrating a fast repair method for timing violations in another static timing analysis according to an embodiment of the present invention.

[0034] Figure 5 This is a structural block diagram of a rapid repair device for establishing time violations in static timing analysis according to an embodiment of the present invention.

[0035] Figure 6 This is a schematic diagram of the structure of a computer device according to an embodiment of the present invention. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0037] The rapid repair method for establishing timing violations in static timing analysis provided by this invention is applied to the critical stage of processing static timing analysis reports to improve chip performance. By acquiring the static timing analysis report, the method identifies target timing paths with establishment timing violations. Redundancy values ​​are calculated for each module along the target timing path to quantify the impact of each module in the timing path. Based on the redundancy value set and the redundancy value subset of each module, the repair order is determined by calculating the redundancy value of each module. This prevents the occurrence of establishment timing violations in the early stages of timing convergence, forming a systematic repair process. Each module is analyzed and repaired sequentially according to the repair order. By comprehensively considering the redundancy values ​​and repair schemes of each module, a globally optimal repair strategy is formulated. The automated calculation and repair process reduces the need for manual intervention and lowers the risk of human error.

[0038] Currently, the rapid repair methods for timing violations established in static timing analysis are mostly used to provide solutions in the later stages of design. The solution for defects in layout and routing still relies on the experience of engineers. Due to the different qualifications of engineers, the solutions provided are sometimes not the most efficient and economical. With the rapid increase in the scale of design, the cycle of manually providing repair solutions is getting longer and longer, which greatly increases the project development time.

[0039] According to an embodiment of the present invention, a method for rapidly repairing timing violations in static timing analysis is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0040] This embodiment provides a fast repair method for establishing time violations in static timing analysis. Figure 1 This is a flowchart of a fast repair method for establishing timing violations in static timing analysis according to an embodiment of the present invention, as shown below. Figure 1 As shown, the process includes the following steps:

[0041] Step S101: Obtain the static timing analysis report.

[0042] In an optional embodiment, to ensure the accuracy of the mathematical statistics in this invention, the time series path obtained in the static time series analysis report should include at least 10,000 paths. Including more time series paths means that it can more comprehensively cover various situations in the design, thereby obtaining more accurate time series analysis results. By increasing the number of time series paths, the impact of random errors on the overall results can be reduced, the accuracy of the analysis can be improved, and it also helps to more comprehensively detect time series problems in the design.

[0043] In an optional embodiment, the static timing analysis report shall include standard cell location information, interconnect crosstalk information, expanded clock path information, standard cell delay information, and interconnect delay information. The above information is used to help calculate the clock tree skew value, logic level redundancy value, standard cell delay redundancy value, interconnect crosstalk redundancy value, path detour redundancy value, and other redundancy values ​​of the target timing path.

[0044] Step S102: Extract the target timing path based on the static timing analysis report. The target timing path has establishment time violations and a target timing path passes through at least one module.

[0045] In an optional embodiment, based on the static timing analysis report, the target timing path with setup time violation is extracted. The target timing path does not meet the minimum settling time requirement required for the signal to reach the target logic gate, i.e. the setup time requirement. Since the fully flattened timing path is based on the whole chip, the target timing path may pass through different design modules. Since each module and the top-level module are physically seamlessly connected, the target timing path will pass through at least one module.

[0046] Step S103: Calculate the redundancy values ​​of various types for each module traversed by the target timing path.

[0047] In one alternative embodiment, the redundancy value includes one or more of the following: logic level redundancy value, standard cell delay redundancy value, interconnect crosstalk delay redundancy value, and path detour redundancy value. The redundancy value provides specific information about each module in the timing path, and understanding the redundancy value of each module helps to develop a more effective repair strategy.

[0048] Step S104: Calculate the set of redundancy values ​​of the data path of the target time-series path and the subset of redundancy values ​​corresponding to each module based on the redundancy values ​​of each module.

[0049] Step S105: Determine the repair order of each module based on the redundancy value of each module corresponding to the target timing path.

[0050] Step S106: According to the repair order of the modules, analyze each module in turn based on the set of redundant values ​​and the subset of redundant values ​​of each module to determine the repair plan for each module.

[0051] Step S107: Based on the repair schemes of each module traversed by the target timing path, obtain the repair strategy for the target timing path.

[0052] The rapid repair method for establishing time violations in static timing analysis provided in this embodiment obtains a static timing analysis report, identifies the target timing path with established time violations, calculates the redundancy value of each module traversed by the target timing path to quantify the influence of each module in the timing path, determines the repair order based on the redundancy value set and the redundancy value subset of each module, forms a systematic repair process, and analyzes and repairs each module in sequence according to the repair order. By comprehensively considering the redundancy value of each module and the repair plan, a globally optimal repair strategy is formulated. The automated calculation and repair process reduces the need for manual intervention.

[0053] This embodiment provides a fast repair method for establishing time violations in static timing analysis. Figure 2 This is a flowchart of a fast repair method for establishing timing violations in another static timing analysis according to an embodiment of the present invention, such as... Figure 2 As shown, the process includes the following steps:

[0054] Step S201: Obtain the static timing analysis report. For details, please refer to [link to relevant documentation]. Figure 1 Step S101 of the illustrated embodiment will not be described again here.

[0055] Step S202: Extract the target timing path based on the static timing analysis report. The target timing path must have establishment time violations, and each target timing path must pass through at least one module. For details, please refer to [link to relevant documentation]. Figure 1 Step S102 of the illustrated embodiment will not be described again here.

[0056] Step S203: Calculate the redundancy values ​​of various types for each module traversed by the target timing path.

[0057] In one optional embodiment, the redundancy value includes one or more of the following: logic level redundancy value, standard cell delay redundancy value, interconnect crosstalk redundancy value, and path detour redundancy value.

[0058] Calculating the delay redundancy value of standard cells can help identify standard cells with excessive delay that affect the overall timing performance. By setting an upper limit for acceptable delay, it can be ensured that the delay of each standard cell is within the preset safety limit, thereby improving circuit performance to achieve the expected frequency.

[0059] Interconnects are critical paths for signal transmission, and their performance directly affects the quality and speed of signal transmission. Crosstalk is an important indicator of interconnect performance, describing unwanted voltage or current noise interference generated on adjacent transmission lines due to electromagnetic coupling during signal transmission. By extracting and recording the crosstalk delay redundancy value of each interconnect, the crosstalk performance of the interconnect can be comprehensively evaluated, thereby identifying potential signal integrity problems.

[0060] Path detour redundancy is used to measure whether there are unnecessary detours in the path of a module in the target timing path. Such detours may increase signal transmission delay and reduce circuit performance.

[0061] Step S204: Calculate the set of redundancy values ​​of the data path of the target time-series path and the subset of redundancy values ​​corresponding to each module based on the redundancy values ​​of each module.

[0062] Step S205: Calculate the clock tree skew value of the target timing path.

[0063] In one alternative embodiment, by calculating the clock tree skew value of the target timing path, the delay difference of the clock signal on the path can be understood. Clock tree skew is one of the key factors affecting timing convergence. Therefore, accurately evaluating the skew value helps to identify and solve potential problems in the design phase. If the skew value is too large, it may lead to timing violations.

[0064] Step S206: Determine the redundancy value of the target time-series path based on the sum of the elements in the redundancy value set of the data path of the target time-series path.

[0065] In one alternative embodiment, by calculating the redundancy sum of the target timing path, additional resources available for repair or optimization on that path can be evaluated, which helps determine whether it is possible to resolve the timing problem by adjusting the redundant resources without requiring a more complex redesign or additional hardware resources.

[0066] Step S207: Determine whether the redundancy value is greater than or equal to the first preset violation value.

[0067] If the sum of the redundancy values ​​is greater than or equal to the first preset violation value, then proceed to step S209;

[0068] If the sum of the redundancy values ​​is less than the first preset violation value, proceed to the next step.

[0069] In an optional embodiment, a preset violation value is used to determine whether the effect of eliminating redundant values ​​has reached the standard for repairing violations. For example, the first preset violation value is 1.2 times the preset violation value. The preset violation value is a value set in advance according to the circuit design specifications and performance requirements. That is, if the sum of redundant values ​​is greater than or equal to 1.2 times the preset violation value, the repair order of each module is determined according to the redundancy value of each module corresponding to the target timing path. If the sum of redundant values ​​is less than 1.2 times the preset violation value, the next step is executed.

[0070] In an optional embodiment, if the sum of the redundancy values ​​is greater than or equal to the first preset violation value, it indicates that there is a large optimization space in the circuit. The repair order needs to be determined according to the redundancy values ​​of each module in order to prioritize the parts with the greatest impact. If the sum of the redundancy values ​​is less than the first preset violation value, it indicates that the redundancy delay in the circuit is relatively small. In this case, it may be necessary to consider the impact of other factors on timing performance.

[0071] Step S208: Determine whether the sum of the redundancy value and the preset multiple of the clock tree skew value is greater than the first preset violation value.

[0072] If the sum of the redundancy value and the preset multiple of the clock tree skew value is greater than the first preset violation value, then the repair strategy of the target timing path is determined according to the engineering operation corresponding to each element in the redundancy value set of the target timing path and the repair strategy of the clock tree skew value.

[0073] If the sum of the redundancy value and the preset multiple of the clock tree skew value is less than the first preset violation value, then the target timing path is sent to the target user.

[0074] In one optional embodiment, each element in the redundancy value set of the target timing path represents a different type of redundancy value in different modules. The engineering operation represents the specific measures or steps that need to be taken to eliminate the redundancy values ​​represented by the elements in the redundancy value set of the target timing path. For example, adjusting the layout of interconnects to reduce crosstalk delay, optimizing the design of standard cells to reduce delay, modifying the path to eliminate detour redundancy, redesigning logic circuits to reduce stage delay, and may also include adjusting the skew value of the clock tree to further improve timing performance.

[0075] In an optional embodiment, a repair strategy can be intelligently selected based on the relationship between the redundancy value and the clock tree skew value. For example, if the redundancy value is greater than or equal to a first preset violation value, the repair order can be determined based on the redundancy value of each module, prioritizing the modules with the most redundant resources to improve repair efficiency and success rate. If the redundant resources are insufficient but close to the first preset violation value, and considering the impact of clock tree skew, a comprehensive repair plan can be formulated by comprehensively considering the engineering operations corresponding to the redundancy value and the clock tree skew repair strategy. If the redundant resources are severely insufficient, even considering the clock tree skew repair strategy will not meet the requirements. This process will promptly send the target timing path information to the target user, helping the user to understand the problems in the design in a timely manner and take further measures to solve these problems.

[0076] In an optional embodiment, for example, if the sum of the redundancy value and 0.1 times the clock tree skew value is greater than 1.2 times the preset violation value, then the repair strategy of the target timing path is determined according to the engineering operation corresponding to each element in the redundancy value set of the target timing path and the repair strategy of the clock tree skew value. If the sum of the redundancy value and 0.1 times the clock tree skew value is less than 1.2 times the preset violation value, then the target timing path is sent to the target user.

[0077] In an optional embodiment, if the redundancy sum is less than the first preset violation value, it is further determined whether the sum of the redundancy sum and a preset multiple of the clock tree skew value is greater than the first preset violation value. This is to comprehensively consider the impact of redundant delay and clock tree skew value on timing performance. If the sum of the two is still greater than the first preset violation value, it indicates that the timing performance of the circuit can still be optimized. It is necessary to determine the repair strategy of the target timing path based on the engineering operations corresponding to each element in the redundancy value set and the repair strategy of the clock tree skew value. If the sum of the redundancy sum of all modules and the preset multiple of the clock tree skew value is still less than the first preset violation value, it indicates that the violation of the circuit cannot be repaired by this method and needs to be sent to the target user for manual analysis from more levels.

[0078] Step S209: Determine the repair order of each module based on the redundancy value of each module corresponding to the target timing path.

[0079] Step S210: According to the repair order of the modules, each module is analyzed in turn based on the set of redundant values ​​and the subset of redundant values ​​of each module to determine the repair plan for each module.

[0080] Specifically, step S210 includes:

[0081] Step S2101: According to the repair order of the modules, traverse the sum of all elements in the redundant value subset of each module in turn.

[0082] In an optional embodiment, since there is a certain priority in engineering for eliminating four types of redundant values: interconnect crosstalk delay redundancy, standard cell delay redundancy, path detour redundancy, and logic level redundancy, this priority relationship can be reflected by weight coefficients. For example, weight coefficients of {1.0, 0.8, 0.5, 0.3} are used to determine the order of eliminating redundant values.

[0083] In one optional embodiment, the sum of all elements in the redundant value subset of each module is traversed sequentially according to the repair order of the modules to ensure that the modules with the greatest impact on timing performance are processed first, and key issues are resolved in advance, thereby improving the overall repair efficiency.

[0084] Step S2102: Whether the sum of all elements in the redundant value subset is greater than the second preset violation value.

[0085] If the sum of all elements in the redundancy subset of the current module is greater than the second preset violation value, then stop traversing, and use a greedy algorithm to process the redundancy subset of the current module to determine the amount of redundancy to be eliminated for each type of redundancy in the current module so that the sum of the elimination amounts for each type of redundancy is greater than the second preset violation value and less than the third preset violation value.

[0086] If the sum of all elements in the redundancy subset of the current module is less than or equal to the second preset violation value, then the sum of all elements in the redundancy subset of the previous module is subtracted from the current second preset violation value to obtain the updated second preset violation value. Then the sum of all elements in the redundancy subset of the previous module is subtracted from the current third preset violation value to obtain the updated third preset violation value. Then the next module is traversed in sequence.

[0087] In an optional embodiment, the sum of the redundancy elimination amounts of the target timing path can be expressed by the following formula:

[0088]

[0089] The constraint is: 1.2 * |slack| <F(x)<1.5*|slack|。

[0090] Where, x i denoted as the redundant value eliminated in the i-th iteration step, k represents the total number of iterations, F(x) represents the sum of the redundant values ​​eliminated in the target time path, and |slack| represents the preset violation value.

[0091] In one optional embodiment, for example, the second preset violation value is the difference between 1.2 times the first preset violation value and the sum of all elements in the redundant value subset of the previous module, and the third preset violation value is the difference between 1.5 times the first preset violation value and the sum of all elements in the redundant value subset of the previous module.

[0092] For example, taking module a as an example, the subset of U redundancy values ​​is obtained. a Determine U a If the sum of all elements in the variable is greater than 1.2 times the preset violation value, then the redundant value subset U of module a is checked. a Perform a greedy algorithm to process it; if not, subtract U from both sides of the constraint condition. a The sum of all elements, and U divided by U. a We analyze all elements in the first module and then proceed to the next module for analysis. The analysis of the next module still follows the above principles until a certain module n satisfies the constraint of the minimum threshold of the inequality. At this point, a greedy algorithm can be performed, and the constraint condition of the redundancy sum of the target time-series path can be rewritten as:

[0093]

[0094] Where t is any module, U t Let U be a subset of elements belonging to module t, n represent modules in the target time path that satisfy the constraint of the minimum threshold of the inequality, and F(x) represent the redundancy value of the target time path.

[0095] Suppose module n needs to be processed by a greedy algorithm. In each iteration, a value U that maximizes the redundancy of the target time-series path will be selected. n The element values ​​in the array are used until all constraints of F(x) are satisfied, where U n Let X be a subset of the subordinate modules n in U, and assume that the feasible solution X in the k-th iteration is... k ={x1,x2,…,x k}, then the (k+1)th iteration needs to be performed in {U n not X k Choose the value in the set that maximizes F(x) while also satisfying that F(x) is less than 1.5 times the preset violation value, i.e.:

[0096]

[0097] Where, x k+1 U is the element selected in the (k+1)th iteration that satisfies specific constraints and maximizes the sum of the target temporal path redundancy values. n X is a subset of the subordinate module n in U. k It is the feasible solution for the k-th iteration, and F(x) represents the redundancy of the target time path.

[0098] Then the feasible solution X in the (k+1)th iteration k+1 ={x1,x2,…,x k ,x k+1If, in the (k+1)th iteration, F(x) exceeds 1.2 times the preset violation value for the first time, and at the same time, F(x) is less than 1.5 times the preset violation value, it means that the greedy algorithm has found the optimal solution. At this time, the engineering operations mapped to all elements of all modules that participated in the addition of F(x) are returned, and the analysis of the currently selected time path ends.

[0099] In an optional embodiment, for example, the target timing path passes through module a, module b, and module c. The repair order is determined to be b→c→a according to the entropy weight method. Assuming that 1.2 times the violation value of the target timing path is 60ps, the selectable repair operations in module b can remove three interconnect crosstalk redundancy values ​​of 5ps, 3ps, and 2ps, two standard unit delay redundancy values ​​of 10ps, and one path detour redundancy value of 20ps. Calculation shows that 5+3+2+10+10+20 cannot completely repair the 60ps violation value.

[0100] Further analysis of module c reveals that it needs to repair the remaining 10ps of violation values. Available operations include removing an 8ps standard cell delay redundancy, three interconnect crosstalk redundancy values ​​of 5ps, 3ps, and 1ps, and a 30ps logic level redundancy. Within the available range of 30ps, 8ps, 5ps, 3ps, and 1ps, the remaining 10ps of violation values ​​must be repaired. However, the total number of operations from module b must not exceed 1.5 times the preset violation value, i.e., 75ps. The sum of all redundancy values ​​that can be removed by all operations in this module (30+8+5+3+1) is greater than the remaining 10ps of violation value. Therefore, a greedy algorithm is triggered. Following the principle of selecting the most repairable violation values ​​in each iteration, but with a total sum not exceeding 75ps, the 8ps and 5ps operations will ultimately be selected from module c.

[0101] Finally, combining the operations in module b, this timing path will eventually return the engineering operations corresponding to all removable redundant values ​​in module b, as well as the engineering operations corresponding to the two redundant values ​​of 8ps and 5ps in module c.

[0102] Step S2103: Based on the engineering operations corresponding to the amount of redundancy value elimination of the current module and the engineering operations corresponding to all elements in the redundancy value subset of all previously traversed modules, determine the repair scheme for each module.

[0103] In one optional embodiment, a greedy algorithm is used to process the redundant subset of the current module, which can precisely control the amount of various redundant values ​​eliminated, ensuring that over-optimization is not performed while eliminating redundancy. The preset violation value is dynamically updated during the traversal process, and subsequent judgments can be made based on the eliminated redundant values, ensuring the accuracy and effectiveness of the entire repair process. By comprehensively considering the amount of redundant value elimination of the current module and all previously traversed modules and the corresponding engineering operations, a more comprehensive and optimized repair strategy can be formulated.

[0104] Step S211: Based on the repair schemes of each module traversed by the target timing path, obtain the repair strategy for the target timing path. For details, please refer to [link to relevant documentation]. Figure 1 Step S107 of the illustrated embodiment will not be described again here.

[0105] This embodiment provides a fast repair method for establishing time violations in static timing analysis. Figure 3 This is a flowchart illustrating a fast repair method for establishing timing violations in another static timing analysis according to an embodiment of the present invention, as shown below. Figure 3 As shown, the process includes the following steps:

[0106] Step S301: Obtain the static timing analysis report. For details, please refer to [link to relevant documentation]. Figure 1 Step S101 of the illustrated embodiment will not be described again here.

[0107] Step S302: Extract the target timing path based on the static timing analysis report. The target timing path has establishment time violations, and each target timing path passes through at least one module. For details, please refer to [link to relevant documentation]. Figure 1 Step S102 of the illustrated embodiment will not be described again here.

[0108] Step S303: Calculate the redundancy values ​​of various types for each module traversed by the target timing path. For details, please refer to [link to relevant documentation]. Figure 1 Step S103 of the illustrated embodiment will not be described again here.

[0109] Step S304: Calculate the set of redundancy values ​​of the data path of the target time-series path and the subset of redundancy values ​​corresponding to each module based on the redundancy values ​​of each module.

[0110] In one optional embodiment, the redundancy value subset of the module includes a first weighted value corresponding to each type of redundancy value of the module, and the second weighted value of the redundancy value is obtained by weighting the redundancy values ​​of that type; the redundancy value set of the data path of the target time-series path includes a second weighted value corresponding to each type of redundancy value, and the second weighted value of the redundancy value is obtained by summing the first weighted values ​​of the redundancy values ​​of that type in each module.

[0111] In one optional embodiment, by calculating a subset of redundancy values ​​for each module to form a set of redundancy values ​​for the data path of the target timing path, a detailed understanding of each module's contribution to the overall timing performance can be obtained. In actual circuits, different types of redundancy values ​​may have different degrees of impact on timing performance. For example, some types of redundancy values ​​may be more likely to cause timing violations or have a greater impact on power consumption and area. By introducing a first weighting value and a second weighting value, different types of redundancy values ​​are weighted to reflect their relative importance in the overall timing performance.

[0112] Step S305: Calculate the clock tree skew value of the target timing path.

[0113] Specifically, step S305 includes:

[0114] Step S3051: Determine the first delay based on the sum of the delays of each standard cell and each interconnection along the clock path.

[0115] In an optional embodiment, the first delay D cl Delay X for standard cells along the clock path for transmission cli and the delay N of the interconnect clj The sum of , where i is any standard cell and j is any interconnect, i.e.:

[0116] D cl =∑X cli +∑N clj

[0117] Step S3052: Determine the second delay based on the sum of the delays of each standard cell along the clock path and the delays of each interconnect.

[0118] In an optional embodiment, the second delay D cc To receive the standard cell delay X along the clock path cci and the delay N of the interconnect ccj The sum of , where i is any standard cell and j is any interconnect, i.e.:

[0119] D cc =∑X cci +∑N ccj

[0120] Step S3053: Determine whether the clock is an undesirable clock and whether the first delay is greater than the second delay.

[0121] If the clock is an imperfect clock and the first delay is greater than the second delay, then the clock tree skew value of the target timing path is determined based on the difference between the first delay and the second delay.

[0122] In an optional embodiment, the clock tree skew value f(S) of the target timing path is:

[0123] f(S) = D cl -D cc

[0124] Among them, D cl For the first delay, D cc This is the second delay.

[0125] If the clock is an ideal clock, or if the clock is a non-ideal clock, and the first delay is less than or equal to the second delay, then the clock tree skew value of the target timing path is determined to be 0.

[0126] In one optional embodiment, the clock signal is often not perfect. For example, there may be jitter, offset, or other problems. If the clock is not perfect and the first delay is greater than the second delay, it usually means that the clock signal has been interfered with or delayed to some extent during propagation. Since the first delay is greater than the second delay, it is disadvantageous for setup time checking. Therefore, the clock tree skew value needs to be determined based on the difference between the first delay and the second delay. This can fully take into account the non-ideal nature of the clock signal and make the calculation result more consistent with the actual situation. In order to simplify the calculation and improve efficiency, a reasonable threshold is set for the clock tree skew. When the calculated skew value is less than or equal to this threshold, the synchronization of the clock signal is considered to meet the requirements, and no further adjustment or optimization is required.

[0127] In one alternative embodiment, by taking into account the delay difference between the transmit and receive clock paths, as well as the ideal and non-ideal states of the clock, the clock tree skew value of the target timing path can be accurately evaluated. In the case of a non-ideal clock and a large delay difference, the clock tree skew value can be automatically adjusted to adapt to the actual situation. By setting the skew value, the design process can be simplified to handle the case of an ideal clock or a favorable delay difference.

[0128] Step S306: Determine the repair order of each module based on the redundancy value of each module corresponding to the target timing path.

[0129] Specifically, step S306 includes:

[0130] Step S3061: Based on the various types of redundancy values ​​of each module, establish a redundancy value sequence corresponding to each module. In the redundancy value sequence, one column is used to represent a type of redundancy value.

[0131] In an optional embodiment, for example, the logic level redundancy value f(L) is... n ), standard cell delay redundancy value f(X) ni ), Interconnect crosstalk delay redundancy value f(C) ni ), path detour redundancy value f(D)n The combination forms the redundant value sequence S of the current module n. n The number of columns in the sequence is 4, and the number of rows is determined by the maximum number of redundant values ​​recorded in each of the above redundancy types. Columns with fewer than the maximum number of redundant values ​​are padded with 0. For example, module a can be combined into the following redundant value sequence S. a Redundant value sequence S a The number of rows is determined by the number of redundant values ​​in the interconnect crosstalk record.

[0132]

[0133] Among them, S a f(L) represents the sequence of redundant values ​​for module a. n ) represents the logical level redundancy value, f(X) ni ) represents the standard cell delay redundancy value, f(C) ni ) represents the interconnect crosstalk delay redundancy value, f(D) n ) Path detour redundancy value.

[0134] Step S3062: Perform column operations on the redundant value sequence corresponding to each module, and add the column elements to obtain the sum of the column elements.

[0135] In one alternative embodiment, exemplarily, the sum of the column elements is:

[0136]

[0137] Where t represents the number of rows in the redundant value sequence, and S a1 S represents the sum of crosstalk delay redundancy values ​​of all interconnects of module a in the target timing path. a2 S represents the sum of delay redundancy values ​​of all standard units in module a within the target timing path. a3 S represents the sum of all path detour redundancy values ​​for module a in the target timing path. a4 This represents the sum of all logical level redundancy values ​​of module a in the target timing path.

[0138] Step S3063: The sum of the elements in each column of the redundant value sequence is weighted to obtain the evaluation sequence of each module.

[0139] In an optional embodiment, the sum of the elements in each column is multiplied by preset weight values ​​{k1,k2,k3,k4} for interconnect crosstalk delay redundancy, standard cell delay redundancy, path detour redundancy, and logic level redundancy, respectively. For example, {1.0, 0.8, 0.5, 0.3} can be used to obtain the evaluation sequence A of module a. a :

[0140]

[0141] Where S a1 S a2 S a3 S a4 Corresponding to the sequence S a Columns 1, 2, 3, and 4. Rewrite the above 1×4 sequence as:

[0142] A a ={F(C a )F(X a )F(D a )F(L a )}

[0143] Step S3064: Establish the evaluation matrix of the target time-series path based on the evaluation data of each module.

[0144] In an optional embodiment, for example, if the target timing path contains n modules, then the evaluation sequence of all modules in the target timing path can be combined as follows:

[0145]

[0146] Step S3065: The evaluation matrix is ​​processed using the entropy weight method to obtain the evaluation scores of each module in the target time-series path.

[0147] In an optional embodiment, exemplarily, i and j represent the evaluation sequence A, respectively. all The i-th row and j-th column, the item corresponding to the i-th row and j-th column is F. ij The data were standardized using the range standardization method. Each standardized item is as follows:

[0148]

[0149] Where F j This represents all values ​​in column j.

[0150] The weight P of each indicator is calculated using the following formula. ij .

[0151]

[0152] Where n is the number of rows in the evaluation sequence.

[0153] Calculate the information entropy E for each column. j .

[0154]

[0155] If 0×ln(0) is encountered in the above accumulation terms, then the term is ignored.

[0156] Calculate the information entropy redundancy of each column.

[0157] d j =1-E j

[0158] Calculate the weight of the indicator for each column.

[0159]

[0160] Calculate the evaluation score Z for each module. i .

[0161]

[0162] Step S3066: Determine the repair order of each module based on the evaluation scores of each module.

[0163] In an optional embodiment, for example, the target time-series path passes through module a, module b, and module c at the physical layer. Based on the above parameters, and using the entropy weight method to determine the order of evaluation scores of each module from largest to smallest as module b, module c, and module a, the repair order is b→c→a. That is, if b can be repaired, then modules c and a will not be repaired. If b cannot be completely repaired, then repair will continue in c, and so on.

[0164] In one optional embodiment, the evaluation matrix is ​​processed by the entropy weight method to objectively determine the weight of each redundancy value type, avoiding the bias caused by subjective weighting, improving the objectivity of the evaluation, and the repair order determined by the evaluation score can prioritize the processing of modules with poor performance or large redundancy values, thereby more effectively improving the performance and stability of the overall circuit.

[0165] Step S307: Following the repair order of the modules, analyze each module sequentially based on the set of redundant values ​​and the subset of redundant values ​​for each module to determine the repair plan for each module. For details, please refer to [link to relevant documentation]. Figure 1 Step S106 of the illustrated embodiment will not be described again here.

[0166] Step S308: Based on the repair schemes for each module traversed by the target timing path, obtain the repair strategy for the target timing path. For details, please refer to [link to relevant documentation]. Figure 1 Step S107 of the illustrated embodiment will not be described again here.

[0167] This embodiment provides a fast repair method for establishing time violations in static timing analysis. Figure 4 This is a flowchart illustrating a fast repair method for timing violations in another static timing analysis according to an embodiment of the present invention, as shown below. Figure 4 As shown, the process includes the following steps:

[0168] Step S401: Obtain the static timing analysis report. For details, please refer to [link to relevant documentation]. Figure 1 Step S101 of the illustrated embodiment will not be described again here.

[0169] Step S402: Extract the target timing path based on the static timing analysis report. The target timing path has establishment time violations, and each target timing path passes through at least one module. For details, please refer to [link to relevant documentation]. Figure 1 Step S102 of the illustrated embodiment will not be described again here.

[0170] Step S403: Calculate the redundancy values ​​of various types for each module traversed by the target timing path.

[0171] Specifically, step S403 includes:

[0172] Step S4031: Calculate the logic level redundancy value of any module in the target timing path.

[0173] In some optional implementations, step S4031 above includes:

[0174] Step a1: Extract the level of the standard unit of the data path of the target timing path in the module, as well as the third delay.

[0175] In an optional embodiment, the third delay D da It is determined based on the sum of the standard cell delay and interconnect delay on the data path of the target timing path, by extracting the level L of the standard cells of the data path of the target timing path in the module. a And the third delay D da Understand the delay structure of the target timing path.

[0176] Step a2: Determine the typical value of the standard cell delay based on the median of the set U0 of all standard cell delay information in the static timing analysis report.

[0177] In one alternative embodiment, the median of the set U0 of all standard cell delay information in the static timing analysis report is used to determine the typical value of the standard cell delay X. m The mathematical expression is:

[0178] X m =Median(U0)

[0179] In one alternative embodiment, the median of the set of delay information for all standard cells in the static timing analysis report is used to determine the typical delay value of the standard cells, reducing the impact of extreme values ​​on the results and making the delay assessment more accurate.

[0180] Step a3: Determine the typical value of the sum of the delays of the standard cell and the interconnect based on the ratio of the delay of the standard cell to the delay of the interconnect, and the typical value of the delay of the standard cell.

[0181] In an alternative embodiment, the typical sum of delays for the standard cell and the interconnect is 1.1 × X. m .

[0182] Step a4: Calculate the ideal maximum number of stages for each module based on the typical value of the sum of the delays of the standard cells and interconnects in the module, and the third delay.

[0183] In an alternative embodiment, for example, the ideal maximum level L in module a can be calculated. amax D da With 1.1×X m To make the results more credible, the ratio is increased by 20% model margin and rounded up, i.e.:

[0184]

[0185] Among them, D da X is the sum of the standard cell delay and the interconnect delay in module a. m This represents the typical value for standard cell delay, and ceil is the floor function.

[0186] If the number of stages in the standard cell is greater than the ideal maximum number of stages, then the logic stage redundancy value is calculated based on the number of stages in the standard cell, the ideal maximum number of stages, the ratio of the delay of the standard cell to the delay of the interconnect, and the third delay.

[0187] In an optional embodiment, the logic level redundancy value f(L) a )for:

[0188]

[0189] Among them, L a Let L be the number of levels of the standard unit of module a. amax Let be the ideal maximum series in module a.

[0190] If the number of levels in the standard cell is less than or equal to the ideal maximum number of levels, then the logic level redundancy value is set to 0.

[0191] In an alternative embodiment, the ideal maximum number of stages for each module can be calculated based on the typical value of the sum of the delays of the standard cells and interconnects in the module, as well as a third delay. The ideal maximum number of stages for each module represents the maximum number of standard cell stages that the module can accommodate without adding additional delays.

[0192] In one alternative embodiment, by calculating the sum of delays of standard cells and interconnects, as well as typical values, the delay of the target timing path can be accurately evaluated, improving the accuracy of timing analysis. By calculating the ideal maximum level and logic level redundancy values, the timing performance of the circuit can be better understood, and the design can be optimized as needed to meet performance requirements.

[0193] Step S4032: Calculate the standard cell delay redundancy value of any module in the target timing path.

[0194] In some optional implementations, step S4032 above includes:

[0195] Step b1: Extract the delay of each standard unit in the module, and calculate the delay redundancy value of the standard unit based on the delay of each standard unit in the module and the typical delay value of the standard unit.

[0196] In an optional embodiment, exemplarily, the delay of the i-th standard unit in module a is taken and denoted as X. ai Take the typical delay value X of the standard unit. m If twice the acceptable delay is the upper limit, then the delay redundancy value f(X) of the standard unit is... ai The mathematical expression for ) is:

[0197] f(X ai ) = X ai -2*X m

[0198] In an optional embodiment, the delay of each standard unit in the module is extracted. By setting a set multiple of the typical delay value of the standard unit as the upper limit of the acceptable delay, it can be ensured that the delay of each standard unit will not exceed this limit. The set multiple can be determined according to the specific requirements of the circuit design and the actual situation of the standard unit. Based on the delay of each standard unit in the module and the typical delay value of the standard unit, the delay redundancy value of the standard unit is calculated to reflect the degree of difference between the delay of the standard unit and the typical value.

[0199] Step b2: Determine whether the calculated standard unit delay redundancy value is greater than the set delay redundancy value.

[0200] If the calculated standard cell delay redundancy value is greater than the set delay redundancy value, then the calculated standard cell delay redundancy value is determined as the standard cell delay redundancy value.

[0201] If the calculated standard cell delay redundancy value is less than or equal to the set delay redundancy value, then the calculated standard cell delay redundancy value is set to 0.

[0202] In one optional embodiment, by calculating the delay redundancy value of the standard cell, the standard cell with a large delay is identified, and corresponding measures are taken to optimize it. For example, the delay of the standard cell can be reduced by adjusting the parameters of the standard cell, improving the circuit design, or adopting a more suitable optimization method.

[0203] In one alternative embodiment, by setting an upper limit for acceptable delay and calculating the delay redundancy value of standard cells, the delay of each standard cell is ensured to be within a preset safety limit, thereby improving the performance of the circuit. For standard cells with large delay redundancy values, manual optimization design is required.

[0204] Step S4033: Calculate the path detour redundancy value of any module in the target time-series path.

[0205] In some optional implementations, step S4033 above includes:

[0206] Step c1: Extract the standard unit string length of the module, the sum of the distances between any two adjacent standard units, and the fourth delay.

[0207] In an optional embodiment, the length of the standard unit string is the Manhattan distance between the starting standard unit position and the ending standard unit position in the standard unit string of the module, the sum of the distances between any two adjacent standard units in the standard unit string is the sum of the Manhattan distances between any two adjacent standard units between the starting standard unit position and the ending standard unit position, and the fourth delay is the sum of the delays of all standard units in the standard unit string and the delay of the interconnect.

[0208] Step c2: Determine whether the sum of the distances between any two adjacent standard units in the standard unit string is less than a set distance.

[0209] If the sum of the distances between any two adjacent standard cells in a standard cell string is less than a set distance, then the path detour redundancy value of the standard cell string is set to 0.

[0210] If the sum of the distances between any two adjacent standard cells in the standard cell string is greater than or equal to the set distance, then proceed to the next step.

[0211] In one optional embodiment, for example, if the sum of the distances between any two adjacent standard cells in the standard cell string is less than 50 micrometers, the path detour redundancy value of the standard cell string is determined to be 0; if the sum of the distances between any two adjacent standard cells in the standard cell string is greater than or equal to a set distance, the next step is executed.

[0212] Step c3: Check whether the ratio of the sum of the distances between any two adjacent standard cells to the length of the standard cell string is greater than a set ratio.

[0213] If the ratio of the sum of the distances between any two adjacent standard cells to the length of the standard cell string is greater than a set ratio, then the path detour redundancy value of the standard cell string is calculated based on the sum of the distances between any two adjacent standard cells in the standard cell string and the length of the standard cell string.

[0214] In an optional embodiment, exemplarily, the standard unit string length in the standard unit string i of module a is D. aise The sum of the distances between any two adjacent standard cells in a standard cell string, ∑D ainb Fourth delay N ai If the ratio of the sum of the distances between any two adjacent standard cells to the length of the standard cell string is greater than 2.5, then the path detour redundancy value of the standard cell string is calculated based on the sum of the distances between any two adjacent standard cells in the standard cell string and the length of the standard cell string.

[0215]

[0216] If the ratio of the sum of the distances between any two adjacent standard cells to the length of the standard cell string is less than or equal to a set ratio, then the path redundancy value of the standard cell string is set to 0.

[0217] In one optional embodiment, for example, if the ratio of the sum of the distances between any two adjacent standard cells to the length of the standard cell string is less than or equal to 2.5, then the path redundancy value of the standard cell string is determined to be 0.

[0218] Step c4: Determine the path detour redundancy value of the module based on the sum of the path detour redundancy values ​​of each standard unit string in the module.

[0219] In an optional embodiment, the path detour redundancy value of the module is:

[0220]

[0221] Where n is any module, and i is any consecutive standard unit string in the module.

[0222] In one alternative embodiment, by considering factors such as the length of the standard cell string, the sum of the distances between any two adjacent standard cells, and the delay, the impact of path detours on the timing performance of the circuit can be accurately evaluated, thereby improving the accuracy of timing analysis. For standard cell strings with large path detour redundancy values, manual optimization of layout and routing is required to reduce unnecessary detours.

[0223] Step S4034: Extract and record the crosstalk delay redundancy value of each interconnect line in each module, and determine the crosstalk delay redundancy value of the module based on the sum of the crosstalk delay redundancy values ​​of each interconnect line in the module.

[0224] In an optional embodiment, the crosstalk delay redundancy value for each interconnect in each module is extracted and recorded as f(C). ni), where n is any module and i is any crosstalk delay redundancy value of interconnects in that module.

[0225] Step S404: Calculate the set of redundancy values ​​for the data path of the target timing path, and the subset of redundancy values ​​for each module, based on the redundancy values ​​of each module. For details, please refer to [link to relevant documentation]. Figure 1 Step S104 of the illustrated embodiment will not be described again here.

[0226] Step S405: Determine the repair order of each module based on the redundancy values ​​of each module corresponding to the target timing path. For details, please refer to [link to relevant documentation]. Figure 1 Step S105 of the illustrated embodiment will not be described again here.

[0227] Step S406: Following the repair order of the modules, analyze each module sequentially based on the set of redundant values ​​and the subset of redundant values ​​for each module to determine the repair plan for each module. For details, please refer to [link to relevant documentation]. Figure 1 Step S106 of the illustrated embodiment will not be described again here.

[0228] Step S407: Based on the repair schemes for each module traversed by the target timing path, obtain the repair strategy for the target timing path. For details, please refer to [link to relevant documentation]. Figure 1 Step S107 of the illustrated embodiment will not be described again here.

[0229] This embodiment provides a rapid repair device for establishing time violations in static timing analysis. Figure 5 This is a structural block diagram of a rapid repair device for establishing timing violations in static timing analysis according to an embodiment of the present invention, as shown below. Figure 5 As shown, the system includes:

[0230] Module 501 is used to obtain the static time series analysis report;

[0231] Extraction module 502 is used to extract target time series paths based on static time series analysis reports. The target time series paths have establishment time violations, and each target time series path passes through at least one module.

[0232] Redundancy calculation module 503 is used to calculate various types of redundancy values ​​of each module traversed by the target timing path;

[0233] The redundancy value set calculation module 504 is used to calculate the redundancy value set of the data path of the target time-series path and the redundancy value subset corresponding to each module based on the redundancy value of each module corresponding to the target time-series path.

[0234] Repair order determination module 505 is used to determine the repair order of each module based on the redundancy value of each module corresponding to the target timing path;

[0235] The repair scheme determination module 506 is used to analyze each module in turn according to the repair order of the modules, based on the set of redundant values ​​and the subset of redundant values ​​of each module, and to determine the repair scheme of each module.

[0236] The repair strategy determination module 507 is used to obtain the repair strategy of the target timing path based on the repair schemes of each module traversed by the target timing path.

[0237] Further functional descriptions of the above modules and units are the same as those in the corresponding embodiments described above, and will not be repeated here.

[0238] Figure 6 This is a schematic diagram of the structure of a computer device provided in an optional embodiment of the present invention, such as... Figure 6 As shown, the computer device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interfaces). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 6 Take a processor 10 as an example.

[0239] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GPA), or any combination thereof.

[0240] The memory 20 stores instructions executable by at least one processor 10 to cause at least one processor 10 to perform the method shown in the above embodiments.

[0241] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the computer device. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0242] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0243] The computer device also includes an input device 30 and an output device 40. The processor 10, memory 20, input device 30, and output device 40 can be connected via a bus or other means. Figure 5 Taking the example of a connection between China and Israel via a bus.

[0244] Input device 30 can receive input numerical or character information, and generate key signal inputs related to user settings and function control of the computer device, such as a touchscreen, keypad, mouse, trackpad, touchpad, joystick, one or more mouse buttons, trackball, joystick, etc. Output device 40 may include display devices, auxiliary lighting devices (e.g., LEDs), and haptic feedback devices (e.g., vibration motors). The aforementioned display devices include, but are not limited to, liquid crystal displays, light-emitting diodes, displays, and plasma displays. In some alternative embodiments, the display device may be a touchscreen.

[0245] This invention also provides a computer-readable storage medium. The methods described above according to embodiments of the invention can be implemented in hardware or firmware, or implemented as computer code that can be recorded on a storage medium, or implemented as computer code downloaded via a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and then stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods shown in the above embodiments.

[0246] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A method for fast repair of establishing time violation in static timing analysis, characterized in that, The method comprises: acquiring a static timing analysis report; extracting a target timing path having established a time violation from the static timing analysis report, one target timing path passing through at least one module; calculating a plurality of types of redundancy values of each module passed through by the target timing path; calculating a redundancy value set of a data path of the target timing path and a redundancy value subset corresponding to each module according to the redundancy values of the modules corresponding to the target timing path; determining a repair order of each module according to the redundancy values of the modules corresponding to the target timing path; sequentially analyzing each module according to the redundancy value set and the redundancy value subset of each module in the repair order of the modules to determine a repair scheme of each module; obtaining a repair strategy of the target timing path according to the repair schemes of the modules passed through by the target timing path; wherein the sequentially analyzing each module according to the redundancy value set and the redundancy value subset of each module in the repair order of the modules to determine a repair scheme of each module comprises: sequentially traversing a sum of all elements in the redundancy value subset of each module and comparing the sum of all elements in the redundancy value subset with a second preset violation value according to the repair order of the modules; if the sum of all elements in the redundancy value subset of the current module is greater than the second preset violation value, stopping the traversal, performing a greedy algorithm processing on the redundancy subset of the current module to determine an elimination amount of each type of redundancy value in the current module, so that the sum of the elimination amounts of each type of redundancy value is greater than the second preset violation value and less than a third preset violation value; each time a module is traversed, the sum of all elements in the redundancy value subset of the previous module is subtracted from the current second preset violation value to obtain an updated second preset violation value, and the sum of all elements in the redundancy value subset of the previous module is subtracted from the current third preset violation value to obtain an updated third preset violation value; determining a repair scheme of each module according to the engineering operations corresponding to the elimination amounts of each type of redundancy value of the current module and the engineering operations corresponding to all elements in the redundancy value subset of all modules traversed before.

2. The method of claim 1, wherein, After the step of calculating the redundancy value set of the data path of the target timing path and the redundancy value subset corresponding to each module according to the redundancy values of the modules corresponding to the target timing path, and before the step of determining the repair order of each module according to the redundancy values of the modules corresponding to the target timing path, the method further comprises: calculating a clock tree skew value of the target timing path; determining a redundancy value sum of the target timing path according to the sum of each element in the redundancy value set of the data path of the target timing path; if the redundancy value sum is greater than or equal to a first preset violation value, performing the step of determining the repair order of each module according to the redundancy values of the modules corresponding to the target timing path; If the sum of the redundancy value and the preset multiple of the clock tree skew value is greater than the first preset violation value, a repair strategy of the target timing path is determined according to a repair strategy of each element in the redundancy value set of the target timing path and the clock tree skew value; If the sum of the redundancy value and the preset multiple of the clock tree skew value is less than the first preset violation value, the target timing path is sent to a target user.

3. The method of claim 2, wherein, The clock tree skew value of the target timing path is calculated, comprising: a first delay is determined according to a sum of a delay of each standard cell on a clock path and a delay of each interconnection line; a second delay is determined according to a sum of a delay of each standard cell on a clock path and a delay of each interconnection line; If the clock is an ideal clock, or if the clock is a non-ideal clock and the first delay is less than or equal to the second delay, the clock tree skew value of the target timing path is determined to be 0.

4. The method of claim 1, wherein the redundancy value comprises one or more of a logic stage redundancy value, a standard cell delay redundancy value, an interconnection line crosstalk delay redundancy value, and a path bypass redundancy value. The logic stage redundancy value of any module in the target timing path is calculated, comprising: a third delay is determined according to a sum of a delay of a standard cell on a data path of the target timing path and a delay of an interconnection line; 5. The method of claim 4, wherein, a standard cell delay typical value is determined according to a median of all standard cell delay information sets in a static timing analysis report; a typical value of a sum of a delay of the standard cell and a delay of the interconnection line is determined according to a ratio of the delay of the standard cell to the delay of the interconnection line and the standard cell delay typical value; an ideal maximum stage number of each module is calculated according to the typical value of the sum of the delay of the standard cell and the delay of the interconnection line and the third delay; if the stage number of the standard cell is greater than the ideal maximum stage number, a logic stage redundancy value is calculated according to the stage number of the standard cell, the ideal maximum stage number, the ratio of the delay of the standard cell to the delay of the interconnection line, and the third delay; if the stage number of the standard cell is less than or equal to the ideal maximum stage number, the logic stage redundancy value is determined to be 0. The standard cell delay redundancy value of any module in the target timing path is calculated, comprising: a delay of each standard cell in the module is extracted; 6. The method of claim 4, wherein, a standard cell delay redundancy value is calculated according to the delay of each standard cell in the module and a set multiple of the standard cell delay typical value; if the calculated standard cell delay redundancy value is greater than a set delay redundancy value, the calculated standard cell delay redundancy value is determined to be the standard cell delay redundancy value; ​ ​ If the calculated standard cell delay redundancy value is less than or equal to the set delay redundancy value, the standard cell delay redundancy value is determined as 0.

7. The method of claim 4, wherein, The step of calculating the path detour redundancy value of any module in the target timing path comprises: extracting a standard cell string length of the module, a sum of distances between any adjacent standard cells in the module, and a fourth delay, the standard cell string length being a Manhattan distance between a start standard cell position and an end standard cell position of a standard cell string of the module, the sum of distances between any adjacent standard cells in the standard cell string being a sum of Manhattan distances between any two adjacent standard cells between the start standard cell position and the end standard cell position, the fourth delay being a sum of delays of all standard cells in the standard cell string and a delay of an interconnection line, the standard cell string of the module being a continuous standard cell group in the data path of the target timing path in the module; If the sum of distances between any adjacent standard cells in the standard cell string is less than a set distance, the path detour redundancy value is determined as 0; If the sum of distances between any adjacent standard cells in the standard cell string is greater than or equal to the set distance, and a ratio of the sum of distances between any adjacent standard cells and the standard cell string length is greater than a set ratio, a standard cell string path detour redundancy value is calculated according to the sum of distances between any adjacent standard cells in the standard cell string and the standard cell string length; If the sum of distances between any adjacent standard cells in the standard cell string is greater than the set distance, and the ratio of the sum of distances between any adjacent standard cells and the standard cell string length is less than or equal to the set ratio, the standard cell string path detour redundancy value is determined as 0; The path detour redundancy value of the module is determined according to a sum of standard cell string path detour redundancy values of each standard cell string in the module.

8. The method of claim 1, wherein, The redundancy value set of the data path of the target timing path and the redundancy value subset corresponding to each module are calculated according to redundancy values of each module corresponding to the target timing path, and the redundancy value set of the target timing path comprises: The redundancy value subset of the module comprises first weighting values corresponding to each type of redundancy value of the module, and a second weighting value of the redundancy value is obtained according to the type of the redundancy value; The redundancy value set of the target timing path comprises second weighting values corresponding to each type of redundancy value, and the second weighting value of the redundancy value is obtained according to a sum of first weighting values of the type of the redundancy value in each module.

9. The method of claim 1, wherein, The repair order of each module is determined according to the redundancy values of each module corresponding to the target timing path, and the repair order of each module comprises: A redundancy value sequence corresponding to each module is established according to each type of redundancy value of each module, and one sequence in the redundancy value sequence is used to represent one type of redundancy value; Column operations are performed on the redundancy value sequences corresponding to each module, and a sum of column elements is obtained by adding the column elements; Weighting processing is performed on the sum of column elements in the redundancy value sequence to obtain an evaluation sequence of each module; An evaluation matrix of the target timing path is established according to the evaluation sequence of each module; An evaluation score of each module in the target timing path is obtained by processing the evaluation matrix by using an entropy weight method. The repair order of each module is determined according to the evaluation scores of the modules.

10. An apparatus for rapidly repairing time violations in static timing analysis, characterized in that, The device comprises: An acquisition module is configured to acquire a static timing analysis report. An extraction module is configured to extract a target timing path from the static timing analysis report, the target timing path having an established time violation, and one target timing path passing through at least one module. A redundancy value calculation module is configured to calculate a plurality of types of redundancy values of each module passed through by the target timing path. A redundancy value set calculation module is configured to calculate a redundancy value set of a data path of the target timing path and a redundancy value subset corresponding to each module according to the redundancy values of each module corresponding to the target timing path. A repair order determination module is configured to determine a repair order of each module according to the redundancy values of each module corresponding to the target timing path. A repair scheme determination module is configured to analyze each module in sequence according to the redundancy value set and the redundancy value subset of each module according to the repair order of the module, and determine a repair scheme of each module. A repair strategy determination module is configured to obtain a repair strategy of the target timing path according to the repair schemes of each module passed through by the target timing path. The repair scheme determination module is specifically configured to: sequentially traverse a sum of all elements in the redundancy value subset of each module according to the repair order of the module, and compare the sum of all elements in the redundancy value subset with a second preset violation value; if the sum of all elements in the redundancy value subset of the current module is greater than the second preset violation value, stop traversing, perform a greedy algorithm processing on the redundancy subset of the current module, and determine an elimination amount of each type of redundancy value in the current module, so that the sum of the elimination amounts of each type of redundancy value is greater than the second preset violation value and less than a third preset violation value; each time a module is traversed, subtract the sum of all elements in the redundancy value subset of the previous module from the current second preset violation value to obtain an updated second preset violation value, and subtract the sum of all elements in the redundancy value subset of the previous module from the current third preset violation value to obtain an updated third preset violation value; and determine the repair scheme of each module according to the engineering operation corresponding to the elimination amount of each type of redundancy value in the current module and the engineering operation corresponding to all elements in the redundancy value subset of all modules traversed before.

11. A computer device, characterized by It comprises: A memory and a processor, which are communicatively connected, the memory stores computer instructions, and the processor executes the computer instructions to perform the method in any one of claims 1 to 9.

12. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer instructions for causing a computer to perform the method in any one of claims 1 to 9.

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