System and method for executing variable component subscript solicer algorithm with quantum computer

Abstract

In some implementations, the apparatus may comprise a quantum circuit generated by a classical computer, the quantum circuit having: a subset of qubits comprising at least three qubits arranged to execute a linear gate string; a first layer having a vertically centered arrangement of at least three Ry gates on each linear gate string of each subset of quantum bits; a second layer having entanglement gates followed by a sequence of single qubit gates on each linear gate string, where each entanglement gate entangles the linear gate string of subsequent qubits; a third layer having a stepped shape of the second layer; parameters associated with a physical environment are received. The device may execute a VQE algorithm based on parameters of the quantum circuit and the physical environment. The method can further output an approximation of the fundamental state of the physical environment.

Description

Technical Field

[0001] The present disclosure relates to executing quantum algorithms with quantum computing devices utilizing quantum circuits. Background Art

[0002] Conventional computers can be used to generate quantum circuits in order to execute quantum algorithms on quantum computers, such as noisy intermediate-scale quantum (NISQ) devices. The variational quantum eigensolver (VQE) algorithm may be one of the most promising algorithms to be implemented on NISQ devices. However, the VQE algorithm suffers from a plethora of problems, such as barren plateaus, and thus, algorithm development has proven to be challenging. Summary of the invention

[0003] A system of one or more computers may be configured to perform specific operations or actions by means of having software, firmware, hardware, or a combination thereof installed on the system, which in operation causes the system to perform the actions. One or more computer programs may be configured to perform specific operations or actions by means of including instructions which, when executed by a data processing device, cause the device to perform the actions.

[0004] In one general aspect, the method may include generating, by a classical computer, a quantum circuit having a subset of qubits, the subset of qubits including at least three qubits from a plurality of qubits arranged to perform a linear gate string, wherein the subset of qubits is arranged vertically and performs a linear gate string in a horizontal direction. The method may further include a first layer having a vertically centered arrangement of at least three Ry gates on each linear gate string of each qubit subset. The method may also include a second layer having a step shape of a Cz entanglement gate followed by an Ry gate on each linear gate string, wherein the entanglement gate entangles the linear gate string of subsequent qubits. The method may further include a third layer having a step shape of the second layer, wherein the third layer does not overlap vertically with the second layer. The method may include receiving parameters associated with a physical environment. The method may also include performing VQE by a quantum computer based on the parameters of the quantum circuit and the physical environment. The method may also include outputting an approximation of a base state of the physical environment via the quantum computer.

[0005] Other embodiments of this aspect include corresponding computer systems, apparatus, and computer programs recorded on one or more computer storage devices, each configured to perform the actions of the method.

[0006] Implementations may include one or more of the following features. The method may also include initializing at least three Ry gates of the first layer based on random values, and initializing at least three Ry gates of the second layer with a value of zero. The method may further include initializing at least three Ry gates of the third layer based on negative values ​​of the Ry gates of the first layer on the corresponding gate string. The method may also include an additional layer, which may be included between the second layer and the third layer, and wherein one or more Ry gates of the additional layer are initialized with a value of zero. The method may further include applying Figure 7 or Figure 8 Prior to parameterizing the circuit of the qubit subset, configuring the qubit subset to an initial state of entanglement. The initial state of entanglement may be a mean field state. The method may also include wherein the initial state of entanglement is not a product state. The method may further include wherein the rightmost Ry gate of the linear gate train associated with the third qubit of the qubit subset is vertically centered with the rightmost Ry gate of the second qubit of the qubit subset. The method may also include wherein the total number of layers is an odd number. The method may also include wherein the quantum computer is a noisy intermediate-scale quantum computer. Implementations of the described techniques may include hardware, methods or processes, or computer tangible media. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 Operations acting on example qubits are shown.

[0008] Figure 2 A schematic example of a quantum computer is shown.

[0009] Figure 3 Illustrative exemplary methods for generating control signals to perform operations on a quantum computing device and for processing measurement signals from a quantum computing device are shown.

[0010] Figure 4 A schematic example of a hybrid system including classical and quantum computing devices is shown.

[0011] Figure 5 is a flow chart of an example process for performing VQE based on executing quantum circuits on a quantum computing device.

[0012] Figure 6 is a flow chart of an example process for initializing a quantum circuit.

[0013] Figure 7 is a diagram showing an example arrangement of a quantum circuit.

[0014] Figure 8 is a diagram showing an example initialization of the layers of a quantum circuit. DETAILED DESCRIPTION

[0015] Embodiments of the present disclosure are described herein. However, it should be understood that the disclosed embodiments are merely examples, and other embodiments may take various and alternative forms. The drawings are not necessarily drawn to scale; some features may be enlarged or minimized to show the details of a particular component. Therefore, the specific structural and functional details disclosed herein should not be interpreted as limiting, but merely as a representative basis for teaching those skilled in the art to adopt the embodiments in various ways. As will be understood by those of ordinary skill in the art, the various features illustrated and described with reference to any of the figures may be combined with the features illustrated in one or more of the other figures to produce embodiments that are not explicitly illustrated or described. The combination of features shown provides representative embodiments of typical applications. However, for specific applications or implementations, various combinations and modifications of features consistent with the teachings of the present disclosure may be required.

[0016] As used herein, "a", "an", and "the" refer to both singular and plural referents unless the context clearly indicates otherwise. For example, a "processor" programmed to perform various functions refers to one processor programmed to perform each function, or more than one processor programmed together to perform each of the various functions.

[0017] The VQE algorithm may be one of the most promising algorithms to be implemented on current NISQ devices. However, the VQE algorithm suffers from a plethora of problems, such as barren plateaus, and thus, algorithm development has proven to be challenging. The systems and methods described herein can be configured to prepare good ground state approximations with shallow circuit depths that are suitable for implementation on current NISQ devices.

[0018] The systems and methods described herein can be configured to exploit VQE optimization strategies that can avoid the barren plateau problem and have very shallow circuit depths. The systems and methods described herein can exploit configurations that generate good ground state approximations on current NISQ devices without applying any error mitigation techniques. The systems and methods described herein can demonstrate the potential of VQE algorithms in exploiting the capabilities of NISQ devices and highlight the importance of algorithm development in demonstrating the full potential of quantum hardware.

[0019] VQE algorithms may suffer from certain issues. Furthermore, VQE algorithms can exploit the power of both classical and quantum computers, and previous VQE implementations on current quantum devices have reduced performance. Despite some progress, previous implementations have not yet developed VQE algorithms that can exploit the power of current NISQ devices.

[0020] The systems and methods described herein propose a VQE optimization strategy that exploits shallow circuit depth and a small number of gates to generate a good ground state approximation, which makes the strategy conducive to implementation on current NISQ devices.

[0021] The main three elements of the systems and methods described herein may include mean-field starting states, shallow circuit construction, and identity block initialization over a parameterized set of gates.

[0022] The systems and methods described herein can exploit mean-field starting states by initializing the circuit to a classical inspired state that is not a product state. In some embodiments, the choice of starting state can affect the trainability of shallow-depth hardware-efficient ansatz. For example, a small amount of prior knowledge of the input state can help avoid the effects of barren plateaus in VQE optimization. In addition, the systems and methods described herein can be configured to exploit entanglement of parameterized gates.

[0023] The systems and methods described herein can be configured to utilize shallow circuit structures. The systems and methods described herein can be configured to utilize a specific circuit architecture that is hardware friendly due to shallow circuit depth and linear entanglement graphs.

[0024] The systems and methods described herein may include an identity block initialization on a parameterized set of gates. In some embodiments, the identity block initialization may select parameterized gates in such a way that the entire partial operation of the parameterized portion of the circuit remains close to identity, which may aid in VQE optimization. In some embodiments, the parameterized gates may be arranged in layers, where a starting value for the first layer may be randomly selected, a starting value for the last layer may be set to minus the starting value for the first layer, and starting values ​​for intermediate layers may be set to a value of zero.

[0025] The systems and methods described herein can combine all three of the aforementioned elements, which can produce a VQE algorithm with shallow circuit depth and multiple entangled gates, which can avoid the effects of post-selection on the starting values ​​of parameterized gates and the related problems of barren plateaus.

[0026] The systems and methods described herein can be configured to utilize only 3-qubit circuits with 2 repetitions, but the systems and methods described herein can be generalized to larger circuit sizes. In some embodiments, the systems and methods described herein can set the last layer of Ry gates, i.e., θ6, θ7, and θ8, to -θ1, -θ2, and -θ3, respectively, as Figure 8 As shown. The systems and methods described herein can be configured to utilize an even number of repetitions, where all parameterized gates between the first and last application of the Ry gate can be set to zero, and thus the Cz tangle gates can cancel out. As a result, some of the meta-operations of the parameterized portion of the circuit can be initialized to the identity operator.

[0027] Operations acting on the state of a qubit can typically be single-qubit or multi-qubit operations, represented as gates on a quantum circuit. A single-qubit operation can change the state of a qubit into a particular superposition state corresponding to a rotation of the vector |X>, such as Figure 1 As shown. For example, in a superconducting quantum computer this can be achieved by microwave pulses, or in a trapped ion quantum computer by irradiating the ions with a laser beam. Multi-qubit operations can produce entangled states between two or more qubits. For example, in a superconducting quantum computer this can be achieved by connecting the qubits via an intermediate electrical coupling circuit, or in a trapped ion quantum computer by controlling the collective vibrations of the trapped ions.

[0028] Typically, in order to prepare operations for solving a given problem, the corresponding quantum mechanical representation of the problem can be converted into a quantum circuit that can be used to prepare a solution to the given problem. After the predetermined solution has been prepared, i.e. after the operations have been applied to the quantum circuit, a projection measurement of all individual qubits is performed, returning either 0 or 1 for each qubit. On a NISQ device, such measurements are implemented by a hardware-specific readout protocol that applies a series of readout operations, which include control pulses and monitoring the response to the control pulses. For example, a superconducting qubit can be coupled to a hardware resonator. The measured shift in the resonator frequency allows the state of the qubit to be determined, since this shift depends on the state of the coupled qubit. For example, in the case of trapped ions, optical readout can be used, e.g. if the ion emits light, the state of the qubit is 1, or if the ion does not emit light, the state of the qubit is 0, and vice versa. In this way, the qubit can be used to implement logic circuits or gates, just like in classical computing devices.

[0029] exist Figure 2 , a schematic example of a quantum computer is shown. Figure 2 The quantum computing device 100 shown in includes a quantum register 104 configured to perform quantum computation, a manipulation portion 106 configured to manipulate the quantum register (particularly quantum elements forming qubits), and a readout portion 108 configured to collect measurement signals from the quantum register 104 to read out the qubits after quantum mechanical computation. In particular, the manipulation portion 106 provides a manipulation signal for manipulating the quantum register, wherein the manipulation signal is generated based on a received control signal, which is determined based on a corresponding operation that should be performed on the qubit. In some embodiments, a feedback loop between the manipulation portion 106 and the measurement portion 108 may be provided. In contrast to classical computing, where one measurement cycle provides a transistor state, quantum computing includes performing multiple measurement cycles to provide a probability density or probability of a qubit state.

[0030] The quantum register 104 may be based on different quantum elements representing qubits. In some embodiments, qubits may be implemented as quantum elements by photons. Such an optical quantum computing device may include a laser that generates photons provided to a waveguide. A beam splitter may be provided for manipulating the photon state based on a manipulation signal (such as a mechanical rotation applied to a mirror). In such an embodiment, the measurement portion 108 may be a photon detector and the measurement signal may be a photon.

[0031] In other embodiments, the qubit may be implemented by the electronic state of an ion trapped in a magnetic field. In this case, the manipulation portion 106 may utilize a laser, and the manipulation signal may result in providing a control laser pulse. Also, in this case, the readout portion 108 may be a photon detector combined with a readout laser pulse, and the measurement signal 102 may be a photon. Other qubit implementations may be based on superconductors as quantum elements, semiconductor materials with anyons as quantum elements, etc.

[0032] Figure 3 A schematic exemplary method for generating control signals to perform operations on a quantum computing device and for processing measurement signals from a quantum computing device is shown. In most embodiments of quantum computing devices known to date, control signals for the quantum computing device are prepared on a classical computing device, and measurement signals provided by the quantum computing device are further processed on the classical computing device. However, as quantum computing devices mature, other embodiments are conceivable.

[0033] In order to generate control signals to perform operations on the quantum computing device, a problem to be solved by means of the quantum computing device is provided in step S10, specifically as a quantum circuit. Such a problem may, for example, determine the basis states of a particular chemical formula. Other problems may include applying the VQE algorithm to a physical environment. Based on the problem to be solved, an operational description of the problem or sub-problem (such as a quantum circuit) may be generated in step S12, wherein the operational description includes operations to be applied to the qubits (such as gates) of the quantum computer to solve the problem in the quantum mechanical calculation. In addition, the operational description may include a reference state that allows a representation of the initial qubit state to be generated on the quantum computer, and then further operations are applied on the quantum computer by manipulating the qubit state. Based on the operational description, a control signal may then be generated in step S14 to control the quantum computer, for example, by providing a control signal to a manipulation part, which may then manipulate the qubit state based on the control signal. In step S16, the manipulation part then applies the manipulation operation to a single or multiple qubits of the quantum computer, wherein based on the manipulation operation, the qubit performs a quantum mechanical calculation. After the manipulation, a measurement signal may be generated to determine the result of the quantum mechanical calculation in step S18. This step may include a readout, e.g., a measurement, of the qubit state after applying a manipulation operation to the initial qubit state. Then, in step S20, the measurement signal may be converted into a measurement quantity on a classical computer and, in the case of a subproblem, fed back into the problem to be solved. Finally, in step S22, the result of the problem calculation, including the quantum mechanical calculation, may be provided on a classical computing device.

[0034] Figure 4 A schematic example of a hybrid system including classical and quantum computing devices is shown. Figure 3 As described in the method shown, quantum computing devices are often used in conjunction with classical computing devices. Figure 4 As shown, the question preparation system can be implemented to perform e.g. Figure 3The classical computing device 110 of steps S10, S12, S20, S22 of the method shown. The control part can then be provided as an interface between the classical computing device 110 and the quantum computing device 100, wherein the control part can also be a classical computing device, which for example performs step S14. The control part can then be communicatively coupled to the manipulation part 106, which can control the manipulator of the quantum computing device. The manipulation part 106 can also be implemented as a classical computing device, for example, classical control hardware for controlling specific hardware components of a quantum computer that perform qubit manipulation. However, the manipulation part 106 is generally considered to be part of a quantum computer because it directly affects the quantum register. The quantum computing device 100 is suitable for performing the quantum operation S16, in particular by manipulating the qubits of the quantum register. The measurement part 108, which is also generally considered to be part of the quantum computing device, can then perform step S18 by utilizing classical hardware. The measurement part 108 can then be communicatively coupled to the preparation system for further processing of the measurement signal.

[0035] In some embodiments, the classical computing device 110 may utilize one or more processors to execute computer program instructions stored on a non-transitory computer-readable medium communicatively coupled to a processor of the classical computing device 110 or to the manipulation portion 106 of the quantum computing device 100 .

[0036] Figure 5 is a flow chart of an example process 500 for executing a VQE algorithm based on executing a quantum circuit on a quantum computing device 100. In some implementations, Figure 5 One or more process blocks of may be performed by a processor of the classical computing device 110 or the manipulation portion 106 of the quantum computing device 100 .

[0037] like Figure 5 As shown, process 500 may include generating, by a classical computer, a quantum circuit having a subset of qubits, the subset of qubits including at least three qubits from a plurality of qubits arranged to execute a linear string of gates, wherein the subset of qubits is arranged vertically and executes the linear string of gates in a horizontal direction (block 502). In some embodiments, a processor of classical computing device 110 may be configured to generate a shallow state circuit having a shallow circuit depth and a plurality of gates.

[0038] like Figure 5As shown, process 500 may further include generating a first layer for the quantum circuit having a vertically centered arrangement of at least three single-qubit gates (e.g., Ry gate, Rz gate, and Rx gate) on each linear gate string of each qubit subset (block 504). In some embodiments, the processor of classical computing device 110 may arrange the qubits of the qubit subset along a grid, wherein each qubit is assigned a plurality of gates that transform the state of the qubit from an initialized position of a left start position when the qubit is moved to a right measurement position. In some embodiments, the state of each qubit is measured after the qubits have performed the operations assigned to them by measurement portion 108 through their respective gate strings.

[0039] like Figure 5 As shown, process 500 may also include generating a second layer for the quantum circuit, the second layer having a sequence of entangled gates (e.g., Cz gates, Cx gates, and Cy gates) followed by a single-qubit gate on each linear gate string, wherein the entangled gates entangle the linear gate string of the subsequent qubit (block 506). In some embodiments, the processor of the classical computing device 110 may arrange the gates on the linear gate string in the layer, wherein the layer is stacked from a left starting position to a right measurement position. In some embodiments, the controlled Cz gate applies a controlled Z gate to the target qubit based on the state of the control qubit. For example, when the control qubit is in the 0 state, the gate does nothing, but when the control qubit is in the 1 state, the gate applies a Pauli Z gate to the target qubit.

[0040] like Figure 5 As shown, process 500 may further include generating a third layer having a step shape of the second layer for the quantum circuit, wherein the third layer does not vertically overlap the second layer (block 508). In some embodiments, the processor of classical computing device 110 may include the third layer on a linear gate string in a manner such that the rightmost gate of the second layer completes the operation of its corresponding qubit before the first gate of the third layer begins the operation on its corresponding qubit, such as Figure 7 shown.

[0041] like Figure 5 As shown, process 500 may also include receiving parameters associated with the physical environment (block 510). In some embodiments, the processor of the classical computing device 110 may receive parameters associated with one or more atoms in the physical environment. In some embodiments, the parameters may be associated with one or more atoms in the physical environment in which a chemical reaction may occur or is occurring.

[0042] like Figure 5As shown, process 500 may further include executing, by the quantum computer, a VQE algorithm based on parameters of the quantum circuit and the physical environment (block 512). In some embodiments, a subset of qubits of quantum computing device 100 may be assigned to a linear gate string of a quantum circuit. In some embodiments, the qubits may be initialized to a starting state, such as a mean field starting state (i.e., a classically inspired state that is not a product state), which may generate some entanglement between two or more qubits.

[0043] like Figure 5 As shown, process 500 may further include outputting an approximation of a basis state of the physical environment via the quantum computer (block 514). In some embodiments, the processor of classical computing device 110 may receive a measurement of each qubit from the subset of qubits after all operations of the linear string of gates have been executed, which is read by measurement portion 108.

[0044] although Figure 5 Example blocks of process 500 are shown, but in some implementations, process 500 may include Figure 5 Additional blocks, fewer blocks, different blocks, or differently arranged blocks than those shown. Additionally or alternatively, two or more blocks of process 500 may be performed in parallel.

[0045] Figure 6 is a flow chart of an example process 600 for initializing a quantum circuit. In some embodiments, Figure 6 One or more process blocks of may be performed by a processor of the classical computing device 110 or the manipulation portion 106 of the quantum computing device 100 .

[0046] like Figure 6 As shown, process 600 may include initializing at least three single-qubit gates (e.g., Ry gate, Rz gate, and Rx gate) of a first layer based on random values ​​(block 602). In some embodiments, the single-qubit gate may be an Ry gate, and initializing the Ry gate associates a value with the Ry gate for a rotation operation of the Ry gate. In some embodiments, the initialization value of the Ry gate may indicate a rotation value of a qubit performing an operation around the y-axis of the corresponding qubit.

[0047] like Figure 6 As shown, process 600 may further include initializing at least three single-qubit gates of the second layer with a value of zero (block 604). In some embodiments, the value of the processor of classical computing device 110 may initialize the single-qubit gates of the second layer with a value of zero. In some embodiments, the single-qubit gates may be Ry gates, and the Ry gates initialized with a value of zero indicate an operation of rotating the corresponding qubit zero radians around the y-axis.

[0048] like Figure 6As shown, process 600 may also include initializing at least three Ry gates of the last layer based on the negative values ​​of the single-qubit gates of the first layer on the corresponding gate string (block 606). In some embodiments, the value of the processor of classical computing device 110 may initialize the single-qubit gates of the last layer with the negative value of the first layer. For example, the single-qubit gates may be Ry gates, and when the Ry gate of the first Ry gate is initialized to 3.37 radians, the Ry gate of the last layer on the same linear path is initialized to -3.37 radians.

[0049] like Figure 6 As shown, process 600 may further include adding a layer to the quantum circuit between the second layer and the third layer (block 608). In some embodiments, the processor of the classical computing device 110 may further configure the quantum circuit to include an additional layer, where the total number of layers is an odd number. In some embodiments, the additional layer mirrors the configuration and initialization of the second layer and is inserted at a position between the first layer and the last layer.

[0050] like Figure 6 As shown, process 600 may include initializing one or more Ry gates of the additional layer with a value of zero (block 610). In some embodiments, the processor of classical computing device 110 may initialize the Ry gates of the additional layer to zero, wherein the Ry gates initialized with a value of zero indicate an operation to rotate the corresponding qubit about the y-axis by zero radians.

[0051] although Figure 6 Example blocks of process 600 are shown, but in some implementations, process 600 may include Figure 6 Additional blocks, fewer blocks, different blocks, or differently arranged blocks than those shown in . Additionally or alternatively, two or more blocks of process 600 may be performed in parallel.

[0052] Figure 7 is a diagram showing an example arrangement 700 of a quantum circuit having two layers. The quantum circuit may be configured by a processor of a classical computing device 110.

[0053] like Figure 7 As shown, arrangement 700 may include a starting position 702 for each qubit subset. In some embodiments, before manipulation portion 106 of quantum computing device 100 executes the VGE algorithm, the qubits at position 702 are initialized to a starting state.

[0054] like Figure 7 As further shown, the arrangement 700 may also include a first layer 704 of gates composed of Ry gates, forming a straight line in the vertical direction. In some embodiments, this layer shape is not repeated and is only used for the first layer of the arrangement 700.

[0055] Also like Figure 7As shown, arrangement 700 may include Cz gate 706 and Ry gate 708. In some embodiments, Cz gate 706 may be the first logic gate of the second layer of arrangement 700, followed by Ry gate 708. In some embodiments, Cz and Ry gates are added to each linear string of gates and are spaced to form a staircase structure.

[0056] like Figure 7 As further shown in FIG. 7 , the device 700 may include an Ry gate 710 at the rightmost position of the last linear gate string. In some embodiments, the Ry gate 710 is the only Ry gate in the second layer that is vertically symmetrical to another Ry gate in the second layer.

[0057] Figure 8 8 is a diagram illustrating an example initialization of an uninitialized quantum circuit 800 to generate an initialized quantum circuit 850. Quantum circuit 800 may be initialized by a processor of a classical computing device 110.

[0058] like Figure 8 As shown, the uninitialized quantum circuit 800 consists of three layers, a first uninitialized layer 802 , a second uninitialized layer 804 , and a third uninitialized layer 806 .

[0059] like Figure 8 As further shown, the initialized circuit 850 is composed of three layers, a first initialized layer 852, a second initialized layer 854, and a last initialized layer 856. In some embodiments, the first initialized layer 852 can be initialized with a random number. For example, Ry gate 0, Ry gate 1, and Ry gate 2 are initialized with 3.37, 2.29, and 5.41, respectively. In some embodiments, the second initialized layer 854 can be initialized with a value of 0. In some embodiments, the last initialized layer 856 can be initialized with a negative value of the corresponding Ry gate of the first initialized layer 852. For example, Ry gate 6, Ry gate 7, and Ry gate 8 are initialized with -3.37, -2.29, and -5.41, respectively.

[0060] Although exemplary embodiments are described above, it is not intended that these embodiments describe all possible forms included in the claims. The words used in the specification are descriptive words, not restrictive, and it should be understood that various changes can be made without departing from the spirit and scope of the present disclosure. As mentioned above, the features of the various embodiments can be combined to form further embodiments of the present invention that may not be explicitly described or illustrated. Although various embodiments may have been described as providing advantages or superiority over other embodiments or prior art implementations in terms of one or more desired characteristics, it is recognized by those of ordinary skill in the art that one or more features or characteristics can be compromised to achieve the desired overall system properties, depending on the specific application and implementation. These properties may include, but are not limited to, cost, strength, durability, life cycle cost, marketability, appearance, packaging, size, maintainability, weight, manufacturability, ease of assembly, etc. Therefore, to the extent that any embodiment is described as not as ideal as other embodiments or prior art implementations in terms of one or more features, these embodiments are not outside the scope of the present disclosure and may be ideal for specific applications.

Claims

1. A method of performing a variational quantum eigensolver (VQE) algorithm using a quantum circuit executed on a quantum computer, the method comprising: A quantum circuit is generated by a classical computer, the quantum circuit comprising: a qubit subset comprising at least three qubits from a plurality of qubits arranged to perform a linear train of gates, wherein the qubit subset is arranged vertically and performs the linear train of gates in a horizontal direction; a first layer, comprising a vertically centered arrangement of at least three single-qubit gates on each linear gate string of each qubit subset; The second layer includes an entanglement gate followed by a sequence of single-qubit gates on each linear gate string, where each entanglement gate entangles the linear gate string of the subsequent qubit; a third layer, comprising a sequence of the second layer, wherein the third layer does not vertically overlap the second layer; receiving parameters associated with a physical environment; executing the VQE algorithm by the quantum computer based on parameters of the quantum circuit and the physical environment; and An approximation of the fundamental state of the physical environment is output via a quantum computer.

2. The method according to claim 1, wherein the method further comprises: Initialize at least three single-qubit gates of the first layer based on random values; Initialize at least three single-qubit gates of the second layer with the value zero; as well as At least three single-qubit gates of a third layer are initialized based on the negative values ​​of the single-qubit gates of the first layer on the corresponding linear gate trains.

3. The method of claim 2, wherein an additional layer is included between the second layer and the third layer, and wherein one or more single-qubit gates of the additional layer are initialized with a value of zero.

4. The method according to claim 1, wherein the method further comprises: Configure a subset of qubits into an entangled initial state. The method according to claim 4 , wherein the entangled initial state is not a product state.

6. The method of claim 1 , wherein the rightmost single-qubit gate of the linear gate train associated with a third qubit of the subset of qubits is vertically centered with the rightmost single-qubit gate of the second qubit of the subset of qubits. The method according to claim 1 , wherein the total number of layers is an odd number.

8. The method according to claim 1, wherein: The quantum computer is a noisy medium-scale quantum computer.

9. A system for executing a variational quantum eigensolver (VQE) algorithm on a quantum circuit, the system comprising: A quantum computer comprising a plurality of qubits, and a classical computer comprising at least one processor and at least one non-transitory computer-readable medium having computer program instructions configured to control the quantum computer, the instructions causing the system to: A quantum circuit is generated by a classical computer, the quantum circuit comprising: a qubit subset comprising at least three qubits from a plurality of qubits arranged to perform a linear train of gates, wherein the qubit subset is arranged vertically and performs the linear train of gates in a horizontal direction; a first layer, comprising a vertically centered arrangement of at least three single-qubit gates on each linear gate string of each qubit subset; The second layer includes an entanglement gate followed by a sequence of single-qubit gates on each linear gate string, where each entanglement gate entangles the linear gate string of the subsequent qubit; a third layer, comprising a sequence of the second layer, wherein the third layer does not vertically overlap the second layer; receiving parameters associated with a physical environment; executing the VQE algorithm by the quantum computer based on parameters of the quantum circuit and the physical environment; and An approximation of the fundamental state of the physical environment is output via a quantum computer.

10. The system of claim 9, wherein the instructions cause the system to further: Initialize at least three single-qubit gates of the first layer based on random values; Initializing at least three single-qubit gates of the second layer with the value zero; and At least three single-qubit gates of a third layer are initialized based on the negative values ​​of the single-qubit gates of the first layer on the corresponding linear gate trains.

11. The system of claim 10, wherein an additional layer is included between the second layer and the third layer, and wherein one or more single-qubit gates of the additional layer are initialized with a value of zero.

12. The system of claim 9, wherein the instructions cause the system to further: Configure a subset of qubits into an entangled initial state.

13. The system of claim 12, wherein the entangled initial state is not a product state.

14. The system of claim 9, wherein the rightmost single-qubit gate of the linear gate train associated with a third qubit of the subset of qubits is vertically centered with the rightmost single-qubit gate of the second qubit of the subset of qubits.

15. The system of claim 9, wherein the total number of layers is an odd number.

16. The system of claim 9, wherein: The quantum computer is a noisy medium-scale quantum computer.

17. A system for executing a variational quantum eigensolver (VQE) algorithm on a quantum circuit, the system comprising: A quantum computer comprising a plurality of qubits, and a classical computer comprising at least one processor and at least one non-transitory computer-readable medium having computer program instructions configured to control the quantum computer, the instructions causing the system to: A quantum circuit is generated by a classical computer, the quantum circuit comprising: a qubit subset comprising at least three qubits from a plurality of qubits arranged to perform a linear train of gates, wherein the qubit subset is arranged vertically and performs the linear train of gates in a horizontal direction; a first layer, comprising a vertically centered arrangement of at least three single-qubit gates on each linear gate string of each qubit subset; The second layer includes an entanglement gate followed by a sequence of single-qubit gates on each linear gate string, where each entanglement gate entangles the linear gate string of the subsequent qubit; a third layer, comprising a sequence of the second layer, wherein the third layer does not vertically overlap the second layer; receiving parameters associated with a physical environment; executing the VQE algorithm by the quantum computer based on parameters of the quantum circuit and the physical environment; and An approximation of the fundamental state of the physical environment is output via a quantum computer.

18. The system of claim 17, wherein the instructions cause the system to further: Initialize at least three single-qubit gates of the first layer based on random values; Initializing at least three single-qubit gates of the second layer with the value zero; and At least three single-qubit gates of a third layer are initialized based on the negative values ​​of the single-qubit gates of the first layer on the corresponding linear gate trains.

19. The system of claim 17, wherein the instructions cause the system to further: Configure a subset of qubits into an entangled initial state.

20. The system of claim 17, wherein the rightmost single-qubit gate of the linear gate train associated with a third qubit of the subset of qubits is vertically centered with the rightmost single-qubit gate of the second qubit of the subset of qubits.

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