Geometry processing pipeline, graphics processing core, processor, and vertex cache method

Abstract

The application discloses a geometry processing pipeline, a graphics processing core, a processor and a vertex cache method, and belongs to the chip field. The geometry processing pipeline comprises a vertex cache unit with a vertex index cache, a vertex processing pipeline, a vertex storage and a primitive pipeline unit. The geometry processing pipeline shown in the application realizes vertex granularity vertex cache testing, does not need to depend on primitives obtained through primitive assembly any more, and is beneficial to realizing a distributed architecture geometry processing pipeline with delayed primitive assembly.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of chips, in particular to a geometry processing pipeline, a graphics processing core, a processor and a vertex caching method. BACKGROUND

[0002] Primitive assembly and vertex shading are two different stages in the graphics rendering process of a GPU (Graphics Processing Unit). The primitive assembly is used to convert vertices into complete geometric primitives, while the vertex shading is to calculate the vertices. Before vertex shading, the GPU needs to perform hit testing on each vertex to determine whether the vertex processing program needs to be started to process or use the previous processing result.

[0003] In related technologies, hit testing requires a complete primitive as a basic unit, and hit testing is performed on all vertices in the primitive at the same time to ensure that the vertex shading results of the assembled primitives can be output by the GPU at the same time during subsequent primitive assembly.

[0004] This way is not conducive to the splitting of each stage in the rendering process, and can easily lead to dependencies between stages such as primitive assembly, hit testing and vertex shading. SUMMARY

[0005] The present application provides a geometry processing pipeline, a graphics processing core, a processor and a vertex caching method, and the technical solution is as follows:

[0006] According to an aspect of the present application, a geometry processing pipeline is provided, which comprises a vertex caching unit having a vertex index cache, a vertex processing pipeline, a vertex storage and a primitive pipeline unit;

[0007] The vertex caching unit and the primitive pipeline unit are configured to receive a plurality of vertex indexes arranged in sequence, the plurality of vertex indexes being used to indicate a plurality of vertices, and the plurality of vertex indexes corresponding to the plurality of vertices one by one.

[0008] The vertex caching unit is configured to add a vertex index of a first vertex in the plurality of vertex indexes that is not hit in the vertex index cache into the vertex index cache; generate a vertex shader task to which the first vertex belongs; generate a pipeline index of the first vertex, the pipeline index being used to identify the first vertex in the geometry processing pipeline; send the vertex shader task to which the first vertex belongs and the pipeline index to the vertex processing pipeline to perform vertex processing; and send a mapping relationship between the vertex index of the first vertex and the pipeline index to the primitive pipeline unit.

[0009] The vertex storage is configured to save vertex processing results of the first vertex based on the pipeline index.

[0010] The primitive pipeline unit is configured to perform primitive assembly and primitive processing on a first primitive to which the first vertex belongs based on split initial state information, the plurality of vertex indexes, and the mapping relationship, the split initial state information being used to indicate a split manner in which the plurality of vertices are split into at least one primitive.

[0011] According to an aspect of the present application, a graphics processing core is provided, and the graphics processing core comprises a geometry processing pipeline.

[0012] According to an aspect of the present application, a graphics processing core is provided, and the graphics processing core comprises a geometry processing pipeline.

[0013] The N graphics processing cores are connected to the system bus respectively, and the system bus is connected to the storage unit.

[0014] The system configuration unit is connected to each of the N graphics processing cores respectively.

[0015] Each of the graphics processing cores comprises the geometry processing pipeline.

[0016] According to an aspect of the present application, a vertex caching method is provided, and the method is executed by the geometry processing pipeline, the geometry processing pipeline comprising a vertex caching unit having a vertex index cache, a vertex processing pipeline, a vertex storage, and a primitive pipeline unit.

[0017] The method comprises:

[0018] The vertex caching unit and the primitive pipeline unit receive a plurality of vertex indexes arranged in sequence, the plurality of vertex indexes being used to indicate a plurality of vertices, and the plurality of vertex indexes corresponding to the plurality of vertices one by one.

[0019] The vertex caching unit adds a vertex index of a first vertex in the plurality of vertex indexes which is not hit in the vertex index cache into the vertex index cache, generates a vertex shader task to which the first vertex belongs, generates a pipeline index of the first vertex, the pipeline index being used to identify the first vertex in the geometry processing pipeline, sends the vertex shader task to which the first vertex belongs and the pipeline index to the vertex processing pipeline to execute vertex processing, and sends a mapping relationship between the vertex index of the first vertex and the pipeline index to the primitive pipeline unit.

[0020] The vertex storage stores vertex processing results of the first vertex based on the pipeline index;

[0021] The primitive pipeline unit performs primitive assembly and primitive processing on a first primitive to which the first vertex belongs based on split initial state information, the plurality of vertex indexes, and the mapping relationship, the split initial state information being used to indicate a split manner in which the plurality of vertices are split into at least one primitive.

[0022] The technical scheme provided in the application has at least the following beneficial effects:

[0023] The processing of the vertex is implemented without primitive assembly, and the hit test is implemented at the vertex granularity. Specifically, the pipeline index used internally by the geometry pipeline is generated by the vertex cache unit, so that the vertex processing result is stored in the vertex storage together with the pipeline index corresponding to the vertex after the processing of the vertex shading program, which makes the vertex shading program not need to confirm the primitive in which the vertex is located during the processing, that is, the decoupling of the vertex shading and the hit test and the decoupling between different geometry processing pipelines are implemented, and thus the geometry processing pipeline shown in the embodiment of the application can be applied to a distributed structure processor. Compared with the geometry processing pipeline in the related art in which the primitive is used as the hit test granularity, the geometry processing pipeline provided in the embodiment of the application improves the processing efficiency of the geometry processing pipeline. That is, the vertex cache unit can perform the hit test without obtaining the primitive assembly information, so that the hit test and the vertex shading can be performed in parallel, and the processing performance of the geometry processing pipeline is improved. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to more clearly illustrate the technical scheme in the embodiments of the application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative effort.

[0025] Figure 1 A schematic diagram of a geometry pipeline provided by an exemplary embodiment of the application is shown;

[0026] Figure 2 A schematic diagram of a vertex cache unit provided by an exemplary embodiment of the application is shown;

[0027] Figure 3 A processing flowchart of a hit test control subunit provided by an exemplary embodiment of the application is shown;

[0028] Figure 4Fig. 1 shows a schematic diagram of a processing flow of a vertex pipeline unit according to an example embodiment of the present application;

[0029] Figure 5 Fig. 2 shows a schematic diagram of a processing flow of a geometry processing pipeline according to an example embodiment of the present application;

[0030] Figure 6 Fig. 3 shows a schematic diagram of a processing flow of a geometry processing pipeline according to an example embodiment of the present application;

[0031] Figure 7 Fig. 4 shows a schematic diagram of a processing flow of a geometry processing pipeline according to an example embodiment of the present application;

[0032] Figure 8 Fig. 5 shows a schematic diagram of a geometry processing pipeline according to an example embodiment of the present application;

[0033] Figure 9 Fig. 6 shows a schematic diagram of a processing flow of a geometry processing pipeline according to an example embodiment of the present application;

[0034] Figure 10 Fig. 7 shows a schematic diagram of an image processing core according to an example embodiment of the present application;

[0035] Figure 11 Fig. 8 shows a schematic diagram of an image processor according to an example embodiment of the present application;

[0036] Figure 12 Fig. 9 shows a flowchart of a vertex caching method according to an example embodiment of the present application. DETAILED DESCRIPTION

[0037] For the purpose of clarity, technical solutions and advantages of the present application will be further described in detail below with reference to the accompanying drawings.

[0038] The example embodiments will be described in detail herein with reference to the accompanying drawings. The following description is presented with reference to the accompanying drawings, in which a similar reference can indicate similar elements or features. The embodiments described in the following examples are not meant to be all inclusive of all embodiments consistent with the present application. Rather, they are meant to be illustrative of some of the apparatus and methods consistent with the present application as detailed in the appended claims.

[0039] The terminology used in the disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used in the description of the disclosure and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term “and / or” as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0040] It should be noted that the user information (including but not limited to user equipment information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in the present application are all information and data authorized by the user or authorized by all parties, and the collection, use and processing of related data need to comply with relevant laws, regulations and standards of relevant countries and regions. For example, the setting operation and other information involved in the present application are obtained under sufficient authorization.

[0041] It should be understood that although the terms first, second, etc. can be employed in this disclosure to describe various information, the information should not be limited to these terms. These terms are only used to distinguish one type of information from another type of information. For example, a first parameter can also be referred to as a second parameter without departing from the scope of the disclosure, and similarly, a second parameter can also be referred to as a first parameter. Depending on the context, the word “if’ as used herein can be interpreted as meaning “when” or “in response to determining” or “in response to ascertaining”.

[0042] First, the related terms involved in the present application are introduced:

[0043] GPU (Graphics Processing Unit, Graphics Processing Unit) rendering pipeline (Rendering Pipeline): It is a key concept in computer graphics, which is a stage in GPU responsible for processing and converting graphics data for rendering.

[0044] The main task of the rendering pipeline is to convert the input geometric primitives (such as points, lines, triangles, etc.) into visible pixels on the screen. It is composed of multiple stages, each of which performs specific geometric calculations and transformations.

[0045] The following are the typical stages of the geometry pipeline:

[0046] (1) Vertex Input (Vertex Input): This stage passes vertex data from the application to the geometry pipeline. Vertex data includes position, color, normal, etc.

[0047] (2) Vertex Shader: In this stage, the vertex shader performs calculations on each input vertex and can perform various transformations and operations such as model transformation, view transformation, projection transformation, etc. It can also calculate lighting, texture coordinates, etc.

[0048] (3) Primitive Assembly: In this stage, the primitive assembler converts vertices into complete geometric primitives such as points, lines, triangles, etc.

[0049] (4) Geometry Shader: In the geometry shader stage, the geometry shader can operate and generate new geometric primitives. It can create new primitives, change the shape, size, position, etc. of the primitives.

[0050] (5) Clipping: In this stage, the clipper compares the primitives with the screen boundaries and discards the parts outside the view volume.

[0051] (6) Screen Mapping: This stage maps the clipped primitives to pixel coordinates in screen space.

[0052] (7) Rasterization: The rasterization stage converts geometric primitives into pixels on the screen and determines the position, color, etc. of each pixel.

[0053] (8) Fragment Shader: In the fragment shader stage, the fragment shader performs calculations on each rasterized pixel. It can perform pixel-level lighting calculations, texture sampling, depth testing, etc.

[0054] (9) Pixel Operations: The last stage is pixel operations, which performs the final pixel processing such as blending, dithering, anti-aliasing, etc.

[0055] The goal of the rendering pipeline is to process geometric graphics and generate the final image in an efficient way. Through parallel processing and specialized hardware support, the GPU can quickly perform these calculations to achieve real-time graphics rendering.

[0056] The rendering pipeline can generally be divided into two parts: the geometry processing part (i.e., the geometry pipeline) and the pixel processing part (also known as the fragment pipeline). The geometry processing part includes vertex input, vertex shading, primitive assembly, set shading, clipping, and screen mapping parts, and the geometry pipeline mainly focuses on the processing and transformation of geometry data. It receives input geometry primitives (such as points, lines, triangles, etc.) and converts them into pixels on the screen after a series of stages. The geometry pipeline is responsible for performing geometric calculations such as model transformation, view transformation, projection transformation, etc., and generating new geometry primitives, changing the shape, size, position, etc. of the primitives.

[0057] The pixel processing part generally includes rasterization, fragment shading, and pixel operation parts. The fragment pipeline focuses on pixel-level processing. It receives the pixels on the screen generated by the rasterization stage and processes each pixel through a series of stages. The main stages include fragment shading, depth testing, stencil testing, transparency blending, etc. The fragment pipeline is responsible for performing pixel-level lighting calculations, texture sampling, depth testing, etc. to determine the final color and attributes of each pixel.

[0058] These two pipelines are consecutive stages in the rendering pipeline, and they depend on and closely cooperate with each other to finally generate visual images. The geometry pipeline converts geometry data into pixel data, while the fragment pipeline performs final processing and calculations on each pixel. Through parallel processing and specialized hardware support, GPUs can efficiently execute these pipeline stages to achieve real-time graphics rendering.

[0059] Vertex Cache: A cache used in graphics processing units (GPUs) to store processed vertex data. In the geometry processing of GPUs, vertex cache is generally used to reduce the number of vertices that need to be processed by the GPU. In graphics rendering, vertices are the basic components of three-dimensional models, each containing position, normal, texture coordinates, etc. In the rendering process, the vertices of the model need to be used multiple times, and the vertex cache is used to temporarily store these vertex data.

[0060] The role of vertex cache is to reduce the repeated calculation of vertex data in the rendering process. When a vertex is processed, its result is stored in the vertex cache, and the next time the vertex is needed, it can be directly read from the cache without re-computing. This can improve rendering efficiency, especially when processing large three-dimensional models, it can significantly reduce the amount of computation required for rendering and improve rendering performance.

[0061] The vertex cache is usually implemented by the internal hardware of the GPU. After the input of the vertex, before the start of the vertex shading, the GPU needs to perform a hit-test on the input vertex, if the input vertex hits the vertex existing in the cache, then the GPU does not need to start the vertex shading program for this new input vertex, but uses the processing result of the previously existing vertex. If the input vertex does not hit any vertex in the cache, then the GPU needs to start the vertex shading program for this new input vertex, at the same time, the GPU also inserts this vertex into the vertex cache for the hit-test of the subsequent vertex. The vertex hit-test is generally not performed on a single vertex, but on a complete primitive as a basic unit, and the hit-test is performed on all vertices in the primitive at the same time, so that the vertex shading result of the assembled primitive can be output by the GPU at the same time when the primitive is assembled subsequently.

[0062] wave / warp: a group of consecutive threads in the process of a shading program. In GPU programming, "wave" / "warp" is a common concept in the architecture of the GPU, and the embodiments of the present application take wave as an example. Wave represents a group of consecutive threads in the process of a shading program, and these threads can execute the same instruction together. A wave usually also contains a certain number of threads, but this number can be different according to different GPU architectures. Different GPU architectures can use a SIMD (Single Instruction Multiple Data) execution model, in which the threads in a wave execute the same instruction, but the data operated can be different, or a "SIMT (Single Instruction Multiple Threads)" execution model. Wave is very important for optimizing the performance of the GPU program, and the maximum utilization of the parallel execution capability of the warp can improve the efficiency of the program.

[0063] Figure 1 A schematic diagram of a geometry pipeline provided by an example embodiment of the present application is shown. The geometry processing pipeline 100 includes a vertex cache unit 110 with a vertex index cache, a vertex processing pipeline 120, a vertex storage 130, and a primitive pipeline unit 140;

[0064] Optionally, the vertex cache unit 110 and the primitive pipeline unit 140 are configured to receive a plurality of vertex indexes arranged in sequence, the plurality of vertex indexes being used to indicate a plurality of vertices, and the plurality of vertex indexes corresponding to the plurality of vertices one by one.

[0065] Optionally, the sequentially arranged plurality of vertex indexes refer to the plurality of vertex indexes arranged according to the arrangement order of the plurality of vertices in the primitive, for example, the vertex indexes corresponding to the plurality of vertices in each primitive are continuous, and the vertex indexes corresponding to the plurality of vertices in each primitive are arranged in a clockwise order or an anticlockwise order according to the arrangement order of the plurality of vertices in the primitive.

[0066] Optionally, the vertex cache unit 110 is configured to add the vertex index of the first vertex not hit in the vertex index cache in the plurality of vertex indexes into the vertex index cache; generate a vertex shader task to which the first vertex belongs; generate a pipeline index of the first vertex, the pipeline index being used to identify the first vertex in the geometry processing pipeline 100; send the vertex shader task to which the first vertex belongs and the pipeline index to the vertex processing pipeline 120 to perform vertex processing; and send a mapping relationship between the vertex index of the first vertex and the pipeline index to the primitive pipeline unit 140.

[0067] Optionally, the vertex cache hit refers to that the vertex index of the vertex has been stored in the vertex index cache; and the vertex cache miss refers to that the vertex index of the vertex does not exist in the vertex index cache.

[0068] Optionally, the vertex shader task includes the vertices processed by the vertex shading program each time the vertex shading program is started. That is, in order to improve the hardware performance and efficiency, the vertex shading program is not started immediately each time a vertex is input. Instead, the vertex shading program is started for a certain number of vertices. The vertices in one batch are a vertex shader task (referred to as a shader task).

[0069] Optionally, the pipeline index is used to identify the first vertex in the geometry processing pipeline 100. Alternatively, the pipeline index is used to identify the first vertex in the vertex storage 130.

[0070] Optionally, the vertex storage 130 is configured to save the vertex processing result of the first vertex based on the pipeline index.

[0071] Optionally, the vertex processing result of the first vertex refers to the vertex processing result of the first vertex after the vertex shading program, or the calculation result of the vertex shading program on the first vertex. The vertex shading program is used to calculate the first vertex, such as calculating the lighting and texture coordinates of the first vertex.

[0072] Optionally, the primitive pipeline unit 140 is configured to perform primitive assembly and primitive processing on a first primitive to which the first vertex belongs based on the split initial state information, the plurality of vertex indexes and the mapping relationship, the split initial state information being used to indicate a split manner of splitting the plurality of vertices into at least one primitive.

[0073] Optionally, the primitive assembling is to determine the vertices belonging to the first primitive from the plurality of vertices; or, the primitive assembling is to determine the vertex indices belonging to the first primitive from the plurality of vertex indices; or, the primitive assembling is to determine the vertices belonging to the first primitive from the plurality of vertices and assemble the vertices into the first primitive; or, the primitive assembling is to determine the vertex indices belonging to the first primitive from the plurality of vertex indices and assemble the vertex indices into the first primitive. The vertices include a first vertex; the vertex indices include a vertex index of the first vertex.

[0074] Optionally, the primitive processing is to perform a primitive-related processing on the first primitive. The primitive processing includes, but is not limited to, rasterization, primitive shading, and tessellation. The tessellation is a method to further divide a primitive into smooth surfaces.

[0075] Optionally, the split initial state information is to indicate a split manner of splitting the plurality of vertices into the at least one primitive; or, the split initial state information is to indicate the vertices of the plurality of vertices that need to perform the primitive assembling; or, the split initial state information is to indicate the vertices of the plurality of vertices that need to be processed by the primitive pipeline unit 140; or, the split initial state information is to indicate the split manner of processing the plurality of vertices by the primitive pipeline unit 140. The split manner includes, but is not limited to, the vertices that need to be processed, the number of vertices included in each primitive, the primitive type, and the ordering manner of the vertices corresponding to the primitive in the plurality of vertices.

[0076] For example, the vertices that need to be processed are the 2nd to 15th vertices of the plurality of vertices when the plurality of vertices is 16 vertices. The number of vertices included in each primitive is 3 when the primitive is a triangle. The primitive type is to indicate the shape of the primitive or the arrangement of the plurality of primitives, such as a triangle, a quadrangle, a line strip, a triangle strip, and the like. The line strip is to form a line segment primitive with the previous vertex for each vertex except the first vertex, and all the line segment primitives form a continuous strip structure in space. The triangle strip is to form a triangle primitive with the previous two vertices for each vertex except the first triangle primitive, and all the triangle primitives form a continuous strip structure in space. The ordering manner of the vertices corresponding to the primitive in the plurality of vertices is, for example, to arrange the vertices in a clockwise order or in a counterclockwise order, and the like.

[0077] Optionally, the primitive pipeline unit 140 determines the first primitive to which the first vertex belongs based on the split initial state information and the plurality of vertex indexes; obtains the vertex processing result of the first vertex from the vertex storage 130 based on the mapping relationship; and performs primitive processing based on the vertex processing result of the first vertex to obtain the first primitive to which the first vertex belongs. Alternatively, the primitive pipeline unit 140 determines the first primitive to which the first vertex belongs based on the split initial state information and the plurality of vertex indexes, the first primitive including the plurality of vertices; obtains the vertex processing result of each vertex in the plurality of vertices from the vertex storage 130 based on the mapping relationship between the vertex index and the pipeline index of the plurality of vertices; and performs primitive processing based on the vertex processing result of each vertex to obtain the first primitive to which the first vertex belongs.

[0078] In summary, the geometric processing pipeline provided in the embodiments of the present application implements processing of vertices without primitive assembly, and implements hit test at the vertex granularity. Specifically, a pipeline index used internally by the geometric processing pipeline is generated by the vertex cache unit, so that the vertex processing result and the pipeline index corresponding to the vertex are stored in the vertex storage after processing by the vertex shading program, which enables the vertex shading program to confirm the primitive in which the vertex is located during processing, i.e., the decoupling of vertex shading and hit test and the decoupling between different geometric processing pipelines are achieved, and thus the geometric processing pipeline shown in the embodiments of the present application can be applied to a distributed processor. Compared with the geometric processing pipeline in the related art that uses a primitive as the hit test granularity, the geometric processing pipeline provided in the embodiments of the present application improves the processing efficiency of the geometric processing pipeline. That is, the vertex cache unit can perform hit test without obtaining primitive assembly information, so that hit test and vertex shading can be performed in parallel, and the processing performance of the geometric processing pipeline is improved.

[0079] Next, a generation manner of the pipeline index is shown.

[0080] Optionally, the vertex cache unit 110 is configured to generate the pipeline index based on a shader identifier corresponding to the first vertex and a vertex cache index, wherein the shader identifier is used to identify a vertex shader task to which the first vertex belongs, and the vertex cache index is used to identify a cache position of the first vertex in the vertex index cache.

[0081] Optionally, the pipeline index is obtained by concatenating the shader identifier and the vertex cache index; or, the pipeline index is a combination of the shader identifier and the vertex cache index in a predetermined format. For example, the shader identifier of the first vertex is 1, and the vertex cache index of the first vertex is 5; if the pipeline index is obtained by concatenating the shader identifier and the vertex cache index, the pipeline index of the first vertex is 15. In this scheme, the number of bits of the vertex cache index is fixed. For example, the number of bits of the vertex cache index is 1 bit as shown above. If the number of bits of the vertex cache index is 2 bits, the pipeline index of the first vertex can be 105, that is, the pipeline index of the first vertex is considered to be 05. Similarly, the number of bits of the shader identifier can also be fixed or not fixed. Or, if the pipeline index is a combination of the shader identifier and the vertex cache index in a predetermined format, for example, the predetermined format is "shader identifier-vertex cache index". For example, the shader identifier of the first vertex is 1, and the vertex cache index of the first vertex is 5; at this time, the pipeline index of the first vertex is 1-5.

[0082] In other embodiments, the pipeline identifier of the first vertex can also be a unique identifier generated by the vertex cache unit. For example, the current timestamp is used as the pipeline identifier of the first vertex, or the pipeline identifier of the first vertex is set as i if the first vertex is the i-th vertex processed by the vertex cache unit; or, the pipeline identifier of the first vertex can also be an identifier generated by the vertex cache unit based on the storage position of the first vertex in the vertex index cache.

[0083] In summary, the geometric processing pipeline provided by the embodiments of the present application can obtain the pipeline identifier by the shader identifier and the vertex cache index, that is, use an internal identifier of the geometric processing pipeline instead of using the vertex index, which can reduce the dependence of the geometric processing pipeline on external information, make the geometric processing pipeline more independent, and reduce the coupling degree of the geometric processing pipeline and other modules. Moreover, the identification by the shader identifier and the vertex cache index can also enable the geometric processing pipeline to directly determine the corresponding vertex shader task according to the identifier, which can realize fast query in vertex storage compared with directly generating a unique identifier.

[0084] Next, the specific structure in the vertex cache unit 110 is shown, as shown in Figure 2

[0085] In addition to the above-mentioned vertex index cache 111, the vertex cache unit 110 further includes a hit test control subunit 112, a shader task assembly subunit 113, and a shader task mapping subunit 114.

[0086] ​Optionally, the hit test control subunit 112 is configured to perform a vertex hit test on each vertex index in the plurality of vertex indices; add a vertex index of a first vertex in the plurality of vertex indices that is not hit in the vertex index cache 111 into the vertex index cache 111; generate a vertex shader task to which the first vertex belongs; generate a pipeline index of the first vertex; and send the pipeline index of the first vertex to the shader task assembling unit 113.

[0087] Optionally, the shader task assembling subunit 113 is configured to send the vertex shader task to which the first vertex belongs and the pipeline index to the vertex processing pipeline 120 to perform vertex processing.

[0088] Optionally, the hit test control subunit 112 sends the pipeline index of the first vertex to the shader task assembling unit 113, and the shader task assembling subunit 113 sends the vertex shader task to which the first vertex belongs and the pipeline index to the vertex processing pipeline 120 to perform vertex processing.

[0089] Optionally, the vertex shader task to which the first vertex belongs includes a vertex index of the first vertex, and the vertex processing pipeline 120 reads vertex data of the first vertex from the storage unit based on the vertex index included in the vertex shader task to perform vertex processing, the vertex data including at least one of: three-dimensional coordinates of the vertex, a normal vector of the vertex, a texture coordinate, or a vertex tangent. Alternatively, the hit test control subunit 112 also sends the mapping relationship to the shader task assembling subunit 113, and the shader task assembling subunit 113 sends the mapping relationship to the vertex processing pipeline 120, the vertex processing pipeline 120 obtains a vertex index based on the mapping relationship and the pipeline index, and reads vertex data of the first vertex from the storage unit based on the vertex index. Alternatively, the hit test control subunit 112 also sends the vertex index of the first vertex to the shader task assembling subunit 113, and the shader task assembling subunit 113 sends the vertex index to the vertex processing pipeline 120, and the vertex processing pipeline 120 reads vertex data of the first vertex from the storage unit based on the vertex index.

[0090] Optionally, the shader task mapping subunit 114 is configured to send a mapping relationship between the vertex index of the first vertex and the pipeline index to the primitive pipeline unit 140.

[0091] Optionally, the vertex cache unit 110 receives a plurality of vertex indexes and sends them to the hit test control subunit 112. The hit test control subunit 112 performs a vertex hit test on each vertex index in the plurality of vertex indexes in sequence, and compares it with the vertex indexes cached in the vertex index cache 111. If it is a hit (i.e. the vertex index in the vertex index cache 111 includes the vertex index to be tested), the next vertex is tested. If it is a miss, the hit test control subunit 112 adds the vertex to the vertex index cache 111, and sends the vertex to the shader task assembly subunit 113 to prepare for starting a corresponding vertex shader task. In addition, for the vertex after being added to the vertex index cache 111, the hit test control subunit 112 also needs to generate a pipeline index for the newly inserted vertex, and determine the mapping relationship between the vertex index and the pipeline index of the vertex, and then sends the mapping relationship to the shader task mapping subunit 114, and the mapping relationship is saved by the shader task mapping subunit 114.

[0092] Optionally, the shader task assembly subunit 113 receives the pipeline index sent by the hit test control subunit 112 and saves it. When the number of vertices saved in the shader task assembly subunit 113 reaches the task requirement number (i.e. the number of waves / warps) for starting a vertex shader task, the pipeline indexes of the vertices belonging to the vertex shader task are sent to the vertex processing pipeline 120, and the vertex processing pipeline 120 executes the corresponding vertex shading program for these vertices.

[0093] Optionally, the shader task mapping subunit 114 saves the mapping relationship of each missed vertex, and the mapping relationship is sent by the shader task mapping subunit 114 to the primitive pipeline unit 140 for primitive assembly by the primitive pipeline unit 140.

[0094] In addition to the hit test of the vertex, the hit test control subunit 112 also needs to send control information to force the start of the shader task assembly subunit 113.

[0095] In summary, the geometric processing pipeline provided by the embodiments of the present application shows the specific structure of the vertex cache unit, which includes, in addition to the vertex index cache, a shader task assembly subunit for sending vertex shader tasks, a shader task mapping subunit for saving the mapping relationship between the vertex index and the pipeline index, and a hit test control subunit for performing hit test. The clear division of different functions of the vertex cache unit is conducive to improving the maintainability and scalability of the vertex cache unit.

[0096] The vertex cache unit 110 starts a vertex shader task to which the first vertex belongs, and there are three cases.

[0097] Case one: the number of vertices reaches a trigger threshold.

[0098] Case two: the vertex index cache is full.

[0099] Case three: there is no unprocessed vertex.

[0100] Next, the three cases of starting the shader task are introduced in turn. It should be noted that the order of introduction does not represent the advantages and disadvantages of the starting mode of the shader task.

[0101] Case one: the number of vertices reaches a trigger threshold.

[0102] In some embodiments, the vertex cache unit 110 is configured to, in a case where the number of unprocessed vertices reaches a trigger threshold, send, based on the unprocessed vertices, a vertex shader task to which the first vertex belongs and a pipeline index of the unprocessed vertices to the vertex processing pipeline 120 for vertex processing; wherein the unprocessed vertices include the first vertex.

[0103] Optionally, the trigger threshold is pre-set.

[0104] For example, the trigger threshold is less than the number of vertices that can be stored in the vertex index cache 111, and then the above can be understood as sending, based on the unprocessed vertices, the vertex shader task to which the first vertex belongs in a case where the number of unprocessed vertices reaches the trigger threshold, the vertex shader task being used to indicate that the unprocessed vertices are vertices that need to be executed for vertex processing.

[0105] For example, the trigger threshold is equal to the number of vertices that can be stored in the vertex index cache 111, and at this time, it is similar to case two, which will not be described here.

[0106] For example, the trigger threshold is greater than the number of vertices that the vertex index cache 111 can store. In the case that the vertex index cache 111 is full but the number of unsent vertices does not reach the trigger threshold, the vertex index cache 111 is emptied, and the vertex buffer index in the pipeline index at this time can be cumulative. For example, the number of vertices that the vertex index cache 111 can store is 8, and the trigger threshold is 16. In the case that the vertex index cache 111 is first stored full, that is, 8 vertices are stored in the vertex index cache and the corresponding vertex buffer index is 0-7, the vertex index cache 111 is emptied, but when generating the pipeline index for the subsequent vertices, the corresponding vertex buffer index is numbered from 8, that is, the vertex index cache 111 is emptied but the accumulator corresponding to the vertex buffer index is not initialized. Alternatively, different shader identifiers are set for the vertices in the vertex index cache 111 belonging to different batches, that is, a vertex shader task includes multiple shader identifiers.

[0107] Optionally, in the case that the vertex buffer unit 110 includes the vertex index cache 111, the hit test control subunit 112, the shader task assembly subunit 113, and the shader task mapping subunit 114, the shader task assembly subunit 113 is configured to, in the case that the number of unsent vertices reaches the trigger threshold, send, based on the unsent vertices, a vertex shader task to which the first vertex belongs and the pipeline index of the unsent vertices to the vertex processing pipeline to perform vertex processing.

[0108] In summary, the geometry processing pipeline provided by the embodiments supports, in the case that the trigger threshold is less than the number of vertices that the vertex index cache can store, expanding the hit detection range for new vertices, thereby searching for duplicate vertices in a larger range, reducing the number of duplicate vertex shading, reducing the number of repeated processing of the vertex shading program, indirectly improving the processing efficiency of the geometry processing pipeline, improving the shading performance, and reducing the power consumption of the geometry processing pipeline. In the case that the trigger threshold is greater than the number of vertices that the vertex index cache 111 can store, the decoupling of primitive assembly and vertex processing can also be achieved, thereby reducing the hardware requirements for the vertex index cache.

[0109] Case two: the vertex index cache is full.

[0110] In some embodiments, the vertex buffer unit 110 is configured to, in the case that the vertex index cache 111 is full, send, based on the unsent vertices, a vertex shader task to which the first vertex belongs and the pipeline index of the unsent vertices to the vertex processing pipeline 120 to perform vertex processing; wherein the unsent vertices include the first vertex.

[0111] Optionally, one vertex shader task corresponds to the vertices in a batch of vertex index caches 111.

[0112] For example, when the vertex index cache 111 is full, it is determined that the vertex shader task to which the first vertex belongs is sent for the vertex that is not sent currently. After the vertex shader task is assembled, the vertex shader task and the pipeline index corresponding to the vertex in the vertex shader task are sent to the vertex processing pipeline 120 to perform vertex processing.

[0113] Alternatively, the method can also be designed based on the above case one, that is, when the number of vertices that are not sent reaches the trigger threshold, the vertex shader task to which the first vertex belongs and the pipeline index of the vertices that are not sent are sent to the vertex processing pipeline based on the vertices that are not sent to perform vertex processing, and the preset threshold is equal to the number of vertices that can be stored in the vertex index cache 111. The judgment can also be based on the vertex index cache without being based on the number of vertices that are not sent.

[0114] Alternatively, when the vertex cache unit 110 includes the vertex index cache 111, the hit test control subunit 112, the shader task assembly subunit 113, and the shader task mapping subunit 114, the shader task assembly subunit 113 is configured to send the vertex shader task to which the first vertex belongs and the pipeline index of the vertices that are not sent to the vertex processing pipeline based on the vertices that are not sent when the number of vertices that are not sent reaches the number of vertices that can be stored in the vertex index cache 111; wherein the vertices that are not sent include the first vertex. Or, when the vertex index cache 111 is full, the vertex shader task to which the first vertex belongs and the pipeline index of the vertices that are not sent are sent to the vertex processing pipeline based on the vertices that are not sent to perform vertex processing.

[0115] In summary, the geometric processing pipeline provided by the embodiments of the present application sends a vertex shader task when the vertex index cache is full, thereby improving the space utilization of the vertex index cache. Since the vertex shader task is sent when the vertex index cache is full, compared with sending a vertex shader task when the vertex index cache is not full, the number of vertices processed by one vertex shader task is larger, thereby ensuring that more vertices can be detected. In the case where multiple duplicate vertices are close to each other, the probability of duplicate vertex processing can be reduced, and the effectiveness of vertex processing can be improved.

[0116] Case three: there is no vertex that is not processed.

[0117] In some embodiments, the vertex cache unit 110 is configured to, in a case where there is no remaining vertex to be processed in the plurality of vertices, send, to the vertex processing pipeline, a vertex shader task to which the first vertex belongs and a pipeline index of the unsent vertex based on the unsent vertex; wherein the unsent vertex includes the first vertex.

[0118] For example, in a case where there is no remaining vertex to be processed in the plurality of vertices, it is determined that the current unsent vertex group forms a vertex shader task, which is the vertex shader task to which the first vertex belongs. After the vertex shader task is formed, the vertex shader task and a pipeline index corresponding to a vertex in the vertex shader task are sent to the vertex processing pipeline 120 to perform vertex processing.

[0119] Optionally, in a case where the vertex cache unit 110 includes the vertex index cache 111, the hit test control subunit 112, the shader task assembly subunit 113, and the shader task mapping subunit 114, the shader task assembly subunit 113 is configured to, in a case where there is no remaining vertex to be processed in the plurality of vertices, send, to the vertex processing pipeline, a vertex shader task to which the first vertex belongs and a pipeline index of the unsent vertex based on the unsent vertex; wherein the unsent vertex includes the first vertex.

[0120] In summary, the geometry processing pipeline provided by the embodiments of the present application can directly send a vertex shader task in a case where all the vertices have been processed, instead of waiting for the next batch of vertices, thereby avoiding the geometry processing pipeline from being in a standby state due to waiting for the next batch of vertices, and releasing the geometry processing pipeline as early as possible, so that the GPU can allocate tasks to the geometry processing pipeline in an idle state again, and the running efficiency of the geometry processing pipeline is improved.

[0121] It should be noted that the above case one, case two and case three can be independently implemented or combined, for example, case one and case three can be combined, in the case where there are remaining vertices in the plurality of vertices which are not processed, case one is executed; in the case where there are no remaining vertices in the plurality of vertices which are not processed, case three is executed. Case two and case three can be combined, in the case where there are remaining vertices in the plurality of vertices which are not processed, case one is executed, and in the case where there are no remaining vertices in the plurality of vertices which are not processed, case three is executed. Case one and case two can be combined, in the case where the number of vertices for which the vertex shader task is to be established and the number of vertices which can be stored in the vertex index cache are equal, case two is executed; in the case where the number of vertices for which the vertex shader task is to be established and the number of vertices which can be stored in the vertex index cache are not equal, case one is executed. Case one, case two and case three can be combined, in the case where there are remaining vertices in the plurality of vertices which are not processed and the number of vertices for which the vertex shader task is to be established and the number of vertices which can be stored in the vertex index cache are not equal, case one is executed; in the case where there are remaining vertices in the plurality of vertices which are not processed and the number of vertices for which the vertex shader task is to be established and the number of vertices which can be stored in the vertex index cache are equal, case two is executed; in the case where there are no remaining vertices in the plurality of vertices which are not processed, case three is executed.

[0122] In addition, the above only shows the case where the vertex index of the first vertex is not hit in the vertex index cache, and in the case where the vertex index of the first vertex is hit in the vertex index cache, in some embodiments, the vertex cache unit 110 is configured to ignore processing of a second vertex in the plurality of vertices which is hit in the vertex index cache.

[0123] Wherein, hit means that the vertex index cache 111 has the vertex index of the vertex.

[0124] Optionally, in the case where the vertex index of the second vertex is hit, the processing of the second vertex is ignored, that is, the pipeline index is not generated for the second vertex; the vertex processing is not performed on the second vertex, that is, the vertex index of the second vertex is not sent to the vertex processing pipeline 120; and the mapping relationship between the vertex index and the pipeline index of the second vertex is not sent to the primitive pipeline unit 140. Thus, unnecessary calculation is avoided, the power consumption of the geometry processing pipeline is reduced, and the processing efficiency of the geometry processing pipeline is improved.

[0125] For example, in the case of case two, the flow of the hit test performed by the hit control subunit 112 is further introduced, as shown in Figure 3 .

[0126] Step 1, initialize the shader identifier and the vertex cache index.

[0127] The hit test control subunit 112 needs to initialize data, including shader identification, and vertex buffer index. For example, the shader identification is initialized as 0, and the vertex buffer index is initialized as 0.

[0128] Step 2, receive vertex index.

[0129] The hit test control subunit 112 receives a plurality of vertex indexes, and obtains a vertex index that needs to be processed from the plurality of vertex indexes.

[0130] Step 3, hit test.

[0131] The hit test control subunit 112 performs a hit test on the obtained vertex index to obtain a hit test result of a vertex corresponding to the vertex index.

[0132] Step 4, determine whether it is hit.

[0133] The hit test control subunit 112 determines whether it is hit.

[0134] If the hit test result of the vertex is hit, it means that the vertex index of the vertex already exists in the vertex shader task to be sent / sent, and it is not necessary to repeatedly send the vertex shader task for the vertex, and at this time, the next vertex can be processed, that is, step 12 is jumped to execute.

[0135] If the hit test result of the vertex is not hit, it means that the vertex index of the vertex does not exist in the vertex shader task to be sent / sent, but it is also possible that it has been processed, but the range saved by the vertex index buffer 111 is limited, and more information cannot be provided, resulting in a miss. But the miss means that the vertex or the vertex index corresponding to the vertex needs to be processed, that is, step 5 is sequentially executed.

[0136] Step 5, test whether the vertex index buffer can accommodate a new vertex index.

[0137] The hit test control subunit 112 needs to check whether the vertex index buffer 111 has enough space to save the missed vertex index.

[0138] Step 6, determine whether the vertex index buffer is full.

[0139] The hit test control subunit 112 determines whether the vertex index buffer 111 is full.

[0140] If the vertex index cache 111 has no enough space to save, i.e. the vertex index cache is full, the hit test control subunit 112 needs to send control information to drive the downstream shader task assembly subunit 113 to send the previously accumulated vertex to the vertex shader program to formally start the vertex shader task, i.e. sequentially execute step 7.

[0141] If the vertex index cache 111 is not full, the hit vertex index is saved to the vertex index cache 111, i.e. jump to execute step 10.

[0142] Step 7, send the cache content to the vertex processing pipeline to execute the vertex shader task.

[0143] The cache content refers to the unsent vertex stored in the vertex index cache 111. The vertex index cache 111 caches the vertex or the vertex index of each vertex, but each vertex index corresponds to a vertex cache index in the vertex index cache 111. The shader identifier is saved in the hit test control subunit 112, and the generation and accumulation of the shader identifier is responsible by the hit test control subunit 112.

[0144] The hit test control subunit 112 sends control information to the shader task assembly subunit 113, and the control information is used to instruct the shader task assembly subunit to send the pipeline index of the stored multiple vertices to the vertex processing pipeline 120, so that the vertex processing pipeline 120 starts the vertex shader program to execute the vertex shader task. Or, the control information is used to instruct the shader task assembly subunit 113 to send the pipeline index of the stored multiple vertices and the mapping relationship to the vertex processing pipeline 120, so that the vertex processing pipeline 120 starts the vertex shader program to execute the vertex shader task. Or, the control information is used to instruct the shader task assembly subunit 113 to send the pipeline index of the stored multiple vertices and the multiple vertex indexes to the vertex processing pipeline 120, so that the vertex processing pipeline 120 starts the vertex shader program to execute the vertex shader task.

[0145] Optionally, the shader task assembly subunit 113 stores the pipeline index of each vertex, and the control information is only used to instruct the shader task assembly subunit 113 to send the pipeline index of each vertex to the vertex processing pipeline 120; or, the shader task assembly subunit 113 stores the pipeline index of each vertex, and the control information includes the shader identifier in addition to instructing the shader task assembly subunit 113 to send the pipeline index of each vertex to the vertex processing pipeline 120, and the shader identifier is used for the shader task assembly subunit 113 to generate the pipeline index of each vertex based on the vertex cache index of each vertex and the shader identifier.

[0146] Step 8, accumulate the shader identifier.

[0147] At the same time when the control information is sent, i.e. at the same time when the cache content is sent to the vertex processing pipeline 120, the hit test control subunit 112 accumulates the shader identifier, i.e. initiates the next vertex shader task.

[0148] In some embodiments, the above-mentioned step 7 and step 8 can be executed in an exchanged order, or can be executed simultaneously.

[0149] Step 9, mark the cache content as invalid.

[0150] Since the vertex in the vertex index cache 111 has been sent at this time, the vertex index cached in the vertex index cache 111 can be safely cleared, such as marking the content in the vertex index cache 111 as invalid by the hit test control subunit 112.

[0151] Step 10, add the vertex index to the vertex index cache to generate a vertex cache index.

[0152] If the vertex index cache 111 has enough space to save the missed vertex index, the hit test control subunit 112 adds the missed vertex index to the vertex index cache 111, and generates the vertex cache index corresponding to the vertex index according to the position of the vertex index in the vertex index cache 111.

[0153] Step 11, fill in the mapping table of the shader identifier and the vertex cache index and the current vertex index.

[0154] The hit test control subunit 112 obtains the pipeline identifier according to the shader identifier and the vertex cache index, and saves the pipeline identifier and the current processed vertex index to the mapping table. The mapping table is used to indicate the mapping relationship between the pipeline identifier and the vertex index of a plurality of vertices. The mapping table is located in the shader task mapping subunit 114, i.e. the hit test control subunit 112 sends the mapping relationship between the shader identifier and the vertex cache index (or the pipeline index) and the vertex index, i.e. the mapping relationship between the pipeline index and the vertex index, to the shader task mapping subunit 114, and the shader task mapping subunit 114 is responsible for saving and sending the mapping relationship to the primitive pipeline unit 140.

[0155] Step 12, determine whether there is a new vertex.

[0156] That is, the hit test control subunit 112 determines whether a plurality of vertices have been processed. If there is no new vertex, i.e. there is no unprocessed vertex in the plurality of vertices, sequentially execute step 13.

[0157] If there is a new vertex, i.e. there is still an unprocessed vertex in the plurality of vertices, continue to obtain an unprocessed vertex to continue the vertex processing, i.e. jump to step 2.

[0158] Step 13, send the cached content to the shader to perform the shading task.

[0159] If there is no more vertex to be processed, the hit test control subunit 112 needs to follow the scene flow that the vertex index cache 111 is full to force to start the vertex shading program for the vertex that is not full in the vertex index cache 111 to perform the vertex shader task, i.e. send the control information to the shader task assembling subunit 113.

[0160] Step 14, accumulate the shader identification.

[0161] The hit test control subunit 112 accumulates the shader identification, i.e. starts the next vertex shader task to prepare for the subsequent input of the plurality of vertex indices.

[0162] Step 15, mark the cached content as invalid.

[0163] Since the vertex indices in the vertex index cache 111 have been sent at this time, these cached vertex indices in the vertex index cache 111 can be safely cleared, e.g. the hit test control subunit 112 directly marks the content in the vertex index cache 111 as invalid.

[0164] Next, the primitive assembling process of the primitive pipeline unit 140 is shown.

[0165] In some embodiments, the primitive pipeline unit 140 includes a primitive assembling pipeline and a primitive processing pipeline;

[0166] Optionally, the primitive assembling pipeline is configured to perform primitive assembling based on the split initial state information, the plurality of vertex indices and the mapping relationship to obtain primitive assembling information of a first primitive to which the first vertex belongs. The primitive processing pipeline is configured to perform primitive processing on the first primitive based on the primitive assembling information of the first primitive. Or, the primitive assembling pipeline is configured to perform primitive assembling based on the split initial state information and the plurality of vertex indices to obtain primitive assembling information of a first primitive to which the first vertex belongs. The primitive processing pipeline is configured to perform primitive processing on the first primitive based on the primitive assembling information of the first primitive and the mapping relationship.

[0167] Optionally, the primitive assembling information includes at least one of a pipeline index of each vertex of the first primitive, a vertex index of each vertex and a mapping relationship between the vertex index of each vertex and the pipeline index.

[0168] Optionally, the primitive assembly information of the first primitive comprises pipeline indexes of respective vertices of the first primitive, the respective vertices of the first primitive comprising the first vertex. The primitive processing pipeline is configured to receive the primitive assembly information sent by the primitive assembly pipeline; acquire vertex processing results of the respective vertices from the vertex storage based on the pipeline indexes of the respective vertices carried by the primitive assembly information; and perform primitive processing on the first primitive based on the vertex processing results of the respective vertices.

[0169] For example, the primitive processing pipeline accesses the vertex storage according to the primitive assembly information sent by the primitive assembly pipeline, acquires vertex processing results of the vertices indicated in the primitive assembly information from the vertex storage, and assembles the primitive based on the results, and further supports performing primitive processing, including but not limited to rasterization, starting a geometry shader, or starting a tessellation function.

[0170] Optionally, the primitive assembly information of the first primitive comprises vertex indexes of respective vertices of the first primitive, the respective vertices of the first primitive comprising the first vertex. The primitive processing pipeline is configured to receive the primitive assembly information sent by the primitive assembly pipeline; determine pipeline indexes of the respective vertices based on the mapping relationship and the vertex indexes of the respective vertices carried by the primitive assembly information; acquire vertex processing results of the respective vertices from the vertex storage based on the pipeline indexes of the respective vertices; and perform primitive processing on the first primitive based on the vertex processing results of the respective vertices.

[0171] Optionally, the mapping relationship is sent by the primitive assembly pipeline to the primitive processing pipeline; or, the mapping relationship is sent by the primitive assembly pipeline to the primitive processing pipeline by being carried in the primitive assembly information, that is, the primitive assembly information comprises the vertex indexes of the respective vertices of the first primitive and the mapping relationship; or, the mapping relationship is sent by the vertex cache unit (or a shader task mapping subunit) to the vertex processing pipeline.

[0172] That is, optionally, the shader task mapping subunit is configured to send the mapping relationship between the vertex indexes and the pipeline indexes to the primitive assembly pipeline or the primitive processing pipeline.

[0173] Optionally, the primitive assembly pipeline 141 performs primitive assembly based on the split initial state information, the plurality of vertex indexes and the mapping relationship to obtain primitive assembly information of a first primitive to which the first vertex belongs; determines whether the respective vertices of the first primitive have completed vertex processing; and in a case where the respective vertices of the first primitive have all completed vertex processing, sends the primitive assembly information to the primitive processing pipeline 142, so that the primitive processing pipeline 142 performs primitive processing based on the primitive assembly information.

[0174] Optionally, the primitive assembling pipeline 141 performs primitive assembling based on the split initial state information, the plurality of vertex indices and the mapping relationship to obtain primitive assembling information of a first primitive to which the first vertex belongs; and sends the primitive assembling information to the primitive processing pipeline 142. The primitive processing pipeline 142 determines whether each vertex is completed with vertex processing based on the primitive assembling information after receiving the primitive assembling information. In a case where each vertex of the first primitive is completed with vertex processing, the primitive processing pipeline 142 performs primitive processing on the first primitive according to the primitive assembling information and vertex processing results of each vertex.

[0175] Optionally, the manner of determining whether each vertex of the first primitive is completed with vertex processing can be querying whether the vertex processing results of each vertex are included in the vertex storage 130. In a case where the vertex processing results of each vertex are included in the vertex storage 130, it is determined that each vertex of the first primitive is completed with vertex processing. In a case where the vertex processing results of each vertex of the first primitive are not included in the vertex storage 130, it is determined that each vertex of the first primitive is not completed with vertex processing. Alternatively, the manner of determining whether each vertex of the first primitive is completed with vertex processing can be confirming whether vertex shader tasks corresponding to each vertex are completed by the vertex processing pipeline 120. In a case where the vertex processing pipeline 120 indicates that the vertex shader tasks corresponding to each vertex are completed, it is determined that each vertex of the first primitive is completed with vertex processing. In a case where the vertex processing pipeline 120 indicates that the vertex shader tasks corresponding to each vertex are not completed, it is determined that each vertex of the first primitive is not completed with vertex processing. Optionally, the vertex processing pipeline 120 sends a shader identifier of each completed vertex shader task to the primitive processing pipeline 142. Alternatively, the primitive processing pipeline 142 sends the shader identifier to the vertex processing pipeline 120, and the vertex processing pipeline 120 sends indication information to the primitive processing pipeline 142 to indicate whether a vertex shader task corresponding to the shader identifier is completed after receiving the shader identifier.

[0176] For example, the primitive assembly information includes the pipeline indexes of the vertices of the first primitive; the primitive assembly pipeline 141 determines the vertex indexes of the vertices belonging to the first primitive from the plurality of vertex indexes based on the split initial state information, such as the first primitive being A-B-C, that is, the first primitive includes three vertices, and the vertex indexes of the three vertices are A, B, and C respectively; the primitive assembly pipeline 141 determines the pipeline indexes of the vertices of the first primitive based on the vertex indexes of the vertices of the first primitive and the mapping relationship, such as the mapped first primitive being wave0-3, wave1-4, and wave0-5, where for waveX-Y, waveX represents the shader identifier, X is a positive integer, Y represents the vertex cache index, and waveX-Y can also be understood as the Yth vertex in the Xth wave (that is, vertex shader task 0); then the primitive assembly pipeline 141 obtains the primitive assembly information based on the pipeline indexes of the vertices of the first primitive and sends the primitive assembly information to the primitive processing pipeline 142; the primitive processing pipeline 142 determines the vertex shader tasks (wave0 and wave1) related to the first primitive according to the pipeline indexes of the vertices of the first primitive indicated in the primitive assembly information; the primitive processing pipeline 142 determines whether the above two vertex shader tasks are executed from the vertex processing pipeline 120; in the case where the above two vertex shader tasks are executed, the vertex processing results of the vertices are read from the vertex storage according to the pipeline indexes of the vertices, and the primitive processing is performed based on the vertex processing results of the vertices.

[0177] In some embodiments, the split initial state information includes at least one vertex that needs to be skipped in the plurality of vertices; the primitive assembly pipeline is configured to, in a case where the first vertex belongs to the at least one vertex that needs to be skipped, skip the first vertex; and in a case where the first vertex does not belong to the at least one vertex that needs to be skipped, determine the primitive assembly information of the first primitive to which the first vertex belongs based on at least two of the arrangement position of the first vertex in the plurality of vertices, the vertex index, and the mapping relationship.

[0178] For example, in a case where the primitive assembly information of the first primitive includes the pipeline indexes of the vertices of the first primitive; the primitive assembly pipeline determines the primitive assembly information of the first primitive to which the first vertex belongs based on the arrangement position of the first vertex in the plurality of vertices, the plurality of vertex indexes, and the mapping relationship in a case where the first vertex does not belong to the at least one vertex that needs to be skipped. For example, the primitive assembly pipeline first determines the first primitive to which the first vertex belongs and the vertex indexes of the vertices of the first primitive based on the arrangement position of the first vertex in the plurality of vertices and the plurality of vertex indexes, the vertices including the first vertex; and determines the pipeline indexes of the vertices based on the vertex indexes of the vertices and the mapping relationship.

[0179] For example, if the primitive assembly information of the first primitive includes vertex indexes of each vertex of the first primitive, the primitive assembly pipeline determines the primitive assembly information of the first primitive to which the first vertex belongs based on the arrangement position of the first vertex in the plurality of vertices and the plurality of vertex indexes, in a case where the first vertex does not belong to the at least one vertex that needs to be skipped. For example, the primitive assembly pipeline first determines the first primitive to which the first vertex belongs and the vertex indexes of each vertex of the first primitive based on the arrangement position of the first vertex in the plurality of vertices and the plurality of vertex indexes, each vertex including the first vertex.

[0180] For example, the split initial state information indicates indexes of vertices in the plurality of vertices that need to be processed. For example, the plurality of vertices are 16 vertices, and the split initial state information indicates that the start offset of the valid vertex is 2, that is, the valid vertex that needs to be processed starts from the second vertex.

[0181] In some embodiments, the geometry processing pipeline is located in a first graphics processing core, and the split initial state information is from a second graphics processing core, the second graphics processing core being a previous graphics processing core connected to the first graphics processing core, or the second graphics processing core being a central graphics processing core of the first graphics processing core.

[0182] For example, the second graphics processing core being a previous graphics processing core connected to the first graphics processing core means that one output end of the second graphics processing core is connected to one input end of the first graphics processing core, and the second graphics processing core generates and sends the split initial state information to the primitive pipeline unit 140 of the first graphics processing core.

[0183] For example, the second graphics processing core being a central graphics processing core of the first graphics processing core means that there are a plurality of graphics processing cores in the graphics processor, and the plurality of graphics processing cores include a central graphics processing core, the central graphics processing core being used to generate split initial state information required by each graphics processing core. The second graphics processing core is the central graphics processing core of the first graphics processing core.

[0184] In summary, the geometry processing pipeline provided by the embodiments of the present application further shows the specific structure of the primitive pipeline unit, the vertex indexes are split by the primitive assembly pipeline to obtain vertex indexes corresponding to at least one primitive, and then the primitive assembly information of the at least one primitive is obtained, and then the primitive processing pipeline assembles and calculates the primitive based on the primitive assembly information, thereby realizing the decoupling of primitive assembly and primitive processing.

[0185] In the case that the primitive assembly information includes the pipeline indexes of the respective vertices, the vertex processing result of each vertex is obtained from the vertex storage directly based on the pipeline indexes by the primitive processing pipeline, the vertex shading in the geometry processing pipeline and the decoupling of the primitive assembly and the external vertex index are realized, and the flexibility of the combined processing pipeline is improved.

[0186] In addition, the process of primitive assembly according to the split initial state information is also shown, that is, invalid vertex indexes that do not need to be processed exist in the multiple vertex indexes, and these vertex indexes are arranged in front of and behind the multiple vertex indexes, so that the anti-interference capability of the multiple vertex indexes in the sending process is improved.

[0187] In addition, the split initial state information can come from the last graphics processing core or the central graphics processing core, that is, the geometry processing pipeline shown in the embodiments of the present application supports both distributed graphics processors and centralized graphics processors, and the application scenarios of the geometry processing pipeline are expanded.

[0188] For the primitive pipeline unit 140, on the one hand, it receives the multiple vertex indexes, and on the other hand, it receives the mapping relationship between the vertex indexes and the pipeline identifiers sent by the vertex cache unit 110. When the primitive pipeline unit 140 receives the split initial state information, it can start to assemble the primitive.

[0189] For example, the processing process of the primitive pipeline unit 140 is further introduced as shown in the following. Figure 4

[0190] Step 1, receiving the vertex index.

[0191] The primitive pipeline unit 140 receives the multiple vertex indexes and obtains a vertex index that needs to be processed from the multiple vertex indexes.

[0192] Step 2, judging whether it is a vertex that needs to be skipped.

[0193] According to the split initial state information, it is judged whether the vertex is a vertex that needs to be skipped. If yes, the vertex is skipped, and step 3 is executed. If no, step 4 is executed to start to assemble the primitive.

[0194] Step 3, skipping, not assembling the primitive.

[0195] After skipping, step 8 is executed to judge whether there is a new vertex that needs to be processed.

[0196] Step 4, starting to assemble the primitive.

[0197] ​The primitive pipeline unit 140 determines the primitive assembly information of the primitive to which the current vertex belongs based on the currently processed vertex index, the position of the currently processed vertex index in the plurality of vertex indexes, and the split initial state information. The primitive assembly information includes the vertex index of the current vertex.

[0198] Step 5, determining the pipeline index based on the vertex index and the mapping relationship.

[0199] The primitive pipeline unit 140 determines the pipeline index of the vertex based on the vertex index and the mapping relationship sent by the vertex cache unit.

[0200] Optionally, the primitive assembly information of the primitive to which the current vertex belongs is determined based on the currently processed vertex index, the position of the currently processed vertex index in the plurality of vertex indexes, the split initial state information, and the mapping relationship. The primitive assembly information includes the pipeline index of the current vertex.

[0201] Step 6, obtaining the vertex processing result of the vertex constituting the primitive from the vertex storage.

[0202] The primitive pipeline unit 140 queries the vertex processing result of the vertex from the vertex storage according to the pipeline index of the vertex. It is determined whether the vertex processing result of all vertices of the current primitive has been queried. When the vertex processing result of all vertices constituting the primitive has been queried from the vertex storage, the primitive is formally processed.

[0203] Step 7, processing the primitive.

[0204] The processing of the primitive includes but is not limited to starting the primitive shader, starting the tessellation pipeline, or performing the rasterization operation.

[0205] Step 8, determining whether there is a new vertex.

[0206] That is, it is determined whether all the plurality of vertices have been processed. If there is no new vertex, that is, there is no vertex in the plurality of vertices that has not been executed for primitive processing, the processing of the primitive pipeline unit 140 is ended.

[0207] If there is a new vertex, that is, there is a vertex in the plurality of vertices that has not been processed, an unprocessed vertex is continuously obtained to continue the primitive processing, that is, the step 1 is executed.

[0208] In the case that the primitive pipeline unit 140 comprises a primitive assembly pipeline and a primitive processing pipeline, the above steps 1 to 4 are performed by the primitive assembly pipeline, the above steps 5 to 7 are performed by the primitive processing pipeline, and both the primitive assembly pipeline and the primitive processing pipeline need to perform step 8, in which case step 8 should be performed between steps 4 and 5 for the primitive assembly pipeline; or, the above steps 1 to 5 are performed by the primitive assembly pipeline, the above steps 6 and 7 are performed by the primitive processing pipeline, and both the primitive assembly pipeline and the primitive processing pipeline need to perform step 8 or neither of them performs step 8, in which case step 8 should be performed between steps 5 and 6 for the primitive assembly pipeline.

[0209] Next, reference is made to Figures 5 to 7 , which shows the specific processing procedure of the geometry processing pipeline shown in the embodiments of the present application.

[0210] As shown in Figure 5 , the vertex indices are A, B, C, D, B, C, A, E, F, C, G, B, C, H, C, I, J, K, A, B, C, i.e. each vertex is represented by a capital letter to indicate its corresponding vertex index. If the vertex processing pipeline 120 is to be shaded in the granularity of 8 vertices when invoking the vertex shader program, these vertices will, after being subjected to hit test in turn, start two vertex shader tasks in total, which are vertex shader task 0 and vertex shader task 1. Vertex shader task 0 processes vertices A, B, C, D, E, F, G, H, while vertex shader task 1 processes I, J, K, A, B, C. Vertex shader task 1 is forced to start because there is no unprocessed vertex, so it does not form a group of 8 vertices. When forming vertex shader task 0, the mapping relationship is shown in the mapping table 60 in Figure 5 , i.e. vertex A is mapped to 0-0, i.e. the 0th vertex of vertex shader task 0, and the same applies to the rest. When forming vertex shader task 1, the mapping relationship is shown in the mapping table 61 in Figure 5 , i.e. vertex I is mapped to 1-0, i.e. the 0th vertex of vertex shader task 1, vertex J is mapped to 1-1, i.e. the 1st vertex of vertex shader task 1, vertex K is mapped to 1-2, i.e. the 2nd vertex of vertex shader task 1, vertex A is mapped to 1-3, i.e. the 3rd vertex of vertex shader task 1, vertex B is mapped to 1-4, i.e. the 4th vertex of vertex shader task 1, and vertex C is mapped to 1-5, i.e. the 5th vertex of vertex shader task 1. It should be noted that although two mapping tables (one for each vertex shader task) are shown in the above Figure 5 , in fact, the two mapping tables are one unified mapping table.

[0211] In the original input stream, there are 21 vertices in total, and after the vertex cache unit 110, only 2 shader tasks are run, and 8+6=14 vertices are sent in total, that is, the vertex shader program processes 14 vertices in total. This is because the embodiment of the application makes full use of the feature that vertices are shared between primitives to reduce the number of repeated vertex processing times. Since the last A, B, and C vertices and the previous A, B, and C vertices are separated by other vertices, the last A, B, and C need to run again in vertex shader task 1.

[0212] The vertex shader task 0 and the vertex shader task 1 are sent to the vertex processing pipeline 120, and after processing, the result is output to the vertex storage 130. Next, the primitive assembly is started by the primitive pipeline unit 140.

[0213] The primitive pipeline unit 140 needs to split according to the split initial state information in addition to receiving the input vertex stream data and the mapping relationship table sent by the vertex cache unit 110.

[0214] Next, the process of the primitive pipeline unit 140 assembling primitives according to different split initial state information is shown.

[0215] Example 1:

[0216] If the primitive topology is a triangle list, and the split initial state information sent indicates that the primitive assembly needs to start from the third vertex (that is, skip the first two vertices A and B).

[0217] As shown in Figure 6 , after skipping the first two vertices AB, the primitive pipeline unit 140 assembles the primitives according to the triangle list rule, which are triangles CDB, CAE, FCG, BCH, CIJ, and KAB. Among them, the last single vertex C cannot form a complete primitive, so it is directly discarded. In the primitive assembly process, according to the mapping relationship table sent, the vertex processing result of each triangle forming vertex is found in the vertex storage 130. For example, for triangle CDB, vertex C is mapped to 0-2, D is mapped to 0-3, and B is mapped to 0-1, which means that this triangle needs to obtain the vertex processing result of the vertex shader task from the 2nd, 3rd, and 1st vertices in the vertex shader task 0 to assemble the primitive.

[0218] Example 2:

[0219] If the split initial state information indicates that the primitive assembly needs to start from the second vertex (that is, skip the first vertex A), then as shown in Figure 7 .

[0220] The triangles split by primitive pipeline unit 140 are BCD, BCA, EFC, GBC, HCI, and JKA. At this time, primitive pipeline unit 140 can still look up the shader identifier-vertex cache index of each vertex from the provided mapping table, and then find the vertex processing result of the corresponding vertex from vertex storage 130 to assemble primitives for further processing.

[0221] The presence of clipping points does not affect the workflow of this application. Clipping points are skipped during hit testing. However, they provide more information for primitive assembly.

[0222] Furthermore, although the number of shaders and caches is the same in this example (8), in practice, the number can be unequal. For example, there could be 32 threads for shader tasks, while the vertex cache could have 128 positions for testing (to search for duplicate vertices over a wider range, reducing the number of vertex shaders). In this case, when each cache is full (i.e., all 128 positions are filled), there are 4 corresponding shader tasks. A mapping table can also provide this mapping relationship. Conversely, if there are 128 threads for shader tasks but only 32 vertex caches, this application can achieve the same purpose.

[0223] In some embodiments, such as Figure 8 As shown, the geometry processing pipeline 100 includes a vertex buffer module 110, a vertex processing pipeline 120, a vertex storage 130, and a primitive pipeline unit 140. The vertex buffer module 110 is connected to the vertex processing pipeline 120, the vertex processing pipeline 120 is connected to the vertex storage 130, the vertex storage 130 is connected to the primitive pipeline unit 140, and the vertex buffer unit 110 is connected to the primitive processing pipeline. Optionally, the primitive pipeline unit 140 includes a primitive assembly pipeline 141 and a primitive processing pipeline 142. The primitive assembly pipeline 141 is connected to the primitive processing pipeline 142, the primitive assembly pipeline 141 is connected to the vertex buffer unit 110, and the primitive processing pipeline 142 is connected to the vertex storage 130. Optionally, Figure 8Only one typical geometry processing pipeline 100 is shown in the embodiments of the present application, but the connection relationship of each unit inside the geometry pipeline 100 can also be different according to different implementation manners, for example, the vertex storage 130 can be connected to the primitive assembly pipeline 141 so that the primitive assembly pipeline 141 can read the vertex processing result from the vertex storage 130; the primitive processing pipeline 142 can also be connected to the vertex cache unit 110 so that the vertex cache unit 110 directly sends the mapping relationship to the primitive processing pipeline 142, and the like, that is, there can be a circuit connection between each unit for sending and receiving the information (such as the split initial state information, the plurality of vertex indexes, the pipeline index, the mapping relationship, etc.) shown in the embodiments of the present application. The embodiments of the present application do not limit this, but the protection scope of the embodiments of the present application is not limited thereto.

[0224] The functions of each unit in the entire geometry processing pipeline 100 are further introduced.

[0225] First, the geometry processing pipeline 100 receives a plurality of vertex indexes.

[0226] For example, the plurality of vertex indexes are sent to the geometry processing pipeline 100 in the form of a vertex stream from a vertex splitting unit. The vertex splitting unit is a unit connected to the geometry pipeline 100 in the image processing core. The vertex splitting unit is used to receive drawing instructions from an application program or a driver program; obtain vertex index data required by the drawing instructions from a storage unit, or generate vertex index data by itself. The vertex splitting unit splits the vertex index data into vertex segments (i.e., the plurality of vertex indexes mentioned in the embodiments of the present application) having the same number of vertex indexes according to the splitting mode specified by the drawing instructions or the driver program or the system configuration module, and sends the vertex segments to the geometry processing pipeline.

[0227] The plurality of vertex indexes are directly sent to the vertex cache unit 110 and the subsequent vertex processing pipeline 120, and after starting the vertex shader task, the vertex processing result is input into the vertex storage 130. On the other hand, the plurality of vertex indexes are directly sent to the primitive assembly pipeline 141. When the primitive assembly pipeline 141 receives the split initial state information, combined with the mapping relationship sent from the vertex cache unit 110, it can start primitive assembly, obtain primitive assembly information, and send it to the primitive processing pipeline 142.

[0228] The primitive processing pipeline 142 accesses the vertex storage 130 according to the primitive assembly information sent by the primitive assembly pipeline 141, so that the vertex processing result calculated by the vertex shading program can be used to assemble primitives for further primitive processing, including but not limited to rasterization, starting a geometry shader, or starting a tessellation function.

[0229] The vertex buffer unit 110 is designed to reduce the number of times the vertex shader program runs. By designing a buffer structure, the vertices sent within a certain period of time are recorded. If a new vertex is found in this buffer, it means that the corresponding vertex has already been sent by the vertex shader program, and there is no need to send it again.

[0230] In the geometry processing pipeline, vertex processing pipeline 120 processes the vertices corresponding to the pipeline indices sent by vertex buffer unit 110. Vertex processing pipeline 120 initiates user-defined vertex shading programs for these vertices and outputs the vertex processing results to vertex storage 130 for subsequent pipelines to use. Vertex processing pipeline 120 operates on a one-to-one basis, inputting and outputting vertex results. Therefore, vertex processing pipeline 120 neither increases nor decreases the number of vertices, nor does it change the order of input vertices, outputting vertex processing results to vertex storage 130 in the order of input. Since the work performed by vertex processing pipeline 120 is actually vertex shading, the vertex processing results can also be called vertex shading results.

[0231] However, for the vertex processing pipeline 120, when running the vertex shader program, in order to improve hardware performance and efficiency, the vertex shader program is not started immediately for each input vertex. Instead, based on the wave / warp design concept, the vertex shader program is only started for these vertices after a certain number of vertices have been collected. In this embodiment, this batch of started vertices is referred to as a vertex shader task (hereinafter referred to as shader task).

[0232] For example, such as Figure 9 The image illustrates a scene where a vertex shader with 8 threads is launched. It should be noted that modern GPU shaders typically have 16 or 32 threads; this example uses 8 threads. The actual number of threads in a shader within each graphics processing core or GPU is not limited, but the scope of this application is not limited thereto. Figure 9 The input vertices shown are processed by the vertex processing pipeline 120, which initiates them as two vertex shader tasks, each containing eight vertices. Vertex shader task 0 corresponds to vertices A, B, C, D, E, F, G, and H, while vertex shader task 1 corresponds to vertices I, J, K, A, L, G, H, and M. A vertex may appear in multiple vertex shader tasks; for example, vertices A, G, and H may appear in vertex shader task 0 and vertex shader task 1, respectively.

[0233] Figure 10 A schematic diagram of a graphics processing core is shown. The graphics processing core 10 includes a geometry processing pipeline 100, which is the geometry processing pipeline mentioned above, including a vertex cache unit with vertex index cache, a vertex processing pipeline, a vertex storage and a primitive pipeline unit, which are not described here again. Optionally, the primitive pipeline unit includes a primitive assembly pipeline and a primitive processing pipeline.

[0234] Optionally, the graphics processing core 10 further includes a vertex splitting unit 200. The first end of the vertex splitting unit 200 is connected with the vertex cache unit 110, and the second end of the vertex splitting unit 200 is connected with the primitive assembly pipeline 141. The vertex splitting unit 200 is used to split at least one vertex index into a plurality of vertex indexes, and send the plurality of vertex indexes to the vertex cache unit 110 and the primitive assembly pipeline 141.

[0235] For example, the vertex splitting unit 200 receives a drawing instruction specified by an application program or a driver program, and then obtains vertex indexes required by the drawing instruction from a storage unit, or generates vertex indexes by itself. The vertex splitting unit 200 splits the vertex indexes into vertex segments with the same number of vertex indexes according to a splitting mode specified by the drawing instruction or the driver program or a system configuration module, i.e. the plurality of vertex indexes mentioned above.

[0236] Optionally, the graphics processing core 10 further includes a storage access arbitrator 300 and a pixel processing pipeline 400. The first end of the storage access arbitrator 300 is connected with the output end of the primitive processing pipeline 142, and the second end of the storage access arbitrator 300 is connected with the pixel processing pipeline 400. The third end of the storage access arbitrator 300 is used to be connected with a system bus, and the system bus is connected with a storage unit. The storage access arbitrator 300 is used to arbitrate access to the storage unit by one of the primitive processing pipeline 142 and the pixel processing pipeline 400.

[0237] In summary, the image processing core provided by the embodiments of the present application realizes the processing of vertices without assembling graphics primitives, and realizes hit testing at the vertex granularity. Specifically, a pipeline index used internally by a geometry pipeline is generated by the vertex cache unit, so that the vertex processing result is stored in the vertex storage together with the pipeline index corresponding to the vertex after the processing of the vertex shader, which makes the vertex shader not need to confirm the graphics primitive in which the vertex is located during processing, that is, the decoupling of vertex shading and hit testing and the decoupling between different geometry processing pipelines are realized, and thus the geometry processing pipeline shown in the embodiments of the present application can be applied to a distributed processor. Compared with the geometry processing pipeline in the related art which uses a graphics primitive as the hit testing granularity, the geometry processing pipeline provided in the embodiments of the present application improves the processing efficiency of the geometry processing pipeline. That is, the vertex cache unit can perform hit testing without obtaining graphics primitive assembly information, so that hit testing and vertex shading can be performed in parallel, and the processing performance of the geometry processing pipeline is improved.

[0238] Figure 11 A schematic diagram of a graphics processor provided by an example embodiment of the present application is shown.

[0239] In some embodiments, the graphics processor includes N graphics processing cores 10, a system configuration unit 20, a system bus 30 and a storage unit 40, N being a positive integer; the N graphics processing cores 10 are connected to the system bus 30 respectively, the system bus 30 is connected to the storage unit 40; the system configuration unit 20 is connected to each of the N graphics processing cores 10 respectively; and each of the graphics processing cores 10 includes the geometry processing pipeline 100.

[0240] Optionally, the N graphics processing cores 10 are homogeneous, that is, the performance of the graphics processor can be adjusted by simply increasing or reducing the number of graphics processing cores 10 to meet the requirements of throughput, performance and power consumption of the graphics processor in different application scenarios, which reduces the complexity of design and verification.

[0241] In summary, the graphic processor provided by the embodiment of the present application realizes the processing of the vertex without assembling the primitive, and realizes the hit test of the vertex granularity. Specifically, the pipeline index used in the geometric processing pipeline is generated by the vertex cache unit, so that the vertex processing result and the pipeline index corresponding to the vertex are stored in the vertex storage after the processing of the vertex shader, which makes the vertex shader not need to confirm the primitive where the vertex is located during the processing, that is, the decoupling of the vertex shading and the hit test and the decoupling between different geometric processing pipelines are realized, and thus the geometric processing pipeline shown in the embodiment of the present application can be applied to the distributed processor. Compared with the geometric processing pipeline with the primitive as the hit test granularity in the related art, the geometric processing pipeline provided by the embodiment of the present application improves the processing efficiency of the geometric processing pipeline. That is, the vertex cache unit can perform the hit test without obtaining the primitive assembly information, so that the hit test and the vertex shading can be performed in parallel, and the processing performance of the geometric processing pipeline is improved.

[0242] Figure 12 A flowchart of a vertex caching method provided by an example embodiment of the present application is shown. The method is performed by the geometric processing pipeline 100 shown above. The geometric processing pipeline 100 includes a vertex cache unit with a vertex index cache, a vertex processing pipeline, a vertex storage, and a primitive pipeline unit. The method includes the following steps.

[0243] In step 510, the vertex cache unit and the primitive pipeline unit receive a plurality of vertex indexes arranged in sequence, and the plurality of vertex indexes are used to indicate a plurality of vertices, and the plurality of vertex indexes correspond to the plurality of vertices one by one.

[0244] Optionally, the plurality of vertex indexes arranged in sequence means that the plurality of vertex indexes are arranged according to the arrangement order of the plurality of vertices in the primitive, for example, the vertex indexes corresponding to the plurality of vertices in each primitive are continuous, and the vertex indexes corresponding to the plurality of vertices in each primitive are arranged in the clockwise order or the counterclockwise order according to the arrangement order of the plurality of vertices in the primitive.

[0245] In step 520, the vertex cache unit adds the vertex index of a first vertex in the plurality of vertex indexes which is not hit in the vertex index cache into the vertex index cache, generates a vertex shader task to which the first vertex belongs, generates a pipeline index of the first vertex, the pipeline index is used to identify the first vertex in the geometric processing pipeline, sends the vertex shader task to which the first vertex belongs and the pipeline index to the vertex processing pipeline to perform vertex processing, and sends the mapping relationship between the vertex index of the first vertex and the pipeline index to the primitive pipeline unit.

[0246] Optionally, the vertex cache hit means that the vertex index of the vertex has been stored in the vertex index cache; and the vertex cache miss means that the vertex index of the vertex does not exist in the vertex index cache.

[0247] Optionally, the vertex shader task includes the vertex processed by the vertex shader program each time the vertex shader program is started. That is, in order to improve the hardware performance and efficiency, the vertex shader program is not started immediately each time a vertex is input. Instead, the vertex shader program is started for a certain number of vertices after the vertices are collected. The batch of vertices started in this way is a vertex shader task (referred to as a shader task).

[0248] Optionally, the pipeline index is used to identify the first vertex in the geometry processing pipeline. Alternatively, the pipeline index is used to identify the first vertex in the vertex cache.

[0249] In some embodiments, the vertex cache unit generates the pipeline index based on a shader identifier corresponding to the first vertex and a vertex cache index; wherein the shader identifier is used to identify the vertex shader task to which the first vertex belongs; and the vertex cache index is used to identify the cache location of the vertex index of the first vertex in the vertex index cache.

[0250] In some embodiments, the vertex cache unit sends the vertex shader task to which the first vertex belongs and the pipeline index of the unsent vertex to the vertex processing pipeline to perform vertex processing based on the unsent vertex when the number of unsent vertices reaches a trigger threshold; wherein the unsent vertex includes the first vertex. For details, refer to the above case one.

[0251] In some embodiments, the vertex cache unit sends the vertex shader task to which the first vertex belongs and the pipeline index of the unsent vertex to the vertex processing pipeline to perform vertex processing based on the unsent vertex when the vertex index cache is full; wherein the unsent vertex includes the first vertex. For details, refer to the above case two.

[0252] In some embodiments, the vertex cache unit sends the vertex shader task to which the first vertex belongs and the pipeline index of the unsent vertex to the vertex processing pipeline to perform vertex processing based on the unsent vertex when there is no remaining vertex in the plurality of vertices that has not been processed; wherein the unsent vertex includes the first vertex. For details, refer to the above case three.

[0253] In some embodiments, the vertex cache unit ignores processing of a second vertex in the plurality of vertices that hits the vertex index cache.

[0254] In some embodiments, the vertex cache unit includes a vertex index cache, a hit test control subunit, a shader task assembly subunit, and a shader task mapping subunit, as shown inFigure 2 The hit test control subunit performs a vertex hit test on each vertex index in the plurality of vertex indexes; adds a vertex index of a first vertex in the plurality of vertex indexes that is not hit in the vertex index cache to the vertex index cache; generates a vertex shader task to which the first vertex belongs; generates a pipeline index of the first vertex; and sends the pipeline index of the first vertex to the shader task assembling subunit; the shader task assembling subunit sends the vertex shader task to which the first vertex belongs and the pipeline index to the vertex processing pipeline to perform vertex processing; and the shader task mapping subunit sends a mapping relationship between the vertex index of the first vertex and the pipeline index to the primitive pipeline unit.

[0255] Step 530: The vertex storage saves a vertex processing result of the first vertex based on the pipeline index.

[0256] Illustratively, the vertex processing result of the first vertex refers to a vertex processing result of the first vertex after the vertex shading program, or a calculation result of the vertex shading program on the first vertex. The vertex shading program is used to calculate the first vertex, such as calculating the lighting, texture coordinates, etc. of the first vertex.

[0257] Step 540: The primitive pipeline unit performs primitive assembly and primitive processing on a first primitive to which the first vertex belongs based on the split initial state information, the plurality of vertex indexes, and the mapping relationship. The split initial state information is used to indicate a split manner of splitting the plurality of vertices into at least one primitive.

[0258] Optionally, the primitive assembly refers to determining each vertex belonging to the first primitive from the plurality of vertices; or, the primitive assembly refers to determining each vertex index belonging to the first primitive from the plurality of vertex indexes; or, the primitive assembly refers to determining each vertex belonging to the first primitive from the plurality of vertices and assembling the each vertex into the first primitive; or, the primitive assembly refers to determining each vertex index belonging to the first primitive from the plurality of vertex indexes and assembling the each vertex index to obtain the first primitive. The each vertex includes the first vertex; and the each vertex index includes the vertex index of the first vertex.

[0259] Optionally, the primitive processing refers to performing a processing related to the first primitive. The primitive processing includes, but is not limited to, rasterization, primitive shading, and tessellation. The tessellation is a method of further dividing the primitive to obtain a smooth surface.

[0260] Optionally, the split initial state information is used to indicate a split manner of splitting the plurality of vertices into the at least one primitive; or, the split initial state information is used to indicate vertices of the plurality of vertices that need to perform primitive assembly; or, the split initial state information is used to indicate vertices of the plurality of vertices that need to be processed by the primitive pipeline unit; or, the split initial state information is used to indicate a split manner of processing the plurality of vertices by the primitive pipeline unit. The split manner includes, but is not limited to, vertices that need to be processed, a number of vertices included in each primitive, a primitive type, and an ordering manner of vertices corresponding to the primitive in the plurality of vertices.

[0261] For example, the vertices that need to be processed are the 2nd to 15th vertices of the plurality of vertices, and the split initial state information is used to indicate the vertices that need to be processed. The number of vertices included in each primitive is 3 when the primitive is a triangle. The primitive type is used to indicate the shape of the primitive or the arrangement of the plurality of primitives, such as a triangle, a quadrangle, a line strip, a triangle strip, and the like. The line strip is a strip structure formed by a plurality of line segments in space, and each line segment is formed by a vertex and a previous vertex except the first vertex. The triangle strip is a strip structure formed by a plurality of triangles in space, and each triangle is formed by a vertex and two previous vertices except the first triangle.

[0262] Optionally, the primitive pipeline unit performs primitive assembly based on the split initial state information and the plurality of vertex indexes to determine a first primitive to which a first vertex belongs, acquires vertex processing results of the first vertex from the vertex storage based on the mapping relationship, and performs primitive processing based on the vertex processing results of the first vertex to obtain the first primitive to which the first vertex belongs. Alternatively, the primitive pipeline unit performs primitive assembly based on the split initial state information and the plurality of vertex indexes to determine a first primitive to which a first vertex belongs, the first primitive including the plurality of vertices, acquires vertex processing results of each vertex of the plurality of vertices from the vertex storage based on the mapping relationship between the vertex indexes and the pipeline indexes, and performs primitive processing based on the vertex processing results of each vertex to obtain the first primitive to which the first vertex belongs.

[0263] In some embodiments, the primitive pipeline unit includes a primitive assembly pipeline and a primitive processing pipeline. The primitive assembly pipeline performs primitive assembly based on the split initial state information, the plurality of vertex indexes, and the mapping relationship to obtain primitive assembly information of a first primitive to which a first vertex belongs. The primitive processing pipeline performs primitive processing based on the primitive assembly information of the first primitive to obtain the first primitive.

[0264] Or, the primitive assembly pipeline is configured to execute primitive assembly based on the split initial state information and the plurality of vertex indexes to obtain primitive assembly information of a first primitive to which the first vertex belongs; and the primitive processing pipeline is configured to execute primitive processing based on the primitive assembly information of the first primitive and the mapping relationship to obtain the first primitive.

[0265] In some embodiments, the primitive assembly information of the first primitive includes a pipeline index of each vertex of the first primitive, and the each vertex of the first primitive includes the first vertex; the primitive processing pipeline receives the primitive assembly information sent by the primitive assembly pipeline; acquires vertex processing results of the each vertex from the vertex storage based on the pipeline index of the each vertex carried by the primitive assembly information; and executes the primitive processing based on the vertex processing results of the each vertex to obtain the first primitive.

[0266] In some embodiments, the primitive assembly information of the first primitive includes a vertex index of each vertex of the first primitive, and the each vertex of the first primitive includes the first vertex; the primitive processing pipeline receives the primitive assembly information sent by the primitive assembly pipeline; determines a pipeline index of the each vertex based on the vertex index of the each vertex carried by the primitive assembly information and the mapping relationship; acquires vertex processing results of the each vertex from the vertex storage based on the pipeline index of the each vertex; and executes the primitive processing based on the vertex processing results of the each vertex to obtain the first primitive.

[0267] In some embodiments, the split initial state information includes at least one vertex of the plurality of vertices that needs to be skipped; the primitive assembly pipeline skips the first vertex in a case where the first vertex belongs to the at least one vertex that needs to be skipped; and in a case where the first vertex does not belong to the at least one vertex that needs to be skipped, determines the primitive assembly information of the first primitive to which the first vertex belongs based on at least two of the arrangement position of the first vertex in the plurality of vertices, the plurality of vertex indexes and the mapping relationship.

[0268] In some embodiments, the geometry processing pipeline is located in a first graphics processing core, and the split initial state information is from a second graphics processing core, the second graphics processing core being a previous graphics processing core connected to the first graphics processing core; or the second graphics processing core being a central graphics processing core of the first graphics processing core.

[0269] In summary, the method provided by the embodiments of the present application realizes the processing of the vertex without assembling the primitive, and realizes the hit test in the vertex granularity. Specifically, the pipeline index used in the geometry pipeline is generated by the vertex cache unit, so that the vertex processing result is stored in the vertex storage together with the pipeline index corresponding to the vertex after the processing of the vertex shader, which makes the vertex shader not need to confirm the primitive where the vertex is located during the processing, that is, the decoupling of the vertex shading and the hit test and the decoupling between different geometry processing pipelines are realized, and thus the geometry processing pipeline shown in the embodiments of the present application can be applied to the processor with a distributed structure. Compared with the geometry processing pipeline with the primitive as the hit test granularity in the related art, the geometry processing pipeline provided in the embodiments of the present application improves the processing efficiency of the geometry processing pipeline. That is, the vertex cache unit can perform the hit test without obtaining the primitive assembly information, so that the hit test and the vertex shading can be performed in parallel, and the processing performance of the geometry processing pipeline is improved.

[0270] It should be understood that "multiple" mentioned herein refers to two or more. The "and / or" describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B can represent the following three cases: A exists alone, A and B exist together, and B exists alone. The character " / " generally represents that the associated objects before and after it are in an "or" relationship. In addition, the step numbers described herein only exemplarily show a possible execution order between steps, and in some other embodiments, the above steps can also be executed in a sequence different from the number, such as simultaneously executing two steps with different numbers or executing two steps with different numbers in an order opposite to the illustration, and the embodiments of the present application do not limit this.

[0271] The above only describes optional embodiments of the present application and does not limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A geometric processing pipeline, characterized in that, The geometry processing pipeline includes: a vertex cache unit with a vertex index cache, a vertex processing pipeline, and a vertex storage and primitive pipeline unit; The vertex cache unit and the primitive pipeline unit are used to receive a plurality of vertex indices arranged in order, the plurality of vertex indices being used to indicate a plurality of vertices, and the plurality of vertex indices corresponding one-to-one with the plurality of vertices; The vertex caching unit is configured to add the vertex index of the first vertex that is not found in the vertex index cache from the plurality of vertex indices to the vertex index cache; generate the vertex shader task to which the first vertex belongs; generate the pipeline index of the first vertex, the pipeline index being used to identify the first vertex in the geometry processing pipeline; send the vertex shader task to which the first vertex belongs and the pipeline index to the vertex processing pipeline for vertex processing; and send the mapping relationship between the vertex index and the pipeline index of the first vertex to the primitive pipeline unit. The vertex storage is used to save the vertex processing results of the first vertex based on the pipeline index; The primitive pipeline unit is used to perform primitive assembly and primitive processing on the first primitive to which the first vertex belongs, based on the initial state information of the split, the multiple vertex indices and the mapping relationship. The initial state information of the split is used to indicate the splitting method of splitting the multiple vertices into at least one primitive.

2. The geometric processing pipeline according to claim 1, characterized in that, The vertex cache unit is used to generate the pipeline index based on the shader identifier and vertex cache index corresponding to the first vertex; The shader identifier is used to identify the vertex shader task to which the first vertex belongs; the vertex cache index is used to identify the cache position of the vertex index of the first vertex in the vertex index cache.

3. The geometric processing pipeline according to claim 1, characterized in that, The vertex caching unit is configured to, when the number of unsent vertices reaches a trigger threshold, send the vertex shader task to which the first vertex belongs and the pipeline index of the unsent vertices to the vertex processing pipeline to execute the vertex processing. The unsent vertices include the first vertex.

4. The geometric processing pipeline according to claim 1, characterized in that, The vertex caching unit is configured to, when the vertex index cache is full, send the vertex shader task to which the first vertex belongs and the pipeline index of the unsent vertices to the vertex processing pipeline to perform vertex processing. The unsent vertices include the first vertex.

5. The geometric processing pipeline according to claim 1, characterized in that, The vertex caching unit is used to send the vertex shader task to which the first vertex belongs and the pipeline index of the unsent vertex to the vertex processing pipeline to perform vertex processing when there are no unprocessed remaining vertices among the plurality of vertices. The unsent vertices include the first vertex.

6. The geometric processing pipeline according to any one of claims 1 to 5, characterized in that, The vertex caching unit is used to ignore the second vertex among the plurality of vertices that is hit in the vertex index cache.

7. The geometric processing pipeline according to any one of claims 1 to 5, characterized in that, The vertex cache unit further includes: a hit test control subunit, a shader task assembly subunit, and a shader task mapping subunit; The hit test control subunit is configured to perform a vertex hit test on each of the plurality of vertex indices; add the vertex index of the first vertex that is not hit in the vertex index cache to the vertex index cache; generate the vertex shader task to which the first vertex belongs; generate the pipeline index of the first vertex; and send the pipeline index of the first vertex to the shader task assembly subunit. The shader task assembly subunit is used to send the vertex shader task to which the first vertex belongs and the pipeline index to the vertex processing pipeline to perform vertex processing; The shader task mapping subunit is used to send the mapping relationship between the vertex index and the pipeline index of the first vertex to the primitive pipeline unit.

8. The geometric processing pipeline according to any one of claims 1 to 5, characterized in that, The primitive pipeline unit includes: a primitive assembly pipeline and a primitive processing pipeline; The primitive assembly pipeline is used to perform primitive assembly based on the split initial state information, the multiple vertex indices, and the mapping relationship to obtain primitive assembly information of the first primitive to which the first vertex belongs; the primitive processing pipeline is used to perform primitive processing on the first primitive based on the primitive assembly information of the first primitive. Alternatively, the primitive assembly pipeline is used to perform primitive assembly based on the split initial state information and the multiple vertex indices to obtain primitive assembly information of the first primitive to which the first vertex belongs; the primitive processing pipeline is used to perform primitive processing on the first primitive based on the primitive assembly information of the first primitive and the mapping relationship.

9. The geometric processing pipeline according to claim 8, characterized in that, The primitive assembly information of the first primitive includes the pipeline index of each vertex of the first primitive, and each vertex of the first primitive includes the first vertex. The primitive processing pipeline is used to receive the primitive assembly information sent by the primitive assembly pipeline; Based on the pipeline index of each vertex carried by the primitive assembly information, the vertex processing results of each vertex are obtained from the vertex storage. Based on the vertex processing results of each vertex, the primitive processing is performed on the first primitive.

10. The geometric processing pipeline according to claim 8, characterized in that, The primitive assembly information of the first primitive includes the vertex index of each vertex of the first primitive, and each vertex of the first primitive includes the first vertex. The primitive processing pipeline is used to receive the primitive assembly information sent by the primitive assembly pipeline; Based on the mapping relationship and the vertex index of each vertex carried by the primitive assembly information, the pipeline index of each vertex is determined. Based on the pipeline index of each vertex, the vertex processing results of each vertex are obtained from the vertex storage; based on the vertex processing results of each vertex, the primitive processing is performed on the first primitive.

11. The geometric processing pipeline according to claim 8, characterized in that, The initial state information for splitting includes: at least one vertex among the plurality of vertices that needs to be skipped; The primitive assembly pipeline is used to skip the first vertex if the first vertex belongs to at least one of the vertices that need to be skipped; and to determine the primitive assembly information of the first primitive to which the first vertex belongs based on at least two of the following: the first vertex's position in the plurality of vertices, the plurality of vertex indices, and the mapping relationship, if the first vertex does not belong to at least one of the vertices that need to be skipped.

12. The geometric processing pipeline according to any one of claims 1 to 5, characterized in that, The geometry processing pipeline is located in the first graphics processing core, and the split initial state information comes from the second graphics processing core, which is the previous graphics processing core connected to the first graphics processing core; or, the second graphics processing core is the central graphics processing core of the first graphics processing core.

13. A graphics processing core, characterized in that, The graphics processing core includes a geometry processing pipeline, wherein the geometry processing pipeline is the geometry processing pipeline as described in any one of claims 8 to 11.

14. The graphics processing core according to claim 13, characterized in that, The graphics processing core also includes: a memory access arbitrator and a pixel processing pipeline; The first end of the storage access arbitrator is connected to the output end of the primitive processing pipeline, the second end of the storage access arbitrator is connected to the pixel processing pipeline, and the third end of the storage access arbitrator is used to connect to the system bus, which is connected to a storage unit. The storage access arbitrator is used to arbitrate access to the storage unit by one of the primitive processing pipeline and the pixel processing pipeline.

15. The graphics processing core according to claim 13 or 14, characterized in that, The graphics processing core further includes: a vertex splitting unit; the first end of the vertex splitting unit is connected to the vertex buffer unit, and the second end of the vertex splitting unit is connected to the primitive assembly pipeline; The vertex splitting unit is used to split at least one vertex index to obtain the plurality of vertex indices; and to send the plurality of vertex indices to the vertex caching unit and the primitive assembly pipeline.

16. A graphics processor, characterized in that, The graphics processor includes: N graphics processing cores, a system configuration unit, a system bus, and a storage unit, where N is a positive integer; The N graphics processing cores are respectively connected to the system bus, and the system bus is connected to the storage unit; The system configuration unit is connected to each of the N graphics processing cores; Each of the graphics processing cores includes a geometry processing pipeline as described in any one of claims 1 to 12.

17. A vertex caching method, characterized in that, The method is performed by a geometry processing pipeline as described in any one of claims 1 to 12, the geometry processing pipeline comprising: a vertex cache unit with a vertex index cache, a vertex processing pipeline, and a vertex storage and primitive pipeline unit; The method includes: The vertex cache unit and the primitive pipeline unit receive a plurality of vertex indices arranged in sequence, the plurality of vertex indices being used to indicate a plurality of vertices, and the plurality of vertex indices corresponding one-to-one with the plurality of vertices; The vertex caching unit adds the vertex index of the first vertex that is not found in the vertex index cache from the plurality of vertex indices to the vertex index cache; generates the vertex shader task to which the first vertex belongs; generates the pipeline index of the first vertex, the pipeline index being used to identify the first vertex in the geometry processing pipeline; sends the vertex shader task to which the first vertex belongs and the pipeline index to the vertex processing pipeline to perform vertex processing; and sends the mapping relationship between the vertex index and the pipeline index of the first vertex to the primitive pipeline unit; The vertex storage stores the vertex processing results of the first vertex based on the pipeline index; The primitive pipeline unit performs primitive assembly and primitive processing on the first primitive to which the first vertex belongs, based on the split initial state information, the multiple vertex indices and the mapping relationship. The split initial state information is used to indicate the splitting method of splitting the multiple vertices into at least one primitive.

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