Method and apparatus for calculating gamma correction in a RISC-V processor

Abstract

Disclosed is a method and device for calculating Gamma correction in a RISC-V processor, which can improve the execution efficiency and calculation accuracy of the Gamma correction algorithm on the RISC-V processor. The Gamma correction is divided into a six-stage pipeline structure: the first stage is composed of a floating-point adder and a floating-point shifter, which maps the input pixel value in the integer range of 0-255 to the real number range of 0-1; the second stage performs a reciprocal operation on the Gamma value; the third stage performs a logarithmic operation on the input pixel value, using the method of lookup table and piecewise linear approximation; the fourth stage uses a floating-point multiplier to multiply the result of the reciprocal operation by the result of the logarithmic operation; the fifth stage performs an exponential operation on the result output by the fourth stage; the sixth stage is composed of a floating-point shifter and a floating-point subtractor, which remaps the image pixel value after Gamma correction back to the integer range of 0-255.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a method for calculating gamma correction in a RISC-V processor, and a device for calculating gamma correction in a RISC-V processor. Background Art

[0002] In modern image and video processing systems, gamma correction plays a crucial role in improving the visual effect of images. Gamma correction can adjust the brightness and contrast of images, enabling more delicate details to be presented on different display devices. When traditional gamma correction algorithms are implemented on some general-purpose processors or software, they often face the problem of low computational efficiency. Especially in resource-constrained embedded systems or image processing scenarios with high real-time requirements, the existing technologies are difficult to meet the needs of efficient and fast gamma correction calculations.

[0003] As an emerging open-source instruction set architecture, the RISC-V architecture has significant advantages such as being streamlined, flexible, and scalable, and has been increasingly widely used in embedded systems and Internet of Things devices. However, there is currently no calculation method for gamma correction algorithms specifically designed for RISC-V processors. Therefore, it is of great practical significance to develop an efficient calculation method for gamma correction algorithms applicable to RISC-V processors. Summary of the Invention

[0004] To overcome the defects of the prior art, the technical problem to be solved by the present invention is to provide a method for calculating gamma correction in a RISC-V processor, which can improve the execution efficiency and calculation accuracy of gamma correction algorithms on RISC-V processors.

[0005] The technical solution of the present invention is: This method for calculating gamma correction in a RISC-V processor divides gamma correction into a six-stage pipeline structure:

[0006] The first stage is composed of a floating-point adder and a floating-point shifter, which maps the input pixel value within the integer range of 0-255 to the real number range of 0-1;

[0007] The second stage performs a reciprocal operation on the gamma value, and also includes a lookup table, which outputs the corresponding γ value according to different input pixel values to implement the adaptive strategy of gamma correction;

[0008] The third stage performs a logarithmic operation on the input pixel value, using a lookup table and a piecewise linear approximation method;

[0009] The fourth stage uses a floating-point multiplier to multiply the result of the reciprocal operation by the result of the logarithmic operation, and the result is used as the input of the fifth stage;

[0010] The fifth stage performs an exponential operation on the result output by the fourth stage to obtain the output pixel value within the range of 0-1 after Gamma correction;

[0011] The sixth stage consists of a floating-point shifter and a floating-point subtractor, which remaps the image pixel values after Gamma correction back to the integer range of 0-255.

[0012] The beneficial technical effects of the present invention are as follows:

[0013] (1) By adopting an approximate calculation strategy combining a lookup table and piecewise linear approximation, the computational complexity and execution time of the complex power operations in the Gamma correction algorithm are significantly reduced, and the computational efficiency is greatly improved.

[0014] (2) A relatively high data accuracy is maintained throughout the calculation process. Compared with the traditional algorithm mainly based on fixed-point operations, the problems of image detail loss and color distortion caused by quantization errors are effectively avoided, and the original details of the image can be accurately restored.

[0015] (3) Through a special design for the hardware architecture characteristics of the RISC-V processor, by reasonably organizing the data structure and calculation process, the resource utilization rate of the processor is effectively reduced.

[0016] There is also provided a device for calculating Gamma correction in a RISC-V processor, which includes:

[0017] A normalization processing module, which consists of a floating-point adder and a floating-point shifter, and maps the input pixel values within the integer range of 0-255 to the real number range of 0-1;

[0018] A reciprocal operation module, which performs a reciprocal operation on the Gamma value, and also includes a lookup table that outputs the corresponding γ value according to different input pixel values to implement the adaptive strategy of Gamma correction;

[0019] A logarithmic operation module, which performs a logarithmic operation on the input pixel values by using a lookup table and piecewise linear approximation;

[0020] A product operation module, which uses a floating-point multiplier to multiply the result of the reciprocal operation by the result of the logarithmic operation, and the result is used as the input of the fifth stage;

[0021] An exponential operation module, which performs an exponential operation on the result output by the product operation module to obtain the output pixel value within the range of 0-1 after Gamma correction;

[0022] The inverse normalization processing module, which consists of a floating-point shifter and a floating-point subtractor, remaps the image pixel values after Gamma correction back to the integer range of 0 - 255. Description of the Drawings

[0023] Figure 1 A schematic diagram showing a method for calculating Gamma correction in a RISC-V processor according to the present invention is shown.

[0024] Figure 2 It is a schematic diagram of the floating-point shifter structure according to the present invention.

[0025] Figure 3 It is a schematic diagram of the reciprocal operation structure according to the present invention.

[0026] Figure 4 It is a schematic diagram of the logarithmic module operation structure according to the present invention.

[0027] Figure 5 It is a schematic diagram of the overall structure of the exponential module according to the present invention.

[0028] Figure 6 It is a schematic diagram of the symbol processing unit structure according to the present invention.

[0029] Figure 7 It is a schematic diagram of the integer decomposition unit structure according to the present invention.

[0030] Figure 8 It is a schematic diagram of the exponential operation structure according to the present invention. Detailed Embodiment

[0031] When a conventional RISC-V processor executes the Gamma correction algorithm, a large number of floating-point extension instructions will be generated by the compiler, which affects the image processing efficiency and increases the execution burden of the processor. The present invention designs a method for calculating the Gamma correction algorithm based on a RISC-V floating-point processor, divides the Gamma correction algorithm into six-level pipelining for operation, designs corresponding floating-point shift arithmetic units (replacing floating-point multipliers and floating-point dividers), floating-point reciprocal arithmetic units (replacing floating-point dividers), and floating-point absolute value arithmetic units, and specially processes special cases in logarithmic operations to improve the execution efficiency and calculation accuracy of the Gamma correction algorithm on the RISC-V processor.

[0032] Specifically, this method for calculating Gamma correction in a RISC-V processor divides Gamma correction into a six-level pipeline structure:

[0033] The first level consists of a floating-point adder and a floating-point shifter, which maps the pixel values within the integer range of 0 - 255 input to the real number range of 0 - 1;

[0034] The second stage performs a reciprocal operation on the Gamma value, which also includes a lookup table that outputs the corresponding γ value according to different input pixel values to implement an adaptive strategy for Gamma correction;

[0035] The third stage performs a logarithmic operation on the input pixel value, using the method of lookup table and piecewise linear approximation;

[0036] The fourth stage uses a floating-point multiplier to multiply the result of the reciprocal operation by the result of the logarithmic operation, and the result is used as the input of the fifth stage;

[0037] The fifth stage performs an exponential operation on the result output by the fourth stage to output the pixel value within the range of 0-1 after Gamma correction;

[0038] The sixth stage consists of a floating-point shifter and a floating-point subtractor, which remaps the image pixel value after Gamma correction back to the integer range of 0-255.

[0039] The beneficial technical effects of the present invention are as follows:

[0040] (1) By adopting an approximate calculation strategy combining a lookup table and piecewise linear approximation, the calculation amount and execution time of complex power operations in the Gamma correction algorithm are significantly reduced, and the calculation efficiency is greatly improved.

[0041] (2) A relatively high data precision is maintained throughout the calculation process. Compared with the traditional algorithm mainly based on fixed-point operation, the problems of image detail loss and color distortion caused by quantization error are effectively avoided, and the original details of the image can be accurately restored.

[0042] (3) Through a special design for the hardware architecture characteristics of the RISC-V processor, by reasonably organizing the data structure and calculation process, the resource utilization rate of the processor is effectively reduced.

[0043] Preferably, in the first stage, for a floating-point number , shifting it n bits to the left is equivalent to , shifting it n bits to the right is equivalent to , performing addition and subtraction operations on the exponent E, and keeping the sign bit S and the mantissa bit F unchanged; Exponent: shifting it n bits to the left, the exponent increases by n; shifting it n bits to the right, the exponent decreases by n; if the exponent overflows, return 255 or 0, and the exception status flag is inexact.

[0044] Preferably, in the second stage, first convert 1 to the standard format of IEEE-754 floating-point number, keep the sign bit unchanged, and then perform corresponding processing on the exponent bit and the mantissa bit respectively.

[0045] Preferably, the third stage includes a control unit, an amplification unit, a look-up table, a selection unit, a multiplexer, a floating-point multiplier, and two floating-point adders;

[0046] The control unit determines how to process the input normalized pixel value and selects the corresponding processing method for the input pixel. There are three cases for the processing of the input pixel. The first case is when is equal to 0 or 1, and the corresponding result is directly output. The second case is when is very close to 0. In this case, is amplified and then processed using the base change formula. The third case is processed using the look-up table and linear approximation method.

[0047] The amplification unit amplifies the pixel value that is very close to 0.

[0048] The look-up table stores the slope, intercept, and pre-calculated value of ln2.

[0049] The selection unit finds the corresponding division interval according to the pixel value.

[0050] The multiplexer outputs the corresponding result.

[0051] Preferably, the fifth stage includes a sign processing unit, an integer decomposition unit, an integer shifter, an exponentiation unit, a multiplication unit, and a reciprocal operation unit;

[0052] The sign processing unit calculates the value of . For a floating-point number , the absolute value is . The sign bit S is set to 0, and the exponent bit and mantissa bit remain unchanged.

[0053] The integer decomposition unit decomposes the exponent part into an integer part and a fractional part. The value of the integer part n is calculated using a floating-point divider and a floating-point to integer converter, and the value of the fractional part r is calculated using a floating-point multiplier and a floating-point adder. These values are used as the input values for the integer shifter and the exponentiation operation respectively.

[0054] This is implemented through the integer shifter in the shared ALU module.

[0055] This is implemented using the look-up table and piecewise linear approximation method, and includes a comparator, a look-up table, a data selector, a floating-point multiplier, and a floating-point adder.

[0056] The value of is calculated using a floating-point multiplier and the reciprocal operation method.

[0057] Those of ordinary skill in the art can understand that all or part of the steps in implementing the methods of the above embodiments can be completed by instructing relevant hardware through a program. The program can be stored in a computer-readable storage medium. When the program is executed, it includes the steps of the methods of the above embodiments, and the storage medium can be: ROM / RAM, magnetic disk, optical disk, memory card, etc. Therefore, corresponding to the method of the present invention, the present invention also simultaneously includes a device for calculating Gamma correction in a RISC-V processor, and this device is usually represented in the form of functional modules corresponding to the steps of the method. This device includes:

[0058] A normalization processing module, which is composed of a floating-point adder and a floating-point shifter, and maps the input pixel value within the integer range of 0 - 255 to the real number range of 0 - 1;

[0059] A reciprocal operation module, which performs a reciprocal operation on the Gamma value, and also includes a look-up table. The look-up table outputs the corresponding γ value according to different input pixel values to implement the adaptive strategy of Gamma correction;

[0060] A logarithmic operation module, which performs a logarithmic operation on the input pixel value, using the method of look-up table and piecewise linear approximation;

[0061] A product operation module, which uses a floating-point multiplier to perform a product operation on the result of the reciprocal operation and the result of the logarithmic operation, and its result is used as the input of the fifth stage;

[0062] An exponential operation module, which performs an exponential operation on the result output by the product operation module to output the pixel value within the range of 0 - 1 after Gamma correction;

[0063] An inverse normalization processing module, which is composed of a floating-point shifter and a floating-point subtractor, and remaps the image pixel value after Gamma correction back to the integer range of 0 - 255.

[0064] Preferably, in the normalization processing module, for a floating-point number , shifting n bits to the left is equivalent to , shifting n bits to the right is equivalent to , performing addition and subtraction operations on the exponent E, and keeping the sign bit S and the mantissa bit F unchanged; exponent: shifting n bits to the left, the exponent increases by n; shifting n bits to the right, the exponent decreases by n; if the exponent overflows, return 255 or 0, and the exception status flag is inexact.

[0065] Preferably, in the reciprocal operation module, first convert 1 to the standard format of IEEE-754 floating-point number, keep the sign bit unchanged, and then perform corresponding processing on the exponent bit and the mantissa bit respectively.

[0066] Preferably, the logarithmic operation module includes a control unit, an amplification unit, a lookup table, a selection unit, a multiplexer, a floating-point multiplier, and two floating-point adders;

[0067] The control unit determines how to process the input normalized pixel value and selects the corresponding processing for the input pixel There are three cases for the processing of the input pixel. The first case is when is equal to 0 or 1, and the corresponding result is directly output; the second case is when is very close to 0, and is amplified and then processed using the base change formula; the third case is processed using the lookup table and the method of linear approximation;

[0068] The amplification unit amplifies the pixel value that is very close to 0 ;

[0069] The lookup table stores the slope, intercept, and pre-calculated value of ln2;

[0070] The selection unit finds the corresponding division interval according to the pixel value ;

[0071] The multiplexer outputs the corresponding result.

[0072] Preferably, the fifth stage includes a sign processing unit, an integer decomposition unit, an integer shifter, an exponentiation unit, a multiplication unit, and a reciprocal operation unit;

[0073] The sign processing unit calculates the value. For a floating-point number , the absolute value is , the sign bit S is set to 0, and the exponent bit and mantissa bit remain unchanged;

[0074] The integer decomposition unit decomposes the exponent part into an integer part and a fractional part, calculates the value of the integer part n using a floating-point divider and a floating-point to integer unit, and calculates the value of the fractional part r using a floating-point multiplier and a floating-point adder, which are respectively used as the input values of the integer shifter and the exponentiation operation;

[0075] It is implemented by sharing the integer shifter in the ALU module;

[0076] It is implemented using the method of lookup table and piecewise linear approximation, and includes a comparator, a lookup table, a data selector, a floating-point multiplier, and a floating-point adder;

[0077] Calculate using a floating-point multiplier and a reciprocal operation method value.

[0078] The present invention will be described in more detail below.

[0079] The Gamma correction formula is:[[]]

[0080] ,

[0081] where:[[]]

[0082] : Input pixel value, with a value range of 0 ≤ ≤ 255;

[0083] γ: Gamma correction value, with a value range of 0 <γ <2.5;

[0084] : Output pixel value, with a value range of 0 ≤ ≤ 255.

[0085] As Figure 1 shown, to perform Gamma correction, it is first necessary to normalize the input pixel value, then perform a power operation, that is, perform pre-compensation processing on the normalized data, and finally perform denormalization processing. And the overall operation is divided into a six-stage pipeline to reduce the critical path and improve the performance of the processor.

[0086] Gamma correction steps:[[]]

[0087] Normalization:[[]] ,

[0088] Power operation:[[]] ,

[0089] Denormalization:[[]] ,

[0090] where:[[]]

[0091] The power operation module is converted to:[[]] ,

[0092] : Is the normalized pixel value, with a value range of 0 ≤ ≤ 1;

[0093] : The value range is -∞ < ≤ 0;

[0094] : The value range is -∞ < ≤ 0;

[0095] : The value range is 0 < ≤ 1.

[0096] The first-level data normalization unit is serially composed of a floating-point adder and a floating-point shifter, and is used to output the normalized pixel value .

[0097] As Figure 2 shown, it is the structure diagram of the floating-point shifter.

[0098] For a floating-point number , shifting it n bits to the left is equivalent to , and shifting it n bits to the right is equivalent to . Mainly perform addition and subtraction operations on the exponent E, keep the sign bit S and the mantissa bit F unchanged. Exponent: When shifting n bits to the left, the exponent increases by n; when shifting n bits to the right, the exponent decreases by n; if the exponent overflows (exceeds the maximum value or is less than the minimum value), return 255 or 0, and the exception status flag is inexact.

[0099] The second-level lookup table is used to output the corresponding γ value according to different pixel values , so that different gray-level regions are correspondingly enhanced.

[0100] The reciprocal operation is used to change the γ value to for exponent calculation, aiming to ensure that when the data after the power operation is input to the display device, the display device can correctly reproduce the brightness of the original image.

[0101] As Figure 3 shown, it is the structure diagram of the reciprocal operation. The reciprocal operation can be regarded as a special case of the floating-point division operation.

[0102] For a floating-point number , its reciprocal , so the sign bit remains unchanged, and only the exponent bit and the mantissa bit need to be adjusted. The exponent E is directly negated, and the mantissa bit is , and the calculation of the mantissa is implemented using the radix-2 restoring remainder algorithm in the floating-point divider.

[0103] The third-level logarithm module is used to calculate the value of. As Figure 4 shown, it includes a control unit, a selection unit, an amplification unit, a lookup table, a floating-point multiplier, two floating-point adders, and a multiplexer.

[0104] The control unit is used to control how to perform operations according to the input pixel value . When the pixel value is 0 or 1, directly output the result. When the pixel value When it is very close to 0 (the set threshold is 0.01), first magnify the pixel value and then perform corresponding calculations according to the base conversion formula. In other cases, use the method of lookup table and linear piecewise approximation for calculation.

[0105] When the pixel value is very close to 0, problems of numerical precision and calculation overflow will be faced. Therefore, to avoid this situation, first magnify the pixel value and then perform corresponding calculations according to the base conversion formula. When the control unit detects , use the base conversion formula to convert to: , is larger than , so the value is more stable and has higher precision.

[0106] In other cases, first divide the interval, divide [0,1] into multiple intervals: [0,0.05), [0.05,0.1)…[0.95,1].

[0107] The lookup table stores the slope and intercept: calculate the slope and intercept of each interval in advance and store them in the lookup table.

[0108] Calculate : According to the value of , first find the corresponding interval through the selection unit, then find the slope and intercept of the corresponding interval from the lookup table, and finally calculate through the floating-point multiplier and floating-point adder: .

[0109] The fourth stage uses a floating-point multiplier to calculate the product of the value output by the second stage and the value output by the third stage , that is, the value of , which is the input value of the exponent module.

[0110] The fifth stage is the exponent module to find the value of . As shown in Figure 5 , it includes a sign processing unit, an integer decomposition unit, an integer shifter, an exponent operation unit, a multiplication operation unit and a reciprocal operation unit.

[0111] Let , and -∞≤ ≤0, then .

[0112] Wherein:

[0113] ,

[0114] is the integer part of is the fractional part of, with a value range of .

[0115] Wherein the symbol processing unit is used to calculate the value of. As Figure 6 shown, for a floating-point number , find the absolute value as , so only set the sign bit S to 0 (keep the positive number case unchanged), and keep the exponent bit and mantissa bit unchanged.

[0116] The integer decomposition unit is used to decompose the exponent part into an integer part and a fractional part. As Figure 7 shown, use a floating-point divider and a floating-point to integer unit to calculate the value of the integer part n, and use a floating-point multiplier and a floating-point adder to calculate the value of the fractional part r, which are used as the input values of the integer shifter and the exponent operation respectively.

[0117] is directly implemented by sharing the integer shifter in the ALU module.

[0118] is also implemented by using the method of look-up table and piecewise linear approximation. As Figure 8 shown, it includes a comparator, a look-up table, a multiplexer, a floating-point multiplier and a floating-point adder. The specific implementation method is the same as that of the logarithm operation method.

[0119] Finally, use a floating-point multiplier and the reciprocal operation method to calculate the value of.

[0120] The sixth stage is the data denormalization unit, which consists of a floating-point shifter and a floating-point subtractor, and is used to remap the image pixel value after Gamma correction back to the 0-255 integer range.

[0121] The above is only a preferred embodiment of the present invention, and does not impose any form of limitation on the present invention. Any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention shall still fall within the protection scope of the technical solution of the present invention.

Claims

1. A method for calculating gamma correction in a RISC-V processor, characterized by: Gamma correction is divided into a six-stage pipeline structure: The first stage consists of a floating-point adder and a floating-point shifter, which maps the input pixel value in the integer range of 0-255 to the real number range of 0-1; The second stage performs a reciprocal operation on the Gamma value, which also includes a lookup table. The lookup table outputs the corresponding γ value according to the different input pixel values to implement the adaptive strategy of Gamma correction; The third stage performs logarithmic operations on the input pixel values using a lookup table and piecewise linear approximation method; The fourth stage uses a floating-point multiplier to multiply the result of the reciprocal operation and the result of the logarithm operation, and the result is used as the input of the fifth stage; The fifth stage performs an exponential operation on the output of the fourth stage, and outputs a pixel value in the range of 0-1 after gamma correction; The sixth stage consists of a floating-point shifter and a floating-point subtractor, which remaps the image pixel values after gamma correction back to the integer range of 0-255.

2. The method for calculating gamma correction in a RISC-V processor according to claim 1, wherein: In the first level, for a floating point number , shifting left by n bits is equivalent to , shifting right by n bits is equivalent to , perform addition and subtraction operations on the exponent E, and the sign bit S and the mantissa bit F remain unchanged; the exponent: if it is shifted left by n bits, the exponent increases by n; if it is shifted right by n bits, the exponent decreases by n; if the exponent overflows, it returns 255 or 0, and the exception status flag is inaccurate.

3. The method for calculating Gamma correction in the RISC-V processor according to claim 2, characterized in that: In the second stage, 1 is first converted to the standard format of IEEE-754 floating point numbers, with the sign bit remaining unchanged, and then the exponent bit and the mantissa bit are processed accordingly.

4. The method for calculating Gamma correction in the RISC-V processor according to claim 3, wherein: The third stage includes a control unit, an amplification unit, a lookup table, a selection unit, a multiple-to-one data selector, a floating-point multiplier, and two floating-point adders; The control unit selects how to process the input normalized pixel values and processes the input pixels in three cases. The first case is when is equal to 0 or 1, and the corresponding result is directly output; the second case is when is very close to 0, and it is processed by magnifying and then using the change-of-base formula; the third case is processed by using a look-up table and linear approximation methods; Amplify the pixel values that are very close to 0 Perform amplification processing; The lookup table stores the slope, intercept, and pre-calculated ln2 values; The selection unit finds the corresponding division interval according to the pixel value ; The multiple-choice data selector outputs the corresponding results.

5. The method for calculating Gamma correction in the RISC-V processor according to claim 4, characterized in that: The fifth stage includes a sign processing unit, an integer decomposition unit, an integer shifter, an exponential operation unit, a multiplication operation unit, and a reciprocal operation unit; Symbolic Processing Unit Computation The value of a floating point number , the absolute value is , set the sign bit S to 0, and the exponent bit and mantissa bit remain unchanged; The integer decomposition unit decomposes the exponential part into an integer part and a fractional part, uses the floating-point divider and the floating-point to integer conversion unit to calculate the value of the integer part n, and uses the floating-point multiplier and the floating-point adder to calculate the value of the fractional part r, which serve as the input values of the integer shifter and the exponential operation respectively; Implemented by sharing the integer shifter in the ALU module; It is implemented by using the lookup table and piecewise linear approximation method; Calculate the value using a floating-point multiplier and a reciprocal operation method value 6. The device for calculating gamma correction in a RISC-V processor according to claim 1, wherein: It includes: Normalization processing module, which consists of a floating-point adder and a floating-point shifter, maps the input pixel value in the integer range of 0-255 to the real number range of 0-1; The reciprocal operation module performs the reciprocal operation on the Gamma value, which also includes a lookup table. The lookup table outputs the corresponding γ value according to different input pixel values to implement the adaptive strategy of Gamma correction; A logarithmic operation module performs logarithmic operations on input pixel values using a lookup table and piecewise linear approximation method; A product operation module uses a floating-point multiplier to perform a product operation on the result of the reciprocal operation and the result of the logarithm operation, and the result is used as the input of the exponential module; An exponential module performs an exponential operation on the result output by the product operation module, and outputs a pixel value in the range of 0-1 after gamma correction; The denormalization processing module, which consists of a floating-point shifter and a floating-point subtractor, remaps the pixel values of the gamma-corrected image back to the integer range of 0-255.

7. The device for calculating gamma correction in a RISC-V processor according to claim 6, characterized in that: In the normalization processing module, for a floating-point number , shifting it n bits to the left is equivalent to , shifting it n bits to the right is equivalent to . Performing addition and subtraction operations on the exponent E, while keeping the sign bit S and the mantissa bit F unchanged; Exponent: When shifting n bits to the left, the exponent increases by n; when shifting n bits to the right, the exponent decreases by n; If the exponent overflows, return 255 or 0, and the exception status flag is inexact.

8. The device for calculating gamma correction in a RISC-V processor according to claim 7, wherein: In the reciprocal operation module, 1 is first converted into the standard format of IEEE-754 floating point number, the sign bit remains unchanged, and then the exponent bit and the mantissa bit are processed accordingly.

9. The apparatus for calculating the Gamma correction method in the RISC-V processor according to claim 8, wherein: The logarithmic operation module includes a control unit, an amplification unit, a lookup table, a selection unit, a multiplexer, a floating-point multiplier, and two floating-point adders; The control unit is based on the normalized pixel value of the input Choose how to process the input pixels. There are three cases for the processing. The first case is when When it is equal to 0 or 1, the corresponding result is output directly; the second case is when When it is very close to 0, Amplify and then use the base replacement formula for processing; the third case uses the lookup table and linear approximation method for processing; Amplify the pixel values that are very close to 0 Perform amplification processing; The lookup table stores the slope, intercept, and pre-calculated value of ln2; The selection unit finds the corresponding division interval according to the pixel value ; The multiplexer outputs the corresponding result.

10. The apparatus for calculating the method of gamma correction in the RISC-V processor according to claim 9, wherein: The exponential module includes a sign processing unit, an integer decomposition unit, an integer shifter, an exponential operation unit, a multiplication operation unit, and a reciprocal operation unit; Symbolic Processing Unit Computation The value of a floating point number , the absolute value is , set the sign bit S to 0, and the exponent bit and mantissa bit remain unchanged; The integer decomposition unit decomposes the exponent part into an integer part and a fractional part, calculates the value of the integer part n using a floating-point divider and a floating-point to integer unit, calculates the value of the fractional part r using a floating-point multiplier and a floating-point adder, and uses them as the input values for the integer shifter and the exponential operation respectively; Implemented by sharing the integer shifter in the ALU module; Implemented by using a lookup table and piecewise linear approximation; Calculate the value using a floating-point multiplier and a reciprocal operation method value

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