Display panel, display driving method and display device

Abstract

The present application belongs to the field of display driving technology, and specifically relates to a display panel, a display driving method and a display device, wherein the display panel includes N rows of scan lines, M columns of data lines, and an array-arranged pixel circuit; each pixel circuit includes a pixel unit and a control unit, and the first control end of the 2n-1 row control unit and the first control end of the 2n row control unit are respectively connected to the n-th row scan line; when the n-th row scan line is turned on: the data signal on the m-th column data line controls any one of the m-th column 2n-1 row control unit and the m-th column 2n row control unit to be turned on or turned on alternately in time-sharing, or the data signal on the m-th column data line controls any one of the m-th column 2n-1 row control unit and the m-th column 2n row control unit to be turned on or turned on alternately in time-sharing; the present application reduces the number of scan lines by half under display conditions of the same resolution, which not only reduces the power consumption and cost of the panel, but also improves the refresh rate and aperture ratio.

Description

Technical Field

[0001] The present disclosure belongs to the field of display driving technology, and particularly relates to a display panel, a display driving method, and a display device. Background Art

[0002] Current display panels are equipped with pixel units arranged in a matrix, and each pixel unit requires a data line for providing data signals and a scan line for controlling the pixel unit to turn on and off. With the continuous updating and iteration of display technology, high-resolution panels have gradually become mainstream products in the market. High resolution means that more data lines and scan lines are required, which causes the RC loading (resistance-capacitance load, abbreviated as RC loading) of the display panel to continue to increase, resulting in high power consumption of the display panel.

[0003] It can be seen that how to reduce the power consumption of display panels is an urgent problem to be solved. Summary of the Invention

[0004] The present application provides a display panel, a display driving method and a display device, which solve the problem of high power consumption of the display panel. The present application reduces the number of scan lines by half under display conditions of the same resolution, which not only reduces the power consumption and cost of the panel, but also improves the refresh rate and aperture rate.

[0005] In a first aspect, the present application provides a display panel, the display panel comprising: N rows of scan lines, M columns of data lines, and an array of pixel circuits; each pixel circuit comprises a pixel unit and a control unit, the control unit being configured to charge the pixel unit through a data signal on the data line when in an on state; the control unit comprising a first control terminal, a second control terminal, an input terminal, and an output terminal; the first control terminal of the 2n-1 row control unit and the first control terminal of the 2n row control unit are respectively connected to the n-th row scan line; the second control terminal and the input terminal of the m-th column control unit are both connected to the m-th column data line, or the second control terminal of the m-1 even-numbered row control unit is respectively connected to the m-th column data line. The control end and input end, as well as the second control end and input end of the control unit of the mth column odd row, are all connected to the data line of the mth column; the output end of each control unit is connected to the input end of the corresponding pixel unit; when the scan line of the nth row is turned on: the data signal on the data line of the mth column controls any one of the control unit of the mth column 2n-1 row and the control unit of the mth column 2n row to be turned on or turned on alternately in time-sharing, or the data signal on the data line of the mth column controls any one of the control unit of the mth column 2n-1 row and the m-1th column 2n row to be turned on or turned on alternately in time-sharing; wherein, n=[1, ..., N], m=[1, ..., M], and N and M are both positive integers greater than 1.

[0006] Optionally, the control unit includes: a first switch tube, the control end of the first switch tube is connected to the data line, and the first end of the first switch tube is connected to the scan line; a second switch tube, the control end of the second switch tube is connected to the second end of the first switch tube, the first end of the second switch tube is connected to the data line, and the second end of the second switch tube is connected to the pixel unit; when the second control end and the input end of the m-th column control unit are both connected to the m-th column data line, the turn-on voltage of the first switch tube of the m-th column 2n-1 row control unit is opposite to that of the first switch tube of the m-th column 2n-1 row control unit; when the second control end and the input end of the m-th column even row control unit and the second control end and the input end of the m-th column odd row control unit are both connected to the m-th column data line, the turn-on voltage of the first switch tube of the m-th column 2n row control unit is opposite to that of the first switch tube of the m-th column 2n-1 row control unit.

[0007] Optionally, when the second control end and input end of the control unit of the m-1th column even row and the second control end and input end of the control unit of the mth column odd row are both connected to the data line of the mth column, in the pixel circuits of the 1st column 2n-1th row and the M-1th column 2nth row, the control unit further includes: a third switch tube, the control end of the third switch tube is connected to the data line, the first end of the third switch tube is connected to the scan line, and the second end of the third switch tube is connected to the control end of the second switch tube; wherein the turn-on voltages of the third switch tube and the first switch tube are opposite.

[0008] Optionally, the pixel unit in the 3i+1th column is a first color sub-pixel, the pixel unit in the 3i+2th column is a second color sub-pixel, and the pixel unit in the 3i+3th column is a third color sub-pixel; wherein, i=[0,1,2,…,I], when M is a multiple of 3 otherwise

[0009] Optionally, the pixel units in the 3j+1th row are first color sub-pixels, the pixel units in the 3j+2th row are second color sub-pixels, and the pixel units in the 3j+3th row are third color sub-pixels; wherein j = [0, 1, 2, ..., J], when 2N is a multiple of 3 otherwise

[0010] Optionally, the pixel unit includes a liquid crystal capacitor, and a pixel electrode of the liquid crystal capacitor is connected to an output end of the control unit.

[0011] Optionally, the pixel unit includes: a storage capacitor, the first end of the storage capacitor is connected to the output end of the control unit, and the second end of the storage capacitor is connected to the power supply end; a driving transistor, the control end of the driving transistor is connected to the first end of the storage capacitor, and the first end of the driving transistor is connected to the second end of the storage capacitor; a light-emitting diode, the anode of the light-emitting diode is connected to the second end of the driving transistor, and the cathode of the light-emitting diode is grounded.

[0012] Optionally, during the n-th row scan line on time period of the current frame, each column of data lines outputs a corresponding first data signal, and during the n-th row scan line on time period of the next frame, each column of data lines outputs a corresponding second data signal; or, during the n-th row scan line on time period of the current frame, each column of data lines alternately outputs a corresponding first data signal and a second data signal; or, during the n-th row scan line on time period of the current frame, odd-numbered or even-numbered column data lines output corresponding first data signals and second data signals; wherein, the polarities of the first data signal and the second data signal are opposite.

[0013] In a second aspect, the present application provides a display driving method, which includes: obtaining a first target conduction polarity corresponding to the first control end of each control unit in the display panel and a second target conduction polarity corresponding to the second control end of each control unit; generating a scan signal corresponding to each row of scan lines and a data signal corresponding to each column of data lines based on all first target conduction polarities, all second target conduction polarities and the display picture of the current frame, so that when the nth row of scan line is turned on, the data signal on the mth column of the data line controls any one of the mth column 2n-1 row control unit and the mth column 2n row control unit to be turned on or turned on alternately in time-sharing, or the data signal on the mth column of the data line controls any one of the mth column 2n-1 row control unit and the m-1 column 2n row control unit to be turned on or turned on alternately in time-sharing.

[0014] In a third aspect, the present application provides a display device, comprising: a gate drive circuit for outputting a scan signal; a source drive circuit for outputting a data signal; and a display panel, wherein the scan line of the display panel is connected to the gate drive circuit, and the data line of the display panel is connected to the source drive circuit.

[0015] The technical solution provided by this application has at least the following beneficial effects:

[0016] 1. In this application, two adjacent rows of pixel circuits share a scan line, and the pixel circuits connected to the same scan line are controlled by data lines so as not to be turned on at the same time. Under the display conditions of the same resolution, the number of scan lines is reduced by half, so that the RC loading on the scan line is also reduced, thereby reducing the power consumption of the display panel.

[0017] 2. This application reduces the number of scan lines by half, which not only reduces the production cost of the display panel, but also increases the refresh rate and aperture rate of the panel, thereby improving the market competitiveness of the product.

[0018] 3. Since the RC loading value of the display panel is proportional to the noise value, this application can reduce the panel noise and improve display accuracy while reducing the panel RC loading. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0020] Figure 1 Shown is a schematic structural diagram of a first display panel provided in an embodiment of the present application.

[0021] Figure 2 Shown is a schematic structural diagram of a second display panel provided in an embodiment of the present application.

[0022] Figure 3 Shown is a circuit diagram of a first pixel circuit provided in an embodiment of the present application.

[0023] Figure 4 Shown is a circuit diagram of a second pixel circuit provided in an embodiment of the present application.

[0024] Figure 5 Shown is a circuit diagram of a third pixel circuit provided in an embodiment of the present application.

[0025] Figure 6 The figure is a flow chart of a display driving method provided in an embodiment of the present application.

[0026] Figure 7 Shown is a first display screen and waveform diagram provided in an embodiment of the present application.

[0027] Figure 8 Shown is a second display screen and waveform diagram provided in an embodiment of the present application.

[0028] Figure 9 Shown is a third display screen and waveform diagram provided in an embodiment of the present application.

[0029] Figure 10FIG2 is a schematic diagram of a pixel structure of a display panel provided in an embodiment of the present application.

[0030] Description of reference numerals:

[0031] 100, display panel; 110, scan line; 120, data line; 130, pixel circuit; 131, control unit; 132, pixel unit;

[0032] T0, driving transistor; T1, first switching tube; T2, second switching tube; T3, third switching tube; Cc, storage capacitor; Cs, pixel capacitor; Ct, energy storage capacitor; OLED, light-emitting diode. DETAILED DESCRIPTION

[0033] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art.

[0034] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner.In the following description, many specific details are provided so as to provide a full understanding of the embodiments of the present application. However, it will be appreciated by those skilled in the art that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps etc. can be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0035] The present application is further described below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be understood as limiting the present application.

[0036] Figure 1 FIG. 1 is a schematic structural diagram of a first display panel provided in an embodiment of the present application; FIG. Figure 1 As shown, the display panel 100 includes: N rows of scan lines 110, M columns of data lines 120, and pixel circuits 130 arranged in an array; wherein, the number of columns of the pixel circuits 130 is M, and the number of rows is 2N; that is, the number of columns of the pixel circuits 130 in the display panel 100 is the same as the number of columns of the data lines 120, and the number of rows of the pixel circuits 130 is twice that of the scan lines. Figure 1 The scan lines 110 and data lines 120 in FIG. 1 cross but are not connected. Figure 1In the figure, G1, G2 and GN represent the first row scan line, the second row scan line and the Nth row scan line respectively, and S1, S2, S3 and SM represent the first column data line, the second column data line, the third column data line and the Mth column data line respectively.

[0037] In one embodiment, each pixel circuit 130 includes a pixel unit 132 and a control unit 131. The control unit 131 is used to input the data signal on the data line 120 into the pixel unit 132 when it is in a conductive state, thereby charging the pixel unit 132 through the data signal on the data line 120; on the contrary, when the control unit 131 is in an off state (i.e., a non-conductive state), the data signal on the data line 120 cannot be input into the pixel unit 132, thereby not charging the pixel unit 132; it should be noted that the display panel 100 can be a liquid crystal display (LCD) or an OLED (Organic Light-Emitting Diode) display; when the display panel 100 is a liquid crystal display, the pixel unit 132 includes liquid crystal molecules; when the display panel 100 is an OLED display, the pixel unit 132 includes a light-emitting diode.

[0038] like Figure 1 As shown, the control unit 131 includes a first control terminal K1, a second control terminal K2, an input terminal Vi and an output terminal Vo; the first control terminal K1 of the 2n-1th row control unit 131 and the first control terminal K1 of the 2nth row control unit 131 are respectively connected to the nth row scan line 110, the second control terminal K2 of the mth column control unit 131 is connected to the mth column data line 120, and the input terminal Vi of the mth column control unit 131 is also connected to the mth column data line 120; the output terminal Vo of each control unit 131 is connected to the input terminal of the corresponding pixel unit 132.

[0039] It should be noted that n and m in this embodiment are variables, N and M are constants, the value range of variable n is 1 to N, the value range of variable m is 1 to M, and N and M are both positive integers greater than 1; in addition, the control units 131 of two adjacent rows in this embodiment are connected to the corresponding same scan line 110, the adjacent two rows refer to the 2n-1th row and the 2nth row, and the corresponding same scan line 110 refers to the nth row scan line 110.

[0040] For example, when n=1, the first control terminals K1 of the first row control unit 131 and the second row control unit 131 are both connected to the first row scan line 110 .

[0041] When m=1, the second control terminal and input terminal of the mth column control unit are both connected to the mth column data line, which means: the second control terminal K2 of all control units 131 in the 1st column is connected to the 1st column data line 120, and the input terminal Vi of all control units 131 in the 1st column is also connected to the 1st column data line 120.

[0042] In this embodiment, the on-off states of the m-th column and 2n-row control unit 131 are opposite to those of the m-th column and 2n-1-row control unit 131, so that when the n-th row scan line 110 is turned on, the data signal on the m-th column data line 120 controls either the m-th column and 2n-1-row control unit 131 or the m-th column and 2n-row control unit 131 to be turned on or turned on alternately in time-sharing manner.

[0043] It should be noted that, in this embodiment, the on-off state of the control unit 131 is controlled by the scan line 110 and the data line 120 at the same time through the first control terminal K1 and the second control terminal K2, and the on-off state of the control unit 131 in the mth column and the 2n-1th row is opposite to that of the control unit 131 in the mth column and the 2nth row. Thus, the data signal on the data line 120 in the mth column can control the odd-numbered row control units 131 in the mth column to be in the on state during the on-time period of the scan line 110 in the nth row, and the data signal on the data line 120 in the mth column can control the even-numbered row control units 131 in the mth column to be in the on state during the on-time period of the scan line 110 in the nth row. 31 is in the on state, and the data signal on the data line 120 in the mth column can also control the odd-row control unit 131 in the mth column and the even-row control unit 131 in the mth column to be turned on alternately in a time-sharing manner during the on time period of the scan line 110 in the nth row; wherein the time-sharing alternating conduction includes that the odd-row control unit 131 in the mth column is turned on for a first time length first, and the even-row control unit 131 in the mth column is turned on for a second time length; or the even-row control unit 131 in the mth column is turned on for a first time length first, and the odd-row control unit 131 in the mth column is turned on for a second time length; the sum of the first time length and the second time length is less than or equal to the on time length of the scan line 110 in the nth row.

[0044] Figure 2 FIG. 1 is a schematic structural diagram of a second display panel provided in an embodiment of the present application; FIG. Figure 2 As shown, the display panel 100 includes: N rows of scan lines 110, M columns of data lines 120, and pixel circuits 130 arranged in an array; wherein the number of columns of the pixel circuits 130 is M-1 columns, and the number of rows is 2N rows; that is, the number of columns of the pixel circuits 130 in the display panel 100 is one less than the number of data lines 120, and the number of rows of the pixel circuits 130 is twice that of the scan lines. Figure 2 The scan lines 110 and data lines 120 in FIG. 1 cross but are not connected. Figure 2In the figure, G1, G2 and GN represent the first row scan line, the second row scan line and the Nth row scan line respectively, and S1, S2, S3, S4 and SM represent the first column data line, the second column data line, the third column data line, the fourth column data line and the Mth column data line respectively.

[0045] like Figure 2 As shown, the control unit 131 includes a first control terminal K1, a second control terminal K2, an input terminal Vi and an output terminal Vo; the first control terminal K1 of the 2n-1th row control unit 131 and the first control terminal K1 of the 2n-row control unit 131 are respectively connected to the n-th row scan line 110, the second control terminal K2 of the m-1th column 2n-row control unit 131 and the second control terminal K2 of the m-th column 2n-1th row control unit 131 are respectively connected to the m-th column data line 120, the input terminal Vi of the m-1th column 2n-row control unit 131 and the input terminal Vi of the m-th column 2n-1th row control unit 131 are respectively connected to the m-th column data line 120; the output terminal Vo of each control unit 131 is connected to the input terminal of the corresponding pixel unit 132.

[0046] It should be noted that, in this embodiment, the value range of the variable m is 2 to M-1. When m=2, the second control terminal K2 of the control unit 131 of the m-1th column and the 2n-1th row and the second control terminal K2 of the control unit 131 of the m-th column and the 2n-1th row are respectively connected to the data line 120 of the m-th column, indicating that the second control terminal K2 of the even-row control unit 131 in the 1st column and the second control terminal K2 of the odd-row control unit 131 in the 2nd column are both connected to the data line 120 of the 1st column; the input terminal Vi of the control unit 131 of the m-1th column and the input terminal Vi of the control unit 131 of the m-1th row and the input terminal Vi of the control unit 131 of the m-th column and the 2n-1th row are respectively connected to the data line 120 of the m-th column, indicating that the input terminal Vi of the even-row control unit 131 in the 1st column and the input terminal Vi of the odd-row control unit 131 in the 2nd column are also both connected to the data line 120 of the 1st column.

[0047] In this embodiment, the on-off states of the m-1th column and 2nth row control unit 131 are opposite to those of the m-1th column and 2n-1th row control unit 131, so that when the n-th row scan line 110 is turned on, the data signal on the m-th column data line 120 controls either the m-1th column and 2n-1th row control unit 131 or the m-1th column and 2nth row control unit 131 to be turned on or turned on alternately in time.

[0048] It should be noted that, in this embodiment, the on-off state of the control unit 131 is controlled by the scan line 110 and the data line 120 at the same time through the first control terminal K1 and the second control terminal K2, and the on-off state of the control unit 131 in the m-1th column and the 2nth row is opposite to that of the control unit 131 in the m-1th column and the 2n-1th row. Thus, the data signal on the data line 120 in the m-th column can control the odd-numbered row control units 131 in the m-th column to be in the on state during the on-time period of the scan line 110 in the nth row, and the data signal on the data line 120 in the m-th column can control the even-numbered row control units 131 in the m-1th column to be in the on state during the on-time period of the scan line 110 in the nth row. 1 is in the on state, and the data signal on the data line 120 in the mth column can also control the odd-row control unit 131 in the mth column and the even-row control unit 131 in the m-1th column to be turned on alternately in a time-sharing manner during the on time period of the scan line 110 in the nth row; wherein the time-sharing alternating conduction includes that the odd-row control unit 131 in the mth column is turned on for a first time length, and the even-row control unit 131 in the m-1th column is turned on for a second time length; or the even-row control unit 131 in the m-1th column is turned on for a first time length, and the odd-row control unit 131 in the mth column is turned on for a second time length; and the sum of the first time length and the second time length is less than or equal to the on time length of the scan line 110 in the nth row.

[0049] In addition, Figure 2 In the embodiment, the second control terminal K2 and the input terminal Vi of the control unit 131 of the 2n-1th row of the 1st column are respectively connected to the data line 120 of the 1st column, and the second control terminal K2 and the input terminal Vi of the control unit 131 of the 2nth row of the M-1th column are respectively connected to the data line 120 of the Mth column; it should be noted that since the value range of m in the above embodiment is 2 to M-1, that is, the data line 120 of the 2nd column to the data line 120 of the M-1th column are all connected to the control units 131 in the two adjacent columns, but the data line 120 of the first column is 20 and the last column data line 120 are special. Based on this, the second control terminal K2 of the odd-row control unit 131 in the first column pixel circuit 130 and the input terminal Vi of the odd-row control unit 131 in the first column pixel circuit 130 are both connected to the first column data line 120, and the second control terminal K2 of the even-row control unit 131 in the last column pixel circuit 130 and the input terminal Vi of the even-row control unit 131 in the last column pixel circuit 130 are both connected to the last column data line 120.

[0050] In summary, the display panel provided in this embodiment has at least the following beneficial effects:

[0051] 1. In this application, two adjacent rows of pixel circuits share a scan line, and the pixel circuits connected to the same scan line are controlled by data lines so as not to be turned on at the same time. Under the display conditions of the same resolution, the number of scan lines is reduced by half, so that the RC loading on the scan line is also reduced, thereby reducing the power consumption of the display panel.

[0052] 2. This application reduces the number of scan lines by half, which not only reduces the production cost of the display panel, but also increases the refresh rate and aperture rate of the panel, thereby improving the market competitiveness of the product.

[0053] 3. Since the RC loading value of the display panel is proportional to the noise value, this application can reduce the panel noise and improve display accuracy while reducing the panel RC loading.

[0054] Figure 3 FIG. 1 is a circuit diagram of a first pixel circuit provided in an embodiment of the present application; FIG. Figure 2 As shown, the control unit 131 includes: a first switch tube T1 and a second switch tube T2; the control end of the first switch tube T1 is connected to the data line 120, and the first end of the first switch tube T1 is connected to the scan line 110; the control end of the second switch tube T2 is connected to the second end of the first switch tube T1, the first end of the second switch tube T2 is connected to the data line 120, and the second end of the second switch tube T2 is connected to the pixel unit 132.

[0055] Figure 3 3a is a circuit diagram in which the second control terminal and the input terminal of the m-th column control unit are both connected to the m-th column data line. In this embodiment, the turn-on voltage of the first switch tube T1 of the m-th column and 2n-1-th row control unit 131 is opposite to that of the first switch tube T1 of the m-th column and 2n-th row control unit 131. It should be noted that the turn-on voltages of the first switch tube T1 of the control unit 131 in the mth column and the 2n-1th row are opposite to those of the first switch tube T1 of the control unit 131 in the mth column and the 2nth row, indicating that the types of the first switch tubes T1 of the two control units 131 are different, that is, when the first switch tube T1 of the control unit 131 in the mth column and the 2n-1th row is a P-type MOS tube, the first switch tube T1 of the control unit 131 in the mth column and the 2nth row is an N-type MOS tube; optionally, when the first switch tube T1 of the control unit 131 in the mth column and the 2n-1th row is an N-type MOS tube, the first switch tube T1 of the control unit 131 in the mth column and the 2nth row is a P-type MOS tube, so that the data signal at the same time can control one of the two control units 131 to be in the on state, thereby preventing the problem of two rows of pixel circuits being charged at the same time.

[0056] Figure 33b in the figure represents a circuit schematic diagram in which the second control terminal and input terminal of the control unit of the even row in the m-1th column and the second control terminal and input terminal of the control unit of the odd row in the mth column are connected to the data line in the mth column. In this embodiment, the turn-on voltage of the first switch tube T1 of the control unit 131 of the m-1th column and the 2n-1th row is opposite to that of the first switch tube T1 of the control unit 131 of the m-1th column and the 2n-1th row. It should be noted that the turn-on voltages of the first switch tube T1 of the control unit 131 in the m-1th column and the 2nth row are opposite to those of the first switch tube T1 of the control unit 131 in the m-1th column and the 2nth row, indicating that the types of the first switch tubes T1 of the two control units 131 are different, that is, when the first switch tube T1 of the control unit 131 in the m-1th column and the 2nth row is a P-type MOS tube, the first switch tube T1 of the control unit 131 in the m-1th column and the 2nth row is an N-type MOS tube; optionally, when the first switch tube T1 of the control unit 131 in the m-1th column and the 2nth row is an N-type MOS tube, the first switch tube T1 of the control unit 131 in the m-1th column and the 2nth row is a P-type MOS tube, so that the data signal at the same time can control one of the two control units 131 to be in the on state, thereby preventing the problem of two rows of pixel circuits 130 being charged at the same time.

[0057] It can be seen that the specific working principle of the control unit 131 in this embodiment is as follows: taking the case where the first switch tube T1 is a P-type MOS tube and the second switch tube T2 is an N-type MOS tube as an example, when the data signal output by the data line 120 of the mth column is low and the scan line 110 of the nth row outputs a high level, the first switch tube T1 is turned on, and the high level on the scan line 110 of the nth row turns on the second switch tube T2, so that the data signal output by the data line 120 of the mth column charges the pixel unit 132; on the contrary, when the data signal output by the data line 120 of the mth column is high, the first switch tube T1 is turned off, regardless of the data signal output by the scan line 110 of the nth row 0 outputs a high level or a low level, the second switch tube T2 cannot be turned on, and thus the pixel unit 132 cannot be charged. In addition, when the m-th column data line 120 outputs a low level, the first switch tube T1 is turned on, but the n-th row scan line 110 outputs a low level, the second switch tube T2 cannot be turned on. Therefore, it can be seen that the switching states of the first switch tube T1 and the second switch tube T2 affect the on-off state of the control unit 131, that is, when both the first switch tube T1 and the second switch tube T2 are turned on, the control unit 131 is in the on state; when at least one of the first switch tube T1 and the second switch tube T2 is turned off, the control unit 131 is in the off state.

[0058] It is also worth noting that the switch tube formed by a-Si (amorphous silicon) can have a conduction (opening) voltage of about 0.2V. For the lowest grayscale display, the data voltage provided by the data line 120 is generally not 0V, but about 0.3V. Therefore, the first switch tube T1 can also be turned on for the lowest grayscale display. The scan line 110 provides a voltage of about 20V, causing the first switch tube T1 to enter the saturation region. The voltage of the scan line 110 is applied to the gate of the second switch tube T2 through the first switch tube T1, thereby controlling the second switch tube T2 to turn on.

[0059] Furthermore, the grayscale voltage above the lowest grayscale display is generally 0.5V, and any higher grayscale voltage is sufficient to activate the first switch T1. Furthermore, combined with the voltage provided by the scan line 110, the first switch T1 can operate in a saturation region. Therefore, when no data voltage is provided, the voltage on the data line 120 can remain at 0V.

[0060] Figure 4 FIG2 is a circuit diagram of a second pixel circuit provided by an embodiment of the present application. In the pixel circuit 130 at the 1st column, 2n-1th row and the M-1th column, 2nth row, the control unit 131 is configured to: Figure 3 b further includes: a third switch tube T3, a control end of the third switch tube T3 is connected to the data line 120, a first end of the third switch tube T3 is connected to the scan line 110, and a second end of the third switch tube T3 is connected to the control end of the second switch tube T2; wherein the turn-on voltages of the third switch tube T3 and the first switch tube T1 are opposite.

[0061] In this embodiment, the control unit 131 in the 2n-1th row of the 1st column and the control unit 131 in the 2nth row of the M-1th column have an additional third switch tube T3 compared to other control units 131. However, the turn-on voltage of the third switch tube T3 is opposite to the turn-on voltage of the first switch tube T1. That is, a data signal of any polarity output on the data line 120 in the 1st column can charge the pixel unit 132 in the 2n-1th row of the 1st column. Correspondingly, a data signal of any polarity output on the data line 120 in the M-1th column can charge the pixel unit 132 in the 2nth row of the M-1th column, thereby improving the display effect.

[0062] In one embodiment of the present application, Figure 3 and 4As shown, the pixel unit 132 includes: a storage capacitor Cc, a driving transistor T0 and a light-emitting diode OLED, wherein the first end of the storage capacitor Cc is connected to the output end Vo of the control unit 131, and the second end of the storage capacitor Cc is connected to the power supply end VDD; the control end of the driving transistor T0 is connected to the first end of the storage capacitor Cc, and the first end of the driving transistor T0 is connected to the second end of the storage capacitor Cc; the anode of the light-emitting diode OLED is connected to the second end of the driving transistor T0, and the cathode of the light-emitting diode OLED is grounded VSS.

[0063] In this embodiment, when the control unit 131 is in the on state, the storage capacitor Cc is charged by the data signal on the data line 120, and under the action of the driving voltage output by the power supply end, the driving transistor T0 outputs a corresponding driving current to drive the light emitting diode OLED to emit light.

[0064] Figure 5 FIG. 1 is a circuit diagram of a third pixel circuit provided in an embodiment of the present application. Figure 5 As shown, the pixel unit 132 includes a liquid crystal capacitor Cs, the pixel electrode of which is connected to the output terminal Vo of the control unit 131. The liquid crystal capacitor Cs is generally formed by a pixel electrode, a common electrode, and liquid crystal molecules between the pixel electrode and the common electrode. Applying data signals of varying magnitude to the pixel electrode causes the liquid crystal molecules to rotate to different angles, thereby adjusting the brightness of the pixel unit 132. In this embodiment, the pixel unit 132 also includes a storage capacitor Ct, the pixel electrode of which is connected to the output terminal Vo of the control unit 131 to maintain the charging voltage.

[0065] Figure 6 FIG. 1 is a flow chart of a display driving method provided by an embodiment of the present application; FIG. Figure 6 As shown, the display driving method applied to the display panel of the above embodiment specifically includes the following steps:

[0066] Step S100: Acquire a first target conduction polarity corresponding to a first control terminal of each control unit in a display panel and a second target conduction polarity corresponding to a second control terminal of each control unit.

[0067] In this embodiment, the first target conduction polarity represents the voltage polarity that turns on the second switch, and the second target conduction polarity represents the voltage polarity that turns on the first switch. If the second switch is a PMOS transistor, the corresponding first target conduction polarity is negative; if the first switch is an NMOS transistor, the corresponding second target conduction polarity is positive. The first target conduction polarity corresponding to the first control terminal and the second target conduction polarity corresponding to the second control terminal can be obtained based on the transistor types of the first and second switches in each control unit.

[0068] Step S200: Generate a corresponding scan signal on each row of the scan line and a corresponding data signal on each column of the data line according to all the first target conduction polarities, all the second target conduction polarities and the display image of the current frame, so that when the scan line of the nth row is turned on, the data signal on the data line of the mth column controls any one of the control unit of the mth column and the 2n-1 row and the control unit of the mth column and the 2n-1 row to be turned on or turned on alternately in time-sharing, or the data signal on the data line of the mth column controls any one of the control unit of the mth column and the 2n-1 row and the m-1 row and the 2n-1 row to be turned on or turned on alternately in time-sharing.

[0069] It should be noted that, by obtaining the target conduction polarity of any one of the control unit in the mth column and the 2n-1th row and the control unit in the mth column and the 2nth row in step S200, the target conduction polarity corresponding to the other control unit can be calculated, that is, based on at least one target conduction polarity obtained in step S200, the target conduction polarity corresponding to all control units in the display panel can be obtained; then, based on the display image of the current frame, the generated data signal can charge half or all of the pixel units in the display panel.

[0070] In this embodiment, the display image of the current frame includes but is not limited to all pixel units being fully lit, two adjacent rows of pixel units being half lit, and two adjacent columns of pixel units being half lit. In this embodiment, N=2, M=3 are used as an example to illustrate multiple display images:

[0071] (1) Case 1: When all pixel units are fully lit in the current frame display: During the period when the nth row scan line is on in the current frame, each column of data line alternately outputs the corresponding first data signal and second data signal. The polarities of the first data signal and the second data signal are opposite. The waveforms output by G1 and S1 are as follows: Figure 7 As shown in 7a, the fully lit display screen is as follows Figure 7 As shown in 7b in FIG, the waveforms of S2 and S3 are similar to those of S1 and will not be described in detail here.

[0072] (2) Case 2: When the display image of the current frame is half-lit for two adjacent rows of pixel units: during the period when the n-th row scan line of the current frame is on, each column of data line outputs a corresponding first data signal; during the period when the n-th row scan line of the next frame is on, each column of data line outputs a corresponding second data signal; wherein, the first scan signal of the current frame can be a high level or a low level, and the polarity of the first scan signal is determined according to the conduction polarity of the second switch tube; the waveforms output by G1 and S1 are as follows: Figure 8 As shown in 8a, the display image of two adjacent rows of pixel units with half of them lit is as follows Figure 88b in the figure; in addition, in the display picture of the next frame, the two adjacent rows of pixel units light up the other half symmetrically; in this case, by outputting different scanning signals in the current frame and the next frame through the data line, it is possible to charge only the odd-numbered rows of pixel units in the current frame and only the even-numbered rows of pixel units in the next frame. Based on the full-bright display picture in case 1, the power consumption can be further reduced by half or the refresh rate can be doubled; in addition, the interlaced display of two adjacent frames can also prevent screen crosstalk.

[0073] (3) Case 3: When the display image of the current frame is half-lit for two adjacent columns of pixel units: during the period of time when the nth row of scan lines is turned on, the odd-numbered or even-numbered column data lines output the corresponding first data signal and second data signal; the waveforms output by G1, S1, S2 and S3 are as follows: Figure 9 As shown in 9a, the display image of two adjacent columns of pixel units with half of them lit is as follows Figure 9 As shown in 9b; in addition, in the display of the next frame, the two adjacent columns of pixel units light up the other half symmetrically; in this case, the power consumption can be reduced by half, all data lines can be charged at the same time to save scanning time, and the interlaced display of the upper and lower frames can prevent screen crosstalk.

[0074] Therefore, the display panel driving method provided in the present application can drive different screens for the same pixel architecture according to the application scenario, thereby improving the compatibility and diversity of the display panel.

[0075] In one embodiment of the present application, the pixel unit in the 3i+1th column is a first color sub-pixel, the pixel unit in the 3i+2th column is a second color sub-pixel, and the pixel unit in the 3i+3th column is a third color sub-pixel; wherein, i = [0, 1, 2, ..., I], when M is a multiple of 3 otherwise express The result is rounded down; it should be noted that, when i=0, the pixel units in the first column are first color sub-pixels, the pixel units in the second column are second color sub-pixels, the pixel units in the third column are third color sub-pixels, and so on. The first color sub-pixels, the second color sub-pixels, and the third color sub-pixels are arranged in column intervals; the first color sub-pixels, the second color sub-pixels, and the third color sub-pixels can be red sub-pixels, green sub-pixels, and blue sub-pixels, respectively; Figure 7-9 As shown, the first color sub-pixel, the second color sub-pixel and the third color sub-pixel may also be a blue sub-pixel, a green sub-pixel and a red sub-pixel respectively; in addition, The result of rounding down means taking the integer part of 2M divided by 3. For example, when M=7, then

[0076] In one embodiment of the present application, the pixel units in the 3j+1th row are first color sub-pixels, the pixel units in the 3j+2th row are second color sub-pixels, and the pixel units in the 3j+3th row are third color sub-pixels; wherein j = [0, 1, 2, ..., J], when 2N is a multiple of 3 otherwise express The result of is rounded down; The result of rounding down means taking the integer part of N divided by 3. For example, when N=7, then It should be noted that when j=0, the pixel units in the first row are all first color sub-pixels, the pixel units in the second row are all second color sub-pixels, the pixel units in the third row are all third color sub-pixels, and so on. The first color sub-pixels, the second color sub-pixels, and the third color sub-pixels are arranged at intervals of rows; Figure 10 As shown, the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel may be a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively.

[0077] In this application, a single scan line can simultaneously control the charging of two rows of pixel units, reducing the number of scan lines by half, lowering the RC loading of the scan lines and solving the problem of high power consumption of the display panel. Furthermore, by combining a driving method that lights up half of the pixel units in one frame and the other half in the next frame, the power consumption of the display panel can be further reduced. The panel driving method provided in this embodiment can be applied to liquid crystal displays and organic light-emitting diode (OLED) displays, improving the market competitiveness of these products.

[0078] In one embodiment, the present application provides a display device, which includes: a gate driving circuit, a gate driving circuit and a display panel shown in the above embodiment; the gate driving circuit is used to output a scanning signal; the source driving circuit is used to output a data signal; the scanning line of the display panel is connected to the gate driving circuit, and the data line of the display panel is connected to the source driving circuit.

[0079] Furthermore, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature specified as "first," "second," or "third" may explicitly or implicitly include one or more of the features. In the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0080] In the description of this specification, the reference terms "some embodiments", "exemplarily", etc. mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0081] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application. Therefore, any changes or modifications made in accordance with the claims and description of the present application should fall within the scope of the patent application.

Claims

1. A display panel, characterized in that: The display panel includes: N rows of scan lines, M columns of data lines, and pixel circuits arranged in an array; each pixel circuit includes a pixel unit and a control unit, the control unit being configured to charge the pixel unit via a data signal on the data line when in an on state; The control unit includes a first control terminal, a second control terminal, an input terminal and an output terminal; the first control terminal of the 2n-1th row control unit and the first control terminal of the 2nth row control unit are respectively connected to the nth row scan line; The second control terminal and input terminal of the control unit in the mth column are both connected to the data line in the mth column, or the second control terminal and input terminal of the control unit in the m-1th even row column and the second control terminal and input terminal of the control unit in the mth odd row column are both connected to the data line in the mth column; the output terminal of each control unit is connected to the input terminal of the corresponding pixel unit; When the scan line in the nth row is turned on: the data signal on the data line in the mth column controls either the control unit in the mth column and the 2n-1th row or the control unit in the mth column and the 2nth row to be turned on or turned on alternately in time-sharing mode, or the data signal on the data line in the mth column controls either the control unit in the mth column and the 2n-1th row or the control unit in the m-1th column and the 2nth row to be turned on or turned on alternately in time-sharing mode; wherein n=[1, ..., N], m=[1, ..., M], and N and M are both positive integers greater than 1; Wherein, the control unit includes: a first switch tube, wherein a control end of the first switch tube is connected to the data line, and a first end of the first switch tube is connected to the scan line; a second switch tube, wherein a control end of the second switch tube is connected to the second end of the first switch tube, a first end of the second switch tube is connected to the data line, and a second end of the second switch tube is connected to the pixel unit; When the second control terminal and the input terminal of the control unit in the mth column are both connected to the data line in the mth column, the turn-on voltage of the first switch tube of the control unit in the mth column and the 2n-1th row is opposite to that of the first switch tube of the control unit in the mth column and the 2nth row; When the second control end and input end of the control unit of the even row of the m-1th column and the second control end and input end of the control unit of the odd row of the mth column are both connected to the data line of the mth column, the turn-on voltage of the first switch tube of the control unit of the 2nth row of the m-1th column is opposite to that of the first switch tube of the control unit of the 2n-1th row of the mth column.

2. The display panel according to claim 1, wherein: When the second control terminal and the input terminal of the control unit of the even row in the m-1th column and the second control terminal and the input terminal of the control unit of the odd row in the mth column are both connected to the data line in the mth column, in the pixel circuits in the 2n-1th row in the 1st column and the 2nth row in the M-1th column, the control unit further includes: a third switch tube, wherein a control end of the third switch tube is connected to the data line, a first end of the third switch tube is connected to the scan line, and a second end of the third switch tube is connected to the control end of the second switch tube; The turn-on voltages of the third switch tube and the first switch tube are opposite.

3. The display panel according to claim 1, wherein: The pixel unit in the 3i+1th column is a first color sub-pixel, the pixel unit in the 3i+2th column is a second color sub-pixel, and the pixel unit in the 3i+3rd column is a third color sub-pixel; wherein, , when M is a multiple of 3, I= -1, otherwise I= .

4. The display panel according to claim 1, wherein: The pixel units in the 3j+1th row are first color sub-pixels, the pixel units in the 3j+2th row are second color sub-pixels, and the pixel units in the 3j+3th row are third color sub-pixels; wherein, , when 2N is a multiple of 3 = -1, otherwise = .

5. The display panel according to any one of claims 1 to 4, characterized in that: The pixel unit includes a liquid crystal capacitor, and a pixel electrode of the liquid crystal capacitor is connected to an output end of the control unit.

6. The display panel according to any one of claims 1 to 4, characterized in that: The pixel unit includes: a storage capacitor, wherein a first end of the storage capacitor is connected to the output end of the control unit, and a second end of the storage capacitor is connected to the power supply end; a driving transistor, wherein a control terminal of the driving transistor is connected to the first terminal of the storage capacitor, and the first terminal of the driving transistor is connected to the second terminal of the storage capacitor; A light emitting diode, wherein an anode of the light emitting diode is connected to the second end of the driving transistor, and a cathode of the light emitting diode is grounded.

7. The display panel according to claim 1, wherein: Each column of data lines outputs a corresponding first data signal during an on-time period of the n-th row of scan lines in a current frame, and each column of data lines outputs a corresponding second data signal during an on-time period of the n-th row of scan lines in a next frame; Or, during the on-time period of the nth row of scan lines in the current frame, each column of data lines alternately outputs the corresponding first data signal and second data signal; Or, during the on-time period of the nth row of scan lines in the current frame, the odd-numbered columns or even-numbered columns of data lines output corresponding first data signals and second data signals; The polarities of the first data signal and the second data signal are opposite.

8. A display driving method, characterized in that: Applied to the display panel according to any one of claims 1 to 7, the display driving method comprises: Acquire a first target conduction polarity corresponding to a first control terminal of each control unit in the display panel and a second target conduction polarity corresponding to a second control terminal of each control unit; According to all the first target conduction polarities, all the second target conduction polarities and the display picture of the current frame, the corresponding scan signal on each row of the scan line and the corresponding data signal on each column of the data line are generated, so that when the n-th row of the scan line is turned on, the data signal on the m-th column of the data line controls any one of the m-th column and the 2n-1-row control unit and the m-th column and the 2n-row control unit to be turned on or turned on alternately in time-sharing, or the data signal on the m-th column of the data line controls any one of the m-th column and the 2n-1-row control unit and the m-1-th column and the 2n-row control unit to be turned on or turned on alternately in time-sharing.

9. A display device, characterized in that: The display device comprises: A gate driving circuit for outputting a scanning signal; A source driving circuit, configured to output a data signal; The display panel according to any one of claims 1 to 7, wherein the scan lines of the display panel are connected to the gate drive circuit, and the data lines of the display panel are connected to the source drive circuit.

Images