Drive circuit, display device, in-cell touch panel device, and control device

Abstract

Provided are a drive circuit, a display device, an in-cell touch panel device, and a control device for a drive circuit, with which it is possible to arbitrarily set, by means of a latch circuit, whether or not the operation of the drive circuit is stopped. A gate drive circuit (20) includes a plurality of unit circuits (21), a latch circuit (22), and a connection circuit (23). The latch circuit (22) is connected in parallel to the plurality of unit circuits (21). When a TPC signal is input, the connection circuit (23) resets the unit circuits (21) constituting the nth stage and the (n + 1) th stage, and stops the operation of the gate drive circuit (20). When an RSM signal is input, the latch circuit charges a node (N1) of the n + 1-stage unit circuit (21) via a transistor (T5) of the connection circuit (23), and restarts the operation of the gate drive circuit (20).

Description

Technical Field

[0001] The present disclosure relates to a driving circuit, a display device, an embedded touch panel device, and a control device for the driving circuit. Background Art

[0002] Patent document 1 discloses a driving circuit capable of stopping operation in the middle of scanning. The driving circuit (shift register) includes a plurality of unit circuits constituting a plurality of stages respectively. The plurality of unit circuits include: a first unit circuit that outputs a shift pulse to a gate bus and a subsequent stage; and a second unit circuit that outputs a shift pulse to a subsequent stage. The second unit circuit includes a transistor having a first electrode connected to a subsequent stage and an internal node connected to a control electrode of the transistor. The potential of the internal node is maintained at a high level during the period when the operation of the driving circuit is stopped. Then, at a moment slightly before the moment when the operation of the driving circuit is to be restarted, the level of the signal supplied to the second electrode of the transistor becomes a high level. Thus, by the transistor being turned on by the internal node maintaining a high level, a shift pulse is output to the subsequent stage, and the operation of the driving circuit is restarted. Prior art literature Patent Literature

[0003] Patent Document 1: International Publication No. 2017 / 006815 Summary of the invention Problem that the invention aims to solve

[0004] In the driving circuit described in Patent Document 1, the first unit circuit and the second unit circuit (latch circuit) are connected in series, and the latch circuit constitutes a part of a plurality of stages. Therefore, in the conventional driving circuit, the operation is necessarily stopped in the latch circuit, and therefore the presence or absence of the stop of the operation of the driving circuit cannot be arbitrarily set by the latch circuit.

[0005] Therefore, the present disclosure is made to solve the above-mentioned problems, and its purpose is to provide a drive circuit, a display device, an in-cell touch panel device, and a control device for the drive circuit, which can arbitrarily set whether to stop the operation of the drive circuit by a latch circuit. Solutions to the problem

[0006] In order to solve the above-mentioned problem, the driving circuit involved in the first mode of the present disclosure is composed of multiple stages, and in response to multiple clock signals being input, a driving signal is supplied to a scanning signal line group. The driving circuit includes: multiple unit circuits, which constitute each stage of the multiple stages and output the driving signal; a latch circuit, which is arranged in parallel with the multiple unit circuits; and a connecting circuit, which is connected to the output node of the latch circuit, the latch circuit is input with a first output signal from a first unit circuit as a first set signal, the first unit circuit constitutes the first stage of the multiple unit circuits, and after the latch circuit is input with the first set signal, the operation of the driving circuit is restarted. When a first control signal is input, a latch circuit output signal is output to the connection circuit via the output node, the latch circuit is input with a second output signal from a second unit circuit as a first reset signal, the second unit circuit constitutes a second stage of the plurality of unit circuits that is later than the first stage, the connection circuit comprises: a reset circuit, which resets the first unit circuit and a third unit circuit in response to a second control signal that stops the operation of the drive circuit, the third unit circuit constituting a next stage of the first stage of the plurality of unit circuits; and a set circuit, which supplies the latch circuit output signal as a second set signal to the third unit circuit.

[0007] A display device according to a second aspect includes: the driving circuit according to the first aspect; and a display including the scanning signal line group.

[0008] An in-cell touch panel device according to a third aspect includes: the driving circuit according to the first aspect; and an in-cell touch panel provided with the scanning signal line group, and detecting a touch by a pointer during a period in which the driving circuit stops operating.

[0009] The control device of the driving circuit involved in the third embodiment is a control device that supplies the multiple clock signals, the first control signal and the second control signal to the driving circuit involved in the above-mentioned first embodiment. The driving circuit includes: multiple latch circuits, which are arranged in parallel with the multiple unit circuits; and multiple connection circuits, which are respectively connected to the output nodes of the multiple latch circuits. In the control device of the driving circuit, an action connection circuit that performs an action is determined from the multiple connection circuits, and the second control signal is not supplied to the connection circuits other than the action connection circuit among the multiple connection circuits, but the second control signal is supplied to the action connection circuit. Effects of the Invention

[0010] According to the above configuration, since the latch circuit is connected in parallel with respect to the plurality of unit circuits, if the second control signal for stopping the operation of the drive circuit is not supplied to the drive circuit, the operation of the drive circuit is not stopped in the latch circuit and the operation of the drive circuit can be continued. In addition, if the second control signal is supplied to the drive circuit, the operation of the drive circuit can be stopped, and if the first control signal is supplied to the drive circuit, the operation of the drive circuit can be restarted. As a result, the presence or absence of stopping the operation of the drive circuit can be arbitrarily set by the latch circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a block diagram showing the configuration of the display device 100 according to the first embodiment. Figure 2 2 is a schematic circuit diagram showing the configuration of the display unit 10 . Figure 3 2 is a diagram showing the structure of the touch panel 1 . Figure 4 2 is a diagram showing a partial configuration of the gate drive circuit 20 . Figure 5 2 is a circuit diagram of the unit circuits 21 constituting the stages other than the n-th stage and the (n+1)-th stage. Figure 6 is a circuit diagram showing a part of the n-th unit circuit 21 and the connection circuit 23 . Figure 7 is a circuit diagram showing a part of the (n+1)th unit circuit 21 and the connecting circuit 23 . Figure 8 2 is a circuit diagram showing the configuration of the latch circuit 22 . Fig. 9 2 is a timing chart of each signal in the gate driving circuit 20 based on the endless driving. Fig.10 It is a timing chart of each signal in the gate driving circuit 20 based on the pause driving. Fig.11 This is a block diagram of a display device 200 according to the second embodiment. Fig.12 It is a diagram showing the configuration of a gate driving circuit 220 of a display device 200 according to the second embodiment. Fig.13 This is a timing chart when the gate driving circuit 220 according to the second embodiment performs non-pause driving. Fig.14 This is a timing chart when the gate driving circuit 220 according to the second embodiment performs pause driving. Fig.15 This is a timing chart of a display device according to a modification of the second embodiment. Fig.16 This is a block diagram of a display device 300 according to the third embodiment. Fig.17 It is a diagram showing the configuration of a gate driving circuit 320 of a display device 300 according to the third embodiment. Fig.18 This is a timing chart related to the operation of the circuit other than the operation circuit according to the third embodiment. Fig.19 This is a timing chart related to the operation of the operation circuit according to the third embodiment. DETAILED DESCRIPTION

[0012] Hereinafter, the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The same reference numerals are given to the parts that are the same as or equivalent to those in the drawings, and their descriptions will not be repeated. In addition, in the drawings referred to below, in order to make the description easier to understand, the configuration is simplified or schematically shown, or some components are omitted. In addition, the size ratios between the components shown in the drawings do not necessarily represent the actual size ratios.

[0013] [First embodiment] (Overall Structure of Display Device) The configuration of the display device 100 according to the first embodiment will be described. Figure 1 It is a block diagram showing the configuration of the display device 100 according to the first embodiment. Figure 2 2 is a schematic circuit diagram showing the configuration of the display unit 10 . Figure 3 2 is a diagram showing the structure of the touch panel 1 .

[0014] like Figure 1 As shown, the display device 100 includes a touch panel 1 and a control circuit 2. In the first embodiment, the touch panel 1 is configured as an embedded touch panel that realizes a touch detection function and an image display function. That is, the touch panel 1 also serves as a display. In addition, in the first embodiment, the display device 100 is an embedded touch panel device.

[0015] The control circuit 2 includes a processor that performs control processing of the display device 100. Furthermore, the control circuit 2 sends a control signal to the touch panel 1 based on the input image signal. The touch panel 1 displays an image based on the control signal. In addition, the control circuit 2 sends an instruction to perform touch detection to the touch panel 1, and receives information indicating the touch coordinates of the indicator from the touch panel 1 (hereinafter referred to as "touch detection processing"). In addition, within one frame period, the control circuit 2 time-shares the display processing for causing the gate drive circuit 20 to perform an action and the touch detection processing. That is, one frame period includes a touch detection period TP (refer to Fig.10) and a display period TD (refer to Figure 7 ). The control circuit 2 performs multiple touch detection processes in one frame period, for example. In addition, during the touch detection process, the operation of the gate drive circuit 20 is suspended. In addition, the suspension period TR (refer to Fig.10 ) includes the touch detection period TP.

[0016] In the first embodiment, the control circuit 2 is configured to execute the state in which the operation of the gate drive circuit 20 is not suspended (see Fig. 9 ) and the state of the pause period TR in which the operation of the gate drive circuit 20 is paused in one frame period (refer to Fig.10 ) is switched. For example, when the touch panel 1 is used as a display without a touch detection function, the control circuit 2 performs control in a state where the operation of the gate drive circuit 20 is not suspended (hereinafter referred to as "non-suspended drive"); when the touch detection function of the touch panel 1 is used, the control circuit 2 performs control in a state where the operation of the gate drive circuit 20 is suspended during the suspension period TR in one frame period (hereinafter referred to as "suspended drive").

[0017] like Figure 1 As shown, the touch panel 1 includes a display unit 10, a gate drive circuit 20, a source drive circuit 30, and a touch detection control circuit 40. Figure 1 , the gate drive circuit 20, the source drive circuit 30, and the touch detection control circuit 40 are illustrated as being provided in the touch panel 1, but at least one of the gate drive circuit 20, the source drive circuit 30, and the touch detection control circuit 40 may be provided on another substrate disposed outside the touch panel 1. In this case, at least one of the touch panel 1, the gate drive circuit 20, the source drive circuit 30, and the touch detection control circuit 40 is connected via wiring or a flexible printed substrate.

[0018] like Figure 2 As shown, the display unit 10 includes a plurality of gate lines 11, a plurality of source lines 12, a plurality of transistors 13, a plurality of pixel electrodes 14, and a plurality of common electrodes 15. The plurality of gate lines 11 intersect with the plurality of source lines 12 when viewed from above. Furthermore, transistors 13 and pixel electrodes 14 are arranged in each region divided by the plurality of gate lines 11 and the plurality of source lines 12. Furthermore, the transistor 13 includes a gate electrode 13a, a source electrode 13b, and a drain electrode 13c. The gate electrode 13a is connected to the gate line 11. In addition, the source electrode 13b is connected to the source line 12. The drain electrode 13c is connected to the pixel electrode 14. The plurality of gate lines 11 is an example of a scanning signal line group. In addition, in Figure 2, an example in which the gate driving circuit 20 is arranged on one side of the display unit 10 is shown, but the gate driving circuits 20 may be arranged on both sides of the display unit 10 .

[0019] The gate drive circuit 20 is formed on the substrate of the touch panel 1 (formed as a single chip). The gate drive circuit 20 outputs gate signals to the plurality of gate lines 11 in sequence. The source drive circuit 30 is mounted on the substrate of the touch panel 1. The source drive circuit 30 receives the image signal and the source control signal output from the control circuit 2, and generates a source signal (data signal) based on the image signal and the source control signal. Then, the source drive circuit 30 supplies a source signal to each of the plurality of source lines 12. The source drive circuit 30 supplies a source signal to each of the plurality of source lines 12. Then, when the gate signal is supplied to the transistor 13 (when it becomes a gate-on voltage), the source signal is written to the pixel electrode 14 via the transistor 13. As a result, an electric field is generated between the pixel electrode 14 and the common electrode 15, driving the liquid crystal layer not shown in the figure, and displaying an image on the touch panel 1.

[0020] like Figure 3 As shown, the plurality of common electrodes 15 are configured, for example, in a matrix shape. The touch detection control circuit 40 is connected to each of the plurality of common electrodes 15 via the wiring 16. The common electrode 15 is capacitively coupled with the indicator, so that the electrostatic capacitance changes. The touch detection control circuit 40 supplies a touch drive signal (pulse signal) to the plurality of common electrodes 15 during the touch detection process (touch detection period TP). The waveform of the pulse signal changes according to the size of the electrostatic capacitance of the common electrode 15. The touch detection control circuit 40 detects a touch (the position of the touch) based on the indicator according to the waveform of the pulse signal from the common electrode 15. That is, the common electrode 15 also serves as a touch detection electrode. The touch panel 1 is a self-capacitance touch panel. In addition, without being limited to this example, the touch panel 1 may also be configured as a mutual capacitance touch panel.

[0021] (Configuration of Gate Drive Circuit 20) Next, refer to Figures 4 to 8 , the structure of the gate driving circuit 20 is described. Figure 4 2 is a diagram showing a partial configuration of the gate drive circuit 20 . Figure 5 2 is a circuit diagram of the unit circuits 21 constituting the stages other than the n-th stage and the (n+1)-th stage. Figure 6 is a circuit diagram showing a part of the n-th unit circuit 21 and the connection circuit 23 . Figure 7 is a circuit diagram showing a part of the (n+1)th unit circuit 21 and the connecting circuit 23 . Figure 8 2 is a circuit diagram showing the configuration of the latch circuit 22 .

[0022] like Figure 4As shown, the gate driving circuit 20 includes a shift register circuit 20a, which is composed of a plurality of stages and supplies gate signals to a plurality of gate lines 11 in response to a plurality of clock signals being input. Figure 4 In the figure, the nth (n is a natural number) level, three levels before the nth level, and four levels after the nth level are shown in the multiple levels. Figure 4 A connection example is shown in which two-phase clock signals (GCK1 signal and GCK2 signal) are input to the shift register circuit 20a.

[0023] <Configuration of Unit Circuit 21> The shift register circuit 20a includes a plurality of unit circuits 21 forming a plurality of stages. Figure 5 As shown, the unit circuit 21 includes transistors T1 to T3 , a capacitor C1 , and a node N1 .

[0024] The gate electrode and drain electrode of the transistor T1 are connected to the terminal S to which the set signal is input. The source electrode of the transistor T1 is connected to the node N1. That is, the transistor T1 is diode-connected to the terminal S and the node N1. Thus, when the set signal is input, the transistor T1 charges the node N1.

[0025] The drain electrode of the transistor T2 is connected to the node N1. The source electrode of the transistor T2 is supplied with a VSS signal having a reference potential (low potential). The gate electrode of the transistor T2 is connected to the terminal R to which the reset signal is input. Thus, when the reset signal is input, the transistor T2 discharges from the node N1.

[0026] The drain electrode of the transistor T3 is connected to the terminal GCK to which the clock signal is input. The gate electrode of the transistor T3 is connected to the node N1. The source electrode of the transistor T3 is connected to the terminal Q to which the output signal (gate signal G) is output. Figure 4 In FIG. 1 , the gate signal output from the unit circuit 21 constituting the n-3th stage is recorded as “Gn-3”.

[0027] The capacitor C1 is connected between the gate electrode of the transistor T3 and the source electrode of the transistor T3. The capacitor C1 accumulates charge when the node N1 is charged. The capacitor C1 is a bootstrap capacitor. That is, when a clock signal is input to the drain electrode of the transistor T3 and the potential of the source electrode of the transistor T3 rises, the potential of the node N1 rises (bootstrap) due to the charge of the capacitor C1.

[0028] like Figure 4 As shown, the output signal of the unit circuit 21 is output to the gate line 11 as a gate signal G, and is input to the terminal S of the unit circuit 21 constituting the next stage as a set signal, and is input to the terminal R of the unit circuit 21 constituting the previous stage as a reset signal.

[0029] In addition, the “nth level” is an example of the “first level” of the present disclosure. In addition, the “n+1th level” is an example of the “second level” of the present disclosure. In addition, the “unit circuit constituting the nth level” is an example of the “first unit circuit” of the present disclosure. In addition, the “unit circuit constituting the n+1th level” is an example of the “second unit circuit” and the “third unit circuit” of the present disclosure. In addition, the “unit circuit constituting the n+2th level” is an example of the “fourth unit circuit” of the present disclosure.

[0030] <Configuration of the connection circuit 23> like Figure 6 As shown, the connection circuit 23 includes a transistor T4a. The drain electrode of the transistor T4a is connected to the node N1 of the unit circuit 21 constituting the nth level. The source electrode of the transistor T4a is supplied with a VSS signal. The gate electrode of the transistor T4a is connected to the terminal TPC to which the TPC signal is input, and the TPC signal is a signal input when the operation of the gate drive circuit 20 is stopped. Thus, if the TPC signal is input to the transistor T4a, the node N1 of the unit circuit 21 constituting the nth level is discharged, and the unit circuit 21 constituting the nth level is reset. In addition, the "TPC signal" is an example of the "second control signal" of the present disclosure. In addition, the transistor T4a is an example of the "reset circuit" of the present disclosure.

[0031] like Figure 4 As shown, the output signal of the unit circuit 21 constituting the nth level is output to the gate line 11 as the gate signal Gn, and is input to the terminal S of the unit circuit 21 constituting the n+1th level as a set signal, and is input to the terminal R of the unit circuit 21 constituting the n-1th level as a reset signal. Moreover, the output signal of the unit circuit 21 constituting the nth level is also input to the terminal Lset of the latch circuit 22 as a set signal.

[0032] like Figure 7 As shown, the connection circuit 23 includes a transistor T4b and a transistor T5. The drain electrode of the transistor T4b is connected to the node N1 of the unit circuit 21 constituting the n+1th level. The source electrode of the transistor T4b is supplied with a VSS signal. The gate electrode of the transistor T4b is connected to the terminal TPC. Thus, if the TPC signal is input to the transistor T4b, the node N1 of the unit circuit 21 constituting the n+1th level is discharged, and the unit circuit 21 constituting the n+1th level is reset. In addition, the transistor T4b is an example of a "reset circuit" of the present disclosure. In addition, the transistor T5 is an example of a "set circuit" of the present disclosure.

[0033] The gate electrode and drain electrode of the transistor T5 are connected to the terminal Lout from which the output signal is output from the latch circuit 22. The source electrode of the transistor T5 is connected to the node N1. That is, the transistor T5 is diode-connected to the terminal Lout and the node N1. Thus, when the output signal is output from the latch circuit 22, the transistor T5 charges the node N1.

[0034] like Figure 4 As shown, the output signal of the unit circuit 21 constituting the n+1th level is output to the gate line 11 as the gate signal Gn+1, and is input to the terminal S of the unit circuit 21 constituting the n+2th level as a set signal, and is input to the terminal R of the unit circuit 21 constituting the nth level as a reset signal. Moreover, the output signal of the unit circuit 21 constituting the n+1th level is also input to the terminal Lrst of the latch circuit 22 as a reset signal.

[0035] <Configuration of Latch Circuit 22> like Figure 4 As shown, the latch circuit 22 is connected in parallel with a plurality of unit circuits 21. That is, the output signal from the unit circuit 21 constituting the nth stage is input to the latch circuit 22, and is input to the unit circuit 21 constituting the n+1th stage. Then, the output signal from the unit circuit 21 constituting the n+1th stage is input to the latch circuit 22, and is input to the unit circuit 21 constituting the n+2th stage.

[0036] like Figure 8 As shown, the latch circuit 22 includes transistors T1L to T3L, a capacitor C1L, and a node N1L.

[0037] The gate electrode and drain electrode of the transistor T1L are connected to the terminal Lset to which the set signal is input. The source electrode of the transistor T1L is connected to the node N1L. That is, the transistor T1L is diode-connected to the terminal Lset and the node N1L. Thus, when the set signal is input, the transistor T1L charges the node N1L.

[0038] The drain electrode of the transistor T2L is connected to the node N1L. The source electrode of the transistor T2L is supplied with a VSS signal having a reference potential (low potential). The gate electrode of the transistor T2L is connected to a terminal Lrst to which a reset signal is input. Thus, when the reset signal is input, the transistor T2L discharges from the node N1L.

[0039] The drain electrode of the transistor T3L is connected to the terminal RSM to which the RSM signal is input, and the RSM signal is a signal input when the operation of the gate drive circuit 20 is restarted. The gate electrode of the transistor T3L is connected to the node N1L. The source electrode of the transistor T3L is connected to the terminal Lout to which the output signal is output. In addition, the "RSM signal" is an example of the "first control signal" of the present disclosure. In addition, the terminal Lout is an example of the "output node" of the present disclosure.

[0040] The capacitor C1L is connected between the gate electrode of the transistor T3L and the source electrode of the transistor T3L. The capacitor C1L accumulates charge when the node N1L is charged. The capacitor C1L is a bootstrap capacitor. That is, when the RSM signal is input to the drain electrode of the transistor T3L and the potential of the source electrode of the transistor T3L rises, the potential of the node N1L rises (bootstrap) due to the charge of the capacitor C1L.

[0041] like Figure 4 As shown, the output signal of the latch circuit 22 is input to the gate electrode of the transistor T5 of the connection circuit 23 .

[0042] (Operation of Gate Drive Circuit 20) Next, refer to Fig. 9 and Fig.10 , the operation of the gate drive circuit 20 will be described. is a timing chart of each signal in the gate drive circuit 20 based on non-pause driving. is a timing chart of each signal in the gate drive circuit 20 based on pause driving.

[0043] 〈No-stop drive〉 like Fig. 9 As shown, when the control circuit 2 performs non-pause driving, the TPC signal and the RSM signal are not supplied to the gate drive circuit 20 (they are in an OFF level state).

[0044] At time t1, the node N1 of the unit circuit 21 constituting the nth stage is charged according to the output signal from the unit circuit 21 constituting the n-1th stage. At time t2, the unit circuit 21 constituting the nth stage is supplied with the clock signal GCK2, and outputs the output signal to the gate line 11, the latch circuit 22, and the unit circuit 21 constituting the n+1th stage. At this time, the node N1L of the latch circuit 22 and the node N1 of the unit circuit 21 constituting the n+1th stage are charged.

[0045] At time t3, the clock signal GCK1 is supplied to the unit circuit 21 constituting the n+1th level, and the output signal is output to the gate line 11, the latch circuit 22, and the unit circuit 21 constituting the n+2th level. Since the output signal from the unit circuit 21 constituting the n+1th level is input to the latch circuit 22 as a reset signal, the node N1L is discharged (reset). Then, the gate signal G is sequentially output to the gate line 11 from the unit circuit 21 of the n+2th level and thereafter.

[0046] 〈With stop drive〉 like Fig.10 As shown, when performing pause driving, the control circuit 2 supplies the TPC signal to the gate drive circuit 20 at the beginning of the pause period TR, and supplies the RSM signal to the gate drive circuit 20 at the end of the pause period TR. In addition, touch detection processing is performed during the pause period TR.

[0047] At time t11, the node N1 of the unit circuit 21 constituting the nth stage is charged according to the output signal from the unit circuit 21 constituting the n-1th stage. At time t12, the unit circuit 21 constituting the nth stage is supplied with the clock signal GCK2, and outputs the output signal to the gate line 11, the latch circuit 22, and the unit circuit 21 constituting the n+1th stage. At this time, the node N1L of the latch circuit 22 and the node N1 of the unit circuit 21 constituting the n+1th stage are charged.

[0048] At time t13, the idle period TR starts and the TPC signal is input to the connection circuit 23. Thus, until time t14, the node N1 of the unit circuit 21 constituting the nth stage and the node N1 of the unit circuit 21 constituting the n+1th stage are reset. In addition, the node N1L remains charged.

[0049] At time t15, the RSM signal is input to the latch circuit 22. Thus, the output signal from the terminal Lout of the latch circuit 22 is supplied to the node N1 of the unit circuit 21 constituting the n+1th stage via the transistor T5 of the connection circuit 23. The node N1 of the unit circuit 21 constituting the n+1th stage is charged.

[0050] At time t16, the clock signal GCK1 is supplied to the unit circuit 21 constituting the n+1th stage, and an output signal is output from the unit circuit 21 constituting the n+1th stage. The latch circuit 22 is reset by the output signal from the unit circuit 21 constituting the n+1th stage, and the unit circuit 21 constituting the n+2th stage is charged. Thereafter, each time the clock signals GCK1 and GCK2 are supplied, the gate signals are sequentially output to each stage.

[0051] As described above, the gate drive circuit 20 according to the first embodiment can perform non-pause driving according to whether or not the TPC signal and the RSM signal are supplied (see Fig. 9 ) and with abort drive (refer to Fig.10 )Both of these.

[0052] [Second Embodiment] Next, refer to Figures 11 to 14 , the configuration of the display device 200 according to the second embodiment is described. The second embodiment is a configuration example in which a four-phase clock signal is input to the shift register circuit 220a. The same reference numerals are given to the same configurations as those in the first embodiment and description thereof is omitted. Fig.11 This is a block diagram of a display device 200 according to the second embodiment. Fig.12 It is a diagram showing the configuration of a gate driving circuit 220 of a display device 200 according to the second embodiment. Fig.13 This is a timing chart when the gate driving circuit 220 according to the second embodiment performs non-pause driving. Fig.14 This is a timing chart when the gate driving circuit 220 according to the second embodiment performs pause driving.

[0053] like Fig.11 As shown, the display device 200 includes a control circuit 202 and a gate drive circuit 220. In the second embodiment, the control circuit 202 inputs 4-phase clock signals GCK1 to GCK4 to the gate drive circuit 220. The gate drive circuit 220 includes a shift register circuit 220a, a latch circuit 222, and a connection circuit 223. The 4-phase clock signals GCK1 to GCK4 are input to the shift register circuit 220a. In addition, the output signal of the unit circuit 21 of the shift register circuit 220a is input to the terminal S of the unit circuit 21 constituting the stage after the second stage and the terminal R of the unit circuit 21 constituting the stage before the third stage. In addition, the output signal of the unit circuit 21 constituting the n+3 stage is input to the terminal Lrst of the latch circuit 222 as a reset signal.

[0054] The connection circuit 223 includes: a transistor T4a connected to the node N1 of the unit circuit 21 constituting the n-2th level; a transistor T4a connected to the node N1 of the unit circuit 21 constituting the n-1th level; and a transistor T4a connected to the node N1 of the unit circuit 21 constituting the nth level. In addition, the connection circuit 223 includes: a transistor T4b and a transistor T5 connected to the node N1 of the unit circuit 21 constituting the n+1th level; and a transistor T4b and a transistor T5 connected to the node N1 of the unit circuit 21 constituting the n+2th level.

[0055] The terminal Lout of the latch circuit 222 is connected to the two transistors T5 , respectively.

[0056] like Fig.13 As shown, at time t21, by supplying the clock signal GCK4 to the unit circuit 21 constituting the nth level, the output signal is input from the unit circuit 21 to the terminal Lset of the latch circuit 222 and the unit circuit 21 constituting the n+2th level. As a result, the node N1L and the node N1 of the unit circuit 21 constituting the n+2th level are charged. Thereafter, at time t22, by supplying the clock signal GCK3 to the unit circuit 21 constituting the n+3th level, the output signal is input from the unit circuit 21 to the terminal Lrst of the latch circuit 222 and the unit circuit 21 constituting the nth level. As a result, the latch circuit 222 and the unit circuit 21 constituting the nth level are reset. Then, the unit circuits 21 from the n+4th level onwards sequentially output the gate signal G to the gate line 11.

[0057] like Fig.14 As shown, at time t31, by supplying the clock signal GCK4 to the unit circuit 21 constituting the nth stage, the output signal is input from the unit circuit 21 to the terminal Lset of the latch circuit 222 and the unit circuit 21 constituting the n+2th stage. As a result, the node N1L and the node N1 of the unit circuit 21 constituting the n+2th stage are charged. Thereafter, by inputting the TPC signal to the connection circuit 223 at time t32, the node N1 of each unit circuit 21 from the n-2th stage to the n+2th stage is reset until time t33. Then, during the suspension period TR, the operation of the gate drive circuit 220 stops, and at time t34, the RSM signal is input to the latch circuit 222. As a result, the output signal from the terminal Lout of the latch circuit 222 is input to the node N1 of the unit circuit 21 constituting the n+1th stage and the n+2th stage via the transistor T5 of the connection circuit 223.

[0058] At time t35, the clock signal GCK1 is input to the unit circuit 21 constituting the n+1th level, and the output signal (gate signal Gn+1) is output from the unit circuit 21, and the suspension period TR ends. Thereafter, at time t36, the output signal from the unit circuit 21 constituting the n+3th level is input to the latch circuit 222 as a reset signal, and the latch circuit 222 is reset. Then, the unit circuits 21 from the n+4th level onwards sequentially output the gate signal G to the gate line 11.

[0059] As described above, according to the second embodiment, even when a 4-phase clock signal is input to the shift register circuit 220a, it is possible to switch between non-pause driving and pause driving according to whether or not an RSM signal is input to the latch circuit 222 and a TPC signal is input to the connection circuit 223. In addition, the other configurations and effects of the second embodiment are the same as those of the first embodiment.

[0060] (Variation of the Second Embodiment) Next, refer to Fig.15 , the operation of the display device according to the modified example of the second embodiment is described. Fig.15 This is a timing chart of a display device according to a modification of the second embodiment.

[0061] In a second embodiment, if Fig.14 As shown, the time t34 at which the RSM signal is input to the latch circuit 222 is earlier than the time t35 at which the input of the clock signal GCK1 is restarted by one horizontal synchronization signal. Fig.15 As shown, the time t41 at which the RSM signal is input to the latch circuit 222 is two horizontal synchronization signals earlier than the time t42 at which the input of the clock signal GCK1 is restarted. Fig.15 As shown, the latch circuit 222 can be reset using the output signal from the unit circuit 21 constituting the n+2th stage as a reset signal.

[0062] [Third Embodiment] Next, refer to Figures 16 to 19 , the configuration of the display device 300 based on the third embodiment is described. In the third embodiment, a plurality of latch circuits 322 and a plurality of connection circuits 323 are connected in parallel to the shift register circuit 320a. Furthermore, the gate drive circuit 320 is configured to operate only a determined latch circuit 322 among the plurality of latch circuits 322. In addition, the same reference numerals are given to the same configuration as that of the first embodiment and the description thereof is omitted. Fig.16 This is a block diagram of a display device 300 according to the third embodiment. Fig.17 It is a diagram showing the configuration of a gate driving circuit 320 of a display device 300 according to the third embodiment. Fig.18 This is a timing chart related to the operation of the circuit other than the operation circuit according to the third embodiment. Fig.19 This is a timing chart related to the operation of the operation circuit according to the third embodiment.

[0063] like Fig.16 As shown, the display device 300 includes a control circuit 302 and a gate drive circuit 320. Fig.17 As shown, the gate drive circuit 320 includes a shift register circuit 320a, a plurality of latch circuits 322 connected in parallel to the shift register circuit 320a, and a plurality of connection circuits 323. The shift register circuit 320a is provided with a plurality of (for example, 800) unit circuits 21 (see Figure 5). The latch circuit 322 and the connecting circuit 323 are respectively arranged at each specified level (for example, 100 levels) of the shift register circuit 320a. For example, 7 latch circuits 322 and 7 connecting circuits 323 are provided in the gate drive circuit 320. The latch circuit 322 and the connecting circuit 323 connected to the unit circuit 21 constituting the 100th level of the shift register circuit 320a are set as "latch unit L1", and the subsequent latch circuits 322 and the connecting circuit 323 are set as "latch unit L2", ..., "latch unit L7".

[0064] In the third embodiment, the control circuit 302 is configured to be able to perform control based on four modes, namely, basic drive, intermittent drive, alternating drive, and non-stop drive, as the modes for operating the gate drive circuit 320. The control circuit 302 switches the above four modes by determining the operating circuit to be operated from the latch units L1 to L7. Fig.19 As shown, the TPC signal and the RSM signal are input to the latch unit determined as the operating circuit among the latch units L1 to L7, and the operation of the gate drive circuit 320 is stopped. Fig.18 As shown, the TPC signal and the RSM signal are not input to the latch cells other than the latch cells determined as the operating circuits among the latch cells L1 to L7 , and the operation of the gate driving circuit 320 is not stopped.

[0065] "Basic drive" refers to a driving method in which all latch units L1 to L7 are determined as action circuits and all latch units L1 to L7 stop the action of the gate drive circuit 320. "Intermittent drive" refers to a driving method in which a part of the latch units L1 to L7 (for example, only L2, L4 and L6) is determined as an action circuit, and the action of the gate drive circuit 320 is stopped only in a part of the latch units L1 to L7. "Alternating drive" refers to a driving method in which the action circuit is changed every frame. For example, in an odd frame, the control circuit 302 determines the latch units L2, L4 and L6 as action circuits, and in an even frame, the control circuit 302 determines the latch units L1, L3, L5 and L7 as action circuits. "Non-stop drive" refers to a driving method in which all latch units L1 to L7 are not determined as action circuits.

[0066] According to the third embodiment, the operation of the gate drive circuit 320 can be continued outside the operation circuit in the latch units L1 to L7, and the operation of the gate drive circuit 320 can be stopped in the operation circuit. According to the four modes of basic drive, intermittent drive, alternating drive, and non-stop drive, the level at which the operation of the gate drive circuit 320 is stopped can be arbitrarily set. In addition, the other configurations and effects of the third embodiment are the same as those of the first embodiment.

[0067] [Deformation, etc.] The above-mentioned embodiments are merely examples for implementing the present disclosure. Therefore, the present disclosure is not limited to the above-mentioned embodiments, and the above-mentioned embodiments can be appropriately modified and implemented within the scope of the gist thereof.

[0068] (1) In the first to third embodiments, the capacitive element (bootstrap capacitor) is provided in the unit circuit, but the present disclosure is not limited thereto. For example, the function of the capacitive element C1 described in the first to third embodiments may be replaced by the capacitive component of the transistor T3.

[0069] (2) In the first and second embodiments, examples are shown in which the gate drive circuit is provided in a display device that performs non-stop driving and a display device that performs stop driving, but the present disclosure is not limited to this. That is, the gate drive circuit can be provided in a display device that performs only non-stop driving, or in a touch panel that performs only stop driving. That is, the gate drive circuit of the present disclosure can be mounted on devices of various specifications.

[0070] (3) In the first to third embodiments described above, examples of connections within the gate drive circuit are shown, but the present disclosure is not limited thereto. That is, the connection structure within the gate drive circuit (the input destination of the set signal and the reset signal) may be changed according to the number of phases of the clock signal.

[0071] (4) In the first to third embodiments described above, an example in which a touch detection function is provided in a display device is shown, but the present disclosure is not limited thereto. That is, the touch detection function may not be provided in the display device.

[0072] (5) In the first to fourth embodiments, the display device is constituted by a liquid crystal display panel including a liquid crystal layer, but the present disclosure is not limited thereto. For example, the display device may be constituted by an organic EL (Electro Luminescence) display panel.

[0073] The above-mentioned driving circuit, display device, in-cell touch panel device, and driving circuit control device can also be described as follows.

[0074] The driving circuit involved in the first configuration is composed of a plurality of stages, and in response to the input of a plurality of clock signals, the driving circuit supplies a driving signal to a scanning signal line group, and the driving circuit includes: a plurality of unit circuits, which constitute each of the plurality of stages and output the driving signal; a latch circuit, which is arranged in parallel with the plurality of unit circuits; and a connecting circuit, which is connected to an output node of the latch circuit. The latch circuit receives a first output signal from a first unit circuit as a first set signal, and the first unit circuit constitutes a first stage among the plurality of unit circuits. After receiving the first set signal, the latch circuit receives a first control signal for restarting the operation of the driving circuit, and outputs a latch circuit output signal to the connecting circuit via the output node. The latch circuit receives a second output signal from a second unit circuit as a first reset signal, and the second unit circuit constitutes a second stage among the plurality of unit circuits that is later than the first stage. The connection circuit includes: a reset circuit, which resets the first unit circuit and the third unit circuit in response to the input of a second control signal that stops the operation of the driving circuit, and the third unit circuit constitutes the next level of the first level among the multiple unit circuits; and a set circuit, which supplies the latch circuit output signal as a second set signal to the third unit circuit (first configuration).

[0075] According to the first configuration, since the latch circuit is connected in parallel to the plurality of unit circuits, if the second control signal for stopping the operation of the drive circuit is not supplied to the drive circuit, the operation of the drive circuit is not stopped in the latch circuit and the operation of the drive circuit can be continued. In addition, if the second control signal is supplied to the drive circuit, the operation of the drive circuit can be stopped, and if the first control signal is supplied to the drive circuit, the operation of the drive circuit can be restarted. As a result, the presence or absence of stopping the operation of the drive circuit can be arbitrarily set by the latch circuit.

[0076] In the first configuration, the third unit circuit may also include: an internal node; a first transistor that charges the internal node in response to the first output signal from the first unit circuit being input; a second transistor that outputs the drive signal to any one of the scanning signal lines in the scanning signal line group when the internal node is charged and any one of the plurality of clock signals is input; and a third transistor that discharges from the internal node in response to the second reset signal from the fourth unit circuit being input. The reset circuit and the set circuit may also be connected to the internal node. The reset circuit may also be configured to discharge from the internal node in response to the second control signal being input. The set circuit may also be configured to charge the internal node in response to the latch circuit output signal being input (second configuration).

[0077] According to the second configuration, the reset circuit can directly discharge the internal node of the third unit circuit. In addition, the set circuit can directly charge the internal node of the third unit circuit. Therefore, there is no need to set up additional circuits between the reset circuit and the third unit circuit, and between the set circuit and the third unit circuit.

[0078] In the first or second configuration, the second stage formed by the second unit circuit may be a stage following the first stage. The third unit circuit may also serve as the second unit circuit (third configuration).

[0079] According to the third configuration, it is possible to prevent the configuration of the drive circuit from being complicated.

[0080] In the first or second configuration, the second stage formed by the second unit circuit may be a stage later than the stage formed by the third unit circuit (fourth configuration).

[0081] According to the fourth configuration, even when the number of phases of the plurality of clock signals is large, the second output signal from the second unit circuit can be input to the latch circuit to reset the latch circuit.

[0082] A display device according to a fifth configuration includes: a driving circuit according to any one of the first to seventh configurations; and a display provided with the scanning signal line group (fifth configuration).

[0083] According to the fifth configuration, it is possible to provide a display device in which the presence or absence of stopping the operation of the drive circuit can be arbitrarily set by the latch circuit.

[0084] The in-cell touch panel device according to the sixth configuration includes: the driving circuit of any one of the first to seventh configurations; and an in-cell touch panel that is provided with the scanning signal line group and detects a touch by a pointer during a period in which the driving circuit stops operating (sixth configuration).

[0085] According to the sixth configuration, it is possible to provide an in-cell touch panel device in which the presence or absence of stopping the operation of the drive circuit can be arbitrarily set by the latch circuit.

[0086] The control device of the drive circuit involved in the seventh configuration is a control device of the drive circuit that supplies the multiple clock signals, the first control signal, and the second control signal to any one of the drive circuits of the first to fourth configurations. The drive circuit includes: multiple latch circuits, which are arranged in parallel with the multiple unit circuits; and multiple connection circuits, which are respectively connected to the output nodes of the multiple latch circuits. In the control device of the drive circuit, an action connection circuit that performs an action is determined from the multiple connection circuits, and the second control signal is not supplied to the connection circuits other than the action connection circuit among the multiple connection circuits, but the second control signal is supplied to the action connection circuit (seventh configuration).

[0087] Here, in the conventional display device, since the position (level) of stopping the operation is fixed, the position cannot be changed. In contrast, according to the seventh configuration, the operation of the driving circuit can be continued except for the action connection circuit among the plurality of connection circuits, and the operation of the driving circuit can be stopped in the action connection circuit. Thus, the level (position) of stopping the operation can be arbitrarily changed according to the action connection circuit determined from the plurality of connection circuits. Description of Reference Numerals

[0088] 1: touch panel, 2: control circuit, 10: display unit, 11: gate line, 12: source line, 13: transistor, 13a: gate electrode, 13b: source electrode, 13c: drain electrode, 14: pixel electrode, 15: common electrode, 16: wiring, 20: gate drive circuit, 20a: shift register circuit, 21: unit circuit, 22: latch circuit, 23: connection circuit, 30: source drive circuit, 40: touch detection control circuit, 100: display device, 200: display device, 202: control circuit, 220: gate drive circuit, 220a: shift register circuit, 222: latch circuit, 223: connection circuit, 300: display device, 302: control circuit, 320: gate drive circuit , 320a: shift register circuit, 322: latch circuit, 323: connection circuit, C1: capacitor element, C1L: capacitor element, G: gate signal, GCK: terminal, GCK1~GCK4: clock signal, Gn: gate signal, L1~L7: latch unit, Lout: terminal, Lrst: terminal, Lset: terminal, N1: node, N1L: node, Q: terminal, R: terminal, RSM: terminal, S: terminal, T1: transistor, T1L: transistor, T2: transistor, T2L: transistor, T3: transistor, T3L: transistor, T4a: transistor, T4b: transistor, T5: transistor, TD: display period, TP: touch detection period, TPC: terminal, TR: suspension period.

Claims

1. A driving circuit, which is composed of a plurality of stages and supplies a driving signal to a scanning signal line group in response to a plurality of clock signals being input, wherein the driving circuit is characterized in that it comprises: a plurality of unit circuits constituting each of the plurality of stages and outputting the drive signal; a latch circuit, which is arranged in parallel with the plurality of unit circuits; as well as A connecting circuit connected to an output node of the latch circuit, The latch circuit receives a first output signal from a first unit circuit as a first set signal, the first unit circuit constituting a first stage of the plurality of unit circuits. When the latch circuit receives the first control signal for restarting the operation of the drive circuit after receiving the first set signal, the latch circuit outputs the latch circuit output signal to the connection circuit via the output node. The latch circuit receives a second output signal from a second unit circuit as a first reset signal, the second unit circuit constituting a second stage of the plurality of unit circuits that is later than the first stage. The connecting circuit comprises: a reset circuit that, in response to input of a second control signal for stopping the operation of the drive circuit, resets the first unit circuit and a third unit circuit, the third unit circuit constituting a stage next to the first stage among the plurality of unit circuits; as well as The set circuit supplies the latch circuit output signal as a second set signal to the third unit circuit.

2. The driving circuit according to claim 1, characterized in that: The third unit circuit comprises: Internal nodes; a first transistor that charges an internal node in response to the first output signal from the first unit circuit being input; a second transistor, which outputs the driving signal to any one of the scanning signal lines in the scanning signal line group when the internal node is charged and any one of the plurality of clock signals is input; as well as a third transistor that discharges from the internal node in response to a second reset signal being input from a fourth unit circuit that constitutes a stage later than a stage constituted by the third unit circuit, The reset circuit and the set circuit are connected to the internal node, The reset circuit discharges the internal node in response to the second control signal being input. The setting circuit charges the internal node in response to the latch circuit output signal being input.

3. The driving circuit according to claim 1 or 2, characterized in that: The second stage formed by the second unit circuit is a subsequent stage of the first stage, The third unit circuit also serves as the second unit circuit.

4. The driving circuit according to claim 1 or 2, characterized in that: The second stage formed by the second unit circuit is a stage later than the stage formed by the third unit circuit.

5. A display device, characterized in that: include: The driving circuit according to claim 1; as well as A display is provided with the scanning signal line group.

6. An embedded touch panel device, characterized in that: include: The driving circuit according to claim 1; as well as The in-cell touch panel is provided with the scanning signal line group and detects a touch by a pointer during a period when the operation of the driving circuit is stopped.

7. A control device for a drive circuit, which supplies the plurality of clock signals, the first control signal, and the second control signal to the drive circuit according to claim 1, wherein the control device is characterized in that: The driving circuit comprises: a plurality of latch circuits, which are arranged in parallel with the plurality of unit circuits; as well as a plurality of connection circuits, which are respectively connected to the output nodes of the plurality of latch circuits, In the control device of the drive circuit, determining an action connection circuit to perform an action from among the plurality of connection circuits, The second control signal is not supplied to connection circuits other than the operating connection circuit among the plurality of connection circuits, but the second control signal is supplied to the operating connection circuit.

Images