Voltage holding circuit and system on chip

Abstract

The invention provides a voltage holding circuit and a system on chip. The voltage holding circuit comprises a charge pump, a trigger unit, a first switch unit and a voltage holding unit, the trigger unit is respectively connected with the charge pump and the control end of the first switch unit; the first end of the first switch unit is connected to the output end of the charge pump, and the second end of the first switch unit is connected to the voltage holding unit; the voltage holding unit is also used for connecting a DNW array of the memory. By controlling the charge pump to work or rest, the voltage of the input end of the voltage maintaining unit is within the first target voltage interval, so that the voltage of the parasitic capacitor of the DNW array is maintained within the second target voltage interval. When the read-write operation of the memory needs to be carried out, the power supply voltage of the electronic equipment can quickly boost the memory to the working voltage, so that the read-write operation of the memory is quickly responded, and the low power consumption in the standby mode is ensured.

Description

Technical Field

[0001] The present invention relates to the field of electronic equipment, and in particular to a voltage holding circuit and a system on chip. Background Art

[0002] In standby mode (also known as SLEEP mode or Standby Mode), electronic devices will reduce power consumption to extend the battery standby time. Flash memory (FLASH memory) is usually set in electronic devices, and due to the working characteristics of flash memory, flash memory may not be able to perform read and write operations normally at a lower voltage. When data needs to be read from the flash memory, in order to ensure the reliability of data access, the electronic device will switch to read mode, at which time the power supply is sufficient to support the flash memory read operation.

[0003] Due to the characteristics of flash memory, when an electronic device switches from standby mode to read mode, especially when the flash memory requires a voltage higher than the normal operating voltage VDD to perform operations, maintaining sufficient voltage supply will increase power consumption, which conflicts with the goal of saving energy in standby mode. Summary of the invention

[0004] The object of the present invention is to provide a voltage holding circuit and a system on chip to improve the above-mentioned problem.

[0005] In order to achieve the above purpose, the technical solution adopted by the embodiment of the present invention is as follows:

[0006] In a first aspect, an embodiment of the present invention provides a voltage holding circuit, the voltage holding circuit comprising a charge pump, a trigger unit, a first switch unit and a voltage holding unit;

[0007] The trigger unit is connected to the control end of the charge pump and the control end of the first switch unit respectively;

[0008] A first end of the first switch unit is connected to the output end of the charge pump, and a second end of the first switch unit is connected to the voltage holding unit;

[0009] The voltage holding unit is also used to connect to the DNW array of the memory.

[0010] Optionally, the trigger unit is used to send a start signal to the charge pump when a first trigger condition is met, and control the first switch unit to switch to a closed state, so that the charge pump charges the voltage holding unit to keep the input terminal voltage of the voltage holding unit within a first target voltage range;

[0011] The trigger unit is used for sending a rest signal to the charge pump and controlling the first switch unit to switch to an off state when a second trigger condition is met;

[0012] The voltage maintaining unit is used to charge the DNW array so that the voltage of the parasitic capacitor of the DNW array is maintained within a second target voltage range.

[0013] Optionally, the trigger unit is used to detect the current voltage at the output end of the charge pump;

[0014] The trigger unit is used to determine that the first trigger condition is met when the current voltage is lower than the first voltage threshold;

[0015] The trigger unit is used to determine that the second trigger condition is met when the current voltage reaches a second voltage threshold.

[0016] Optionally, the trigger unit is used to record the start-up interval duration of the charge pump, and when the start-up interval duration is equal to a first time threshold, it is determined that the first trigger condition is met;

[0017] The trigger unit is used to record the continuous start-up time of the charge pump, and when the continuous start-up time is equal to the second time threshold, determine that the second trigger condition is met;

[0018] The start-up interval duration indicates the duration from the last time the charge pump entered the rest state to the current time, and the continuous start-up duration indicates the duration from the last time the charge pump entered the start-up state to the current time.

[0019] Optionally, the voltage holding unit includes a first capacitor and an NMOS tube;

[0020] At the connection between one electrode of the first capacitor and the gate of the NMOS tube, a connection terminal is led out as an input end of the voltage holding unit, which is used to connect the second end of the first switch unit;

[0021] The other electrode of the first capacitor is grounded, the drain of the NMOS tube is connected to the output end of the charge pump, and the source of the NMOS tube is connected to the DNW array.

[0022] Optionally, the voltage holding circuit further includes a first resistor, a second resistor and a second switch unit;

[0023] One end of the first resistor is connected to the second end of the first switch unit, the other end of the first resistor is connected to one end of the second resistor, and the other end of the second resistor is grounded;

[0024] One end of the second switch unit is connected to a terminal connected between the first resistor and the second resistor, and the other end of the second switch unit is connected to an input end of the voltage holding unit;

[0025] The trigger unit is connected to the control end of the second switch unit, and the trigger unit is used to control the second switch unit to maintain a consistent state with the first switch unit.

[0026] Optionally, the voltage maintaining unit further includes a third switching unit;

[0027] A first end of the third switch unit is connected to the output end of the charge pump, and a second end of the third switch unit is connected to the drain of the NMOS tube.

[0028] Optionally, when the electronic device deploying the voltage holding circuit is in a standby mode, the third switch unit is in a closed state;

[0029] When the electronic device is in the working mode, the third switch unit is in an off state.

[0030] In a second aspect, an embodiment of the present invention provides a system on chip, which includes a memory and the above-mentioned voltage holding circuit.

[0031] In a third aspect, an embodiment of the present invention provides an electronic device, comprising the above-mentioned system on chip.

[0032] Compared with the prior art, the voltage holding circuit and system on chip provided by the embodiment of the present invention include a charge pump, a trigger unit, a first switch unit and a voltage holding unit; the trigger unit is respectively connected to the control end of the charge pump and the first switch unit; the first end of the first switch unit is connected to the output end of the charge pump, and the second end of the first switch unit is connected to the voltage holding unit; the voltage holding unit is also used to connect the DNW array of the memory. By controlling the charge pump to work or rest, the input voltage of the voltage holding unit is within the first target voltage range, so that the voltage of the parasitic capacitance of the DNW array is maintained within the second target voltage range. When the memory needs to be read and written, the power supply voltage of the electronic device can quickly increase the memory to the working voltage, thereby quickly responding to the read and write operations of the memory and ensuring low power consumption in standby mode.

[0033] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0035] Figure 1 This is one of the voltage holding circuits provided in the embodiments of the present invention.

[0036] Figure 2 This is the second voltage holding circuit provided in the embodiment of the present invention.

[0037] Figure 3 This is the third voltage holding circuit provided in the embodiment of the present invention.

[0038] In the figure: 10 - charge pump; 20 - trigger unit; 30 - voltage holding unit; 40 - DNW array. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0040] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0041] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings. At the same time, in the description of the present invention, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0042] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0043] In the description of the present invention, it should be noted that the terms "upper", "lower", "inside", "outside", etc. indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, or are directions or positional relationships in which the product of the invention is usually placed when in use. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present invention.

[0044] In the description of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "disposed" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0045] Some embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0046] In order to enable the electronic device to quickly respond to the read and write operations of the memory with low power consumption in the standby mode, the embodiment of the present invention provides an optional implementation method. In the standby mode, the parasitic capacitance of the DNW (Deep N Well) array of the memory is kept close to the working voltage of the memory through the voltage holding circuit, so that when the read and write operations are required, the memory can be quickly raised to the working voltage, thereby quickly responding to the read and write operations of the memory. In the embodiment of the present invention, the memory can be but is not limited to a flash memory (FLASH memory).

[0047] Since the S / D needs to see negative voltage when the memory cell is operating, it is impossible to use the conventional NMOS with PSUB as GND, and a separate NMOS with pwell+deep N well needs to be made. A large memory array generally contains many memory cells, so many NMOS deep N wells have a natural large parasitic capacitance (parasitic PN junction between Pwell and PSUB).

[0048] Please refer to Figure 1 , Figure 1 This is one of the voltage holding circuits provided by the embodiments of the present invention. The voltage holding circuit comprises a charge pump 10 , a trigger unit 20 , a first switch unit K1 and a voltage holding unit 30 .

[0049] The trigger unit 20 is connected to the charge pump 10 and the control end of the first switch unit K1 respectively.

[0050] A first end of the first switch unit K1 is connected to the output end (Vout) of the charge pump 10 , and a second end of the first switch unit K1 is connected to the voltage holding unit 30 .

[0051] The voltage holding unit 30 is also used to connect to the DNW array 40 of the memory.

[0052] The trigger unit 20 is used to send a start signal to the charge pump 10 when the first trigger condition is met, and control the first switch unit K1 to switch to a closed state, so that the charge pump 10 charges the voltage holding unit 30 and keeps the input voltage of the voltage holding unit 30 within the first target voltage range.

[0053] Optionally, the first trigger condition being met indicates that the input voltage of the voltage holding unit 30 drops to a third voltage threshold, and the third voltage threshold may be a lower limit of the first target voltage range.

[0054] The trigger unit 20 is used to send a rest signal to the charge pump 10 and control the first switch unit K1 to switch to an off state when the second trigger condition is met.

[0055] Optionally, the second trigger condition being met indicates that the input voltage of the voltage holding unit 30 (voltage at point A) rises to a fourth voltage threshold (maximum value of the input voltage of the voltage holding unit 30), and the fourth voltage threshold may be an upper limit of the first target voltage interval.

[0056] The voltage holding unit 30 is used to charge the DNW array 40 so that the voltage of the parasitic capacitor Cg of the DNW array 40 (the voltage at point B) is maintained within the second target voltage range.

[0057] Optionally, the lower limit of the second target voltage range is higher than the supply voltage of the voltage source of the electronic device in the standby mode. The input voltage of the voltage holding unit 30 (voltage at point A) and the voltage of the parasitic capacitor Cg of the DNW array 40 (voltage at point B) maintain a preset voltage difference, so when the input voltage of the voltage holding unit 30 is within the first target voltage range, it can be ensured that the voltage of the parasitic capacitor Cg of the DNW array 40 (voltage at point B) remains within the second target voltage range.

[0058] In the voltage holding circuit provided in the embodiment of the present invention, the charge pump 10 is triggered to work by the first trigger condition, so that the input voltage of the voltage holding unit 30 is within the first target voltage interval, thereby keeping the voltage of the parasitic capacitor Cg of the DNW array 40 within the second target voltage interval. When the memory needs to be read and written, the power supply voltage of the electronic device can quickly increase the memory to the working voltage, thereby quickly responding to the memory read and write operations.

[0059] At the same time, the charge pump 10 is triggered to stop working and enter a rest state by the second trigger condition, thereby ensuring low power consumption in the standby mode, allowing the system to have higher reliability and lower power consumption in the standby mode, and only perform limited operations when necessary.

[0060] Based on the foregoing, regarding how to determine whether a rising trigger condition is met, an embodiment of the present invention provides an optional implementation, please refer to the following.

[0061] The trigger unit 20 is used to detect the current voltage at the output terminal of the charge pump 10 .

[0062] It should be understood that in the embodiment of the present invention, the trigger unit 20 can detect the current voltage at the output end of the charge pump 10, that is, the voltage at point C in the figure.

[0063] The trigger unit 20 is used to determine that a first trigger condition is satisfied when the current voltage is lower than a first voltage threshold.

[0064] It should be understood that when the charge pump 10 stops working, the voltages at point A, point B, and point C shown in the figure will all drop and have a certain correlation. In an optional scenario, the output end of the charge pump can also be connected to other component units, or multiple voltage holding circuits share a charge pump. Point C is located at the output end of the charge pump 10, and its voltage change is most obvious, which is easier to monitor, so the current voltage at the output end of the charge pump 10 is detected, and based on this, it is determined whether the trigger condition is met.

[0065] It should be noted that if the current voltage at the output end of the charge pump 10 (point C voltage) is lower than the first voltage threshold, the input end voltage (point A voltage) of the voltage holding unit 30 has dropped to the third voltage threshold, and it is determined that the first trigger condition is met.

[0066] The trigger unit 20 is used to determine that a second trigger condition is satisfied when the current voltage reaches a second voltage threshold.

[0067] It should be noted that if the current voltage at the output of the charge pump 10 (voltage at point C) reaches the second voltage threshold, the input voltage of the voltage holding unit 30 (voltage at point A) has risen to the fourth voltage threshold, and the second trigger condition is determined to be met.

[0068] The first voltage threshold may be, but is not limited to, 5.7V, and the second voltage threshold may be, but is not limited to, 6V.

[0069] Based on the foregoing, regarding how to determine whether a rising trigger condition is met, an embodiment of the present invention provides an optional implementation, please refer to the following.

[0070] The trigger unit 20 is used to record the start-up interval duration of the charge pump 10 , and when the start-up interval duration is equal to the first time threshold, it is determined that the first trigger condition is met.

[0071] When the charge pump 10 stops working, the input voltage (point A voltage) of the voltage holding unit 30 slowly decreases. When the start interval is equal to the first time threshold, the input voltage (point A voltage) of the voltage holding unit 30 has dropped to the third voltage threshold, and it is determined that the first trigger condition is met.

[0072] The trigger unit 20 is used to record the continuous start-up time of the charge pump 10, and when the continuous start-up time is equal to the second time threshold, it is determined that the second trigger condition is met.

[0073] When the charge pump 10 starts working and enters the startup state, the input voltage (point A voltage) of the voltage holding unit 30 rises rapidly. When the continuous startup time is equal to the second time threshold, the input voltage (point A voltage) of the voltage holding unit 30 has risen to the fourth voltage threshold, and it is determined that the second trigger condition is met.

[0074] The start interval duration indicates the duration from the last time the charge pump 10 entered the rest state to the current time, and the continuous start duration indicates the duration from the last time the charge pump 10 entered the start state to the current time.

[0075] Based on the above, regarding how to achieve voltage maintenance, the embodiment of the present invention also provides an optional implementation method, please refer to Figure 2 , Figure 2 This is the second voltage holding circuit provided in the embodiment of the present invention.

[0076] The voltage holding unit 30 includes a first capacitor C1 and an NMOS transistor M1.

[0077] At the connection between one electrode of the first capacitor C1 and the gate of the NMOS transistor M1 , a connection terminal is led out as an input end of the voltage holding unit 30 for connecting the second end of the first switch unit K1 .

[0078] The other electrode of the first capacitor C1 is grounded, the drain of the NMOS transistor M1 is connected to the output end of the charge pump 10 , and the source of the NMOS transistor M1 is connected to the DNW array 40 .

[0079] During a time period when the first switch unit K1 & the second switch unit K2 are disconnected, since the gate of the NMOS tube M1 has a small turn-off current, the first capacitor C1 can ensure that during a time period when the first switch unit K1 & the second switch unit K2 are disconnected, the voltage at point A will not be too low and will be within a reasonable range.

[0080] In some scenarios, the voltage at the output of the charge pump 10 may exceed the first target voltage interval corresponding to the voltage holding unit 30. In this case, regarding how to implement voltage division regulation, the embodiment of the present invention also provides an optional implementation method, please continue to refer to Figure 2 .

[0081] The voltage holding circuit further includes a first resistor R1, a second resistor R2 and a second switch unit K2.

[0082] One end of the first resistor R1 is connected to the second end of the first switch unit K1, the other end of the first resistor R1 is connected to one end of the second resistor R2, and the other end of the second resistor R2 is grounded;

[0083] One end of the second switch unit K2 is connected to a connection terminal between the first resistor R1 and the second resistor R2, and the other end of the second switch unit K2 is connected to an input end of the voltage holding unit 30;

[0084] The trigger unit 20 is connected to the control end of the second switch unit K2 , and is used to control the second switch unit K2 to maintain a consistent state with the first switch unit K1 .

[0085] That is, when the first switch unit K1 is in a closed state, the second switch unit K2 is also in a closed state, and when the first switch unit K1 is in an open state, the second switch unit K2 is also in an open state.

[0086] On the basis of the above, regarding how to further avoid false triggering of the voltage holding function, the embodiment of the present invention also provides an optional implementation method, please refer to Figure 3 , Figure 3 This is the third voltage holding circuit provided in the embodiment of the present invention.

[0087] The voltage holding unit 30 further includes a third switching unit K3 .

[0088] A first end of the third switch unit K3 is connected to the output end of the charge pump 10 , and a second end of the third switch unit K3 is connected to the drain of the NMOS transistor M1 .

[0089] The control end of the third switch unit K3 can be connected to the trigger unit 20 or other control units. Under the control of the trigger unit 20 or other control units, the third switch unit K3 can switch its state.

[0090] When the electronic device deploying the voltage holding circuit is in the standby mode, the third switch unit K3 is in a closed state.

[0091] When the electronic device is in the working mode, the third switch unit K3 is in the off state.

[0092] An embodiment of the present invention further provides a system on chip, which includes a memory and the above-mentioned voltage holding circuit.

[0093] An embodiment of the present invention further provides an electronic device, which includes the above-mentioned system on chip. The electronic device can be, but is not limited to, a portable sensor device, a mobile phone device, a computer device, a server device, and the like.

[0094] In summary, an embodiment of the present invention provides a voltage holding circuit and a system on chip, wherein the voltage holding circuit includes a charge pump, a trigger unit, a first switch unit, and a voltage holding unit; the trigger unit is connected to the control end of the charge pump and the first switch unit respectively; the first end of the first switch unit is connected to the output end of the charge pump, and the second end of the first switch unit is connected to the voltage holding unit; the voltage holding unit is also used to connect the DNW array of the memory. By controlling the charge pump to work or rest, the input voltage of the voltage holding unit is within the first target voltage range, so that the voltage of the parasitic capacitor of the DNW array is maintained within the second target voltage range. When the memory needs to be read and written, the power supply voltage of the electronic device can quickly increase the memory to the working voltage, thereby quickly responding to the read and write operations of the memory and ensuring low power consumption in standby mode.

[0095] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

[0096] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A voltage holding circuit, characterized in that: The voltage holding circuit comprises a charge pump, a trigger unit, a first switch unit and a voltage holding unit; The trigger unit is connected to the control end of the charge pump and the control end of the first switch unit respectively; A first end of the first switch unit is connected to the output end of the charge pump, and a second end of the first switch unit is connected to the voltage holding unit; The voltage holding unit is also used to connect to the DNW array of the memory.

2. The voltage holding circuit according to claim 1, wherein: The trigger unit is used to send a start signal to the charge pump when a first trigger condition is met, and control the first switch unit to switch to a closed state, so that the charge pump charges the voltage holding unit to keep the input terminal voltage of the voltage holding unit within a first target voltage range; The trigger unit is used for sending a rest signal to the charge pump and controlling the first switch unit to switch to an off state when a second trigger condition is met; The voltage maintaining unit is used to charge the DNW array so that the voltage of the parasitic capacitor of the DNW array is maintained within a second target voltage range.

3. The voltage holding circuit according to claim 2, characterized in that: The first trigger condition being met indicates that the input voltage of the voltage holding unit drops to a third voltage threshold, and the third voltage threshold is the lower limit of the first target voltage range; The satisfaction of the second trigger condition indicates that the voltage at the input end of the voltage holding unit rises to a fourth voltage threshold, and the fourth voltage threshold is the upper limit of the first target voltage range.

4. The voltage holding circuit according to claim 2, wherein: The trigger unit is used to detect the current voltage of the output end of the charge pump; The trigger unit is used to determine that the first trigger condition is met when the current voltage is lower than the first voltage threshold; The trigger unit is used to determine that the second trigger condition is met when the current voltage reaches a second voltage threshold.

5. The voltage holding circuit according to claim 2, wherein: The trigger unit is used to record the start-up interval duration of the charge pump, and when the start-up interval duration is equal to the first time threshold, determine that the first trigger condition is met; The trigger unit is used to record the continuous start-up time of the charge pump, and when the continuous start-up time is equal to the second time threshold, determine that the second trigger condition is met; The start-up interval duration indicates the duration from the last time the charge pump entered the rest state to the current time, and the continuous start-up duration indicates the duration from the last time the charge pump entered the start-up state to the current time.

6. The voltage holding circuit according to any one of claims 1 to 5, characterized in that: The voltage holding unit includes a first capacitor and an NMOS tube; At the connection between one electrode of the first capacitor and the gate of the NMOS tube, a connection terminal is led out as an input end of the voltage holding unit, which is used to connect the second end of the first switch unit; The other electrode of the first capacitor is grounded, the drain of the NMOS tube is connected to the output end of the charge pump, and the source of the NMOS tube is connected to the DNW array.

7. The voltage holding circuit according to claim 6, wherein: The voltage holding circuit further includes a first resistor, a second resistor and a second switch unit; One end of the first resistor is connected to the second end of the first switch unit, the other end of the first resistor is connected to one end of the second resistor, and the other end of the second resistor is grounded; One end of the second switch unit is connected to a terminal connected between the first resistor and the second resistor, and the other end of the second switch unit is connected to an input end of the voltage holding unit; The trigger unit is connected to the control end of the second switch unit, and the trigger unit is used to control the second switch unit to maintain a consistent state with the first switch unit.

8. The voltage holding circuit according to claim 6, wherein: The voltage holding unit further includes a third switch unit; A first end of the third switch unit is connected to the output end of the charge pump, and a second end of the third switch unit is connected to the drain of the NMOS tube.

9. The voltage holding circuit according to claim 8, characterized in that: When the electronic device deploying the voltage holding circuit is in a standby mode, the third switch unit is in a closed state; When the electronic device is in working mode, the third switch unit is in an off state.

10. A system on chip, characterized in that: The system on chip comprises a memory and the voltage holding circuit according to any one of claims 1 to 9.

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