A multi-mode temperature correction scheme for resistive random access memory

Abstract

The application discloses a multi-mode temperature correction scheme for resistive switching memory, which firstly performs mathematical modeling on the temperature characteristics of a resistive switching device, deduces a relationship between column current and actual current of a memory array, and then obtains a corresponding temperature correction formula to correct the reading current. The correction scheme is suitable for both single-device selection mode and multi-device selection mode, and can effectively improve the reliability of memory reading under high temperature conditions. The application further introduces a parallel structure to save the additional time cost caused by implementing the correction scheme. The application has important value in high-density storage and computing-in-memory applications.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor devices and integrated circuits, and specifically relates to a multi-mode temperature correction scheme for resistive random access memory. Background Technology

[0002] Among numerous emerging memory technologies, resistive random access memory (RRAM) has demonstrated great potential in improving chip area and power efficiency due to its advantages such as ease of multi-value storage, low power consumption, non-volatility, and high integration, making it of significant technical value in data storage and in-memory computing applications. However, with the rapid development of memory chips towards high storage density and three-dimensional integration, the heat generation problem faced by RRAM is becoming increasingly prominent. As its basic unit, the resistive switching device's conductance is highly sensitive to temperature changes; temperature rise significantly causes conductance shift, resulting in a strong dependence of the gate current of the memory array on temperature. This phenomenon seriously affects the stability and reliability of read operations, becoming one of the key factors hindering its large-scale application. Therefore, designing a general temperature correction scheme for RRAM is particularly important, and its design mainly faces the following two challenges. First, the device itself has complex temperature characteristics: research has found that resistive switching devices exhibit semiconductor-like temperature characteristics in the low conductance state, i.e., conductance is positively correlated with temperature; while in the high conductance state, they exhibit metal-like temperature characteristics, i.e., conductance is negatively correlated with temperature. Secondly, the memory needs to meet the requirements of multi-mode applications. For example, in in-memory computing applications, the memory needs to flexibly switch between single-device gating and multi-device gating modes. Mathematical modeling of the temperature characteristics of the resistive switching device is performed to derive the relationship between the column current and the actual current, thereby obtaining the corresponding temperature correction formula. Summary of the Invention

[0003] To address the issue of decreased reliability and stability of resistive random access memory (RSM) with increasing temperature, this invention proposes a multi-mode temperature correction scheme for RSM. This correction scheme effectively improves the reliability of memory reads under high-temperature conditions and is applicable to both single-device gating and multi-device gating modes.

[0004] To achieve the above objectives, the present invention adopts the following technical solution:

[0005] For a memory array composed of m×n resistive switching devices (m and n are positive integers), a mathematical model of the temperature characteristics of a single resistive switching device is first performed. Temperature characteristic curves for each resistive state of the device are obtained through testing. From the characteristic curves, it can be found that within a local temperature range, the relationship between the conductance and temperature of a certain resistive state can be linearized. The resulting model formula is shown below:

[0006]

[0007] Where T is any temperature, T0 is the rated operating temperature, and G ij Let be the conductance of the cell device in the i-th row and j-th column of the memory array at temperature T0. Let β and G be the conductance values ​​of the cell device in the i-th row and j-th column of the memory array at temperature T. M These are constants extracted from the temperature characteristic curves of the resistive switching device at each resistance state obtained from testing. They are only related to the resistive switching device itself. 1≤i≤m, 1≤j≤n.

[0008] Furthermore, in the memory array, during a read operation, the word lines (WL) of all devices to be read are set high; each read voltage is input via the bit line (BL) and applied to the resistive switching device in the cell containing the high-level WL address, forming a current, and thus forming a total current output on the source line (SL). According to Ohm's law and Kirchhoff's laws, the expression for the current in the j-th column of SL is as follows:

[0009]

[0010] Where p is the number of resistive switching devices simultaneously selected in the j-th column, 1≤p≤m, and is 1 in single-device mode. V i I is the reading voltage input in the i-th row. j Let be the current value of the j-th column of the memory array at temperature T0. Let be the current value of the j-th column of the memory array at temperature T. Combining the above equations, we can obtain... and I j The relationship is that the purpose of temperature correction is to accurately obtain the current I at the rated operating temperature T0 at any temperature T. j Therefore, the corrective formula obtained is as follows:

[0011]

[0012] The significance of this correction formula lies in the fact that, due to G M Since β and T0 are constants, regardless of the operating temperature, it can be determined solely from the current state. State I at rated operating temperature j This effectively suppresses the effects of temperature. This invention names it Correction Formula 1.0.

[0013] In most cases, the reading voltage is a constant value V, thus correction formula 1.0 can be simplified to:

[0014]

[0015] This correction formula 1.0 can also be written in the form of compensation amount, and the calculation is performed when using... with I jWhen compensating for the difference, the formula is as follows:

[0016]

[0017] Furthermore, the temperature characteristics of resistive switching devices can also be extended nonlinearly, and the resulting correction formula is as follows:

[0018]

[0019] Among them, g (k) (G M The term is a higher-order nonlinear term, which can also be extracted from the conductance versus temperature characteristic curve of the resistive switching device. Since the calculation of this correction formula is complex, we consider replacing the higher-order term with a semi-empirical quantity. The final simplified and combined correction formula is as follows:

[0020]

[0021] Where ε is an empirical constant, different from β and G. M This value is not directly extracted from the characteristic curve, but requires manual testing and calibration, and may vary between different resistive switching devices. This nonlinear correction formula, at the cost of additional manual labor, yields a more accurate temperature correction effect compared to correction formula 1.0, and this invention names it correction formula 2.0.

[0022] Furthermore, adapting to the proposed correction formula, this invention proposes a multi-mode, general-purpose, low-cost control strategy for operating the memory array. This strategy employs parallel processing, effectively reducing the additional overhead of obtaining the current state and calculating the formula, and is easy to integrate on-chip into the correction scheme.

[0023] Specifically, this invention proposes an implementation method for the above-mentioned temperature correction scheme on a resistive random access memory chip, comprising:

[0024] 1) The input signal is generated by the DAC module;

[0025] 2) The decoder selects one or more resistive switching devices in the memory array;

[0026] 3) The column current is read by the readout module;

[0027] 4) Based on the above correction formula, the results of the readout module are corrected;

[0028] 5) Output the corrected result to the target register.

[0029] To reduce time overhead and ensure real-time temperature readings to improve calibration accuracy, a parallel step is introduced between input signal generation and calibration execution. This involves calculating the sum of the input quantities and multiplying it by a factor G.M β or (G M -ε)β, derive the intermediate quantities required for the correction formula calculation in advance. or At the same time, the current temperature T is read in parallel through the temperature sensing module.

[0030] The beneficial effects of this invention are as follows: This invention mathematically models the temperature characteristics of resistive switching devices, derives the relationship between the column current and the actual current of the memory array, and then obtains the corresponding temperature correction formula. This formula is applicable to both single-device gating and multi-device gating modes, effectively improving the reliability of memory reads under high-temperature conditions. Furthermore, the introduction of a parallel structure saves the additional time overhead associated with implementing this correction scheme. This is of significant value in high-density storage and in-memory computing applications. Attached Figure Description

[0031] Figure 1 These are the temperature characteristic curves of the resistive switching device used in the embodiments of the present invention for each resistive state.

[0032] Figure 2 This is a schematic diagram of parameter extraction based on temperature characteristic curves in the embodiment.

[0033] Figure 3 This is a schematic diagram of a memory array composed of m×n resistive switching devices in an embodiment of the present invention.

[0034] Figure 4 The control flowchart for applying a temperature correction scheme to the operation of the memory array.

[0035] Figure 5 This is a schematic diagram illustrating the correction effect of the single-device gating mode in the embodiment.

[0036] Figure 6 This is a schematic diagram illustrating the correction effect of the multi-device gating mode at different temperatures in the embodiment.

[0037] Figure 7 The diagram shows the correction effects of the temperature correction scheme based on correction formula 1.0, the temperature correction scheme based on correction formula 2.0, and the no-correction scheme under the multi-device selection mode in the embodiment. Among them, (a) shows the distribution of current error of the three at the operating temperature, and (b) shows the relationship between the read current and the actual current of the three. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of this invention clearer, the multi-mode temperature correction scheme of this invention will be clearly and completely described below with reference to the accompanying drawings and embodiments. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0039] Figure 1 This section presents the temperature characteristic curves of each resistive state of the resistive switching device used in this embodiment. Each resistive switching device uses 4 bits for multi-value storage. Specifically, within a conductance range of 5 μS to 245 μS, a resistive state is set sequentially at 16 μS intervals, for a total of 16 resistive states. Then, for each resistive state, 10 devices are programmed to that state, with temperatures ranging from 25°C to 145°C in 20°C increments. The conductance of these devices is read at each temperature. The results are summarized as follows: Figure 1 The temperature characteristic curves for each resistance state shown reveal that the conductance of the resistive switching device deviates significantly from its value at normal temperatures as the temperature increases. Specifically, in the low resistance state region, i.e. Figure 1 In the lower half, the conductivity increases with increasing temperature; in the high-resistivity region, i.e. Figure 1 In the upper part, the conductivity decreases as the temperature increases. This change in conductivity alters the current read when the device is selected, thus affecting the reliability of the readout results.

[0040] Figure 2 This is a schematic diagram of parameter extraction based on the temperature characteristic curve. The horizontal axis represents the current conductance, and the vertical axis represents the conductance gradient with respect to temperature, which can be obtained from the temperature characteristic curve. The parameters required for implementing this correction formula are β and G. M Both can be extracted from this graph: For the original data, performing linear regression analysis, the gradient of the resulting line is β, and the x-intercept is G. M .

[0041] ε is an empirical constant, which can be obtained through additional calibration tests. In this embodiment, the method is as follows: A memory cell is randomly selected in the memory array, and the resistive switching device in that cell is programmed to an arbitrary conductance. First, the current is read at the rated operating temperature T0, and then again at a higher temperature T. Different values ​​of ε are tried, and correction is performed according to correction formula 2.0 to obtain the ε value that makes the corrected current closest to the current read at the rated operating temperature. The above steps are repeated, and the statistical distribution of all ε values ​​is obtained. The mean of these values ​​is used as the final empirical constant ε for correction formula 2.0. In this embodiment, the measured value is approximately -13.5 μS.

[0042] Figure 3This is a schematic diagram of a resistive switching memory (RSM) array. Each cell's resistive switching device adopts a more general 1T1R structure with three buses: the bit line (BL), the source line (SL), and the word line (WL). To support both single-device and multi-device selection, WL is set parallel to SL, and BL is perpendicular to WL. In all applications, the decoders for WL and SL are multiplexed, meaning they use the same address. In single-device mode, BL and WL each select one address via their decoders; that is, a voltage signal is input on one bus, current flows through the resistive switching device, and the current is output at the SL terminal, subsequently processed by the readout circuit. In multi-device mode, BL and WL can select multiple rows of addresses, meaning voltage signals are input on multiple buses. For each SL, according to Kirchhoff's laws, its current is the sum of the currents of all the resistive switching devices connected to it. In in-memory computing applications, the signal on BL is the input vector (I), and the weight matrix (W) is stored in the memory array. Through multi-device mode operation, the current on SL is the result of matrix-vector multiplication (O = I × W), which greatly accelerates the computational efficiency. However, because the resistive switching device storing the weights is temperature sensitive, ... Figure 3 As shown in the figure, the conductivity at temperature T is... A significant deviation from the conductance G at the rated operating temperature T0 leads to inaccurate output results, which in turn seriously affects the reliability of the memory.

[0043] according to Figure 4 The flowchart shown illustrates the operation of the temperature correction scheme of this invention on a resistive random access memory chip. The main steps are as follows:

[0044] (1) The input signal is generated by the DAC module;

[0045] (2) The decoder selects one or more resistive switching devices in the memory array;

[0046] (3) Read the column current using ADC / SA or other readout modules;

[0047] (4) Based on the correction formula, the results of the readout module are corrected;

[0048] (5) Output the corrected result to the target register.

[0049] To reduce the additional overhead of the correction scheme, additional steps are introduced in parallel based on the above steps: First, between the generation of the input signal and the implementation of the correction, the sum of the input quantities is calculated (this operation is omitted in single-device mode), and multiplied by a factor G. M β or (G M -ε)β, this operation allows us to obtain the intermediate quantities needed for the correction formula calculation in advance. or Firstly, it reduces time overhead; secondly, it reads the temperature data generated by the temperature sensing module in parallel. This operation reduces the additional time cost of communicating with the module and ensures the real-time temperature reading to improve the accuracy of the calibration.

[0050] Figure 5 This diagram illustrates the calibration effect using Calibration Formula 2.0 in single-device gating mode. The left half is a heatmap of read accuracy versus conductance and temperature without calibration, and the right half is a heatmap after calibration. Colors indicate read accuracy, with blue representing higher accuracy and red representing lower accuracy. Results show that the area of ​​the red region in the graph significantly decreased after calibration, demonstrating the effectiveness of the calibration scheme in single-device gating mode.

[0051] Figure 6 This diagram illustrates the correction effect at different temperatures using correction formula 2.0 in multi-device selection mode. The implementation scheme involves 4-bit random programming of the memory array, simultaneously selecting 64 rows during each operation. Therefore, the column current is the sum of the currents flowing through these 64 resistive switching devices. The current error in the diagram is defined as the difference between the column current at the current temperature and at the rated operating temperature. Before correction, this error increased significantly with increasing temperature; after correction, the error is not only significantly reduced but also noticeably less affected by temperature. Analysis shows that this correction scheme can ultimately achieve an error reduction of 5 to 25 times.

[0052] Figure 7 This diagram illustrates the correction effects of three schemes in multi-device selection mode: one based on correction formula 1.0, one based on correction formula 2.0, and one without correction formula. A temperature of 105℃ is used. The left-hand diagram shows the current error distribution of the three schemes at this temperature, while the right-hand diagram more directly shows the relationship between the read current and the actual current.

Claims

1. A multi-mode temperature correction method for resistive switching memory, wherein for a memory array composed of m×n resistive switching devices, the method corrects the current read at any temperature T based on correction formula 1.0 or correction formula 2.

0. The correction is performed to obtain the corresponding current I at the rated operating temperature T0. j ; in, V i Let p be the reading voltage input in the i-th row, p be the number of resistive switching devices simultaneously selected in the j-th column, and I be the reading voltage input in the i-th row. j Let be the current value of the j-th column of the memory array at the rated operating temperature T0. G represents the current value of the j-th column of the memory array at any temperature T; M β are constants; ε is an empirical constant; 1≤i≤m, 1≤p≤m, 1≤j≤n, and m, n, i, j, and p are all positive integers.

2. The multi-mode temperature correction method as described in claim 1, characterized in that, When the reading voltage is constant, temperature correction is performed using the following formula 1.1: Where V is a constant reading voltage.

3. The multi-mode temperature correction method as described in claim 1, characterized in that, The compensation amount is calculated according to Formula 1.2, and then the read current value is compensated to achieve temperature correction. in, To read the current value The amount of compensation to be provided.

4. The multi-mode temperature correction method as described in any one of claims 1, characterized in that, Extracting parameter G from the temperature characteristic curve of the resistive switching device M β, where the horizontal axis of the temperature characteristic curve represents electrical conductivity, and the vertical axis represents the gradient of electrical conductivity with respect to temperature. A linear regression analysis is performed on the original data, and the gradient of the resulting straight line is β, with the horizontal intercept being G. M .

5. The multi-mode temperature correction method as described in claim 1, characterized in that, The empirical constant ε is obtained by the following method: Randomly select a memory cell in the memory array and program the resistive switching device in the cell to an arbitrary conductance. First, read the current at the rated operating temperature T0, and then read the current again at a high temperature T. Try different values ​​of ε and correct them according to the correction formula 2.0 to obtain the ε value that makes the corrected current closest to the current read at the rated operating temperature. Repeat the above steps and obtain the statistical distribution of all ε values. Let the mean of the distribution be used as the empirical constant ε for the final correction formula 2.

0.

6. A method for implementing the multi-mode temperature correction method according to any one of claims 1 to 5 on a resistive random access memory chip, comprising the following steps: 1) The input signal is generated by the DAC module; 2) The decoder selects one or more resistive switching devices in the memory array; 3) The column current is read by the readout module; 4) The multi-mode temperature correction method according to any one of claims 1 to 5 is used to correct the results of the readout module; 5) Output the corrected result to the target register.

7. The implementation method as described in claim 6, characterized in that, A parallel step is introduced between the generation of the input signal and the implementation of correction: the sum of the input quantities is calculated and multiplied by a factor G. M β or (G M -ε)β, derive the intermediate quantities required for the correction formula calculation in advance. or At the same time, the current temperature T is read in parallel through the temperature sensing module.

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