Vector element multiplication in NAND memory

Abstract

The invention relates to vector element multiplication in NAND memory. The memory may include a plurality of strings of memory cells connected in series, each corresponding to a respective number of a plurality of numbers of a multiplicand, and may further include a controller, the controller is configured to cause the memory to generate a respective current flowing through the plurality of strings of serially connected memory cells for each of a plurality of digits of a multiplier having a respective current level indicative of a value that each of the plurality of digits of the multiplier multiplies by a multiplicand, the respective current level is converted to a respective digital value indicative of each of the plurality of digits of the multiplier multiplied by a value and magnitude of the multiplicand, and the respective digital values of each of the plurality of digits of the multiplier are summed.

Description

[0001] Related Applications

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 590,860, filed on October 17, 2023, the entire contents of which are hereby incorporated by reference herein. Technical Field

[0003] The present disclosure relates generally to integrated circuits and methods of operating the same, and in particular, in one or more embodiments, to memories configured to perform artificial intelligence (AI) computational modes (e.g., including matrix dot products involving vector element multiplications). Background Art

[0004] Integrated circuit devices traverse a wide range of electronic devices. One specific type includes memory devices, often simply referred to as memory. Memory devices are typically provided as internal semiconductor integrated circuit devices in a computer or other electronic device. There are many different types of memory, including random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.

[0005] Flash memory has developed into a ubiquitous source of nonvolatile memory for a wide range of electronic applications. Flash memory typically uses a single-transistor memory cell that allows for high storage density, high reliability, and low power consumption. The change in the threshold voltage (Vt) of the memory cell through programming (which is often referred to as writing) or other physical phenomena (such as phase change or polarization) of a charge storage node (such as a floating gate or a charge trap) determines the data state (such as the data value) of each memory cell. Common uses for flash memory and other nonvolatile memories include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, home appliances, vehicles, wireless devices, mobile phones, and removable memory modules, and the uses of nonvolatile memory continue to expand.

[0006] NAND flash memory is a common type of flash memory device, so it is necessary to arrange a logical form of the basic memory cell configuration. Typically, a memory cell array for NAND flash memory is arranged so that the control gates of each memory cell of a row of the array can be connected together to form an access line (e.g., a word line). The columns of the array include strings of memory cells (commonly referred to as NAND strings) connected in series together between a pair of select gates (e.g., a source select transistor and a drain select transistor). Each source select transistor can be connected to a source, and each drain select transistor can be connected to a data line, such as a column bit line. Variations that use more than one select gate between the memory cell string and the source and / or between the memory cell string and the data line are known.

[0007] An artificial neural network (ANN) may use a network of neurons to process inputs to the network and generate outputs from the network. Typically, an ANN may be trained using supervised and / or unsupervised methods.

[0008] Deep learning can use multiple layers of machine learning to gradually extract features from input data and can be implemented via ANNs (e.g., deep neural networks, deep belief networks, recurrent neural networks, and / or convolutional neural networks). Deep learning has been used in many application areas, such as computer vision, speech / audio recognition, natural language processing, machine translation, bioinformatics, drug design, medical image processing, games, etc. Summary of the invention

[0009] According to an aspect of the present disclosure, a memory is provided. The memory comprises: a plurality of data lines; a common source; a plurality of series-connected memory cell strings, wherein each of the plurality of series-connected memory cell strings is selectively connected to a corresponding data line of the plurality of data lines and selectively connected to the common source, and wherein each of the plurality of series-connected memory cell strings corresponds to a corresponding digit of a plurality of digits of a multiplicand; a plurality of access lines, wherein each of the plurality of access lines is connected to a control gate of a corresponding memory cell of each of the plurality of series-connected memory cell strings; and a controller configured to cause the memory to: for each of a plurality of digits of a multiplier: generate a corresponding current flowing through the plurality of series-connected memory cell strings, the corresponding current having a corresponding current level indicating a value of the digit of the plurality of digits of the multiplier multiplied by the multiplicand; and convert the corresponding current level of the digit of the plurality of digits of the multiplier to a corresponding digital value indicating the value and magnitude of the digit of the plurality of digits of the multiplier multiplied by the multiplicand; and sum the corresponding digital value of each of the plurality of digits of the multiplier.

[0010] According to another aspect of the present disclosure, a memory is provided. The memory includes: a plurality of data lines; a common source; a multiply-accumulate (MAC) register including a plurality of partial product registers and an accumulation register; an analog-to-digital converter (ADC) having an input connected to the common source and having an output connected to the MAC register; a plurality of serially connected memory cell strings, wherein each serially connected memory cell string in the plurality of serially connected memory cell strings is selectively connected to a corresponding data line in the plurality of data lines and selectively connected to the common source, and wherein each serially connected memory cell string in the plurality of serially connected memory cell strings corresponds to a corresponding number of a corresponding element of a corresponding vector of a multiplicand matrix having N vectors, wherein N is a large an integer value greater than or equal to 1; a plurality of access lines, wherein each of the plurality of access lines is connected to a control gate of a corresponding memory cell of each of the plurality of series-connected memory cell strings; and a controller configured to cause the memory to: for an element of one or more elements of a first vector of the multiplicand matrix: generate a current flowing through the plurality of series-connected memory cell strings, the current having a current level indicating a value of the element of the first vector multiplied by a number having one or more numbers of a multiplier; and convert the current level of the element of the first vector into a corresponding digital value indicating the value and magnitude of the element of the first vector multiplied by the number of the multiplier.

[0011] According to another aspect of the present disclosure, a memory is provided. The memory includes: a plurality of data lines; a common source; a multiply-accumulate (MAC) register including a plurality of partial product registers and an accumulation register; an analog-to-digital converter (ADC) having an input connected to the common source and having an output connected to the MAC register; a plurality of serially connected memory cell strings, wherein each serially connected memory cell string in the plurality of serially connected memory cell strings is selectively connected to a corresponding data line in the plurality of data lines and selectively connected to the common source, and wherein each serially connected memory cell string in the plurality of serially connected memory cell strings corresponds to a corresponding digit in a plurality of digits of a multiplicand; a plurality of access lines, wherein each access line in the plurality of access lines is connected to a control gate of a corresponding memory cell in each serially connected memory cell string in the plurality of serially connected memory cell strings; and a controller configured to cause the memory to: apply a set of control signals to the plurality of access lines, the set of control signals being configured to activate the corresponding a plurality of serially connected memory cell strings connected to a common source and configured to store and store memory cells of the plurality of serially connected memory cell strings corresponding to a number of the multiplicand having a first logic level, activate memory cells of the plurality of serially connected memory cell strings not corresponding to any number of the multiplicand, and deactivate memory cells of the plurality of serially connected memory cell strings corresponding to a number of the multiplicand having a second logic level different from the first logic level; apply control signals to the plurality of data lines connected to the plurality of serially connected memory cell strings having voltage levels indicative of the value of a number of a multiplier when the plurality of serially connected memory cell strings are connected to the common source; and convert current levels generated by applying the set of control signals to the plurality of access lines and applying the control signals to the plurality of data lines at the input of the ADC when the plurality of serially connected memory cell strings are connected to the common source and the input of the ADC to corresponding digital values ​​corresponding to the value of the multiplicand multiplied by the number of the multiplier. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a simplified block diagram of a memory in communication with a processor as part of an electronic system according to an embodiment.

[0013] Figure 2A to 2B is a schematic diagram of a portion of a memory cell array according to an embodiment.

[0014] Figures 3A to 3D Depicts a deep learning accelerator connected to a host computer and the various processing units that can be used in the deep learning accelerator.

[0015] Figure 4 Describes the matrix-matrix cell.

[0016] Figure 5 Details the calculation of the matrix-matrix unit.

[0017] Fig. 6A and 6B Depicted is a portion of an array of memory cells configured to store the digits of a multiplicand in analog and binary, respectively, according to an embodiment.

[0018] Figure 7 Depicted is a portion of a memory cell array having a block of memory cells for discussing arithmetic operations according to an embodiment.

[0019] Figures 8A to 8F Depicted are registers during a multiply-accumulate operation according to an embodiment.

[0020] Figures 9A to 9F Depicted are registers during a multiply-accumulate operation according to another embodiment.

[0021] Figures 10 to 12 A representation of the current as a function of a variable of interest.

[0022] Fig.13 is a flowchart of a method of operating a memory according to an embodiment.

[0023] Fig.14 is a flowchart of a method of operating a memory according to another embodiment.

[0024] Fig.15 is a flowchart of a method of operating a memory according to another embodiment.

[0025] Fig.16A is a flowchart of a method of operating a memory according to yet another embodiment.

[0026] Fig. 16B is a flow chart of a method of operating a memory according to an alternative embodiment.

[0027] Fig.17 A portion of a memory cell array having more than one block of memory cells is depicted in accordance with an embodiment. DETAILED DESCRIPTION

[0028] In the following detailed description, reference is made to the accompanying drawings which form a part hereof and in which specific embodiments are shown by way of illustration. In the drawings, the same reference numerals describe substantially similar components throughout the several views. Other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description should not be understood in a limiting sense.

[0029] Unless otherwise apparent from the context, the term "conductive" and its various related forms (e.g., conductive, conductively, conducting, conductive, conductivity, etc.) as used herein refer to electrical conduction. Similarly, unless otherwise apparent from the context, the term "connecting" and its various related forms (e.g., connect, connected, connection, etc.) as used herein refer to electrical connection through a conductive path.

[0030] As used herein, the multiple actions of concurrent execution mean that each of these actions executes a corresponding time period, and each of these corresponding time periods overlaps partially or completely with each of the remaining corresponding time periods. In other words, the parts of each of those actions execute at least some time periods simultaneously.

[0031] Unless otherwise defined, directional references such as upper, top, lower, bottom, side, left, right, parallel, orthogonal, etc. used in the description of the drawings refer to such directions relative to the orientation of the drawings themselves.

[0032] It should be recognized herein that even in cases where the expected values ​​may be equal, the variability and accuracy of industrial processes and operations may result in differences from their expected values. These variability and accuracy will generally depend on the technology utilized in the manufacture and operation of the integrated circuit device. Thus, if the expected values ​​are equal, then those values ​​are considered equal regardless of their resulting values.

[0033] Artificial neural networks (ANNs) can use a network of neurons to process inputs to the network and generate outputs from the network. For example, each neuron in the network can receive a set of inputs. Some inputs to neurons can be outputs of specific neurons in the network; and some inputs to neurons can be inputs provided to the neural network. The input / output relationships among neurons in the network represent neuronal connectivity in the network.

[0034] Each neuron may have a bias, an activation function, and a set of synaptic weights for its inputs. The activation function may be in the form of a step function, a linear function, a log-sigmoid function, etc. Different neurons in the network may have different activation functions.

[0035] Each neuron may produce a weighted sum of its inputs and its bias and then produce an output that is a function of the weighted sum computed using the neuron's activation function.

[0036] In general, the relationship between the input and output of an ANN can be defined by an ANN model, which includes data representing the connectivity of neurons in the network, as well as the bias, activation function, and synaptic weights of each neuron. Based on a given ANN model, a computing device can be configured to calculate the output of the network based on a given set of inputs to the network.

[0037] For example, input to the ANN may be generated based on camera input; and output from the ANN may be recognition of an item (eg, an event or an object).

[0038] In general, ANNs can be trained using supervised methods, where parameters in the ANN are adjusted to minimize or reduce the error between known outputs associated with or resulting from respective inputs and calculated outputs produced via application of the inputs to the ANN. Examples of supervised learning / training methods include reinforcement learning and learning with error correction.

[0039] Alternatively, or in combination, the ANN can be trained using unsupervised methods, where the exact output resulting from a given set of inputs is unknown until training is complete. The ANN can be trained to classify items into multiple categories, or to classify data points into clusters. A variety of training algorithms are available for complex machine learning / training paradigms.

[0040] Deep learning can use multiple layers of machine learning to gradually extract features from input data. For example, lower layers can be configured to identify edges in an image; and higher layers can be configured to identify items captured in the image, such as faces, objects, events, etc., based on the edges detected using the lower layers. Deep learning can be implemented via ANNs, such as deep neural networks, deep belief networks, recurrent neural networks, and / or convolutional neural networks.

[0041] Deep learning has been used in many application areas, such as computer vision, speech / audio recognition, natural language processing, machine translation, bioinformatics, drug design, medical image processing, games, etc.

[0042] The granularity of the DLA for operations on vectors and matrices corresponds to the largest unit of vectors / matrices that can be operated on during the execution of an instruction by the DLA. During the execution of an instruction for a predefined operation on a vector / matrix operand, the elements of the vector / matrix operand can be operated on in parallel by the DLA to reduce the execution time and / or energy consumption associated with memory / data accesses. Operations on vector / matrix operands of DLA granularity can be used as building blocks to implement calculations on vectors / matrices of larger sizes.

[0043] The implementation of a typical / practical ANN involves vector / matrix operands of a size larger than the computational granularity of the DLA. To implement such an ANN using the DLA, computations involving large-sized vector / matrix operands may be decomposed into computations of vector / matrix operands of the DLA granularity. The DLA may be programmed via instructions to perform computations involving large vector / matrix operands. For example, the atomic computational capabilities of the DLA to manipulate vectors and matrices of the DLA granularity in response to instructions may be programmed to implement computations in the ANN.

[0044] In some embodiments, the DLA lacks some of the logic operation capabilities of a typical central processing unit (CPU). However, the DLA can be configured with sufficient logic units to process input data provided to the ANN and generate the output of the ANN according to a set of instructions generated for the DLA. Thus, the DLA can perform the calculations of the ANN with little or no assistance from the CPU or another processor. Optionally, a conventional general-purpose processor can also be configured as part of the DLA to perform operations that cannot be effectively implemented using and / or cannot be performed by the vector / matrix processing unit of the DLA.

[0045] A typical ANN may be described / specified in a standard format, such as Open Neural Network Exchange (ONNX). A compiler may be used to convert the description of the ANN into a set of instructions that cause DLA to perform ANN calculations. The compiler may optimize the set of instructions to improve the performance of DLA when implementing the ANN.

[0046] The DLA may have local storage devices, such as registers, buffers, and / or caches, which are configured to store vector / matrix operands and results of vector / matrix operations. Intermediate results in registers can be pipelined / shifted in the DLA as operands for subsequent vector / matrix operations to reduce the time and energy consumption of accessing memory / data, and thereby speed up the typical mode of implementing vector / matrix operations in a typical ANN. The capacity of registers, buffers, and / or caches in the DLA is generally insufficient to hold the entire data set for implementing the calculations of a typical ANN. Therefore, a random access memory coupled to the DLA may be configured to provide improved data storage capabilities for implementing a typical ANN. For example, the DLA may load data and instructions from the random access memory and store the results back in the random access memory.

[0047] Various embodiments described herein seek to facilitate the performance of artificial neural network (ANN) computations within a NAND memory array.Such embodiments may be used as a matrix-matrix unit, a matrix-vector unit, and / or a vector-vector unit of a DLA.

[0048] Figure 11 is a simplified block diagram of a first device (in the form of a memory (e.g., memory device) 100) communicating with a second device (in the form of a processor 130) as part of a third device (in the form of an electronic system) according to an embodiment. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, home appliances, vehicles, wireless devices, mobile phones, and the like. Processor 130 (e.g., a controller external to memory device 100) may be a memory controller or other external host device.

[0049] Memory device 100 includes a memory cell array 104 that may be logically arranged in rows and columns. According to one or more embodiments, memory cell array 104 may contain a memory array structure. Memory cells of a logical row are typically connected to the same access line (commonly referred to as a word line), while memory cells of a logical column are typically selectively connected to the same data line (commonly referred to as a bit line). A single access line may be associated with more than one logical row of memory cells, and a single data line may be associated with more than one logical column. Memory cells of at least a portion of memory cell array 104 ( Figure 1 ) can be programmed to one of at least two target data states.

[0050] Row decoding circuitry 108 and column decoding circuitry 110 are provided to decode address signals. Address signals are received and decoded to access memory cell array 104. Memory device 100 also includes input / output (I / O) control circuitry 112 for managing the input of commands, addresses, and data to memory device 100, and the output of data and status information from memory device 100. Address registers 114 communicate with I / O control circuitry 112 and row decoding circuitry 108 and column decoding circuitry 110 to latch address signals prior to decoding. Command registers 124 communicate with I / O control circuitry 112 and control logic 116 to latch incoming commands.

[0051] A controller (e.g., control logic 116 inside the memory device 100) controls access to the memory cell array 104 in response to commands and may generate status information for the external processor 130, i.e., the control logic 116 is configured to perform access operations (e.g., sensing operations [which may include read operations and verification operations], programming operations, and / or erase operations) on the memory cell array 104. The control logic 116 communicates with the row decoding circuitry 108 and the column decoding circuitry 110 to control the row decoding circuitry 108 and the column decoding circuitry 110 in response to addresses. The control logic 116 may include an instruction register 128, which may represent a computer-usable memory for storing computer-readable instructions. For some embodiments, the instruction register 128 may represent firmware. Alternatively, the instruction register 128 may represent a grouping of memory cells of the memory cell array 104, such as a reserved block of memory cells. The control logic 116 may be configured to, for example, in response to such computer-readable instructions, cause the memory 100 to perform the method of one or more embodiments.

[0052] The control logic 116 may further communicate with a cache register 118. The cache register 118 latches incoming or outgoing data to temporarily store the data while the memory cell array 104 is busy writing or reading other data (respectively) according to the direction of the control logic 116. During a programming operation (e.g., a write operation), data may be transferred from the cache register 118 to the data register 120 for transmission to the memory cell array 104; then, the new data may be latched in the cache register 118 from the I / O control circuitry 112. During a read operation, data may be transferred from the cache register 118 to the I / O control circuitry 112 for output to the external processor 130; then, the new data may be transferred from the data register 120 to the cache register 118. The cache register 118 and / or the data register 120 may form a page buffer of the memory device 100 (e.g., may form part of a page buffer). The page buffer may further include a sensing device (eg, a sensing device) for sensing the data state of a memory cell in the memory cell array 104, such as by sensing the state of a data line connected to the memory cell. Figure 1 1 . The status register 122 may communicate with the I / O control circuitry 112 and the control logic 116 to latch status information for output to the processor 130.

[0053] The control logic 116 may further communicate with a multiply-accumulate (MAC) register 136. The MAC register 136 may represent a volatile memory, latch, or other storage location, for example, volatile or non-volatile. For some embodiments, the MAC register 136 may represent a portion of the data register 120 and / or the cache register 118. The MAC register 136 may further communicate with one or more analog-to-digital converters, as will be depicted in subsequent figures. The MAC register 136 may be configured to store partial products of one or more multiplication operations of elements of a vector of a vector-vector operation, and the corresponding sums of the multiplication operations. The MAC register 136 may further be configured to store dot products of vector-vector operations.

[0054] The memory device 100 receives control signals from the processor 130 via a control link 132 at the control logic 116. The control signals may include chip enable CE#, command latch enable CLE, address latch enable ALE, write enable WE#, read enable RE#, and write protect WP#. Depending on the nature of the memory device 100, additional or alternative control signals (not shown) may be further received via the control link 132. The memory device 100 receives command signals (which represent commands), address signals (which represent addresses), and data signals (which represent data) from the processor 130 via a multiplexed input / output (I / O) bus 134 and outputs data to the processor 130 via the I / O bus 134.

[0055] For example, a command may be received at the I / O control circuitry 112 via input / output (I / O) pins [7:0] of the I / O bus 134 and then may be written into the command register 124. An address may be received at the I / O control circuitry 112 via input / output (I / O) pins [7:0] of the I / O bus 134 and then may be written into the address register 114. Data may be received at the I / O control circuitry 112 via input / output (I / O) pins [7:0] of an 8-bit device or input / output (I / O) pins [15:0] of a 16-bit device and then may be written into the cache register 118. The data may then be written into the data register 120 to program the memory cell array 104. For another embodiment, the cache register 118 may be omitted and the data may be written directly into the data register 120. Data may also be output through input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices. Although reference may be made to I / O pins, they may include any conductive node that provides electrical connection to the memory device 100 by an external device (e.g., processor 130), such as a commonly used conductive pad or conductive bump.

[0056] Those skilled in the art will appreciate that additional circuitry and signals may be provided and simplified. Figure 1 It should be appreciated that the reference Figure 1 The functionality of the various block components described may not necessarily be separated into distinct components or component portions of an integrated circuit device. For example, a single component or component portion of an integrated circuit device may be adapted to perform Figure 1 Alternatively, one or more components or component parts of an integrated circuit device may be combined to perform Figure 1 The functionality of a single block component.

[0057] Additionally, while specific I / O pins are described according to popular conventions for receiving and outputting various signals, it should be noted that other combinations or numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0058] Figure 2A is according to the embodiment as can be used for reference Figure 1 Schematic diagram of a portion of a memory cell array 200A (eg, a NAND memory array) in a memory of the type described. The memory cell array 200A includes access lines (eg, word lines) 202 0 To 202 N and data lines (e.g., bit lines) 204. The memory cell array 200A may be arranged into rows (each corresponding to an access line 202) and columns (each corresponding to a data line 204). Each column may include a string of memory cells (e.g., nonvolatile memory cells) connected in series, such as a NAND string 206. 0 To 206 M Each NAND string 206 may be connected (eg, selectively connected) to a common source (SRC) 216 and may include a memory cell 208. 0 To 208 N Memory unit 208 may represent a non-volatile memory unit used for data storage.

[0059] The memory cells 208 of each NAND string 206 may be connected in series to a select gate 210 (eg, a field effect transistor). 0 To 210 M ) and a selection gate 212 (eg, a field effect transistor) (eg, a selection gate 212 0 To 212 M Select gate 210 0 To 210 M The select gates 212 may be connected to a select line 214 (eg, a source select line (SGS)). 0 To 212M can be connected to different selection lines 215 (eg, selection line 215 0 To 215 M ). The control gate of each select gate 210 may be connected to a select line 214. The control gate of each select gate 212 may be connected to a select line 215. As used herein, a field effect transistor (eg, an integrated circuit device that uses an electric field to control the flow of current) may alternatively be referred to simply as a transistor.

[0060] The source of each select gate 210 may be connected to a common source (SRC) 216. The drain of each select gate 210 may be connected to a memory cell 208 of a corresponding NAND string 206. For example, the select gate 210 0 The drain of the NAND string 206 may be connected to the corresponding 0 The memory unit 208 0 Thus, each select gate 210 of a corresponding NAND string 206 may be configured to selectively connect the NAND string 206 to the common source 216.

[0061] The drain of each select gate 212 can be connected to the data line 204. The source of each select gate 212 can be connected to the memory cell 208 of the corresponding NAND string 206. For example, the select gate 212 0 The source of the NAND string 206 may be connected to the corresponding 0 The memory unit 208 N Thus, each select gate 212 corresponding to a NAND string 206 can be configured to selectively connect that NAND string 206 to a data line 204 .

[0062] The access line 202 and the select lines 214 and 215 may be formed around the channel material structures 244. Each channel material structure 244 may contain channel material that forms the select gate 210, the select gate 212, and the channel of each memory cell 208 of its corresponding NAND string 206. For example, the channel material structure 244 0 A gate 210 may be formed for selecting 0 , select gate 212 0 and NAND string 206 0 Each memory cell 208 0 To 208 N channel.

[0063] The typical construction of memory cell 208 includes a data storage structure 234 (e.g., including a floating gate, a charge trap, or other structure configured to store charge) that can determine the data state of the memory cell (e.g., through a change in threshold voltage), and a control gate 236, such as Figure 2A2. The data storage structure 234 may include conductive structures and / or dielectric structures, while the control gate 236 is typically formed of one or more conductive materials. In some cases, the memory cell 208 may further have a defined source / drain (e.g., source) 230 and a defined source / drain (e.g., drain) 232. The memory cell 208 has its control gate 236 connected to (and in some cases formed of) the access line 202.

[0064] Columns of memory cells 208 may be NAND strings 206 or multiple NAND strings 206 selectively connected to a given data line 204. Rows of memory cells 208 may be memory cells 208 commonly connected to a given access line 202. A row of memory cells 208 may (but need not) include all memory cells 208 commonly connected to a given access line 202. Rows of memory cells 208 may generally be divided into one or more physical page groups of memory cells 208, and a physical page of memory cells 208 generally includes every other memory cell 208 commonly connected to a given access line 202. Other groupings of memory cells 208 commonly connected to a given access line 202 may also define a physical page of memory cells 208. For a particular memory device, all memory cells commonly connected to a given access line 202 may be considered a physical page of memory cells. The portion of a physical page of memory cells that is read during a single read operation or programmed during a single program operation (which may still be an entire row in some embodiments) (e.g., an upper page or a lower page of memory cells) may be considered a logical page of memory cells. A block of memory cells may include memory cells that are configured to be erased together and may share a common source 216. Unless explicitly distinguished, any reference to a page of memory cells herein refers to the memory cells of a logical page of memory cells.

[0065] Figure 2B Is it available for reference Figure 1 Another schematic diagram of a portion of a memory cell array 200B (eg, as a portion of memory cell array 104) in a memory of the type described. Figure 2B The same numbered elements in the Figure 2A Description provided. Figure 2BAdditional details of one example of a three-dimensional NAND memory array structure are provided. The three-dimensional NAND memory array 200B can incorporate vertical structures that can include semiconductor pillars that can be solid or hollow, where a portion of the pillar can serve as a channel region for a memory cell of a NAND string 206, e.g., a region through which current can flow when a memory cell (e.g., a field effect transistor) is activated. The NAND strings 206 can each be selectively connected to a data line 204 through a select transistor 212 (e.g., which can be a drain select transistor, commonly referred to as a select gate drain). 0 To 204 M The plurality of NAND strings 206 can be selectively connected to the same data line 204. Subgroups of the NAND strings 206 can be selectively connected to the common source 216 by biasing the select line 215. 0 To 215 K Each particular select transistor 212 between the NAND string 206 and the data line 204 is selectively activated to connect to its corresponding data line 204. The select transistors 210 can be activated by biasing the select line 214. Each access line 202 can be connected to multiple rows of memory cells in the memory array 200B. The rows of memory cells commonly connected to each other by a particular access line 202 can be collectively referred to as a tier.

[0066] The three-dimensional NAND memory array 200B may be formed on a peripheral circuit system 226. The peripheral circuit system 226 may represent various circuit systems for accessing the memory array 200B. The peripheral circuit system 226 may include complementary circuit elements. For example, the peripheral circuit system 226 may include both n-channel region and p-channel region transistors formed on the same semiconductor substrate, a process commonly referred to as CMOS or complementary metal oxide semiconductor. Although CMOS is generally no longer a strict metal oxide semiconductor construction due to advances in integrated circuit manufacturing and design, the CMOS name is retained for convenience.

[0067] Figure 3A A deep learning accelerator 301 is shown connected to a host 313. The deep learning accelerator 301 may include a processing unit 303, a control unit 305, a local storage device 307, and a communication interface 309.

[0068] When vector and matrix operands (e.g., multiplicands and multipliers) are in local storage device 307, control unit 305 may use processing unit 303 to perform vector and matrix operations according to instructions. In addition, control unit 305 may load instructions and / or operands from host 313 through communication interface 309 and connection (e.g., high-speed / bandwidth connection) 311. Host 313 may be any device (e.g., a controller, memory, application specific integrated circuit (ASIC) or other integrated circuit device) capable of providing model data, instructions, and operands as input to DLA 301 and capable of receiving output (e.g., result data) from DLA 301.

[0069] The data access speed of connection 311 may be configured based on the processing speed of DLA 301. For example, after a certain amount of data and instructions have been loaded into local storage 307, control unit 305 may use processing unit 303 to execute instructions that operate on data to produce output. During the period of time that processing is performed to produce output, the access bandwidth of connection 311 may allow the same amount of data and instructions to be loaded into local storage 307 for the next operation, and allow the same amount of output to be stored back to host 313. For example, while control unit 305 uses a portion of local storage 307 to process data and produce output, communication interface 309 may unload the output of the previous operation from another portion of local storage 307 to host 313 and load operand data and instructions into the other portion. Thus, the utilization and performance of DLA 301 is not limited or reduced by the bandwidth of connection 311.

[0070] The host 313 may be used to store model data for the ANN and buffer input data for the ANN. The model data typically does not change frequently. The model data may include output generated by the compiler for the DLA to implement the ANN. The model data typically includes matrices used in the description of the ANN and instructions generated for the DLA 301 to perform vector / matrix operations of the ANN based on vector / matrix operations at the granularity of the DLA 301. The instructions operate not only on the vector / matrix operations of the ANN, but also on the input data of the ANN.

[0071] The processing unit 303 of the DLA 301 may include a vector-vector unit, a matrix-vector unit and / or a matrix-matrix unit. Figures 3B to 3D Examples of units configured to perform vector-vector operations, matrix-vector operations, and matrix-matrix operations are discussed.

[0072] Figure 3B The processing unit of the matrix-matrix unit 321 is shown configured to perform matrix-matrix operations. For example, Figure 3B The matrix-matrix unit 321 can be used as Figure 3AOne of the processing units 303 of the DLA 301.

[0073] exist Figure 3B In the example, the matrix-matrix unit 321 includes a plurality of kernel buffers 331. 1 To 331 V and multiple mapping memory banks 351 1 To 351 V The integer value V may be equal to the size (eg, maximum size) of the matrix to be operated on by the DLA 301. For example, V may represent the number of rows and the number of columns of the matrix.

[0074] Each mapped memory bank 351 1 To 351 V A vector of matrix operands (e.g., rows of matrix multiplicands) may be stored, the matrix operands having respective storage locations in the mapping memory bank 351. 1 To 351 V and each kernel buffer 331 1 To 331 V A vector of another matrix operand (eg, columns of a matrix multiplier) may be stored, the other matrix operand having columns stored in kernel buffer 331, 1 To 331 V The matrix-matrix unit 321 may be configured to use multiple matrix-vector units 341 that can operate in parallel. 1 To 341 V Performs an element-by-element multiplication and accumulation operation on two matrix operands.

[0075] The cross switch 323 can map the memory bank 351 through the multiplexer (MUX) 325. 1 To 351 V Connect to matrix-vector unit 341 1 To 341 V . Stored in the mapped memory bank 351 1 To 351 V The same matrix operands in the above formula can be provided to each matrix-vector unit 341 via the crossbar switch 323. 1 To 341 V , and the matrix-vector unit 341 1 To 341 V Can be parallelized from the mapped memory bank 351 1 To 351 V Receives data elements. Each kernel buffer 331 1 To 331 V Connectable to matrix-vector unit 341 1 To 341 VThe corresponding one in the matrix-vector unit 341 can provide a vector operand to the corresponding matrix-vector unit 341. 1 To 341 V Can concurrently operate to calculate the data stored in the mapped memory bank 351 1 To 351 V The same matrix operand in is multiplied by the matrix stored in kernel buffer 331 1 To 331 V Operations on corresponding vectors in .

[0076] Figure 3B Matrix-Vector Unit 341 in 1 To 341 V Each of the Figure 3C Implemented in the manner described. Figure 3C Matrix-vector unit 341 is shown configured to perform matrix-vector operations. X processing units, where X is any integer value from 1 to V. For example, Figure 3C Matrix-vector unit 341 X Can be expressed Figure 3B Any matrix-vector unit 341 in the matrix-matrix unit 321.

[0077] exist Figure 3C In each mapping memory bank 351 1 To 351 V Similar to Figure 3B Mapped memory bank 351 1 To 351 V A vector of matrix operands is stored in a manner such that the matrix operands are stored in mapping memory banks 351 respectively. 1 To 351 V Multiple vectors in . Figure 3C The crossbar switch 323 in the mapping memory 351 1 To 351 V The vector is provided to the vector-vector unit 361 X1 To 361 XV . Stored in kernel buffer 331 X The same vector in is provided to the vector-vector unit 361 1 To 361 V .

[0078] Vector - Vector Unit 361 1 To 361 V Can concurrently operate to calculate the memory stored in the mapping memory 351 1 To 351 V The corresponding vector operand in is multiplied by the vector operand stored in kernel buffer 331 XOperations on the same vector operand in .

[0079] Figure 3C Vectors in - Vector Unit 361 1 To 361 V Each of the Figure 3D Implemented in the manner described. Figure 3D A vector-vector unit 361 is shown configured to perform vector-vector operations. YZ A processing unit, where Y and Z are independently any integer values ​​from 1 to V. For example, Figure 3D Vector - Vector Unit 361 YZ Can be used as Figure 3C Matrix-vector unit 341 X Vectors in - Vector Unit 361 X1 To 361 XV Any one of .

[0080] exist Figure 3D , vector-vector unit 361 YZ With multiple multiply-accumulate (MAC) units 371 1 To 371 Q , where Q may be an integer value less than or equal to the number of digits of the elements of the vector on which the operation will be performed (eg, the maximum number of digits). Each MAC unit 371 1 To 371 Q Two numbers (eg, vector elements) may be received as operands, a multiplication of the two numbers may be performed, and the result of the multiplication may be added to the sum maintained in the MAC unit.

[0081] Each vector buffer 381 and 383 may store a corresponding vector as a list of numbers. A pair of numbers (one each from vector buffers 381 and 383) may be provided to each MAC unit 371. 1 To 371 Q As input. MAC unit 371 1 To 371 Q Multiple pairs of numbers can be received in parallel from vector buffers 381 and 383, and multiply-accumulate (MAC) operations can be performed in parallel. From MAC unit 371 1 To 371 Q The output of can be stored in the shift register 375, and the accumulator 377 can calculate the sum of the results in the shift register 375.

[0082] when Figure 3D Vector - Vector Unit 361 YZ exist Figure 3C Matrix-vector unit 341 X When implemented in the vector-vector unit 361YZ The corresponding mapping memory bank 351 (eg, mapping memory bank 351) may be used. Z ) as the vector buffer 381, and using the matrix-vector unit 341 X The corresponding kernel buffer 331 (eg, kernel buffer 331 Y ) as vector buffer 383.

[0083] Vector buffers 381 and 383 may have the same length to store the same number / count of data elements. The length may be equal to the vector-vector unit 361. YZ MAC Unit 371 1 To 371 Q When the length of vector buffers 381 and 383 is the length of MAC unit 371 1 To 371 Q When the count is a multiple of , multiple pairs of inputs (equal to MAC unit 371 1 To 371 Q The count of ) may be provided from vector buffers 381 and 383 as a buffer to MAC unit 371 in each iteration. 1 To 371 Q and the vector buffers 381 and 383 can feed their elements to the MAC unit 371 through multiple iterations 1 To 371 Q middle.

[0084] Figure 4 Depicting a matrix having four matrix-vector units 341 (eg, 341 1 To 341 4 ) of the matrix-matrix unit 321, each of the matrix-vector units 341 contains corresponding four vector-vector units 361 (for example, 361 respectively 11 To 361 14 ,361 21 To 361 24 ,361 31 To 361 34 or 361 41 To 361 44 The rows of the multiplicand matrix (eg, vectors) may be transferred from the mapping memory bank 351 (eg, 351 ) to the mapping memory bank 351 by means of the crossbar switch 323 and the multiplexer 325 for each matrix-vector unit 341. 1 To 351 4 ) is provided to the corresponding vector-vector unit 361. The columns (eg, vectors) of the multiplier matrix may be read from the kernel buffer 331 (eg, 331 1 To 331 4) are provided to the corresponding vector-vector unit 361. The columns (e.g., vectors) of the multiplier matrix may represent pixel data of the image, and the rows (e.g., vectors) of the multiplicand matrix may represent filters used for image recognition (e.g., for recognizing straight or horizontal lines).

[0085] The matrix-matrix unit 321 may be configured to calculate the dot product of a multiplicand matrix and a multiplier matrix, which may have equal dimensions. The vector-vector unit 361 of the matrix-matrix unit 321 may be configured to calculate the dot product of two vectors of two matrices (e.g., rows of the multiplicand matrix and columns of the multiplier matrix), and thus represent corresponding elements of a result matrix. The aggregate result of the vector-vector units 361 of each matrix-vector unit 341 may represent corresponding rows of the result matrix, and the aggregate result of the vector-vector units 361 of all matrix-vector units 341 of the matrix-matrix unit 321 may represent the result matrix.

[0086] Figure 5 Details Figure 4 321 of the matrix-matrix unit. Consider the example of matrix A as the multiplicand and matrix B as the multiplier. According to Equation 1, the dot product of these two matrices A and B produces a result matrix C that will contain the first row of matrix A (e.g., a 11 、a 12 、a 13 and a 14 ) and the first column of matrix B (e.g., b 11 、b 21 、b 31 and b 41 ) to produce the elements of the first row and first column of the matrix C (e.g., c 11 ):

[0087] c 11 =a 11 b 11 +a 12 b 21 +a 13 b 31 +a 14 b 41 Equation 1

[0088] For various rows of matrix A and various columns of matrix B, the remaining elements of matrix C can be determined in a similar manner. For example, for Figure 5 In the matrix depicted in , first, for each value i from 1 to 4, and for each value j from 1 to 4, the element c of the matrix C ij It can be determined by the general equation 2:

[0089]

[0090] Each element of the multiplicand matrix A, the multiplier matrix B, and the result matrix C may represent a number, which may be binary or other. Therefore, each element of the result matrix C may represent the sum or accumulation of the products of the corresponding elements from the rows of the multiplicand matrix A and the columns of the multiplier matrix B. Each matrix-vector unit 341 may calculate a vector (e.g., a row) of the result matrix C through its corresponding vector-vector unit 361, and the matrix-matrix unit 321 may calculate the entire result matrix C through its corresponding matrix-vector unit 341.

[0091] These calculations performed by vector-vector unit 361, matrix-vector unit 341, and matrix-matrix unit 321 may be replicated within NAND memory. Specifically, an array of serially connected (e.g., NAND) memory cells may be configured to generate values ​​representing the dot product of respective vectors from two matrices (e.g., a multiplicand matrix and a multiplier matrix).

[0092] For example, to multiply two numbers within a NAND memory, a group of memory cells commonly connected to the same access line or collectively connected to a group of access lines may be programmed to have a threshold voltage indicating one number (e.g., the multiplicand), while a voltage may be applied to a data line selectively connected to the group of memory cells indicating individual digits (e.g., bits) of another number (e.g., the multiplier). Note that the multiplicand may utilize binary encoding or thermometric encoding to store its data, e.g., a base-10 value of 12 may be binary encoded as 1100, or thermometrically encoded as 111111111111. While thermometric encoding may utilize more memory cells for storage, it may also provide greater precision than binary encoding.

[0093] Subgroups of the group of memory cells may be programmed to represent corresponding digits (binary or thermometric) of the multiplicand, for example, by collectively assuming corresponding resistance values ​​between their corresponding data lines and a common source in response to the same control signal or group of control signals applied to their control gates. Each subgroup of memory cells may contain one or more memory cells (which may include all memory cells) in a single string of serially connected memory cells or multiple strings of serially connected memory cells. As will be described in more detail, the subgroup of memory cells corresponding to one digit of the multiplicand may contain the same number of memory cells and / or the same arrangement of memory cells as the subgroup of memory cells for each remaining digit of the multiplicand. Alternatively, the subgroup of memory cells corresponding to one digit of the multiplicand may contain a different number of memory cells and / or a different arrangement of memory cells than the corresponding subgroup of memory cells for one or more remaining digits of the multiplicand. The group of memory cells can be programmed in a binary manner, for example, each memory cell is activated (for example, to represent a first logic level) or deactivated (for example, to represent a second logic level different from the first logic level) in response to its corresponding control signal, or in an analog manner, for example, different memory cells exhibit different resistance levels (for example, R, R / 2, R / 4, R / 8, etc.) in response to the same control signal.

[0094] When the memory cell group receives its control signal or control signal group, the corresponding digits of the multiplier can be sequentially applied to the corresponding data lines of the memory cell group. In this way, the collective current flowing from the corresponding data lines of the memory cell group through the memory cell group to the common source can indicate the value of the multiplicand multiplied by a digit of the multiplier. This current can be converted to a digital (e.g., binary) value using an analog-to-digital converter (ADC) in a manner well known in the art of integrated circuit design. The voltage levels corresponding to the digits of the multiplier can be applied in a binary manner, for example, applying a first voltage level to produce a first voltage difference between each data line and the common source (e.g., to represent a first logic level), and applying a second voltage level to produce a second voltage difference (e.g., a slight voltage difference) between each data line and the common source that is lower than the first voltage difference (e.g., to represent a second logic level different from the first logic level).

[0095] Alternatively, the voltage level corresponding to the digit of the multiplier may be applied in an analog manner. For example, to represent the first logic level (e.g., "1") of the least significant digit (e.g., the least significant bit or LSB), a first voltage level may be applied to its corresponding data line to generate a first voltage difference between the corresponding data line and the common source, to represent the first logic level of the next significant digit (e.g., the second digit), a second voltage level higher than the first voltage level (e.g., twice the first voltage level) may be applied to its corresponding data line to generate a second voltage difference (e.g., twice the first voltage difference) between the corresponding data line and the common source, to represent the first logic level of the next significant digit (e.g., the third digit), a third voltage level higher than the second voltage level (e.g., twice the second voltage level) may be applied to its corresponding data line to generate a third voltage difference (e.g., twice the second voltage difference) between the corresponding data line and the common source, and so on. Similarly, to represent a second logic level of any number (e.g., “0”), a voltage level may be applied to the data lines to produce a voltage difference between each data line and the common source that is lower than any voltage difference produced for the first logic level (e.g., a slight voltage difference and / or a voltage difference of opposite polarity).

[0096] Fig. 6A and 6B Depicted is a portion of an array of memory cells configured to store the number of a multiplicand in analog and binary form, respectively. Figures 6A to 6B The same numbered elements in the Figure 2A Note that for clarity, Figures 6A to 6B Access line 202 is not depicted.

[0097] exist Fig. 6A The first number corresponding to the multiplicand is 620 0 A subset of memory cells (eg, least significant digits) may include a string of memory cells 206 connected in series. 0 One or more (eg, which may include all memory cells) memory cells of a series connected memory cell string 206 configured to respond to an access line 202 ( Fig. 6A A set of control signals (not depicted) exhibits a resistance value of R / 2 0 or R to represent the number 620 0 The first logic level (eg, “1”) of the digital 620 may be displayed, or a high impedance (High-Z) may be displayed to indicate the digital 620. 0 The next number 620 corresponding to the multiplicand is different from the first logic level (eg, "0"). 1 The memory cell subset may include a series connected memory cell string 206 1One or more memory cells (eg, which may include all memory cells) configured to respond to an access line 202 ( Fig. 6A The resistance value R / 2 is exhibited by the control signal of the group (not depicted in FIG. 1 or R / 2 to represent the number 620 1 The first logic level, or high impedance to represent digital 620 1 The second logic level of the multiplicand corresponds to the next number 620 2 The memory cell subset may include a series connected memory cell string 206 2 One or more memory cells (eg, which may include all memory cells) configured to respond to an access line 202 ( Fig. 6A The resistance value R / 2 is exhibited by the control signal of the group (not depicted in FIG. 2 or R / 4 to represent the number 620 2 The first logic level, or high impedance to represent digital 620 2 This can continue in a similar manner for each additional digit 620 of the multiplicand until the last digit 620 of the multiplicand. M (e.g. the most significant digit), so that the last digit corresponding to the multiplicand is 620 M The memory cell subset may include a series connected memory cell string 206 M One or more memory cells (eg, which may include all memory cells) configured to respond to an access line 202 ( Fig. 6A The resistance value R / 2 is exhibited by the control signal of the group (not depicted in FIG. M To represent the number 620 M The first logic level, or high impedance to represent digital 620 M Thus, each series-connected memory cell string 206 may correspond to a respective digit (eg, a single respective digit) of the multiplicand, and each digit of the multiplicand may correspond to one or more series-connected memory cell strings 206.

[0098] Note that although Fig. 6A A single series-connected memory cell string 206 is depicted as corresponding to each digit 620 of the multiplicand, but each digit 620 of the multiplicand may correspond to one or more series-connected memory cell strings 206. For example, the first digit 620 corresponding to the multiplicand 0The memory cell subset may include one or more memory cells of two series-connected memory cell strings 206, each of which is configured to exhibit a resistance value R to represent the number 620. 0 The first logic level, or high impedance to represent digital 620 0 The second logic level corresponds to the second number 620 of the multiplicand. 1 The memory cell subset of may include one or more memory cells of two series-connected memory cell strings 206, each of which is configured to exhibit a resistance value of R / 2 to represent the number 620. 1 The first logic level, or high impedance to represent digital 620 1 The second logic level corresponds to the third number 620 of the multiplicand. 2 The memory cell subset of may include one or more memory cells of two series-connected memory cell strings 206, each of which is configured to exhibit a resistance value of R / 4 to represent the number 620. 2 The first logic level, or high impedance to represent digital 620 2 The second logic level of the multiplicand is shown in FIG. 6 , and so on. In addition, although the series-connected memory cell strings 206 corresponding to each digit 620 of the multiplicand are depicted as being immediately adjacent to one another, the series-connected memory cell strings 206 corresponding to the digits 620 of the multiplicand may be interleaved with the series-connected memory cell strings 206 that do not correspond to the digits 620 of the multiplicand, e.g., every other series-connected memory cell string 206 or some other mixture of series-connected memory cell strings 206 corresponding to the digits 620 of the multiplicand and series-connected memory cell strings 206 that do not correspond to the digits 620 of the multiplicand. In addition, although depicted as being arranged in order from the least significant digit 620 0 To the most significant figure 620 M , but their order can be changed or even randomized, as this is not expected to change their collective conductance in any significant way.

[0099] exist Figure 6B The first number corresponding to the multiplicand is 620 0 A subset of memory cells (eg, least significant digits) may include a string of memory cells 206 connected in series. 0 One or more memory cells (eg, which may include all memory cells) configured to respond to an access line 202 ( Figure 6B A set of control signals (not depicted) is shown to represent the resistance value R to represent the number 620 0 The first logic level (eg, “1”) of the digital 620 may be displayed as a high impedance. 0The next number 620 corresponding to the multiplicand is different from the first logic level (eg, "0"). 1 The memory cell subset may include a series connected memory cell string 206 1 and 206 2 One or more memory cells (eg, which may include all memory cells) configured to respond to an access line 202 ( Figure 6B The resistance value R of each series-connected memory cell string 206 is represented by the number 620 without using the set of control signals (not depicted in FIG. 6 ). 1 The first logic level of , or the high impedance of each serially connected memory cell string 206 is presented to represent the digital 620 1 The second logic level of the multiplicand corresponds to the next number 620 2 The memory cell subset may include a series connected memory cell string 206 3 To 206 6 One or more memory cells (eg, which may include all memory cells) configured to respond to an access line 202 ( Figure 6B The resistance value R of each series-connected memory cell string 206 is represented by the number 620 without using the set of control signals (not depicted in FIG. 6 ). 2 The first logic level of , or the high impedance of each serially connected memory cell string 206 is presented to represent the digital 620 2 This may continue in a similar manner for each additional digit 620 of the multiplicand until the last digit (e.g., the most significant digit) of the multiplicand, such that the subset of memory cells corresponding to each digit of the multiplicand may include a number of one or more memory cells of the series-connected memory cell strings 206 (e.g., it may include all of the memory cells), which may be twice the number of the series-connected memory cell strings 206 corresponding to the previous digit of the multiplicand, wherein each series-connected memory cell string 206 corresponding to the digit of the multiplicand is configured to respond to an access line 202 ( Figure 6B The device may display a resistance value R to represent the first logic level of the digital 620 by the set of control signals (not depicted in FIG. 6 ), or display a high impedance to represent the second logic level of the digital 620.

[0100] and Fig. 6A As in the example, the first digit of the multiplicand is 620 0The number of series-connected memory cell strings 206 for each remaining digit of the multiplicand may be similarly adjusted corresponding to more than one series-connected memory cell string 206. Additionally, the series-connected memory cell strings 206 corresponding to the digits 620 of the multiplicand may be interleaved with the series-connected memory cell strings 206 that do not correspond to the digits 620 of the multiplicand and / or may be rearranged. Furthermore, Figure 6B It can also be used to describe thermometric encoding. For example, a memory cell group programmed to represent a thermometrically encoded number may include a number of one or more memory cells (e.g., it may include all memory cells) of a memory cell string 206 connected in series, the number being a multiple of the number to be represented (e.g., 1, 2, 3, etc.), for example, to represent the decimal 3, the memory cell group may include three memory cell strings 206 connected in series (e.g., memory cell strings 206 connected in series). 0 To 206 2 ) are each configured to exhibit a resistance value R, wherein the remaining series-connected memory cell string 206 corresponding to the multiplicand may be configured to exhibit a high impedance.

[0101] Figure 7 A portion of a memory cell array (eg, memory cell block 250 ) is depicted for discussing arithmetic operations according to an embodiment. Figure 7 Depicts: Seven series-connected memory cell strings (e.g., 206 0 To 206 6 ), which includes a response to the selection line 215 0 The control signal passes through the select gate (in Figure 7 (not marked) is selectively connected to the data line 204 0 To 204 6 and responds to a control signal applied to select line 214 through a select gate (at Figure 7 ) selectively connected to the common source 216 memory cell (in Figure 7 seven serially connected memory cell strings (in Figure 7 215, which includes a signal responsive to a signal applied to the select line 215. 1 The control signal passes through the select gate (in Figure 7 (not marked) is selectively connected to the data line 204 0 To 204 6 and responds to a control signal applied to select line 214 through a select gate (at Figure 7 ) selectively connected to the common source 216 memory cell (in Figure 7 and seven serially connected memory cell strings (in Figure 7215, which includes a signal responsive to a signal applied to the select line 215. 2 The control signal passes through the select gate (in Figure 7 (not marked) is selectively connected to the data line 204 0 To 204 6 and responds to a control signal applied to select line 214 through a select gate (at Figure 7 ) selectively connected to the common source 216 memory cell (in Figure 7 not marked in the figure).

[0102] Common source 216 may be connected to an input 732 of an analog-to-digital converter (ADC) 730. An output 734 of ADC 730 may include a plurality of signal lines, each configured to provide a respective digital signal having one of two logic levels (e.g., a "1" or a "0" logic level). ADC 730 may be configured to receive an analog signal (e.g., a current) from common source 216 at its input 732 and to generate at its output 734 a set of digital signals representing the magnitude of the current received at its input 732. Consider ADC 730 configured to receive an analog signal (e.g., a current) from common source 216 at its input 732. low To A high An example of a current where A low Can be zero current or a positive value, and A high may be a current level higher than any expected current level to be received by ADC 730. ADC 730 may be further configured to output D digits of output data to its output 734. In this example, resolution Q may be equal to (A high –A low ) / 2^D. Continuing with this example, if D=8, then the signal received at the input 732 of the ADC 730 is greater than or equal to A low and less than A low The current level of +Q may result in a set of digital signals 00000000 generated at output 734, and a current greater than or equal to A received at input 732 of ADC 730. low +Q and less than A low The current level of +2*Q may result in a set of digital signals 00000001 being generated at output 734, and a current level greater than or equal to A received at input 732 of ADC 730. low +2*Q and less than A low The current level of +3*Q may result in a set of digital signals 00000010 generated at output 734, and a current greater than or equal to A received at input 732 of ADC 730. low +3*Q and less than A lowA current level of +4*Q may result in a set of digital signals 00000011 being produced at output 734, and so on, until a current greater than or equal to A is received at input 732 of ADC 730. low A current level of +255*Q may result in a set of digital signals 11111111 produced at output 734. While this example may represent a relationship that approximates a linear function, the function need not be linear in order to produce a digital value representative of the received current level.

[0103] Figures 8A to 8F Depicts registers during a multiply-accumulate operation according to an embodiment. Figure 7 describe Figures 8A to 8F . Figures 8A to 8F An instance of can simulate the way (for example, as referenced Fig. 6A discussed) or in binary form (e.g., as referenced Figure 6B The voltage indicating the number of the multiplier may be applied in a binary manner, for example, a voltage indicating a number having a logic value of 1 or a voltage indicating a number having a logic value of 0.

[0104] The discussion of performing multiply-accumulate operations assumes that the multiplicand is stored in the memory corresponding to access line 202. 3 (For example, its control gate is connected to access line 202 3 ) and drain selection line 215 0 (e.g., by connecting its control gate to drain select line 215 0 The drain select gate 212 is selectively connected to the corresponding data line 204) Figure 7 The memory cell string 206 connected in series 0 To 206 6 730 will be described as a three-digit ADC, for example, with eight possible digital outputs. In practice, ADC 730 may be expected to have higher order outputs (e.g., eight digits, sixteen digits, or more), and therefore higher granularity. Table 1 depicts various levels of current A from common source 216. 1 To A 7 One possible relationship between the digital values ​​of the output of the example ADC 730 is: 1 2 3 4 5 6 7 . Note that the current level A 1 To A 7 ​​​​​​The absolute value of typically depends on the selected design parameters, such as the number of digits from the output of ADC 730, the voltages selected to drive access lines 202 and data lines 204, the maximum expected number of NAND strings 206 that can conduct, etc.

[0105] Table 1 Digital values ​​and currents in three digital ADCs

[0106]

[0107]

[0108] for Figures 8A to 8F In the example of FIG. 1 , the multiplicand may be a digital value of 101 and the multiplier may be a digital value of 011. To store the multiplicand 101 in the series-connected memory cell string 206 in an analog manner using binary encoding 0 To 206 6 , a memory cell string 206 connected in series 0 To 206 6 The threshold voltage of the memory cell of the memory cell string 206 can be programmed so that the memory cell string 206 connected in series 0 To 206 6 The first group of serially connected memory cell strings 206 (eg, serially connected memory cell strings 206 0 ) may be responsive to an input signal applied to access line 202 0 To 202 3 A set of control signals represents a resistance value R (e.g., R / 2 0 ) resistance, the memory cell string 206 connected in series 0 To 206 6 The second group of serially connected memory cell strings 206 (eg, serially connected memory cell strings 206 1 ) may be responsive to an input signal applied to access line 202 0 To 202 3 The set of control signals exhibits high impedance, the series connected memory cell string 206 0 To 206 6 The third group of serially connected memory cell strings 206 (eg, serially connected memory cell strings 206) 2 ) may be responsive to an input signal applied to access line 202 0 To 202 3 The set of control signals exhibits a representative resistance value of R / 4 (e.g., R / 2 2 ) and the memory cell string 206 connected in series 0 To 206 6 The fourth group of serially connected memory cell strings 206 (eg, serially connected memory cell strings 206)3 To 206 6 ) may be responsive to an input signal applied to access line 202 0 To 202 3 The set of control signals exhibits high impedance. Thus, in response to being applied to access line 202 0 To 202 3 The set of control signals connects the memory cell string 206 in series. 0 To 206 6 Collectively, a resistance value of approximately R / 5 may be exhibited, representing a digital value of 101.

[0109] Alternatively, consider an example where the multiplicand is stored in binary using binary encoding. In this example, the series connected memory cell string 206 0 To 206 6 The threshold voltage of the memory cell of the memory cell string 206 can be programmed so that the memory cell string 206 connected in series 0 To 206 6 The first group of serially connected memory cell strings 206 (eg, serially connected memory cell strings 206 0 ) may each respond to an input signal applied to access line 202 0 To 202 3 A set of control signals exhibits a resistance representing a resistance value R, the memory cell string 206 connected in series 0 To 206 6 The second group of serially connected memory cell strings 206 (eg, serially connected memory cell strings 206 1 and 206 2 ) may be responsive to an input signal applied to access line 202 0 To 202 3 The set of control signals exhibits high impedance, and the series-connected memory cell string 206 0 To 206 6 The third group of serially connected memory cell strings 206 (eg, serially connected memory cell strings 206) 3 To 206 6 ) may each respond to an input signal applied to access line 202 0 To 202 3 The set of control signals exhibits a resistance representing a resistance value R. Thus, in response to being applied to access line 202 0 To 202 3 The set of control signals connects the memory cell string 206 in series. 0 To 206 6 Collectively, a resistance value of approximately R / 5 may be exhibited, representing a digital value of 101.

[0110] As a further alternative, consider an example where the multiplicand is stored in binary using thermometric encoding. In this example, the series connected memory cell string 206 0 To 206 6 The threshold voltage of the memory cell of the memory cell string 206 can be programmed so that the memory cell string 206 connected in series 0 To 206 6 The first group of serially connected memory cell strings 206 (eg, serially connected memory cell strings 206 0 To 206 4 ) may each respond to an input signal applied to access line 202 0 To 202 3 A set of control signals exhibits a resistance representing a resistance value R, and the memory cell string 206 connected in series 0 To 206 6 The second group of serially connected memory cell strings 206 (eg, serially connected memory cell strings 206 5 To 206 6 ) may be responsive to an input signal applied to access line 202 0 To 202 3 The set of control signals exhibits high impedance. Thus, in response to being applied to access line 202 0 To 202 3 The set of control signals connects the memory cell string 206 in series. 0 To 206 6 A resistance value close to R / 5 representing a digital value of 101 (eg, a temperature measurement value of 11111) may be collectively exhibited.

[0111] Figures 8A to 8F Depict three partial product registers 840 (eg, 840 0 To 840 2 ) and an accumulation register 842, each of which contains a corresponding six-digit register 844, such as 844 0 To 844 5 . The partial product registers 840 and the accumulator registers 842 collectively may correspond to a portion of the MAC registers 136. Although the example depicts three partial product registers 840, embodiments may include additional partial product registers 840, and may generally include a number of partial product registers 840 greater than or equal to the number of digits of the multipliers to be processed. Similarly, although the example depicts one accumulator register 842, embodiments may include additional accumulator registers, such as for storing partial sums. And although the example depicts six digital registers 844, embodiments may include additional digital registers 844, and may generally include a number of digital registers 844 greater than or equal to the number of digits of the multiplicand to be processed plus the number of digits of the multipliers to be processed.

[0112] To obtain Fig. 8A As a result, Figure 7 The common source 216 in the ADC 730 may be connected to a reference potential (e.g., Vss, 0V, or ground) through the ADC 730. Thus, the voltage level of the common source (Vcs) may be at (or close to) the reference potential. A voltage level may be applied to the source select line 214 to activate the source select gate 210, and a voltage level may be applied to the drain select line 215 to activate the drain select gate 210. 0 to activate its corresponding drain select gate 212, and a voltage level may be applied to the drain select line 215 1 and 215 2 to deactivate its corresponding drain select gate 212. A voltage level indicative of the first digit (eg, the most significant digit) of the multiplier may be applied to each data line 204. 0 To 204 6 Since the first digit of the multiplier is 0, a voltage level V0 may be applied to each data line 204. 0 To 204 6 The voltage level V0 may be equal to (or less than) the voltage level Vcs.

[0113] A voltage level may be applied to access line 202 that is configured to activate a NAND string 206 corresponding to a number of the multiplicand having a first logic level. 0 To 206 6 and deactivates the NAND string 206 corresponding to the number of the multiplicand having the second logic level. 0 To 206 6 The voltage level applied to the access line 202 may further deactivate at least one corresponding memory cell 208 of each NAND string 206 that does not correspond to any number of the multiplicand, e.g., the threshold voltages of these memory cells 208 may be higher than the voltage level applied to their corresponding access lines, e.g., their threshold voltages may correspond to a number of the multiplicand having a second logic level.

[0114] In the example embodiment, whether the multiplicand is stored in analog or binary form using binary coding or in binary form using thermometric coding, access line 202 3 A voltage level may be received that is configured to activate a NAND string 206 corresponding to a number of the multiplicand having a first logic level. 0 To 206 6 and deactivates the NAND string 206 corresponding to the number with the second logic level of the multiplicand or any number not corresponding to the multiplicand. 0 To 206 6of the corresponding memory cell 208. Concurrently, applied to the access line 202 0 To 202 2 The voltage level of the remaining access lines 202 (e.g., the remaining access lines 202 that do not store the multiplicand) may be a pass voltage having a voltage level configured to activate its corresponding memory cell 208 regardless of its corresponding threshold voltage. 3 The voltage level may further deactivate at least one memory cell 208 of each NAND string 206 that does not correspond to any digit of the multiplicand, for example, the threshold voltages of these memory cells 208 may be higher than the voltage level applied to their corresponding access lines, for example, their threshold voltages may correspond to a digit of the multiplicand having a second logic level.

[0115] Note that for embodiments in which the multiplicand is stored in more than one memory cell per NAND string 206, each access line 202 connected to a memory cell 208 corresponding to a number of the multiplicand may receive a voltage level configured to activate the NAND string 206 corresponding to the number of the multiplicand having a first logic level. 0 To 206 6 and deactivates the NAND string 206 corresponding to the number of the multiplicand having the second logic level. 0 To 206 6 The corresponding memory cell 208 of the access line 202 can receive a pass voltage, while the remaining access lines 202 can receive a pass voltage.

[0116] Since the voltage difference (Vds) between the data line 204 and the common source 216 may be 0V or less, no current may be expected to flow to the ADC 730, which may result in the output of the ADC 730 being a digital value of 000, for example, having a value A less than that of Table 1. 1 The digital value 000 can then be stored in the partial product register 840 0 Digital register 844 0 To 844 2 The digital registers 844 that do not depict any values ​​may be considered to each store a value of 0. Figure 8B The result of the first multiplication operation may be shifted to the next partial product register 840 (eg, 840 1 ) and shifted one stage to digital register 844 1 To 844 3 .

[0117] To obtain Figure 8C As a result, Figure 7The common source 216 in the ADC 730 may be connected to a reference potential through the ADC 730. Therefore, the voltage level (Vcs) of the common source may be at (or close to) the reference potential. A voltage level may be applied to the source select line 214 to activate the source select gate 210, and a voltage level may be applied to the drain select line 215 to activate the drain select gate 210. 0 to activate its corresponding drain select gate 212, and a voltage level may be applied to the drain select line 215 1 and 215 2 to deactivate its corresponding drain select gate 212. A voltage level indicating a second number of the multiplier may be applied to each data line 204 0 To 204 6 Since the second digit of the multiplier is 1, a voltage level V1 may be applied to each data line 204. 0 To 204 6 Alternatively, data line 204 corresponding to a NAND string 206 that does not correspond to any digit of the multiplicand may receive voltage level V0 or other voltage level equal to (or lower than) the voltage level of common source 216. Voltage level V1 may be higher than voltage level Vcs so that the voltage difference between data line 204 and common source 216 may be positive.

[0118] A voltage level may be applied to access line 202 that is configured to activate a NAND string 206 corresponding to a number of the multiplicand having a first logic level. 0 To 206 6 and deactivates the NAND string 206 corresponding to the number of the multiplicand having the second logic level. 0 To 206 6 The voltage level applied to the access line 202 may further deactivate at least one memory cell 208 of each NAND string 206 that does not correspond to any number of the multiplicand, e.g., the threshold voltages of these memory cells 208 may be higher than the voltage level applied to their corresponding access lines, e.g., their threshold voltages may correspond to a number of the multiplicand having a second logic level.

[0119] In the example embodiment, whether the multiplicand is stored in analog or binary form using binary coding or in binary form using thermometric coding, access line 202 3 A voltage level may be received that is configured to activate a NAND string 206 corresponding to a number of the multiplicand having a first logic level. 0 To 206 6 and deactivates the NAND string 206 corresponding to the number with the second logic level of the multiplicand or any number not corresponding to the multiplicand. 0 To 2066 of the corresponding memory cell 208. Concurrently, applied to the access line 202 0 To 202 2 The voltage level of may be a pass voltage configured to activate its corresponding memory cell 208 regardless of its corresponding threshold voltage.

[0120] The voltage difference (Vds) between the data line 204 and the common source 216 may be positive, and the current flowing to the ADC 730 may be expected to be greater than or equal to the current level A. 5 and is less than the current level A 6 , which may result in the output of ADC 730 being a digital value of 101. The digital value 101 may then be stored in partial product register 840. 0 Digital register 844 0 To 844 2 In. Fig.8D The result of the first multiplication operation may be shifted to the next partial product register 840 (eg, 840 2 ) and shifted one stage to digital register 844 2 To 844 4 , and the result of the second multiplication operation may be shifted to the next partial product register 840 (eg, 840 1 ), and shifted one stage to digital register 844 1 To 844 3 Note that shifting of the result of a multiplication operation can be used to provide a desired magnitude to its digital value before it is accumulated.

[0121] To obtain Fig. 8E The results can be repeated for reference Figure 8C Describe the process. For example, Figure 7 The common source 216 in the ADC 730 may be connected to a reference potential through the ADC 730. Therefore, the voltage level (Vcs) of the common source may be at (or close to) the reference potential. A voltage level may be applied to the source select line 214 to activate the source select gate 210, and a voltage level may be applied to the drain select line 215 to activate the drain select gate 210. 0 to activate its corresponding drain select gate 212, and a voltage level may be applied to the drain select line 215 1 and 215 2 to deactivate its corresponding drain select gate 212. A voltage level indicative of the third digit (eg, the least significant digit) of the multiplier may be applied to each data line 204. 0 To 204 6 Since the third digit of the multiplier is 1, a voltage level V1 may be applied to each data line 204 0 To 204 6 .

[0122] Access line 202 3 A voltage level may be received that is configured to activate a NAND string 206 corresponding to a number of the multiplicand having a first logic level. 0 To 206 6 and deactivates the NAND string 206 corresponding to the number with the second logic level of the multiplicand or any number not corresponding to the multiplicand. 0 To 206 6 of the corresponding memory cell 208. Concurrently, applied to the access line 202 0 To 202 2 The voltage level of may be a pass voltage configured to activate its corresponding memory cell 208 regardless of its corresponding threshold voltage.

[0123] The voltage difference (Vds) between the data line 204 and the common source 216 may be positive, and the current flowing to the ADC 730 may be expected to be greater than or equal to the current level A. 5 and is less than the current level A 6 , which may result in the output of ADC 730 being a digital value of 101. The digital value 101 may then be stored in partial product register 840. 0 Digital register 844 0 To 844 2 middle.

[0124] As an alternative to shifting the digital value by one order when shifting to the subsequent partial product register 840, the digital value of the output of ADC 730 may be stored directly to a digital register indicating its magnitude. Fig. 8A In the example, the digital value 000 may have been stored in the partial product register 840. 0 Digital register 844 2 To 844 4 and only shifted down to the partial product register 840 2 , without further shifting its magnitude, and in Figure 8C In the example, the digital value 101 may have been stored in the partial product register 840. 0 Digital register 844 1 To 844 3 and only shifted down to the partial product register 840 1 , without further shifting its magnitude. In this way, the order of the numbers to which the multipliers are applied can be changed, since shifting the order to the desired magnitude will be independent of the timing of their application.

[0125] exist Figure 8F In the partial product register 840 0 To 840 2The summation may be performed, for example, in a manner known in the art and stored in the accumulator register 842 to produce a result 01111 representing the product of the multiplicand 101 and the multiplier 011. The result stored in the accumulator register 842 may, for example, represent Figure 5 a of the matrix A in 11 With matrix B b 11 Continuing with this example, the process can be repeated for additional multiplicand / multiplier pairs, such as a 12 With matrix B b 21 The product of, matrix A a 13 With matrix B b 31 The product of and a of the matrix A 14 With matrix B b 41 products, and these products can be added to produce Figure 5 The matrix C described by c 11 Thus, the memory can be operated as a vector-to-vector unit (e.g., consistent with the previous example). Figure 4 Vector - Vector Unit 361 11 ) to produce an element of the result matrix C (e.g., c 11 ) value.

[0126] Figures 9A to 9F Depicts registers during a multiply-accumulate operation according to another embodiment. Figure 7 describe Figures 9A to 9F . Figures 9A to 9F An instance of can simulate the way (for example, as referenced Fig. 6A discussed) or in binary form (e.g., as referenced Figure 6B The voltage indicating the digit of the multiplier may be applied in an analog manner, for example, a voltage indicating a digit having a logical value of 0, or a corresponding voltage level representing the magnitude of a digit having a logical value of 1.

[0127] The discussion of performing multiply-accumulate operations assumes that the multiplicand is stored in the memory corresponding to access line 202. 3 (For example, its control gate is connected to access line 202 3 ) and drain selection line 215 0 (e.g., by connecting its control gate to drain select line 215 0 The drain select gate 212 is selectively connected to the corresponding data line 204) Figure 7 The memory cell string 206 connected in series 0 To 206 6730 is an example of a memory unit 208 of FIG. 730. To simplify the example, ADC 730 will be described as a five-digit ADC, for example, with 32 possible digital outputs. In practice, ADC 730 may be expected to have higher order outputs (e.g., eight digits, sixteen digits, or more), and therefore have a higher granularity.

[0128] Table 2 depicts various levels of current A from the common source 216 1 To A 31 One possible relationship between the digital values ​​of the output of the example ADC 730 is: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 . Note that the current level A 1 To A 31 The absolute value of typically depends on the selected design parameters, such as the number of digits from the output of ADC 730, the voltages selected to drive access lines 202 and data lines 204, the maximum expected number of NAND strings 206 that can conduct, etc.

[0129] Table 2 Digital values ​​and current in five digital ADCs

[0130]

[0131] for Figures 9A to 9F In the example of FIG. 1 , the multiplicand may be a digital value of 101 and the multiplier may be a digital value of 011. The multiplicand 101 may be stored in analog form using binary coding, in binary form using binary coding, or in binary form using thermometric coding, as shown in FIG.​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​ Figures 8A to 8F The series connected memory cell string 206 is described 0 To 206 6 .

[0132] Figures 9A to 9F Depict three partial product registers 840 (eg, 840 0 To 840 2 ) and an accumulation register 842, each of which contains a corresponding six-digit register 844, such as 844 0 To 844 5 . The partial product registers 840 and the accumulator registers 842 collectively may correspond to a portion of the MAC registers 136. Although the example depicts three partial product registers 840, embodiments may include additional partial product registers 840, and may generally include a number of partial product registers 840 greater than or equal to the number of digits of the multipliers to be processed. Similarly, although the example depicts one accumulator register 842, embodiments may include additional accumulator registers, such as for storing partial sums. And although the example depicts six digital registers 844, embodiments may include additional digital registers 844, and may generally include a number of digital registers 844 greater than or equal to the number of digits of the multiplicand to be processed plus the number of digits of the multipliers to be processed.

[0133] Although Figures 8A to 8F The examples begin with the most significant digit of the multiplier, but will be described starting with the least significant digit of the multiplier. Figures 9A to 9F However, if necessary, apply Figures 9A to 9F The order of the numbers of the instances of the multipliers can be performed in a different order.

[0134] To obtain Fig.9A As a result, Figure 7 The common source 216 in the ADC 730 may be connected to a reference potential (e.g., Vss, 0V, or ground) through the ADC 730. Thus, the voltage level of the common source (Vcs) may be at (or close to) the reference potential. A voltage level may be applied to the source select line 214 to activate the source select gate 210, and a voltage level may be applied to the drain select line 215 to activate the drain select gate 210. 0 to activate its corresponding drain select gate 212, and a voltage level may be applied to the drain select line 215 1 and 215 2 to deactivate its corresponding drain select gate 212. A voltage level indicative of the first digit (eg, the least significant digit) of the multiplier may be applied to each data line 204. 0 To 204 6 Since the first digit of the multiplier is 1 and the magnitude is 2^0, a voltage level V1 may be applied to each data line 204. 0 To 2046 Alternatively, data line 204 corresponding to a NAND string 206 that does not correspond to any digit of the multiplicand may receive voltage level V0 or other voltage level equal to (or lower than) the voltage level of common source 216. Voltage level V1 may be higher than voltage level Vcs so that the voltage difference between data line 204 and common source 216 may be positive.

[0135] A voltage level may be applied to access line 202 that is configured to activate a NAND string 206 corresponding to a number of the multiplicand having a first logic level. 0 To 206 6 and deactivates the NAND string 206 corresponding to the number of the multiplicand having the second logic level. 0 To 206 6 The voltage level applied to the access line 202 may further deactivate at least one corresponding memory cell 208 of each NAND string 206 that does not correspond to any number of the multiplicand, e.g., the threshold voltages of these memory cells 208 may be higher than the voltage level applied to their corresponding access lines, e.g., their threshold voltages may correspond to a number of the multiplicand having a second logic level.

[0136] In the example embodiment, whether the multiplicand is stored in analog or binary form using binary coding or in binary form using thermometric coding, access line 202 3 A voltage level may be received that is configured to activate a NAND string 206 corresponding to a number of the multiplicand having a first logic level. 0 To 206 6 and deactivates the NAND string 206 corresponding to the number with the second logic level of the multiplicand or any number not corresponding to the multiplicand. 0 To 206 6 of the corresponding memory cell 208. Concurrently, applied to the access line 202 0 To 202 2 The voltage level of the remaining access lines 202 (e.g., the remaining access lines 202 that do not store the multiplicand) may be a pass voltage having a voltage level configured to activate its corresponding memory cell 208 regardless of its corresponding threshold voltage. 3 The voltage level may further deactivate at least one memory cell 208 of each NAND string 206 that does not correspond to any digit of the multiplicand, for example, the threshold voltages of these memory cells 208 may be higher than the voltage level applied to their corresponding access lines, for example, their threshold voltages may correspond to a digit of the multiplicand having a second logic level.

[0137] Note that for embodiments in which the multiplicand is stored in more than one memory cell per NAND string 206, each access line 202 connected to a memory cell 208 corresponding to a number of the multiplicand may receive a voltage level configured to activate the NAND string 206 corresponding to the number of the multiplicand having a first logic level. 0 To 206 6 and deactivates the NAND string 206 corresponding to the number of the multiplicand having the second logic level. 0 To 206 6 The corresponding memory cell 208 of the access line 202 can receive a pass voltage, while the remaining access lines 202 can receive a pass voltage.

[0138] The voltage difference (Vds) between the data line 204 and the common source 216 may be positive, and the current flowing to the ADC 730 may be expected to be greater than or equal to the current level A of Table 2. 5 and is less than the current level A 6 , which may result in the output of ADC 730 being a digital value of 00101. The digital value 00101 may then be stored in partial product register 840. 0 Digital register 844 0 To 844 4 In. Digital registers 844 that do not depict any value may be considered to each store a value of 0. Fig. 9B In the example, the result of the first multiplication operation may be shifted to the next partial product register 840 (eg, 840 1 ). Note that there is no need to shift the result to a higher order, since the result of the first multiplication operation can represent its expected magnitude.

[0139] To obtain Fig. 9C As a result, Figure 7 The common source 216 in the ADC 730 may be connected to a reference potential through the ADC 730. Therefore, the voltage level (Vcs) of the common source may be at (or close to) the reference potential. A voltage level may be applied to the source select line 214 to activate the source select gate 210, and a voltage level may be applied to the drain select line 215 to activate the drain select gate 210. 0 to activate its corresponding drain select gate 212, and a voltage level may be applied to the drain select line 215 1 and 215 2 to deactivate its corresponding drain select gate 212. A voltage level indicating a second number of the multiplier may be applied to each data line 204. 0 To 204 6 Since the second digit of the multiplier is 1 and the value is 2^1, the voltage level V2 can be applied to each data line 204 0 To 204 6Alternatively, the data lines 204 corresponding to the NAND strings 206 that do not correspond to any digit of the multiplicand may receive the voltage level V0 or other voltage level that is equal to (or lower than) the voltage level of the common source 216 .

[0140] Voltage level V2 may be higher than voltage level Vcs so that the voltage difference between data line 204 and common source 216 may be positive. Voltage level V2 may be higher than voltage level V1. Voltage level V2 may be configured to produce a voltage difference Vds that may be twice the voltage difference representing the least significant digit of the multiplier (e.g., 2^1). In this way, the resulting current in response to voltage difference V2-Vcs may have a current level that is twice the current level in response to voltage difference V1-Vcs so that its resulting current will represent its value and magnitude.

[0141] A voltage level may be applied to access line 202 that is configured to activate a NAND string 206 corresponding to a number of the multiplicand having a first logic level. 0 To 206 6 and deactivates the NAND string 206 corresponding to the number of the multiplicand having the second logic level. 0 To 206 6 The voltage level applied to the access line 202 may further deactivate at least one memory cell 208 of each NAND string 206 that does not correspond to any number of the multiplicand, e.g., the threshold voltages of these memory cells 208 may be higher than the voltage level applied to their corresponding access lines, e.g., their threshold voltages may correspond to a number of the multiplicand having a second logic level.

[0142] In the example embodiment, whether the multiplicand is stored in analog or binary form using binary coding or in binary form using thermometric coding, access line 202 3 A voltage level may be received that is configured to activate a NAND string 206 corresponding to a number of the multiplicand having a first logic level. 0 To 206 6 and deactivates the NAND string 206 corresponding to the number with the second logic level of the multiplicand or any number not corresponding to the multiplicand. 0 To 206 6 of the corresponding memory cell 208. Concurrently, applied to the access line 202 0 To 202 2 The voltage level of may be a pass voltage configured to activate its corresponding memory cell 208 regardless of its corresponding threshold voltage.

[0143] The voltage difference (Vds) between the data line 204 and the common source 216 may be positive, and the current flowing to the ADC 730 may be expected to be greater than or equal to the current level A of Table 2. 10 and is less than the current level A 11 , which may result in the output of ADC 730 being a digital value of 01010. The digital value 01010 may then be stored in partial product register 840. 0 Digital register 844 0 To 844 4 In. Fig.9D In the example, the result of the first multiplication operation may be shifted to the next partial product register 840 (eg, 840 2 ), and the result of the second multiplication operation may be shifted to the next partial product register 840 (eg, 840 1 ). Note that there is no need to shift the result to a higher order since the results of the first and second multiplication operations can represent their respective expected magnitudes.

[0144] To obtain Fig.9E As a result, Figure 7 The common source 216 in the ADC 730 may be connected to a reference potential through the ADC 730. Therefore, the voltage level (Vcs) of the common source may be at (or close to) the reference potential. A voltage level may be applied to the source select line 214 to activate the source select gate 210, and a voltage level may be applied to the drain select line 215 to activate the drain select gate 210. 0 to activate its corresponding drain select gate 212, and a voltage level may be applied to the drain select line 215 1 and 215 2 to deactivate its corresponding drain select gate 212. A voltage level indicative of the third digit (eg, the most significant digit) of the multiplier may be applied to each data line 204. 0 To 204 6 Since the third digit of the multiplier is 0, a voltage level V0 may be applied to each data line 204. 0 To 204 6 The voltage level V0 may be equal to (or less than) the voltage level Vcs.

[0145] If the third digit of the multiplier is 1, then a voltage level V4 may be applied to each data line 204. 0 To 204 6. Voltage level V4 may be higher than voltage level Vcs so that the voltage difference between data line 204 and common source 216 may be positive. Voltage level V4 may be configured to produce a voltage difference Vds that will be four times the voltage difference representing the least significant digit of the multiplier (e.g., 2^2). In this way, the resulting current in response to voltage difference V4-Vcs may have a current level that is four times the current level in response to voltage difference V1-Vcs so that its resulting current will be representative of its value and magnitude.

[0146] A voltage level may be applied to access line 202 that is configured to activate a NAND string 206 corresponding to a number of the multiplicand having a first logic level. 0 To 206 6 and deactivates the NAND string 206 corresponding to the number of the multiplicand having the second logic level. 0 To 206 6 The voltage level applied to the access line 202 may further deactivate at least one memory cell 208 of each NAND string 206 that does not correspond to any number of the multiplicand, e.g., the threshold voltages of these memory cells 208 may be higher than the voltage level applied to their corresponding access lines, e.g., their threshold voltages may correspond to a number of the multiplicand having a second logic level.

[0147] In the example embodiment, whether the multiplicand is stored in analog or binary form using binary coding or in binary form using thermometric coding, access line 202 3 A voltage level may be received that is configured to activate a NAND string 206 corresponding to a number of the multiplicand having a first logic level. 0 To 206 6 and deactivates the NAND string 206 corresponding to the number with the second logic level of the multiplicand or any number not corresponding to the multiplicand. 0 To 206 6 of the corresponding memory cell 208. Concurrently, applied to the access line 202 0 To 202 2 The voltage level of may be a pass voltage configured to activate its corresponding memory cell 208 regardless of its corresponding threshold voltage.

[0148] Since the voltage difference (Vds) between the data line 204 and the common source 216 may be 0V or less, no current may be expected to flow to the ADC 730, which may result in the output of the ADC 730 being a digital value of 00000, for example, having a value A less than that of Table 2. 1The digital value 00000 can then be stored in the partial product register 840 0 Digital register 844 0 To 844 4 middle.

[0149] exist Fig.9F In the partial product register 840 0 To 840 2 The summation may be performed, for example, in a manner known in the art to produce a result 01111 representing the product of the multiplicand 101 and the multiplier 011. The result stored in the accumulator register 842 may represent, for example Figure 5 a of the matrix A in 11 With matrix B b 11 Continuing with this example, the process can be repeated for additional multiplicand / multiplier pairs, such as a 12 With matrix B b 21 The product of, matrix A a 13 With matrix B b 31 The product of and a of the matrix A 14 With matrix B b 41 products, and these products can be added to produce Figure 5 The matrix C described by c 11 Thus, the memory can be operated as a vector-to-vector unit (e.g., consistent with the previous example). Figure 4 Vector - Vector Unit 361 11 ) to produce an element of the result matrix C (e.g., c 11 ) value.

[0150] The expected voltage levels for access line 202 and data line 204 may be determined experimentally, empirically, or by simulation.For example, characterization of the conductance (or resistance) of memory cells 208 and NAND strings 206 is generally a routine task given a generally high level of predictability of performance. Figures 10 to 12 A characterization of the current as a function of a variable of interest can be expressed. For example, Fig.10 A representation of the cell current (Ids) as a function of the access line 202 voltage level (Vgs) for different voltage differences (Vds) from the data line 204 to the common source 216 may be shown. Fig.11 A characterization of the cell current (Ids) as a function of the access line 202 voltage level (Vgs) for different states of the data pattern within the NAND string 206 (eg, erased or programmed) may be represented for a particular voltage difference from the data line 204 to the common source 216. Fig.12A characterization of the cell current (Ids) as a function of the voltage difference (Vds) from the data line 204 to the common source 216 for different access line 202 voltage levels (Vgs) may be presented. With this or similar characterizations, knowledge of the number of NAND strings 206 that can conduct current during a multiplication operation, and the granularity and current capabilities of the available analog-to-digital converters 730, the desired voltage levels for the access line 202 and data line 204 may be readily selected to provide current within the capabilities of the selected ADC 730.

[0151] Various embodiments seek to implement the functionality of a matrix-matrix unit, a matrix-vector unit, and / or a vector-vector unit of a DLA. Fig.13 is a flow chart of a method of operating a memory according to an embodiment. The method may represent actions associated with a matrix-matrix unit. The method may be in the form of computer-readable instructions stored, for example, to instruction register 128. Such computer-readable instructions may be executed by a controller (e.g., control logic 116) to cause relevant components of the memory to perform the method.

[0152] At 1301, the value of variable a may be set to 1. Valid values ​​for variable a may be any integer value from 1 to N, where N may be equal to the number of rows of the multiplicand matrix, which may be equal to the number of columns of the multiplier matrix. At 1303, the value of variable b may be set to 1. Valid values ​​for variable b may be any integer value from 1 to N.

[0153] At 1305, the vector dot product of the a-th vector of the multiplicand matrix and the b-th vector of the multiplier matrix may be determined. Figures 14 to 16B The determination of the vector dot product is described in more detail. The determination of the vector dot product may correspond to the actions of the vector-vector unit 361. For example, referring to Figure 4 , N may be equal to 4, and a vector-vector unit 361 determining that the vector dot product of the a-th vector of the multiplicand matrix and the b-th vector of the multiplier matrix may correspond to any valid values ​​of the variables a and b ab Continuing this example, the matrix-vector unit 341 a The action may correspond to the vector-vector unit 361 ab Actions for any valid value of variable a and all valid values ​​of variable b, e.g., matrix-vector unit 341 a The action may correspond to the vector-vector unit 361 a1 ,361 a2 ,361 a3 and 361 a4Action for any valid value of variable a. Data register 120 may correspond to kernel buffer 331, for example, storing a multiplier vector (which may be received from an external device, similar to receiving data for programming, or may be read from memory cell array 104). Memory cell array 104 may correspond to, for example, a mapped memory bank 351 storing a multiplicand vector. The multiplicand may be stored in analog or binary using binary encoding, or in binary using thermometric encoding.

[0154] At 1307, the value of variable b may be incremented by 1. At 1309, it may be determined whether the value of variable b is greater than N. If not, the process may return to 1305 to determine the vector dot product of the a-th vector of the multiplicand matrix and the incremented b-th vector of the multiplier matrix. If the value of variable b is greater than N, the process may proceed to 1311.

[0155] At 1311, the value of variable a may be incremented by 1. At 1313, it may be determined whether the value of variable a is greater than N. If not, the process may return to 1303 to return the value of variable b to 1. If the value of variable a is greater than N, the process may end at 1315.

[0156] Fig.14 is a flowchart of a method for operating a memory according to another embodiment. The method may be represented by Fig.13 The method may be in the form of computer-readable instructions stored, for example, in the instruction register 128. Such computer-readable instructions may be executed by a controller (e.g., control logic 116) to cause the associated components of the memory to perform the method.

[0157] At 1421, the value of variable k may be set to 1. Valid values ​​of variable k may be any integer value from 1 to N. At 1423, the product of the kth element of the ath vector of the multiplicand matrix and the kth element of the bth vector of the multiplier matrix may be determined. Figures 15 to 16B The determination of the product is described in more detail.

[0158] At 1425, the value of the variable k may be incremented by 1. At 1427, it may be determined whether the value of the variable k is greater than N. If not, the process may return to 1423 to determine the product of the incremented kth element of the a-th vector of the multiplicand matrix and the incremented kth element of the b-th vector of the multiplier matrix. If the value of the variable k is greater than N, the process may proceed to 1429. At 1429, the product of each value of the variable k may be summed to determine the vector dot product of the a-th vector of the multiplicand matrix and the b-th vector of the multiplier matrix. The process may then proceed to 1307.

[0159] Fig.15is a flowchart of a method for operating a memory according to another embodiment. The method may be represented by Fig.14 The method may be in the form of computer-readable instructions stored, for example, to the instruction register 128. Such computer-readable instructions may be executed by a controller (e.g., control logic 116) to cause the associated components of the memory to perform the method.

[0160] At 1531, the value of the variable d may be set to 1. The valid value of the variable d may be any integer value from 1 to D, where D may be equal to the number of digits of the kth element of the bth vector of the multiplier matrix. At 1533, the multiplication partial product of the kth element of the ath vector of the multiplicand matrix and the dth digit of the kth element of the bth vector of the multiplier matrix is ​​multiplied. Reference will be made to the following Figures 16A to 16B The determination of the multiplication partial products is described in more detail.

[0161] At 1535, the value of the variable d may be incremented by 1. At 1537, it may be determined whether the value of the variable d is greater than D. If not, the process may return to 1533 to determine the multiplication partial product of the kth element of the a-th vector of the multiplicand matrix and the incremented dth number of the kth element of the b-th vector of the multiplier matrix. If the value of the variable d is greater than N, the process may proceed to 1539. At 1539, the multiplication partial products for each value of the variable d may be summed to determine the product of the kth element of the a-th vector of the multiplicand matrix and the kth element of the b-th vector of the multiplier matrix. The process may then proceed to 1425.

[0162] Fig.16A is a flowchart of a method for operating a memory according to yet another embodiment. The method may be represented by Fig.15 The actions associated with the multiplication partial product are determined at 1533. The method may be in the form of computer-readable instructions stored, for example, to the instruction register 128. Such computer-readable instructions may be executed by a controller (e.g., control logic 116) to cause the associated components of the memory to perform the method.

[0163] At 1641, a set of control signals may be applied to the plurality of access lines, the set of control signals being configured to activate memory cells of the plurality of series-connected strings of memory cells having corresponding numbers of a first logic level corresponding to the k-th element of the a-th vector of the multiplicand matrix, activate memory cells of the plurality of series-connected strings of memory cells having any numbers of the first logic level not corresponding to the k-th element of the a-th vector of the multiplicand matrix, and deactivate memory cells of the plurality of series-connected strings of memory cells having corresponding numbers of a second logic level different from the first logic level corresponding to the k-th element of the a-th vector of the multiplicand matrix. The first logic level may correspond to a digital value of 1 and the second logic level may correspond to a digital value of 0, but such roles may be reversed.

[0164] The kth element of the ath vector of the multiplicand matrix can be stored as shown in the reference Figures 6A to 6B and memory cells of a plurality of serially connected memory cell strings as described in claim 7. The set of control signals may include a first subset of control signals applied to a first subset of access lines associated with memory cells storing a k-th element of an a-th vector of a multiplicand matrix, and may further include a second subset of control signals (e.g., mutually exclusive with the first subset of control signals) applied to a second subset of access lines not associated with memory cells storing a k-th element of an a-th vector of a multiplicand matrix (e.g., mutually exclusive with the first subset of access lines). Each subset of control signals may include one or more control signals, and each subset of access lines may include one or more access lines. The second subset of control signals and the second subset of access lines may be empty sets, e.g., each memory cell in one or more of the plurality of serially connected memory cell strings may correspond to a corresponding number of the k-th element of the a-th vector of a multiplicand matrix.

[0165] The first subset of control signals applied to the first subset of access lines may include control signals having voltage levels higher than the threshold voltage of memory cells storing the first logic level and lower than the threshold voltage of memory cells storing the second logic level, for example, with reference to Figures 8A to 8F The second subset of control signals applied to the second subset of access lines may include a pass voltage, for example, a voltage level configured to activate a memory cell regardless of its stored value, such as reference voltage. Figures 8A to 8F and / or as described in 9A to 9F.

[0166] At 1643, a control signal may be applied to a plurality of data lines connected to a plurality of series-connected memory cell strings having a voltage level indicating the value of the dth digit of the kth element of the bth vector of the multiplier matrix, e.g., reference Figures 8A to 8FNote that the voltage level of the control signal may further indicate the magnitude of the d-th digit of the k-th element of the b-th vector of the multiplier matrix, for example, Figures 9A to 9F Described. The voltage level of the control signal may be configured to generate a first voltage difference (e.g., a positive voltage difference) between the plurality of data lines and a common source connected to the plurality of series-connected memory cell strings in response to the dth digit of the kth element of the bth vector of the multiplier matrix having a first logic level. The voltage level of the control signal may be configured to generate a second voltage difference (e.g., different from the first voltage difference, which may include a zero or negative voltage difference) between the plurality of data lines and the common source in response to the dth digit of the kth element of the bth vector of the multiplier matrix having a second logic level. At 1645, the resulting current level through the plurality of series-connected memory cell strings may be converted to a digital value corresponding to the multiplication partial product of the kth element of the ath vector of the multiplicand matrix and the dth digit of the kth element of the bth vector of the multiplier matrix (e.g., using an ADC). The process may then proceed to 1535.

[0167] Although it can be referenced Fig.16A In the embodiment discussed above, a control signal having a voltage level indicating that the value of the digital k-th element of the b-th vector of the multiplier matrix has a second logic level is applied, but another embodiment may eliminate the application of such a control signal to the data line, as shown in FIG. Fig. 16B discuss.

[0168] Fig. 16B is a flow chart of a method of operating a memory according to an alternative embodiment. The method may be represented by Fig.15 The actions associated with the multiplication partial product are determined at 1533. The method may be in the form of computer-readable instructions stored, for example, to the instruction register 128. Such computer-readable instructions may be executed by a controller (e.g., control logic 116) to cause the associated components of the memory to perform the method.

[0169] At 1647, it may be determined whether the value of the dth digit of the kth element of the bth vector of the multiplier matrix has a second logic level. If not, then Fig.16AThe process of 1641 to 1645 of the embodiment of the present invention may be repeated. If the value of the dth digit of the kth element of the bth vector of the multiplier matrix is ​​determined to have a second logic level, then at 1649, the digital value corresponding to the multiplication partial product of the kth element of the ath vector of the multiplicand matrix and the dth digit of the kth element of the bth vector of the multiplier matrix may be set to zero, for example, by not applying a control signal to a plurality of access lines and / or not applying a control signal to a plurality of data lines. Note that for some embodiments, the control signal applied to the access line may be maintained through all digits of a given vector of the multiplier matrix during the process of 1533, and may be further maintained through all vectors of the multiplier matrix during the process of 1305. The process may then proceed to 1535.

[0170] Although Figures 13 to 16B The flowchart of depicts one processing order, but other orders may be utilized. For example, instead of variables a, b, k, and d starting with a value of 1 and incrementing to their respective end values ​​N, N, N, and D, one or more of these variables may start with their respective end values ​​and decrement to 1 before continuing at a decision point. Or the processing of individual variables may be performed in a non-sequential order. In addition, processing may be performed concurrently for multiple values ​​of one or more variables. For example, if a first element of a vector of a multiplier matrix is ​​stored to a memory cell of a first block of memory cells (e.g., a memory cell selectively connected to a first common source), a second element of the vector of the multiplier matrix is ​​stored to a memory cell of a second block of memory cells (e.g., a memory cell selectively connected to a second common source isolated from the first common source), a third element of the vector of the multiplier matrix is ​​stored to a memory cell of a third block of memory cells (e.g., a memory cell selectively connected to a third common source isolated from the first common source and the second common source), and so on, then the determination of the product of these elements with their associated elements of the multiplier matrix may be performed concurrently.

[0171] Fig.17 Depicting a portion of a memory cell array (eg, two memory cell blocks 250) according to an embodiment 1 and 250 2 ). Fig.17 Depicting the first memory cell block 250 1 , which has: three memory cell strings connected in series ( Fig.17 215, which includes a signal responsive to a signal applied to the select line 215. 11 The control signal passes through the select gate (in Fig.17 (not marked) is selectively connected to the data line 204 10 To 204 12 and in response to the selection line 214 1 The control signal passes through the select gate (in Fig.17(not marked in FIG. 1 ) is selectively connected to the common source 216 1 The memory cell (in Fig.17 three serially connected memory cell strings (in Fig.17 215, which includes a signal responsive to a signal applied to the select line 215. 12 The control signal passes through the select gate (in Fig.17 (not marked) is selectively connected to the data line 204 10 To 204 12 and in response to the selection line 214 1 The control signal passes through the select gate (in Fig.17 (not marked in FIG. 1 ) is selectively connected to the common source 216 1 The memory cell (in Fig.17 and three serially connected memory cell strings (in Fig.17 215, which includes a signal responsive to a signal applied to the select line 215. 13 The control signal passes through the select gate (in Fig.17 (not marked) is selectively connected to the data line 204 10 To 204 12 and in response to the selection line 214 1 The control signal passes through the select gate (in Fig.17 (not marked in FIG. 1 ) is selectively connected to the common source 216 1 The memory cell (in Fig.17 not marked in the figure).

[0172] Fig.17 The second memory cell block 250 is further depicted. 2 , which has: three memory cell strings connected in series ( Fig.17 215, which includes a signal responsive to a signal applied to the select line 215. 21 The control signal passes through the select gate (in Fig.17 (not marked) is selectively connected to the data line 204 20 To 204 22 and in response to the selection line 214 2 The control signal passes through the select gate (in Fig.17 (not marked in FIG. 1 ) is selectively connected to the common source 216 2 The memory cell (in Fig.17 three serially connected memory cell strings (in Fig.17 215, which includes a signal responsive to a signal applied to the select line 215. 22 The control signal passes through the select gate (in Fig.17 (not marked) is selectively connected to the data line 204 20 To 204 22and in response to the selection line 214 2 The control signal passes through the select gate (in Fig.17 (not marked in FIG. 1 ) is selectively connected to the common source 216 2 The memory cell (in Fig.17 and three serially connected memory cell strings (in Fig.17 215, which includes a signal responsive to a signal applied to the select line 215. 23 The control signal passes through the select gate (in Fig.17 (not marked) is selectively connected to the data line 204 20 To 204 22 and in response to the selection line 214 2 The control signal passes through the select gate (in Fig.17 (not marked in FIG. 1 ) is selectively connected to the common source 216 2 The memory cell (in Fig.17 not marked in the figure).

[0173] Common source 216 1 Can be connected to analog-to-digital converter (ADC) 730 1 Input 732 1 ADC 730 1 The output is 734 1 A plurality of signal lines may be included, each signal line being configured to provide a corresponding digital signal having one of two logic levels (eg, a "1" or a "0" logic level). ADC 730 1 For reference Figure 7 The ADC 730 is configured as described above. Common source 216 2 Can be connected to analog-to-digital converter (ADC) 730 2 Input 732 2 ADC 730 2 The output is 734 2 A plurality of signal lines may be included, each signal line being configured to provide a corresponding digital signal having one of two logic levels (eg, a "1" or a "0" logic level). ADC 730 2 For reference Figure 7 The ADC 730 is configured as described above. 1 and 730 2 The output is 734 1 and 734 2The ADC 730 may be connected to the MAC register 136, for example, to the corresponding part of the MAC register 136 to store the multiplication partial product thereof. Obviously, the additional memory unit block 250 may have a corresponding source 216 connected to the corresponding ADC 730, which is connected to the corresponding part of the MAC register 136, so as to increase the parallelism of performing multiple multiplication operations concurrently.

[0174] in addition, Fig.17 Embodiments of the invention may also be used to increase the number of serially connected strings of memory cells that may be used to store elements of a vector of a multiplicand matrix. For example, a first digit subset (e.g., less significant digits) of the elements of a vector of a multiplicand matrix may be stored in a memory cell block 250. 2 The memory cell of the multiplier matrix can be used to store a second digital subset (eg, more significant digits) of the elements of the vector of the multiplier matrix to the memory cell block 250. 1 The same control signal may be applied to the data lines 204 of both memory cell blocks 250, the corresponding current levels may be converted by the ADC 730, and the resulting values ​​may be stored in the corresponding portions of the MAC registers 136 for subsequent summation.

[0175] in conclusion

[0176] Although specific embodiments have been illustrated and described herein, it should be understood by those of ordinary skill in the art that any arrangement calculated to achieve the same purpose may be substituted for the specific embodiments shown. Many adaptations of the embodiments will be apparent to those of ordinary skill in the art. Therefore, this application is intended to cover any adaptation or variation of the embodiments.

Claims

1. A memory comprising: Multiple data lines; Common source; a plurality of serially connected memory cell strings, wherein each of the plurality of serially connected memory cell strings is selectively connected to a corresponding one of the plurality of data lines and selectively connected to the common source, and wherein each of the plurality of serially connected memory cell strings corresponds to a corresponding one of a plurality of digits of a multiplicand; a plurality of access lines, wherein each access line of the plurality of access lines is connected to a control gate of a corresponding memory cell of each serially connected string of memory cells of the plurality of serially connected strings of memory cells; and A controller configured to cause the memory to: For each of the multiple numbers of the multiplier: generating respective currents flowing through the plurality of serially connected strings of memory cells, the respective currents having respective current levels indicative of a value of the digit of the plurality of digits of the multiplier multiplied by the multiplicand; and converting the respective current levels of the digits of the multipliers to respective digital values ​​indicating the values ​​and magnitudes of the digits of the multipliers multiplied by the multiplicand; and The respective digital values ​​of each of the plurality of digits of the multiplier are summed.

2. A memory according to claim 1, wherein the number of serially connected memory cell strings in the plurality of serially connected memory cell strings corresponding to the least significant digit of the plurality of digits of the multiplicand is equal to the number of serially connected memory cell strings in the plurality of serially connected memory cell strings corresponding to each remaining digit of the plurality of digits of the multiplicand.

3. A memory according to claim 2, wherein each of the plurality of series-connected memory cell strings has a corresponding subgroup of memory cells corresponding to its corresponding digit among the plurality of digits of the multiplicand, and wherein the threshold voltage of the corresponding subgroup of memory cells in the number of series-connected memory cell strings among the plurality of series-connected memory cell strings corresponding to the least significant digit among the plurality of digits of the multiplicand is higher than the threshold voltage of the corresponding subgroup of memory cells in the number of series-connected memory cell strings among the plurality of series-connected memory cell strings corresponding to the more significant digits among the plurality of digits of the multiplicand.

4. The memory of claim 3 , wherein the magnitude of the more significant digits of the multiple digits of the multiplicand is 2^N times the magnitude of the least significant digit of the multiple digits of the multiplicand, and wherein the threshold voltages of the corresponding subset of memory cells of the number of series-connected memory cells of the multiple series-connected memory cell strings corresponding to the least significant digits of the multiple digits of the multiplicand are configured to produce a resistance in response to a set of control signals applied to the multiple access lines, the resistance being 2^N times the resistance produced by the threshold voltages of the corresponding subset of memory cells of the number of series-connected memory cells of the multiple series-connected memory cell strings corresponding to the more significant digits of the multiple digits of the multiplicand in response to the set of control signals applied to the multiple access lines.

5. A memory according to claim 1, wherein the number of serially connected memory cell strings in the plurality of serially connected memory cell strings corresponding to the least significant digits in the plurality of digits of the multiplicand is different from the number of serially connected memory cell strings in the plurality of serially connected memory cell strings corresponding to the more significant digits in the plurality of digits of the multiplicand.

6. A memory according to claim 1, wherein the magnitude of the more significant digits of the multiple digits of the multiplicand is 2^N times the magnitude of the least significant digit of the multiple digits of the multiplicand, and wherein the number of series-connected memory cell strings in the multiple series-connected memory cell strings corresponding to the more significant digits of the multiple digits of the multiplicand is 2^N times the number of series-connected memory cell strings in the multiple series-connected memory cell strings corresponding to the least significant digit of the multiple digits of the multiplicand.

7. The memory of claim 1 , wherein the controller being configured to cause the memory to generate a current flowing through the plurality of serially connected memory cell strings comprises the controller being configured to cause the memory to: for each of the plurality of serially connected memory cell strings in which a corresponding digit of the plurality of digits of the multiplicand has a first logic level, activating each memory cell in the serially connected memory cell string; and For each series-connected memory cell string in which a corresponding digit of the digits of the multiplicand has a second logic level different from the first logic level, each memory cell of the series-connected memory cell string is deactivated.

8. A memory comprising: Multiple data lines; Common source; A multiplication-accumulation MAC register, which includes a plurality of partial product registers and an accumulation register; an analog-to-digital converter ADC having an input connected to the common source and having an output connected to the MAC register; a plurality of serially connected memory cell strings, wherein each serially connected memory cell string of the plurality of serially connected memory cell strings is selectively connected to a corresponding data line of the plurality of data lines and selectively connected to the common source, and wherein each serially connected memory cell string of the plurality of serially connected memory cell strings corresponds to a corresponding number of corresponding elements of a corresponding vector of a multiplicand matrix having N vectors, wherein N is an integer value greater than or equal to 1; a plurality of access lines, wherein each access line of the plurality of access lines is connected to a control gate of a corresponding memory cell of each serially connected string of memory cells of the plurality of serially connected strings of memory cells; and A controller configured to cause the memory to: For an element in one or more elements of the first vector of the multiplicand matrix: generating a current flowing through the plurality of serially connected strings of memory cells, the current having a current level indicative of a value of the element of the first vector multiplied by a number having a multiplier of one or more numbers; and The current levels of the elements of the first vector are converted to corresponding digital values ​​indicative of the values ​​and magnitudes of the elements of the first vector multiplied by the number of the multiplier.

9. The memory of claim 8, wherein the number of the multipliers is a number of elements of a vector of a multiplier matrix, wherein the multiplier matrix has N vectors, and wherein the controller is further configured to cause the memory to: For each integer value a=1 to N: For each integer value b=1 to N: Determine the vector dot product of the a-th vector of the multiplicand matrix and the b-th vector of the multiplier matrix; wherein the controller being configured to cause the memory to determine the vector dot product of the a-th vector of the multiplicand matrix and the b-th vector of the multiplier matrix comprises the controller being configured to cause the memory to determine a respective product of each of one or more elements of the a-th vector of the multiplicand matrix and its corresponding element of one or more elements of the b-th vector of the multiplier matrix, and summing the respective products; wherein the controller is configured to cause the memory to determine the corresponding products of the selected elements of the a-th vector of the multiplicand matrix and the corresponding elements thereof among the one or more elements of the b-th vector of the multiplier matrix, comprising: the controller is configured to cause the memory to determine the corresponding multiplication partial products of each number of the selected elements of the a-th vector of the multiplicand matrix and the corresponding elements thereof of the b-th vector of the multiplier matrix, and sum the corresponding multiplication partial products; and wherein the controller being configured to cause the memory to determine the respective multiplication partial products of the selected elements of the a-th vector of the multiplicand matrix and selected numbers of corresponding elements of the b-th vector of the multiplier matrix comprises the controller being configured to cause the memory to: generating currents flowing through the plurality of serially connected memory cell strings, the currents having respective current levels indicative of the values ​​of the selected elements of the a-th vector of the multiplicand matrix multiplied by the selected numbers of their corresponding elements of the b-th vector of the multiplier matrix; and The respective current levels of the selected elements of the a-th vector of the multiplicand matrix and the selected digits of their corresponding elements of the b-th vector of the multiplier matrix are converted into respective digital values ​​indicating the values ​​and magnitudes of the selected elements of the a-th vector of the multiplicand matrix multiplied by the selected digits of their corresponding elements of the b-th vector of the multiplier matrix.

10. The memory of claim 9, wherein each vector of the multiplicand matrix has N elements, wherein each vector of the multiplier matrix has N elements, and wherein the controller is configured to cause the memory to determine the vector dot product of the a-th vector of the multiplicand matrix and the b-th vector of the multiplier matrix comprises the controller being configured to cause the memory to: For each integer value k=1 to N: determining the product of a k-th element of the a-th vector of the multiplicand matrix and a corresponding k-th element of the b-th vector of the multiplier matrix; and The products of the N elements of the a-th vector of the multiplicand matrix and their corresponding elements of the b-th vector of the multiplier matrix are summed.

11. The memory of claim 10, wherein the controller being configured to cause the memory to determine the product of the kth element of the ath vector of the multiplicand matrix and the kth element of the bth vector of the multiplier matrix comprises the controller being configured to cause the memory to: For each integer value d=1 to D, where D is equal to the number of digits of the corresponding k-th element of the b-th vector of the multiplier matrix: determining a d-th digital multiplication partial product of the k-th element of the a-th vector of the multiplicand matrix and the k-th element of the b-th vector of the multiplier matrix; and The D numbers of the kth element of the bth vector of the multiplier matrix and the kth element of the ath vector of the multiplicand matrix are summed.

12. The memory of claim 11 , wherein the k-th element of the a-th vector of the multiplicand matrix corresponds to the selected element of the a-th vector of the multiplicand matrix, wherein the d-th number of the k-th element of the b-th vector of the multiplier matrix corresponds to the selected number of the element of the b-th vector of the multiplier matrix corresponding to the selected element of the a-th vector of the multiplicand matrix, and wherein the controller is configured to cause the memory to determine the multiplicative partial product of the selected element of the a-th vector of the multiplicand matrix and the selected number of its corresponding element of the b-th vector of the multiplier matrix comprises the controller being configured to cause the memory to: applying a set of control signals to a plurality of access lines, the set of control signals configured to activate memory cells of the plurality of series-connected memory cell strings having corresponding numbers of a first logic level corresponding to the selected element of the a-th vector of the multiplicand matrix, activate memory cells of the plurality of series-connected memory cell strings not corresponding to any numbers of the selected element of the a-th vector of the multiplicand matrix, and deactivate memory cells of the plurality of series-connected memory cell strings having corresponding numbers of a second logic level different from the first logic level corresponding to the selected element of the a-th vector of the multiplicand matrix; applying control signals to the plurality of data lines connected to the plurality of serially connected strings of memory cells having voltage levels indicative of values ​​of the selected digits of the corresponding elements of the bth vector of the multiplier matrix; and The resulting current level received at the input of the ADC is converted to a digital value corresponding to the multiplicative partial product of the selected element of the ath vector of the multiplicand matrix and the selected number of corresponding elements of the bth vector of the multiplier matrix.

13. The memory of claim 12, wherein the selected numbers of the corresponding elements of the bth vector of the multiplier matrix have the first logic level.

14. The memory of claim 12, wherein the control signals applied to the plurality of data lines have voltage levels indicative of both the value and magnitude of the selected numbers of the corresponding elements of the bth vector of the multiplier matrix.

15. A memory comprising: Multiple data lines; Common source; A multiplication-accumulation MAC register, which includes a plurality of partial product registers and an accumulation register; an analog-to-digital converter ADC having an input connected to the common source and having an output connected to the MAC register; a plurality of serially connected memory cell strings, wherein each of the plurality of serially connected memory cell strings is selectively connected to a corresponding one of the plurality of data lines and selectively connected to the common source, and wherein each of the plurality of serially connected memory cell strings corresponds to a corresponding one of a plurality of digits of a multiplicand; a plurality of access lines, wherein each access line of the plurality of access lines is connected to a control gate of a corresponding memory cell of each serially connected string of memory cells of the plurality of serially connected strings of memory cells; and A controller configured to cause the memory to: applying a set of control signals to a plurality of access lines, the set of control signals configured to activate memory cells of the plurality of series-connected strings of memory cells corresponding to respective digits of the multiplicand having a first logic level, activate memory cells of the plurality of series-connected strings of memory cells not corresponding to any digits of the multiplicand, and deactivate memory cells of the plurality of series-connected strings of memory cells corresponding to respective digits of the multiplicand having a second logic level different from the first logic level; applying control signals to the plurality of data lines connected to the plurality of serially connected memory cell strings having voltage levels indicating the value of a digit of a multiplier when the plurality of serially connected memory cell strings are connected to the common source; and The current level produced by applying the set of control signals to the multiple access lines and applying the control signals to the multiple data lines at the input of the ADC when the multiple series-connected memory cell strings are connected to the common source and the input of the ADC is converted into a corresponding digital value corresponding to the value of the multiplicand multiplied by the multiplier.

16. The memory of claim 15, wherein the multiplier has D digits, and wherein the controller is further configured to cause the memory to: For each integer value d=1 to D: In response to the dth digit of the multiplier having the first logic level: applying a set of control signals to the plurality of access lines, the set of control signals configured to activate memory cells of the plurality of series-connected memory cell strings corresponding to respective digits of the multiplicand having the first logic level, activate memory cells of the plurality of series-connected memory cell strings not corresponding to any digits of the multiplicand, and deactivate memory cells of the plurality of series-connected memory cell strings corresponding to respective digits of the multiplicand having a second logic level different from the first logic level; applying corresponding control signals to the plurality of data lines connected to the plurality of serially connected memory cell strings having voltage levels indicative of a value of the d-th digit of the multiplier when the plurality of serially connected memory cell strings are connected to the common source; converting respective current levels resulting from applying the set of control signals to the plurality of access lines and applying the control signals to the plurality of data lines at the input of the ADC when the plurality of series-connected strings of memory cells are connected to the common source and the input of the ADC to respective digital values ​​corresponding to respective multiplication partial products of the multiplicand and the dth digit of the multiplier; and storing the corresponding multiplication partial products of the multiplicand and the dth digit of the multiplier in corresponding partial product registers of the plurality of partial product registers of the MAC register; and The plurality of partial product registers of the MAC register are summed and the sum is stored in the accumulation register of the MAC register.

17. The memory of claim 16, wherein the controller is configured to cause the memory to perform an action in response to the dth digit of the multiplier having the first logic level, comprises the controller being configured to cause the memory to perform the action in response to the dth digit of the multiplier having the first logic level or having the second logic level.

18. The memory of claim 16, wherein the controller is further configured to cause the memory to: in response to the dth digit of the multiplier having the second logic level, store zero to a corresponding partial product register of the plurality of partial product registers of the MAC register.

19. The memory of claim 18, wherein the controller being configured to cause the memory to store the zeros to the respective partial product registers comprises the controller being configured to cause the memory to store the zeros to the respective partial product registers without applying respective control signals to the plurality of data lines connected to the plurality of series-connected strings of memory cells having a voltage level indicative of the value of the dth digit of the multiplier having the second logic level.

20. The memory of claim 19, wherein the controller is configured to cause the memory to store the zeros to the respective partial product registers without applying the respective control signals to the plurality of data lines connected to the plurality of serially connected memory cell strings further comprises the controller being configured to cause the memory to store the zeros to the respective partial product registers without applying the set of control signals to the plurality of access lines.

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