An eFlash control system and method based on instruction pre-reading

Abstract

This application belongs to the field of chip technology and discloses an eFlash control system and method based on instruction pre-reading. The system includes an interconnected instruction pre-reading circuit and an eFlash controller. The instruction pre-reading circuit is used to receive information transmitted by the CPU and, based on the information, sequentially generates an instruction fetch signal and an instruction pre-reading signal. The instruction fetch signal and the instruction pre-reading signal are sequentially sent to the eFlash controller. Upon receiving the instruction fetch signal, the eFlash controller is used to determine whether the read address in the instruction fetch signal is equal to the pre-read address in the pre-read register. If so, it outputs an instruction hit signal. Upon receiving the instruction pre-read signal, the pre-read address in the pre-read register is increased by a preset instruction length. This application can achieve zero-wait cycle instruction fetching without substantially increasing chip area, improving instruction fetch efficiency by approximately 20%.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to an eFlash control system and method based on instruction pre-reading. Background Art

[0002] The eFlash read time typically ranges from 25 to 35 nanoseconds. This means that it takes 25 to 35 nanoseconds from the time a read command is issued on the eFlash interface to the time the data is read. Consequently, the maximum eFlash read speed is limited to 40 MHz. When the system's main frequency exceeds the eFlash read time, the HREADYOUT signal on the eFlash controller's bus must be pulled down to 0 before the data read from the eFlash is valid. Therefore, increasing the system's main frequency does not improve system efficiency linearly, and there will be some loss in energy efficiency.

[0003] Existing eFlash instruction pre-reading methods use a cache design method to predict the data that will be accessed cyclically in the eFlash and store it in the SRAM within the cache, or use a design method with a larger bit width eFlash to pre-read multiple consecutive instructions at a time. Although the two existing pre-reading methods can greatly improve the operating efficiency of the system, the use of cache or a larger bit width eFlash will lead to an increase in chip area and cost. Summary of the Invention

[0004] The present application provides an eFlash control system and method based on instruction pre-reading, which can achieve zero-wait cycle instruction fetching without substantially increasing the chip area, thereby improving instruction fetching efficiency by about 20%.

[0005] In a first aspect, an embodiment of the present application provides an eFlash control system based on instruction pre-reading, including:

[0006] Interconnected instruction prefetch circuit and eFlash controller;

[0007] The instruction pre-read circuit is used to receive the transmission information of the CPU, generate an instruction fetch signal and an instruction pre-read signal in sequence based on the transmission information, and send the instruction fetch signal and the instruction pre-read signal to the eFlash controller in sequence;

[0008] The eFlash controller is used to determine whether the read address in the instruction fetch signal is equal to the pre-read address in the pre-read register when receiving the instruction fetch signal; if so, output an instruction hit signal; and when receiving the instruction pre-read signal, increase the pre-read address in the pre-read register by a preset instruction length.

[0009] Furthermore, the transmission information includes a selection signal, a transmission request signal, a transmission type signal, a transmission operation signal and a transmission completion signal.

[0010] Furthermore, the instruction pre-reading circuit includes a first logic module, a state switching module, a first state machine, a second state machine, and a second logic module; the first logic module is used to receive the transmission information and generate an instruction fetch signal, and send the instruction fetch signal to the state switching module, the first state machine, the second state machine, and the eFlash controller respectively;

[0011] The state switching module is used to flip the state switching signal when detecting the falling edge of the instruction fetch signal, and send the state switching signal to the second state machine and send it to the first state machine through the NOT gate;

[0012] The first state machine is configured to generate a first pre-read signal based on a state switching signal, an instruction fetch signal, and a transmission completion signal, and send the first pre-read signal to a second logic module. The second state machine is configured to generate a second pre-read signal based on the state switching signal, the instruction fetch signal, and the transmission completion signal, and send the second pre-read signal to the second logic module. The second logic module is configured to generate an instruction pre-read signal based on the first pre-read signal and the second pre-read signal, and send the instruction pre-read signal to the eFlash controller.

[0013] Furthermore, the first logic module includes a first NOT gate, a second NOT gate, and an AND gate; the output end of the AND gate is connected to the input end of the state switching module, the first state machine, the second state machine, and the eFlash controller respectively;

[0014] The first NOT gate is used to receive the transfer type signal, flip it and send it to the input end of the AND gate;

[0015] The second NOT gate is used for receiving the transmission operation signal, flipping it and sending it to the input end of the AND gate.

[0016] Furthermore, the second logic module is an OR gate, the input end of the OR gate is connected to the output end of the first state machine and the output end of the second state machine respectively, and the output end of the OR gate is connected to the input end of the eFlash controller.

[0017] Furthermore, the first state machine is specifically configured to generate a first pre-read signal according to the received transmission completion signal and send the signal to the second logic module when the state switching signal is at a high level and a falling edge of the instruction fetch signal is detected.

[0018] Furthermore, the second state machine is specifically configured to generate a second pre-read signal according to the received transmission completion signal and send the signal to the second logic module when the state switching signal is at a high level and a falling edge of the instruction fetch signal is detected.

[0019] Furthermore, the bit width of the eFlash controller is 32 bits.

[0020] Furthermore, the preset instruction length is 4 bits.

[0021] In a second aspect, an embodiment of the present application provides an eFlash control method based on instruction pre-reading, including:

[0022] The instruction pre-reading circuit receives the transmission information from the CPU and generates an instruction fetch signal based on the transmission information;

[0023] The instruction pre-read circuit sends the instruction fetch signal to the eFlash controller;

[0024] The eFlash controller receives an instruction fetch signal and determines whether the read address in the instruction fetch signal is equal to the pre-read address in the pre-read register; if so, it outputs an instruction hit signal;

[0025] The instruction pre-read circuit generates an instruction pre-read signal based on the transmission information and sends the signal to the eFlash controller;

[0026] The eFlash controller receives the instruction pre-read signal and increases the pre-read address in the pre-read register by a preset instruction length.

[0027] In summary, compared with the prior art, the technical solutions provided by the embodiments of the present application have at least the following beneficial effects:

[0028] An embodiment of the present application provides an eFlash control system based on instruction pre-reading, which generates an instruction fetch signal and an instruction pre-read signal through an instruction pre-read circuit. After the eFlash controller completes the corresponding read operation according to the instruction fetch signal, it can immediately update the pre-read address in the pre-read register to the next continuous address according to the instruction pre-read signal and the preset instruction length. When the operation is performed next time according to the instruction fetch signal, because the read address and the pre-read address in the instruction fetch signal are equal, the eFlash controller will directly output an instruction hit signal, indicating that the received instruction fetch signal has been pre-read, and there is no need to wait for the completion of the instruction fetch by pulling down the bus terminal HREADYOUT signal for 1 cycle. The instruction pre-read circuit of the present application can be reused on different process platforms, and the instruction fetch efficiency is improved by about 20% without basically increasing the chip area. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A structural diagram of an instruction pre-reading circuit provided as an exemplary embodiment of the present application.

[0030] Figure 2 A timing diagram of the generation of an instruction fetch signal provided for an exemplary embodiment of the present application.

[0031] Figure 3A state machine operation timing diagram provided for an exemplary embodiment of the present application.

[0032] Figure 4 A schematic diagram of a pre-read hit structure in an eFlash controller provided as an exemplary embodiment of the present application.

[0033] Figure 5 A timing diagram comparing the pre-read hit process provided for an exemplary embodiment of the present application.

[0034] Figure 6 A flowchart of an eFlash control method based on instruction pre-reading is provided as an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0035] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0036] Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative work shall fall within the scope of protection of this application.

[0037] An embodiment of the present application provides an eFlash control system based on instruction pre-reading, including an instruction pre-reading circuit and an eFlash controller connected to each other; the instruction pre-reading circuit is used to receive transmission information from a CPU, and generate an instruction fetch signal and an instruction pre-reading signal based on the transmission information; and the instruction fetch signal and the instruction pre-reading signal are sent to the eFlash controller in sequence.

[0038] The eFlash controller is used to determine whether the read address in the instruction fetch signal is equal to the pre-read address in the pre-read register when receiving the instruction fetch signal; if so, output an instruction hit signal.

[0039] When the eFlash controller receives the instruction pre-read signal, it increases the pre-read address in the pre-read register by a preset instruction length.

[0040] The transmission information includes a selection signal, a transmission request signal, a transmission type signal, a transmission operation signal, and a transmission completion signal. When the bit width of the eFlash controller is 32 bits, the preset instruction length is 4 bits.

[0041] Specifically, see Figure 1 The instruction pre-reading circuit includes a first logic module, a state switching module fsm_sel, a first state machine fsm_0, a second state machine fsm_1 and a second logic module.

[0042] The first logic module is used to receive the transmission information and generate an instruction fetch signal, and send the instruction fetch signal to the state switching module, the first state machine, the second state machine and the eFlash controller respectively.

[0043] like Figure 1 As shown, the first logic module includes a first NOT gate, a second NOT gate and an AND gate; the output end of the AND gate is respectively connected to the input end of the state switching module, the first state machine, the second state machine and the eFlash controller (the eFlash controller is not marked).

[0044] The first NOT gate is used to receive the transmission type signal, flip it, and then send it to the input end of the AND gate.

[0045] The second NOT gate is used for receiving the transmission operation signal, flipping it and sending it to the input end of the AND gate.

[0046] like Figure 1 As shown, the HSEL signal is the selection signal, which is used to indicate which Slave is currently selected for transmission. When HSEL=1, it indicates that the current Slave is selected; HTRANS[1] is the transmission request signal, which is used to indicate the current transmission type.

[0047] HPROT[0] is the transfer type signal, used to indicate whether the current transfer is an instruction or data transfer. When HPROT[0] = 0, it indicates that the transfer is an instruction fetch request. HWRITE is the transfer operation signal, used to indicate the current transfer direction, i.e., a read / write operation. HREADY is the transfer completion signal, used to indicate whether the current transfer is complete. HREADY = 1 indicates that the current transfer is complete.

[0048] See Figure 1 and Figure 2 , the fetch_signal instruction fetch signal is generated by the combinational logic composed of AHB related signals, that is, fetch_signal = HSEL&HTRANS[1]&~HPROT[0]&~HWRITE&HREADY.

[0049] When all the above transmission signals meet the conditions, the fetch_signal instruction fetch signal is 1, indicating that the Master initiates a valid instruction fetch operation to the Slave through the AHB bus.

[0050] The state switching module is used to flip the state switching signal when detecting the falling edge of the instruction fetch signal, and send the state switching signal to the second state machine and then to the first state machine through the NOT gate.

[0051] The first state machine is configured to generate a first pre-read signal based on a state switching signal, an instruction fetch signal, and a transmission completion signal, and send the first pre-read signal to a second logic module. The second state machine is configured to generate a second pre-read signal based on the state switching signal, the instruction fetch signal, and the transmission completion signal, and send the second pre-read signal to the second logic module. The second logic module is configured to generate an instruction pre-read signal based on the first pre-read signal and the second pre-read signal, and send the instruction pre-read signal to the eFlash controller.

[0052] The second logic module is an OR gate, the input end of the OR gate is connected to the output end of the first state machine and the output end of the second state machine respectively, and the output end of the OR gate is connected to the input end of the eFlash controller.

[0053] Figure 1 The falling edge marker between the two state machines and the second logic module indicates that either the first pre-read signal or the second pre-read signal is valid on a falling edge. fetch_signal is the instruction fetch signal. prefetch_signal0 is the first pre-read signal generated by the first state machine fsm_0, and prefetch_signal1 is the second pre-read signal generated by the second state machine fsm_1.

[0054] This application uses two parallel cross-working state machines, fsm_0 and fsm_1, which generate instruction pre-read signals by monitoring the information sent by the CPU to the AHB bus. The initial value of the two state machines after power-on reset is 0. When the instruction fetch signal is monitored, the two state machines begin to work alternately. The detection of the HREADY signal indicates that the instruction fetch operation of the currently operating state machine has been completed. Because the instruction fetch operation initiated by the AHB bus is a pipeline structure, this application uses two parallel cross-working state machines to avoid the situation where the instruction fetch operation is not processed in a timely manner.

[0055] See Figure 3 , fetch_signal instruction fetch signal is used to control the state switching of state machines fsm_0 and fsm_1.

[0056] The first state machine is specifically configured to generate a first pre-read signal according to the received transmission completion signal and send the signal to the second logic module when the state switching signal is at a high level and a falling edge of the instruction fetch signal is detected.

[0057] The second state machine is specifically configured to generate a second pre-read signal according to the received transmission completion signal and send the signal to the second logic module when the state switching signal is at a high level and a falling edge of the instruction fetch signal is detected.

[0058] In the specific implementation process, the initial value of fsm_sel is 0. Every time an instruction fetch operation is monitored, that is, when the fetch_signal signal falls, the fsm_sel signal is flipped, and the switching state machines fsm_0 and fsm_1 work alternately.

[0059] This application assumes that the first state machine fsm_0 records the instruction fetch operation first. When fsm_0=0, the falling edge of the fetch_signal signal is detected, the state switching signal fsm_sel=0 and the transmission completion signal HREADY=1, then fsm_0 is set to 1 (such as Figure 3 As shown by the blue arrow in the middle); when fsm_0=1, HREADY=1 is detected, indicating that the first state machine fsm_0 has completed the instruction fetch operation, fsm_0=0 (as shown in the figure); Figure 3 When the instruction fetch operation is detected again, the parallel second state machine fsm_1 records the instruction fetch operation. When fsm_1 = 0, the falling edge of the fetch_signal signal is detected, the state switching signal fsm_sel = 1 and HREADY = 1, and fsm_1 is set to 1 (as shown in the figure). Figure 3 When fsm_1=1, HREADY=1 is detected, indicating that the instruction fetching operation of the state machine fsm_1 is completed, and fsm_1=0 (as shown in the blue arrow in the figure). Figure 3 When no instruction fetch signal arrives, the state of the state machine remains unchanged, avoiding inefficient continuous pre-reading.

[0060] prefetch_signal0 is the first prefetch signal generated by the first state machine fsm_0, and prefetch_signal1 is the second prefetch signal generated by the second state machine fsm_1. The two state machines work alternately to initiate instruction prefetch signals. The instruction prefetch signal prefetch_signal output by the OR gate is sent to the eFlash controller. Based on prefetch_signal, the eFlash controller initiates an instruction prefetch operation to the eFlash before the master initiates the next instruction fetch operation to the slave via the AHB bus, that is, during the AHB bus idle period, thereby improving eFlash instruction fetch efficiency.

[0061] See Figure 4 and Figure 5 HADDR represents the address bus. fetch_signal is the instruction fetch signal initiated by the CPU ( Figure 1 fetch_addr is the read address of the instruction fetch signal, generated by the HADDR signal and stored in the fetch_addr register. prefetch_signal is the instruction pre-read signal ( Figure 1 As shown), prefetch_addr is the corresponding pre-read address, stored in the prefetch_addr register. Each instruction fetch operation automatically updates prefetch_addr to the next continuous address of the current flash address, that is, prefetch_addr = fetch_addr + 4 (eflash bit width 32bit). When the read address of the initiated instruction fetch signal is the same as the pre-read address, the fetch_hit signal, that is, the instruction hit signal, will be triggered, indicating that the current instruction fetch has been pre-read, and there is no need to wait for the completion of the read instruction by pulling down HREADYOUT for 1cycle. Subsequent continuous instruction fetches trigger fetch_hit without pulling down HREADYOUT, thereby achieving 0 wait cycle instruction fetching and improving instruction fetching efficiency.

[0062] The above embodiment provides an eFlash control system based on instruction pre-reading, which generates an instruction fetch signal and an instruction pre-read signal through an instruction pre-read circuit, so that after the eFlash controller completes the corresponding read operation according to the instruction fetch signal, it can immediately update the pre-read address in the pre-read register to the next continuous address according to the instruction pre-read signal and the preset instruction length, so that the next time an operation is performed according to the instruction fetch signal, because the read address and the pre-read address in the instruction fetch signal are equal, the eFlash controller will directly output an instruction hit signal, indicating that the received instruction fetch signal has been pre-read, and there is no need to wait for the completion of the instruction fetch by pulling down the bus terminal HREADYOUT signal for 1 cycle; the instruction pre-read circuit of the present application can be reused on different process platforms, and the instruction fetch efficiency is improved by about 20% without basically increasing the chip area.

[0063] See Figure 6 Another embodiment of the present application provides an eFlash control method based on instruction pre-reading, including:

[0064] In step S1 , the instruction pre-reading circuit receives the transmission information from the CPU and generates an instruction fetch signal based on the transmission information.

[0065] In step S2 , the instruction pre-read circuit sends an instruction fetch signal to the eFlash controller.

[0066] In step S3 , the eFlash controller receives an instruction fetch signal and determines whether the read address in the instruction fetch signal is equal to the pre-read address in the pre-read register; if so, an instruction hit signal is output.

[0067] In step S4 , the instruction pre-read circuit generates an instruction pre-read signal based on the transmission information and sends the signal to the eFlash controller.

[0068] In step S5, the eFlash controller receives the instruction pre-read signal and increments the pre-read address in the pre-read register by the preset instruction length. The specific limitations of the eFlash control method based on instruction pre-reading provided in this embodiment can be found in the embodiment of an eFlash control system based on instruction pre-reading above, and are not further described here.

[0069] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0070] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. An eFlash control system based on instruction pre-reading, characterized in that: include: Interconnected instruction prefetch circuit and eFlash controller; The instruction pre-read circuit is used to receive transmission information from the CPU, generate an instruction fetch signal and an instruction pre-read signal in sequence based on the transmission information, and send the instruction fetch signal and the instruction pre-read signal in sequence to the eFlash controller; the transmission information includes a selection signal, a transmission request signal, a transmission type signal, a transmission operation signal, and a transmission completion signal; Specifically, the instruction pre-reading circuit includes a first logic module, a state switching module, a first state machine, a second state machine, and a second logic module; the first logic module is used to receive the transmission information and generate the instruction fetch signal, and send the instruction fetch signal to the state switching module, the first state machine, the second state machine, and the eFlash controller respectively; The state switching module is configured to flip the state switching signal upon detecting a falling edge of the instruction fetch signal, and send the state switching signal to the second state machine, and then to the first state machine through a NOT gate; the first state machine is configured to generate a first pre-read signal based on the state switching signal, the instruction fetch signal, and the transfer completion signal, and send the first pre-read signal to the second logic module; the second state machine is configured to generate a second pre-read signal based on the state switching signal, the instruction fetch signal, and the transfer completion signal, and send the second pre-read signal to the second logic module; the second logic module is configured to generate the instruction pre-read signal based on the first pre-read signal and the second pre-read signal, and send the instruction pre-read signal to the eFlash controller; The eFlash controller is used to determine whether the read address in the instruction fetch signal is equal to the pre-read address in the pre-read register when receiving the instruction fetch signal; if so, output an instruction hit signal; and when receiving the instruction pre-read signal, increase the pre-read address in the pre-read register by a preset instruction length.

2. The eFlash control system based on instruction pre-reading according to claim 1, characterized in that: The first logic module includes a first NOT gate, a second NOT gate and an AND gate; the output end of the AND gate is respectively connected to the input end of the state switching module, the first state machine, the second state machine and the eFlash controller; The first NOT gate is used to receive the transmission type signal, flip it, and then send it to the input end of the AND gate; The second NOT gate is used to receive the transmission operation signal, flip it, and then send it to the input end of the AND gate.

3. The eFlash control system based on instruction pre-reading according to claim 1, characterized in that: The second logic module is an OR gate, the input end of the OR gate is connected to the output end of the first state machine and the output end of the second state machine respectively, and the output end of the OR gate is connected to the input end of the eFlash controller.

4. The eFlash control system based on instruction pre-reading according to claim 1, characterized in that: The first state machine is specifically configured to generate the first pre-read signal according to the received transfer completion signal and send the signal to the second logic module when the state switching signal is at a high level and a falling edge of the instruction fetch signal is detected.

5. The eFlash control system based on instruction pre-reading according to claim 1, characterized in that: The second state machine is specifically configured to generate the second pre-read signal according to the received transfer completion signal and send the signal to the second logic module when the state switching signal is at a high level and a falling edge of the instruction fetch signal is detected.

6. The eFlash control system based on instruction pre-reading according to claim 1, characterized in that: The bit width of the eFlash controller is 32 bits.

7. The eFlash control system based on instruction pre-reading according to claim 6, characterized in that: The preset instruction length is 4 bits.

8. An eFlash control method based on instruction pre-reading, characterized in that: The eFlash control system based on instruction pre-reading as claimed in any one of claims 1 to 7 comprises: The instruction pre-reading circuit receives the transmission information of the CPU and generates an instruction fetch signal based on the transmission information; The instruction pre-read circuit sends the instruction fetch signal to the eFlash controller; The eFlash controller receives the instruction fetch signal and determines whether the read address in the instruction fetch signal is equal to the pre-read address in the pre-read register; if so, outputs an instruction hit signal; The instruction pre-read circuit generates an instruction pre-read signal based on the transmission information and sends the signal to the eFlash controller; The eFlash controller receives the instruction pre-read signal and increases the pre-read address in the pre-read register by a preset instruction length.

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