STT-MRAM storage bit, storage device and writing and reading method of STT-MRAM storage bit

Abstract

The invention relates to the technical field of magnetic storage, in particular to an STT-MRAM storage bit, storage equipment and a writing and reading method thereof.The STT-MRAM storage bit comprises a first reference layer, a barrier layer, a free layer, a spacer layer, a second reference layer and a heavy metal layer which are sequentially arranged from bottom to top, the first reference layer, the barrier layer and the free layer form a tunnel junction, and the spacer layer is arranged between the first reference layer and the second reference layer. The free layer is used for generating tunneling resistance, the larger the tunneling resistance ratio is, the larger the reading window of the storage bit is, and in addition, the thermal stability of the storage bit is determined by the magnetic anisotropy strength of the free layer, namely, the data non-volatile retention characteristic; the spacer layer, the second reference layer and the heavy metal layer form a spin current control layer, and the spin polarization current can be enhanced or weakened by controlling the relative direction of the magnetization intensity of the first reference layer and the second reference layer, so that the critical write-in current of the storage bit is changed.

Description

Technical Field

[0001] The present invention relates to the field of magnetic storage technology, and in particular to an STT-MRAM storage bit cell, a storage device, and a writing and reading method thereof. Background Art

[0002] With the rapid development of information technology, memory, as a core component of information processing systems, is crucial to the operating efficiency and stability of the entire system. In recent years, magnetoresistive random access memory (MRAM), as a new type of non-volatile memory, has attracted extensive attention from the international academic and industrial communities due to its unique advantages, such as high compatibility with 28nm and below CMOS logic processes, fast access speed, high reliability, and low power consumption. In particular, spin transfer torque magnetoresistive random access memory (STT-MRAM), as an important type of MRAM, has become the preferred solution to replace embedded flash memory (eFlash) below 22nm process.

[0003] STT-MRAM uses the spin transfer torque effect to write data, and the structural characteristics of its core storage unit, the magnetic tunnel junction (MTJ), determine its working mechanism. The MTJ consists of two magnetic layers (free layer and reference layer) and an insulating layer. The high and low resistance states are switched by controlling the flipping of the magnetization intensity of the free layer, thereby representing the binary data "0" and "1". However, STT-MRAM faces a series of challenges in practical applications.

[0004] First, because the data writing and reading of STT-MRAM share the same current loop, frequent writing operations will cause the performance of the oxide layer in the storage bit to gradually degrade, and may even be broken down due to excessive current, which seriously affects the durability of STT-MRAM. To solve this problem, researchers are committed to reducing the critical write current by optimizing the device materials and structure of MTJ, thereby reducing damage to the oxide layer. However, this strategy brings new problems: the reduction of critical write current will increase the bit error rate during reading, because small current differences may make it difficult to accurately distinguish between high and low resistance states.

[0005] Furthermore, the critical write current density of the MTJ is closely related to its material properties (such as the magnetic anisotropy field of the free layer, saturation magnetic moment, damping coefficient, spin polarization, etc.) and size. Once the material of the MTJ is selected, its critical write current mainly depends on the volume of the MTJ, so reducing the size of the MTJ becomes the main means to reduce the critical write current. However, these material parameters cannot be dynamically adjusted after the device is prepared, which limits the possibility of flexibly regulating the critical write current through external means.

[0006] In summary, while pursuing low write power consumption, STT-MRAM must balance the relationship between endurance and bit error rate. How to achieve highly reliable reading at extremely low write power consumption without sacrificing endurance and bit error rate has become a key issue that needs to be solved in the current development of STT-MRAM technology.

[0007] In view of this, the present invention is proposed. Summary of the invention

[0008] The object of the present invention is to provide an STT-MRAM storage bit, a storage device and a writing and reading method thereof, wherein the storage bit can simultaneously achieve extremely low power consumption writing and high reliability reading, and increase the durability of the storage bit writing process.

[0009] In a first aspect, the present invention provides an STT-MRAM storage bit, comprising, from bottom to top, a first reference layer, a barrier layer, a free layer, a spacer layer, a second reference layer and a heavy metal layer, and by controlling the relative directions of the magnetization intensities of the first reference layer and the second reference layer, the spin polarization current is enhanced or weakened, thereby changing the critical write current of the storage bit.

[0010] The storage bit of the present invention, combined with an external control circuit, can realize dynamic switching of the critical write current point reading of the storage bit, thereby realizing extremely low power consumption writing and high reliability reading in the chip at the same time, and increasing the durability of the chip writing process, solving the problem that traditional STT-MRAM storage bits are difficult to realize extremely low power consumption writing and high reliability reading at the same time.

[0011] As a preferred embodiment of the present technical solution, it also includes a substrate, a bottom metal electrode, a pinning layer and a protective layer, wherein the substrate, the bottom metal electrode and the pinning layer are arranged below the first reference layer in sequence from bottom to top, and the protective layer is arranged above the heavy metal layer.

[0012] Specifically, the STT-MRAM storage bit of the present invention includes, from bottom to top, a substrate, a bottom metal electrode, a pinned layer, a first reference layer, a barrier layer, a free layer, a spacer layer, a second reference layer, a heavy metal layer and a protective layer, wherein the first reference layer, the barrier layer and the free layer are tunnel junctions (MTJs), which can generate tunneling resistance, and the larger the tunneling resistance ratio, the larger the read window of the storage bit. In addition, the magnetic anisotropy strength of the free layer determines the thermal stability of the storage bit, that is, the non-volatile data retention characteristics; and the spacer layer, the second reference layer and the heavy metal layer are spin current control layers, and by controlling the relative directions of the magnetization strengths of the first reference layer and the second reference layer, the spin polarization current can be enhanced or weakened, thereby changing the critical write current of the storage bit.

[0013] As a preferred embodiment of the present technical solution, the first reference layer, the free layer and the second reference layer are all ferromagnetic alloys with in-plane magnetic anisotropy, and the thickness of the second reference layer is greater than that of the first reference layer.

[0014] Further preferably, the first reference layer, the free layer and the second reference layer are all CoFeB ferromagnetic alloys with in-plane magnetic anisotropy, and the thicknesses are all any value between 1.5nm-3nm, but the thickness of the second reference layer is greater than the thickness of the first reference layer, so that the second reference layer has stronger in-plane magnetic anisotropy.

[0015] In the write operation, the magnetization direction of the second reference layer needs to be configured in a direction antiparallel to the first reference layer to achieve extremely low power consumption data writing. A thicker second reference layer can maintain its magnetization direction more stably, thereby ensuring the accuracy and reliability of the write operation. In the read operation, the magnetization direction of the second reference layer is configured in a direction parallel to the first reference layer to increase the critical write current and reduce the probability of miswriting. A thicker second reference layer also helps to achieve this goal because it can more effectively resist external interference and maintain the stability of the magnetization direction.

[0016] In addition, the stability and performance of the second reference layer also make important contributions to the thermal stability of the storage bit. By increasing the thickness of the second reference layer, the data retention capability of the storage bit in a high temperature environment can be further improved.

[0017] As a preferred embodiment of the present technical solution, the barrier layer is a metal oxide having a body-centered cubic lattice structure, so as to effectively generate tunneling resistance in the MTJ.

[0018] Further preferably, the barrier layer is MgO having a body-centered cubic lattice structure, and the thickness thereof is any value between 1 nm and 2 nm.

[0019] As a preferred embodiment of the present technical solution, the spacer layer is a non-magnetic metal element with a large spin diffusion length to meet the functional requirements of the spin flow control layer.

[0020] Further preferably, the spacer layer is a single metal Cu, and its thickness is any value between 1 nm and 3 nm.

[0021] As a preferred embodiment of the present technical solution, the heavy metal layer is a metal material with a large spin Hall angle, so as to give the heavy metal layer the key characteristic of spin current control.

[0022] Further preferably, the material of the heavy metal layer includes any one of metal W, Ta / W alloy and topological insulator, and the thickness thereof is any value between 3 nm and 5 nm, which is not strictly limited in the present invention.

[0023] As a preferred embodiment of the present technical solution, the pinned layer is an anti-magnetic alloy with in-plane magnetic anisotropy, such as IrMn alloy, and its thickness is any value between 15nm and 20nm;

[0024] The protective layer is made of an anti-oxidation conductive material, such as TiN and TaN.

[0025] As a preferred embodiment of the present technical solution, the bottom metal electrode generally uses 20 nm Ta or Ru, which, on the one hand, has a relatively low resistivity, and on the other hand, can serve as a transition material for lattice matching between the substrate and the magnetic layer.

[0026] As a preferred embodiment of the present technical solution, the pinned layer, the first reference layer, the barrier layer, the free layer, the spacer layer and the second reference layer are in an elliptical column structure, the bottom metal electrode and the heavy metal layer are arranged perpendicular to each other, and the colinear current in the short axis direction of the heavy metal layer and the elliptical column structure is used to control the direction of the magnetization intensity of the second reference layer.

[0027] As a preferred embodiment of the present technical solution, one end of the heavy metal layer is connected to the first transistor, the other end is connected to the third transistor, and the bottom metal electrode is connected to the second transistor.

[0028] When the first transistor and the second transistor are turned on and the third transistor is turned off, data can be written and read; when the second transistor is turned off and the first transistor and the third transistor are turned on, the magnetization intensity of the second reference layer can be initialized.

[0029] In a second aspect, the present invention also provides a method for writing and reading the above-mentioned STT-MRAM storage bit, specifically, utilizing the spin-orbit moment effect to dynamically provide a bipolar current in the heavy metal layer through an external circuit to dynamically adjust the critical flip current of the storage bit;

[0030] When performing a write operation, extremely low power consumption data writing is achieved by configuring the magnetization intensity direction of the second reference layer to be antiparallel to the first reference layer;

[0031] When performing a reading operation, the probability of erroneous writing during reading is reduced by arranging the magnetization direction of the second reference layer to be parallel to the first reference layer.

[0032] In a third aspect, the present invention further provides a storage device including the above-mentioned STT-MRAM storage bit, which should also fall within the protection scope of the present invention.

[0033] The STT-MRAM storage bit of the present invention has at least the following beneficial effects:

[0034] The STT-MRAM storage bit of the present invention includes a first reference layer, a barrier layer, a free layer, a spacer layer, a second reference layer and a heavy metal layer in order from bottom to top, wherein the first reference layer, the barrier layer and the free layer form a tunnel junction, which functions to generate tunnel resistance, and the larger the tunnel resistance ratio, the larger the read window of the storage bit. In addition, the magnetic anisotropy strength of the free layer determines the thermal stability of the storage bit, that is, the non-volatile retention characteristics of the data; and the spacer layer, the second reference layer and the heavy metal layer form a spin current control layer, and by controlling the relative direction of the magnetization intensity of the first reference layer and the second reference layer, the spin polarization current can be enhanced or weakened, thereby changing the critical write current of the storage bit. For example, when performing a write operation, the magnetization intensity direction of the second reference layer is configured in advance to the direction antiparallel to the first reference layer through an external circuit, so that extremely low power consumption data writing can be achieved; when performing a read operation, the magnetization intensity direction of the second reference layer is configured to the direction parallel to the first reference layer through an external circuit, thereby increasing the critical write current, and the probability of miswriting during reading can be greatly reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0036] Figure 1 It is a schematic diagram of the structure of the STT-MRAM storage bit of the present invention;

[0037] Figure 2 The working principle of the STT-MRAM storage bit of the present invention is shown in FIG. Figure 1 ;

[0038] Figure 3 The working principle of the STT-MRAM storage bit of the present invention is shown in FIG. Figure 2 ;

[0039] Figure 4 The working principle of the STT-MRAM storage bit of the present invention is shown in FIG. Figure 3 ;

[0040] Figure 5 The working principle of the STT-MRAM storage bit of the present invention is shown in FIG. Figure 4 ;

[0041] Figure 6 It is a schematic diagram of the three-dimensional structure of the STT-MRAM storage bit of the present invention;

[0042] Figure 7 Schematic diagram of the integrated structure of the STT-MRAM storage bit of the present invention. DETAILED DESCRIPTION

[0043] The technical solution of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0044] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0045] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "multiple" means two or more, unless otherwise clearly and specifically defined. In addition, the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal connection of two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0046] Example 1

[0047] like Figure 1-2As shown, this embodiment provides an STT-MRAM storage bit, including a first reference layer, a barrier layer, a free layer, a spacer layer, a second reference layer and a heavy metal layer from bottom to top, wherein the first reference layer, the barrier layer and the free layer constitute a tunnel junction, which functions to generate tunneling resistance, and the larger the tunneling resistance ratio, the larger the read window of the storage bit, and in addition, the magnetic anisotropy strength of the free layer determines the thermal stability of the storage bit, that is, the non-volatile data retention characteristics; and the spacer layer, the second reference layer and the heavy metal layer constitute a spin current control layer, by controlling the relative direction of the magnetization strength of the first reference layer and the second reference layer, the spin polarization current can be enhanced or weakened, thereby changing the critical write current of the storage bit.

[0048] Specifically, Figure 3-4 As shown in the figure, the relative directions of the magnetization intensity of the first reference layer and the second reference layer are different (the direction of the arrow indicates the direction of the magnetization intensity of the magnetic layer), assuming that the direction of electron movement flows from the substrate to the protective layer. After the electron passes through the first reference layer, the spin direction is polarized to the same direction as the magnetization intensity of the first reference layer. When it enters the free layer, the magnetization intensity of the free layer is induced to flip to the direction of the electron spin polarization through the spin transfer torque effect.

[0049] for Figure 3 , when the current passes through the spacer layer and enters the second reference layer, the electrons with the spin direction opposite to the magnetization intensity of the second reference layer will be reflected back and enter the free layer again through the spacer layer. At this time, the effective spin polarization intensity of the electrons in the free layer will be weakened, so the critical flip current increases; on the contrary, for Figure 4 , the critical flip current decreases.

[0050] It can be seen that the relative direction of the magnetization intensity of the first reference layer and the second reference layer determines the magnitude of the critical switching current. Therefore, if the direction of the magnetization intensity of the second reference layer can be dynamically controlled, the critical switching current can be dynamically adjusted.

[0051] like Figure 5 As shown, the present invention utilizes the spin-orbit moment effect to regulate the magnetization intensity of the second reference layer. It is known that the magnetization intensity of the second reference layer is in-plane. When a vertically inward or outward current is passed through the heavy metal layer, spin-polarized electrons will accumulate at the interface between the second reference layer and the heavy metal layer. When a vertically inward current is passed through the heavy metal, the accumulated electron spin polarization direction at the interface is horizontal to the left; when a vertically outward current is passed through the heavy metal, the accumulated electron spin polarization direction at the interface is horizontal to the right; when the spin-polarized electrons accumulate to a certain extent, the magnetization intensity of the second reference layer can be induced to flip in the corresponding direction.

[0052] Therefore, by utilizing the spin-orbit torque effect and designing a reasonable external circuit, a bipolar current can be dynamically provided in the heavy metal layer, that is, the critical flip current of the storage bit can be dynamically adjusted. For example, when performing a write operation, by pre-configuring the magnetization intensity direction of the second reference layer to be antiparallel to the first reference layer, extremely low power consumption data writing can be achieved; when performing a read operation, the magnetization intensity direction of the second reference layer is configured to be parallel to the first reference layer, thereby increasing the critical write current, which can greatly reduce the probability of erroneous writing during reading.

[0053] Example 2

[0054] This embodiment provides an STT-MRAM storage bit cell, including, from bottom to top, a substrate, a bottom metal electrode, a pinning layer, a first reference layer, a barrier layer, a free layer, a spacer layer, a second reference layer, a heavy metal layer, and a protective layer.

[0055] The bottom metal electrode is generally made of 20nm Ta or Ru, which has a relatively low resistivity and can serve as a transition material for lattice matching between the substrate and the magnetic layer.

[0056] The pinning layer is an anti-magnetic iron alloy with in-plane magnetic anisotropy, such as IrMn alloy, and its thickness is any value between 15nm and 20nm;

[0057] The first reference layer is a CoFeB ferromagnetic alloy with in-plane magnetic anisotropy, and the thickness is any value between 1.5nm and 3nm;

[0058] In addition to CoFeB ferromagnetic alloy, FeGa alloy has the characteristics of large saturation magnetostriction coefficient, small coercive force, low saturation magnetic field, fast response speed, high Curie temperature and excellent mechanical properties. It can also be used as an important candidate material for ferromagnetic phase in magnetoelectric coupling films.

[0059] In addition to CoFeB and FeGa, NiFe (Permalloy) also has good magnetic properties and in-plane magnetic anisotropy, and can also be used as the material of the first reference layer.

[0060] The barrier layer is a metal oxide having a body-centered cubic lattice structure, for example, MgO having a body-centered cubic lattice structure, and its thickness is any value between 1 nm and 2 nm;

[0061] In addition to MgO, other metal oxides such as aluminum oxide (Al2O3) or barium oxide (BaO) may also have suitable properties for MTJ barrier layers. However, the specific suitability of these materials depends on their crystal structure, electronic properties and compatibility with adjacent magnetic layers.

[0062] In addition to metal oxides, other types of crystalline materials can also be considered as barrier layers, such as certain nitrides or carbides. These materials may have similar crystal structures and electronic properties to MgO, but further research and verification are needed to determine their suitability.

[0063] The free layer is a CoFeB ferromagnetic alloy with in-plane magnetic anisotropy, and the thickness is any value between 1.5nm and 3nm;

[0064] Similarly, in addition to CoFeB ferromagnetic alloys, materials such as FeGa and NiFe with good magnetic properties and in-plane magnetic anisotropy can also be selected.

[0065] The spacer layer is a non-magnetic metal element with a large spin diffusion length, for example, a metal element Cu, and its thickness is any value between 1nm and 3nm;

[0066] In addition to Cu, other metal elements such as Ag (silver) and Au (gold) may also have properties suitable for the spacer layer. These metals usually have good conductivity and spin diffusion properties, but their specific applicability depends on their electronic structure and compatibility with adjacent layers.

[0067] In addition, certain alloy materials, especially those with low magnetism and high spin diffusion length, may also be suitable as spacer layers, but these alloys may need to be specially processed and optimized to meet the performance requirements of STT-MRAM.

[0068] The second reference layer comprises a CoFeB ferromagnetic alloy with in-plane magnetic anisotropy, and the thickness thereof is any value between 1.5 nm and 3 nm;

[0069] Similarly, in addition to CoFeB ferromagnetic alloys, materials such as FeGa and NiFe with good magnetic properties and in-plane magnetic anisotropy can also be selected.

[0070] The heavy metal layer is a metal material with a large spin Hall angle, for example, any one of metal W, Ta / W alloy and topological insulator, and its thickness is any value between 3nm and 5nm, which is not strictly limited in the present invention;

[0071] In addition to W and Ta, other heavy metals such as Pt (platinum) and Pd (palladium) also have large spin Hall angles. These materials are widely used in the field of spin electronics and may be suitable for heavy metal layers in STT-MRAM.

[0072] In addition, certain heavy metal alloys, such as PtAu, PtPd, etc., can further optimize the spin Hall angle and other related properties through the alloying effect. These alloy materials may have superior performance than single heavy metals.

[0073] The protective layer is a conductive material with oxidation resistance, such as TiN and TaN;

[0074] Among them, the thickness of the second reference layer is greater than that of the first reference layer, so that the second reference layer has a stronger in-plane magnetic anisotropy, so as to enhance the in-plane magnetic anisotropy of the second reference layer, optimize the writing and reading operations, and improve the thermal stability of the storage bit, thereby improving the overall performance and reliability of the STT-MRAM storage bit.

[0075] Example 3

[0076] This embodiment provides a method for preparing the above-mentioned STT-MRAM storage bit, comprising the following steps:

[0077] Substrate preparation: Select appropriate substrate material and perform necessary cleaning and pretreatment to ensure that its surface is clean and suitable for subsequent thin film growth;

[0078] Bottom metal electrode deposition: Use physical vapor deposition (PVD) or chemical vapor deposition (CVD) to deposit a 20nm thick layer of Ta or Ru on the substrate as the bottom metal electrode. The bottom metal electrode not only has a low resistivity, but also serves as a transition material for lattice matching between the substrate and the magnetic layer.

[0079] Pinning layer preparation: deposit a layer of anti-magnetic alloy with in-plane magnetic anisotropy, such as IrMn alloy, on the bottom metal electrode with a thickness of any value between 15nm and 20nm to fix the magnetization direction of the adjacent magnetic layer;

[0080] Preparation of the first reference layer: depositing a layer of CoFeB ferromagnetic alloy with in-plane magnetic anisotropy on the pinned layer, with a thickness of any value between 1.5nm and 3nm;

[0081] Barrier layer preparation: depositing a layer of metal oxide with a body-centered cubic lattice structure, such as MgO, on the first reference layer, with a thickness of any value between 1nm and 2nm;

[0082] Free layer preparation: deposit a layer of CoFeB ferromagnetic alloy with in-plane magnetic anisotropy on the barrier layer, with a thickness of any value between 1.5nm and 3nm;

[0083] Preparation of the spacer layer: deposit a layer of non-magnetic metal element with a large spin diffusion length, such as Cu, on the free layer, with a thickness of any value between 1nm and 3nm;

[0084] Preparation of the second reference layer: depositing a layer of CoFeB ferromagnetic alloy with in-plane magnetic anisotropy on the spacer layer, with a thickness of any value between 1.5nm and 3nm;

[0085] Preparation of heavy metal layer: deposit a layer of metal material with a large spin Hall angle, such as W, Ta / W alloy or topological insulator, on the second reference layer, with a thickness of any value between 3nm and 5nm;

[0086] Preparation of protective layer: depositing a layer of anti-oxidation conductive material, such as TiN or TaN, on the heavy metal layer to protect the entire storage bit from corrosion by the external environment;

[0087] Subsequent processing: annealing, etching and patterning and other subsequent process steps are performed as needed to complete the preparation of the STT-MRAM storage bit.

[0088] During the entire preparation process, the deposition conditions of each layer (such as temperature, pressure, gas flow, etc.) need to be strictly controlled to ensure that the quality and performance of each layer meet the design requirements. At the same time, necessary characterization and testing are also required to verify the performance and reliability of the storage bit.

[0089] Example 4

[0090] like Figure 6 As shown, this embodiment provides a three-dimensional structure of the above-mentioned STT-MRAM storage bit. Specifically, in the storage device, the pinned layer, the first reference layer, the barrier layer, the free layer, the spacer layer and the second reference layer are in an elliptical column structure, and the aspect ratio thereof is preferably greater than 2:1. The bottom metal electrode and the heavy metal layer are arranged perpendicular to each other, and the colinear current in the short axis direction of the heavy metal layer and the elliptical column structure is used to control the direction of the magnetization intensity of the second reference layer.

[0091] Example 5

[0092] like Figure 7 As shown, this embodiment provides an integrated structure of the above-mentioned STT-MRAM storage bit. Specifically, when WL1 and WL2 are turned on and WL3 is turned off, data can be written and read; when WL2 is turned off and WL1 and WL3 are turned on, the magnetization intensity of the second reference layer can be initialized.

[0093] Therefore, the writing and reading methods of the storage bit are as follows:

[0094] Before data is written, WL2 is turned off, and WL1 and WL3 are turned on to initialize the magnetization intensity of the second reference layer and configure it into a low critical current mode;

[0095] Further opening WL1 and WL2 and closing WL3 can achieve extremely low power consumption data writing;

[0096] Similarly, before data reading, WL2 is also turned off, and WL1 and WL3 are turned on to initialize the magnetization intensity of the second reference layer to configure it into a high critical current mode;

[0097] Further opening WL1 and WL2 and closing WL3 can greatly reduce the probability of miswrite during reading.

[0098] In the above description, the technical details of patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above.

[0099] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A STT-MRAM storage bit cell, characterized in that: It includes a first reference layer, a barrier layer, a free layer, a spacer layer, a second reference layer and a heavy metal layer from bottom to top. By controlling the relative directions of the magnetization intensities of the first reference layer and the second reference layer, the spin polarization current is enhanced or weakened, thereby changing the critical write current of the storage bit.

2. The STT-MRAM storage bit cell according to claim 1, wherein: It also includes a substrate, a bottom metal electrode, a pinning layer and a protective layer. The substrate, the bottom metal electrode and the pinning layer are arranged below the first reference layer in sequence from bottom to top, and the protective layer is arranged above the heavy metal layer.

3. The STT-MRAM storage bit cell according to claim 1, wherein: The first reference layer, the free layer and the second reference layer are all ferromagnetic alloys with in-plane magnetic anisotropy, and the thickness of the second reference layer is greater than that of the first reference layer.

4. The STT-MRAM storage bit cell according to claim 1, wherein: The barrier layer is a metal oxide having a body-centered cubic lattice structure.

5. The STT-MRAM storage bit cell according to claim 1, wherein: The spacer layer is a metal single substance which is non-magnetic and has a large spin diffusion length.

6. The STT-MRAM storage bit cell according to claim 2, wherein: The heavy metal layer is a metal material with a large spin Hall angle; The pinning layer is an anti-magnetic iron alloy having in-plane magnetic anisotropy; The protective layer is a conductive material with oxidation resistance.

7. The STT-MRAM storage bit cell according to claim 2, wherein: The pinned layer, the first reference layer, the barrier layer, the free layer, the spacer layer and the second reference layer are in an elliptical column structure, the bottom metal electrode and the heavy metal layer are arranged perpendicular to each other, and the colinear current in the short axis direction of the heavy metal layer and the elliptical column structure is used to control the direction of the magnetization intensity of the second reference layer.

8. The STT-MRAM storage bit cell according to claim 2, wherein: One end of the heavy metal layer is connected to the first transistor, the other end is connected to the third transistor, and the bottom metal electrode is connected to the second transistor.

9. The method for writing and reading a STT-MRAM storage bit according to any one of claims 1 to 8, characterized in that: By utilizing the spin-orbit torque effect, a bipolar current is dynamically provided in the heavy metal layer through an external circuit to dynamically adjust the critical flip current of the storage bit; When performing a write operation, extremely low power consumption data writing is achieved by configuring the magnetization intensity direction of the second reference layer to be antiparallel to the first reference layer; When performing a reading operation, the probability of erroneous writing during reading is reduced by arranging the magnetization direction of the second reference layer to be parallel to the first reference layer.

10. A storage device, characterized in that: The STT-MRAM storage bit cell comprises any one of claims 1 to 8.

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