Semiconductor device and memory device

Abstract

A semiconductor device according to the present disclosure includes a first memory cell and a second memory cell. The first memory cell includes a first active region for an n-type transistor and a second active region for a p-type transistor. The first active region has a first width. The second active region has a second width. The first width is greater than the second width. The second memory cell includes a third active region for an n-type transistor and a first active region for a p-type transistor. The third active region has a third width. The fourth active region has a fourth width. The third width is greater than the fourth width. The first width is greater than the third width. The embodiment of the invention also discloses a memory device.

Description

Technical Field

[0001] Embodiments of the present application relate to a semiconductor device and a memory device. Background Art

[0002] The electronics industry has a growing demand for smaller, faster electronic devices that are able to simultaneously support more increasingly complex and sophisticated functions. As a result, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). To date, these goals have been achieved in large part by shrinking semiconductor IC size (e.g., minimum component size), thereby increasing production efficiency and reducing associated costs. However, this scaling has also increased the complexity of semiconductor manufacturing processes. Therefore, achieving continued advancements in semiconductor ICs and devices requires similar advances in semiconductor manufacturing processes and technologies.

[0003] This reduction in integrated circuit technology not only complicates the manufacturing process, but also poses specific challenges in the design and functionality of memory arrays within memory devices. For example, the operation of memory arrays in different levels of cache memory (e.g., primary cache memory, secondary cache memory, and tertiary cache memory) requires tailored structural designs for SRAM cells to accommodate different performance requirements, such as current drive capability, standby leakage current, and cell size. The traditional approach of using one standard SRAM cell across different cache memory levels is increasingly insufficient because it cannot optimally meet the different performance requirements of these cache memories. Unified SRAM cell parameters across these cache memories may result in suboptimal performance, where the specific requirements of each cache memory level (e.g., strong current drive capability in the primary cache memory, low standby leakage current in the secondary cache memory, and high cell density in the tertiary cache memory) cannot be fully met. This difference highlights the need for a differentiated approach in SRAM cell architecture to improve the overall efficiency and performance of memory devices, especially in the context of advanced semiconductor technologies. Summary of the invention

[0004] According to one aspect of an embodiment of the present application, a semiconductor device is provided, including: a first memory unit, including a first active area for an n-type transistor and a second active area for a p-type transistor, the first active area having a first width, the second active area having a second width, and the first width is greater than the second width; and a second memory unit, including a third active area for the n-type transistor and a fourth active area for the p-type transistor, the third active area having a third width, the fourth active area having a fourth width, and the third width is greater than the fourth width, wherein the first width is greater than the third width.

[0005] According to another aspect of an embodiment of the present application, a memory device is provided, including: a first memory unit, including a first pull-down transistor and a first pull-up transistor, the first pull-down transistor having a first channel region of a first width, the first pull-up transistor having a second channel region of a second width, and the first width is greater than the second width; and a second memory unit, including a second pull-down transistor and a second pull-up transistor, the second pull-down transistor having a third channel region of a third width, the second pull-up transistor having a fourth channel region of a fourth width, and the third width is greater than the fourth width, wherein the first width is greater than the third width.

[0006] According to another aspect of an embodiment of the present application, a memory device is provided, comprising: a first static random access memory (SRAM) cell having a first cell height and a cell width; a second SRAM cell having a second cell height and a cell width; and a third SRAM cell having a third cell height and a cell width, wherein the first cell height is different from the second cell height, and the second cell height is different from the third cell height. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 is a block diagram of an integrated circuit (IC) having memory circuits according to various aspects of the present disclosure.

[0009] Figure 2 is a block diagram of a memory macro having a memory array according to various aspects of the present disclosure.

[0010] Figure 3 is a circuit schematic of a static random access memory (SRAM) cell according to various aspects of the present disclosure.

[0011] Figure 4 Cross-sectional views of various layers of a memory device according to various aspects of the present disclosure are shown.

[0012] Figure 5 and Figure 6 The following are respectively shown according to various aspects of the present disclosure. Figure 3 The layout of the SRAM cell shown includes the device layer and the metal layer.

[0013] Figure 7 Layouts of three regions of a memory device including three different SRAM cell structures according to various aspects of the present disclosure are shown.

[0014] Fig. 8A , Figure 8B , Fig.9A , Fig. 9B , Fig. 9C , Fig.9D , Fig. 10A and Fig. 10B The invention is shown along the Figure 7 Partial cross-sectional views of sections AA, BB, CC, A'-A', B'-B' and CC'.

[0015] Fig.11A and Fig. 11B The present invention shows various aspects of the present invention. Figure 7 An alternative embodiment of one of the SRAM cells in.

[0016] Fig. 12A and Fig. 12B The present invention shows various aspects of the present invention. Figure 7 Another alternative embodiment of the SRAM cell in .

[0017] Fig.13A , Fig. 13B , Fig. 13C , Fig.13D , Fig.13E and Fig.13F The present invention shows various aspects of the present invention. Figure 7 An alternative embodiment of the layout in . DETAILED DESCRIPTION

[0018] The following disclosure provides many different embodiments or examples for realizing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0019] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0020] In addition, when a number or range of numbers is described using "about," "approximately," etc., the term is intended to include numbers within a reasonable range, taking into account variations inherent in manufacturing processes as understood by those of ordinary skill in the art. For example, based on known manufacturing tolerances associated with manufacturing features associated with the number, the number or range encompasses a reasonable range including the described number, such as within + / - 10% of the described number. For example, a material layer having a thickness of "about 5 nm" may include a size range of 4.25 nm to 5.75 nm, where manufacturing tolerances associated with deposited material layers are known to those of ordinary skill in the art to be + / - 15%. When describing aspects of transistors, the source / drain may be referred to individually or collectively as the source or drain, depending on the context.

[0021] Static random access memory (SRAM) is a semiconductor memory that retains data statically as long as power is applied. Unlike dynamic RAM (DRAM), SRAM is faster, more reliable, and does not need to be constantly refreshed. SRAM is widely used in various applications, including computer memory. Computer memory can include different cache memory levels, such as a primary cache memory and a secondary cache memory. Each cache memory level may have different structural design requirements to achieve optimal performance. For example, the primary cache memory is the fastest cache memory and may prefer a structural design to minimize latency and maximize data transfer rate while having strong current drive capabilities. In contrast, the secondary cache memory, which acts as a secondary buffer and is located farther away from the CPU, may prefer a structural design that reduces leakage current, especially in the case of mobile platforms. Similarly, the third-level cache memory may prefer a structural design that accommodates more memory cells in a given area to increase storage capacity. Therefore, a unified SRAM cell across different cache memory levels may result in suboptimal performance because it does not meet the unique requirements of each cache memory type.

[0022] The present disclosure introduces multiple SRAM cell architectures (or structures, configurations) that coexist in a memory device. The SRAM cell architectures differ primarily in aspects such as the active area width of the n-type transistor. Different active area widths result in differences in current drive capability, standby leakage current, and cell size. In one embodiment, the memory device may have different SRAM cell architectures for different cache memory levels, and a unified SRAM cell architecture in the same cache memory level, which improves performance to meet different requirements. Another embodiment allows two or more different SRAM cell architectures to coexist in a cache memory, such as high current and low leakage cell designs that coexist in the same cache memory to further optimize the performance of a particular cache memory.

[0023] Figure 1 FIG. 1 shows a simplified block diagram of an IC 10 according to some embodiments. The IC 10 includes a processing unit 12 and a memory circuit (or memory device) 14 integrated in the IC 10. The processing unit 12 is Figure 1 The processing unit 12 includes an arithmetic logic unit (ALU) 16 and a memory management unit (MMU) 18. The processing unit 12 may include various components such as one or more flip-flops, one or more scan chains, one or more registers, etc. For ease of description, Figure 1 These components are omitted.

[0024] The memory circuit 14 includes memory cells (e.g., SRAM cells and / or DRAM cells) organized into one or more primary cache memories 20, one or more secondary cache memories 22, one or more tertiary cache memories 24, and a main memory 26. Optionally, the memory circuit 14 may also include one or more n-level cache memories (n>3). Any suitable type of SRAM cells and / or DRAM cells may be used. For example, the primary cache memory 20, the secondary cache memory 22, and the tertiary cache memory 24 may be implemented by SRAM cells, while the main memory 26 may be implemented by DRAM cells. The processing unit 12 and the memory circuit 14 are communicatively coupled together via an internal bus system 28 in the IC 10.

[0025] Generally, the first level cache memory is considered to be a higher level cache memory than the second level cache memory, and the second level cache memory is considered to be a higher level cache memory than the third level cache memory. That is, the first level cache memory 20 is the fastest cache memory memory, which is used to store data recently accessed by the processing unit 12. In addition, when the processing unit 12 executes a computer instruction, the first level cache memory 20 is the cache memory that is first accessed and processed. The second level cache memory 22 may not be as fast as the first level cache memory 20, but the capacity can be increased. The third level cache memory 24 works in conjunction with the first and second level cache memories to improve computer performance by preventing bottlenecks caused by long read execution cycles. In addition, the memory performance of the third level cache memory 24 is slower than that of the second level cache memory 22. For example, the first level cache memory 20 can generally have a faster response time than the second level cache memory 22, and the second level cache memory 22 can generally have a faster response speed than the third level cache memory 24. With respect to storage capacity, the L1 cache memory 20 is smaller than the L2 cache memory 22, and the L2 cache memory 22 is smaller than the L3 cache memory 24. For example, one L1 cache memory 20 may include 64K memory bits, one L2 cache memory 22 may include 128K memory bits, and one L3 cache memory 24 may include 512K or even more memory bits.

[0026] The one or more processing units 12 are operable to generate one or more signals to control the operation of the IC 10. Such functionality may be provided, for example, by the processing unit 12 executing instructions retrieved from the memory circuit 14. The MMU 18 of the processing unit 12 is operable to control the storage and retrieval of data and instructions from the primary cache 20, the secondary cache 22, the tertiary cache 24, and the main memory 26 of the memory circuit 14 via the internal bus system 28, and / or from one or more memories external to the IC 10 via one or more interfaces (not shown). The MMU 18 may include a plurality of addressing circuits that may facilitate simultaneous use of the primary cache 20, the secondary cache 22, the tertiary cache 24, and the main memory 26.

[0027] Memory management routines (e.g., cache control routines) may be used to control data and instruction transfers between the primary cache 20, the secondary cache 22, the tertiary cache 24, and the main memory 26. Embodiments of the IC 10 may have fewer components than shown (e.g., the tertiary cache 24 may be optional), may have more components than shown, may combine or separate the components shown, and may rearrange the components shown. For example, the MMU 18 may be divided into multiple MMUs 18 (e.g., a first MMU 18 for controlling the primary cache 20, a second MMU 18 for controlling the secondary cache 22 and the tertiary cache 24, and a third MMU 18 for controlling the main memory 26). In another example, the MMU 18 may be a memory circuit 14 rather than part of the processing unit 12.

[0028] Figure 2 It shows that it can be Figure 1 14. For example, the memory macro 30 may be part of the primary cache 20, the secondary cache 22, the tertiary cache 24, or the main memory 26 in the memory circuit 14. In the illustrated embodiment, the memory macro 30 is an SRAM macro, such as a single-port SRAM macro, a dual-port SRAM macro, or another type of SRAM macro. However, the present disclosure contemplates some embodiments in which the memory macro 30 is another type of memory, such as a dynamic random access memory (DRAM), a non-volatile random access memory (NVRAM), flash memory, or another suitable memory. For clarity, Figure 2 It is simplified for better understanding of the inventive concepts of the present disclosure. Additional features may be added in the memory macro 30, and some of the features described below may be replaced, modified, or eliminated in other embodiments of the memory macro 30.

[0029] The memory macro 30 includes a memory array 32, an input / output (I / O) circuit 34, a word line driver 36, and a control circuit 38. The memory array 32 includes memory cells arranged in rows and columns. In the illustrated embodiment, the memory cells are arranged from the 1st row to the Mth row, each row extending along a first direction (here in the X direction), and arranged from the 1st column to the Nth column, each column extending along a second direction (here in the Y direction), where M and N are positive integers. To simplify the description, Figure 2 Only a few rows and columns and the corresponding memory cells are shown. Each memory cell stores one bit of data. Therefore, according to the position of the memory cell in the memory array 32, the memory cell is also called a bit cell or represented as a BC. MN , where M represents rows and N represents columns. For example, BC11 BC represents a memory cell located in the first row (row 1) and the first column (column 1), which is the memory cell in the first row (row 1) closest to the I / O circuit 34; 12 BC represents a memory cell located in the first row (row 1) and the second column (column 2), which is the memory cell in the first row (row 1) that is the second closest to the I / O circuit 34; 1N BC represents a memory cell located in the first row (row 1) and the last column (column N), which is the memory cell farthest from the I / O circuit 34 in the first row (row 1); MN Denotes the memory cell located in the last row (row M) and the last column (column N). For simplicity, memory cell BC MN It can be called BC.

[0030] Rows 1 to M each include a bit line pair extending in the X direction, which facilitates reading data from and / or writing data to each memory cell BC in true form and / or complementary form row by row. The bit line pair may include a bit line (BL) and a complementary bit line (also referred to as a barred bit line (BLB)). Columns 1 to M each include a word line (WL), which facilitates accessing each memory cell BC column by column. Each memory cell BC is electrically connected to a corresponding bit line pair and a corresponding WL.

[0031] I / O circuit 34 is coupled to memory array 32 through a bit line pair. In some embodiments, I / O circuit 34 is configured to select one of the rows in memory array 32 and provide a bit line signal on one of the bit line pairs arranged on the selected row. The bit line signal is transmitted to the corresponding memory cell BC through the selected bit line pair for writing bit data into the corresponding memory cell BC or reading bit data therefrom.

[0032] The word line driver 36 is coupled to the memory array 32 through the word line WL. In some embodiments, the word line driver 36 is configured to select one of the columns in the memory array 32 and provide a word line signal on one of the word lines WL arranged on the selected column. The word line signal is transmitted to the corresponding memory cell BC through the selected word line WL for writing bit data into the corresponding memory cell BC or reading the corresponding memory cell BC.

[0033] The control circuit 38 is coupled to the I / O circuit 34 and the word line driver 36 and is disposed next to them. The control circuit 38 configures the I / O circuit 34 and the word line driver 36 to generate one or more signals to select at least one WL and at least one bit line pair to access at least one of the memory cells BC for a read operation and / or a write operation. The control circuit 38 includes any circuit suitable for facilitating reading from or writing to the memory cell BC, including but not limited to a column decoder circuit, a row decoder circuit, a column selection circuit, a row selection circuit, a read / write circuit (e.g., configured to read data from and / or write data to the memory cell BC corresponding to the selected bit line pair (in other words, the selected column), other suitable circuits or combinations thereof. In some embodiments, the control circuit 38 is implemented by a processor. In some other embodiments, the control circuit 38 is integrated with the processor. The processor is implemented by a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0034] Figure 3 is a circuit diagram of an exemplary SRAM cell 50, which may be implemented as Figure 2 The memory cell BC in the Figure 1 In the illustrated embodiment, the SRAM cell 50 is a single-port (SP) six-transistor (6T) SRAM cell. In various embodiments, the SRAM cell 50 may be other types of memory cells, such as a dual-port memory cell or a memory cell having more than six transistors. For clarity, Figure 3 It is simplified for better understanding of the inventive concepts of the present disclosure. Additional features may be added in the single-port SRAM cell 50 , and some of the features described below may be replaced, modified, or eliminated in other embodiments of the single-port SRAM cell 50 .

[0035] The exemplary SRAM cell 50 is a single-port SRAM cell that includes six transistors: a pass-gate transistor PG-1, a pass-gate transistor PG-2, a pull-up transistor PU-1, a pull-up transistor PU-2, a pull-down transistor PD-1, and a pull-down transistor PD-2. In operation, the pass-gate transistor PG-1 and the pass-gate transistor PG-2 provide access to a storage portion of the SRAM cell 50, which includes a cross-coupled pair of inverters, an inverter 52, and an inverter 54. Inverter 52 includes a pull-up transistor PU-1 and a pull-down transistor PD-1, and inverter 54 includes a pull-up transistor PU-2 and a pull-down transistor PD-2. In some embodiments, the pull-up transistors PU-1 and PU-2 are configured as p-type FinFET transistors or p-type all-around gate (GAA) transistors, and the pull-down transistors PD-1 and PD-2 are configured as n-type FinFETs or n-type GAA transistors.

[0036] The gate of the pull-up transistor PU-1 is inserted between the source (electrically coupled to the power supply voltage (VDD)) and the first common drain (CD1), and the gate of the pull-down transistor PD-1 is inserted between the source (electrically coupled to the power supply voltage (VSS), which may be an electrical ground) and the first common drain. The gate of the pull-up transistor PU-2 is inserted between the source (electrically coupled to the power supply voltage (VDD)) and the second common drain (CD2), and the gate of the pull-down transistor PD-2 is inserted between the source (electrically coupled to the power supply voltage (VSS)) and the second common drain. In some embodiments, the first common drain (CD1) is a storage node (SN) that stores data in real form, and the second common drain CD2 is a complementary storage node SNB that stores data in complementary form. The gate of the pull-up transistor PU-1 and the gate of the pull-down transistor PD-1 are coupled to the second common drain CD2, and the gate of the pull-up transistor PU-2 and the gate of the pull-down transistor PD-2 are coupled to the first common drain CD1. The gate of the transfer gate transistor PG-1 is inserted between the source (electrically coupled to the bit line BL) and the drain, and the drain is electrically coupled to the first common drain (CD1). The gate of the transfer gate transistor PG-2 is inserted between the source (electrically coupled to the complementary bit line BLB) and the drain, and the drain is electrically coupled to the second common drain (CD2). The gates of the transfer gate transistors PG-1 and PG-2 are electrically coupled to the word line WL. In some implementations, the transfer gate transistors PG-1 and PG-2 provide access to the storage nodes SN and SNB during read operations and / or write operations. For example, the transfer gate transistors PG-1 and PG-2 couple the storage nodes SN and SNB to the bit lines BL and BLB, respectively, in response to the voltage applied to the gates of the transfer gate transistors PG-1 and PG-2 by the word line WL.

[0037] Figure 41 is a partial schematic cross-sectional view of a semiconductor device 100 according to various aspects of the present disclosure, the semiconductor device 100 including a portion of a memory device (eg, Figure 2 Memory macro 30) and / or a portion of an SRAM cell (such as Figure 3 The various layers (levels) of the SRAM cell 50). Figure 4 As shown, each layer includes a device layer DL, a front-side multilayer interconnect structure (FMLI) disposed on the device layer DL, and a back-side multilayer interconnect structure disposed under the device level DL. FMLI and BMLI are collectively referred to as a multilayer interconnect structure MLI. The device layer DL includes devices (e.g., transistors, resistors, capacitors, and / or inductors) and / or device components (e.g., doped wells, gate structures, and / or source / drain components). In some embodiments, the device layer DL includes a substrate 60, a doped region 62 (e.g., an n-well and / or a p-well) disposed in the substrate 60, an isolation component 64, and a transistor T. In the illustrated embodiment, the transistor T includes a suspended channel layer 70 and a gate structure 68 located between the source / drain structure 72, and the gate structure 68 covers and / or surrounds the suspended channel layer 70. Each gate structure 68 has a metal gate stack formed by a gate electrode 74 disposed on a gate dielectric 76 and a gate spacer 78 disposed along the sidewall of the metal gate stack.

[0038] The multi-layer interconnect structures FMLI and BMLI electrically couple various devices and / or components of the device layer DL so that the various devices and / or components can operate according to the design requirements of the memory device. Each of the multi-layer interconnect structures FMLI and BMLI may include one or more interconnect layers. The present disclosure also contemplates an embodiment of the semiconductor device 100 including FMLI but not providing BMLI.

[0039] In the depicted embodiment, the FMLI includes a contact layer (CO level), a via zero layer (V0 level), a metal zero layer (M0 level), a via one layer (V1 level), a metal one layer (M1 level), a via two layer (V2 level), a metal two layer (M2 level), a via three layer (V3 level), and a metal three layer (M3 level). The present disclosure contemplates FMLIs with more or fewer layers and / or levels, for example, the total number of metal layers (levels) of the FMLI is 2 to 10. Each layer of the FMLI includes conductive features (e.g., metal lines, metal vias, and / or metal contacts) disposed in one or more dielectric layers (e.g., an interlayer dielectric (ILD) layer and a contact etch stop layer (CESL)). In some embodiments, conductive features of the same level of the FMLI (e.g., the M0 level) are formed simultaneously. In some embodiments, conductive features of the same level of the FMLI have top surfaces that are substantially coplanar with each other and / or bottom surfaces that are substantially coplanar with each other. The CO level includes source / drain contacts (MD) disposed in the dielectric layer 66; the V0 level includes gate vias VG, source / drain contact vias VD, and butt contacts disposed in the dielectric layer 66. The M0 level includes an M0 metal line disposed in the dielectric layer 66, wherein the gate vias VG connect the gate structure to the M0 metal line, the source / drain vias V0 connect the source / drain to the M0 metal line, and the butt contacts connect the gate structure and the source / drain together and to the M0 metal line. The V1 level includes a V1 via disposed in the dielectric layer 66, wherein the V1 via connects the M0 metal line to the M1 metal line. The M1 level includes an M1 metal line disposed in the dielectric layer 66. The V2 level includes a V2 via disposed in the dielectric layer 66, wherein the V2 via connects the M1 line to the M2 line. The M2 level includes an M2 metal line disposed in the dielectric layer 66. The V3 level includes V3 vias disposed in dielectric layer 66 , wherein the V3 vias connect the M2 lines to the M3 lines.

[0040] In the depicted embodiment, the BMLI includes a backside via zero layer (BV0 level), a backside metal zero layer (BM0 level), a backside via one layer (BV1 level), and a backside metal one layer (BM1 level). The present disclosure contemplates a BMLI having more or fewer layers and / or levels, for example, the total number of metal layers (levels) of the BMLI is 2 to 10. Each layer of the BMLI includes conductive features (e.g., metal lines, metal vias, and / or metal contacts) disposed in one or more dielectric layers (e.g., an interlayer dielectric (ILD) layer and a contact etch stop layer (CESL)). In some embodiments, conductive features of the same level of the BMLI (e.g., the BM0 level) are formed simultaneously. In some embodiments, conductive features located at the same level of the BMLI have top surfaces that are substantially coplanar with each other and / or bottom surfaces that are substantially coplanar with each other. The BV0 level includes a via BV0 formed below the device layer DL. For example, the via BV0 may include one or more backside source / drain vias formed directly below the source / drain features 72 of the device layer DL and coupled to these source / drain features 72 through the silicide layer. The via BV0 may include one or more backside gate vias formed directly below and in direct contact with the gate structure 68 of the device layer DL. The BM0 level includes a BM0 metal line formed below the BV0 level and disposed in the backside dielectric structure 66'. The backside gate via connects the gate structure 68 to the BM0 metal line, and the backside source / drain via connects the source / drain 72 to the BM0 metal line. The BV1 level includes a BV1 via disposed in the backside dielectric structure 66', wherein the BV1 via connects the BM0 metal line to the BM1 metal line. The BM1 level includes a BM1 metal line formed under the BV1 layer.

[0041] According to various aspects of the present disclosure, an exemplary manufacturing process for forming a device layer DL and a multilayer interconnect structure MLI of the semiconductor device 100 may include forming an active region on a substrate, forming an isolation structure (e.g., shallow trench isolation (STI)) between adjacent active regions, forming a dummy gate above the active region, forming a gate spacer on a sidewall of the dummy gate, recessing the active region to form a source / drain recess, forming an internal spacer and a source / drain component in the source / drain recess, depositing an interlayer dielectric (ILD) layer on the source / drain component and the dummy gate structure, performing a planarization process (e.g., a chemical mechanical planarization (CMP) process) to expose the dummy gate structure, replacing the dummy gate structure with a metal gate structure, replacing the dummy gate structure with a metal gate structure, and forming contacts, vias, and metal layers in the multilayer interconnect MLI.

[0042] In order to better understand the inventive concept of the present disclosure, the Figure 4Additional features may be added in various layers of the memory, and some of the features described may be replaced, modified, or eliminated in other embodiments of the memory. Figure 4 This is merely an example and may not reflect an actual cross-sectional view of the memory macro 30 and / or the SRAM cell 50 discussed in further detail below.

[0043] Figure 5 and Figure 6 Shown as Figure 3 An exemplary layout 200 of an SRAM cell 50 is shown, wherein Figure 5 The DL level, CO level and V0 level of the layout 200 are shown. Figure 6 The V0 level and the M0 level of the layout 200 are shown. To facilitate the description of the positional relationship, Figure 6 It also shows that Figure 5 The SRAM cell 50 has active regions (such as active regions 205A, 205B, 205C, and 205D) as shown. Figure 5 and Figure 6 The dashed line in the figure indicates the cell boundary 202. The cell boundary 202 is a rectangular frame that is longer in the Y direction than in the X direction, for example, about 3.5 times to about 6 times longer. A first dimension of the cell boundary 202 in the X direction is represented as a cell width W, and a second dimension of the cell boundary 202 in the Y direction is represented as a memory cell height H. When the SRAM cell 50 is repeated in the memory array (such as Figure 2 ), the cell width W may be represented and referred to as the memory cell pitch in the memory array along the X direction, and the cell height H may be represented and referred to as the memory cell pitch in the memory array along the Y direction. In the illustrated embodiment, the cell width W is twice the polysilicon pitch. The polysilicon pitch refers to the minimum center-to-center distance between two adjacent gate structures along the X direction.

[0044] The SRAM cell 50 includes an active region 205 (including 205A, 205B, 205C, and 205D) oriented longitudinally along the X direction, and a gate structure 240 (including 240A, 240B, 240C, and 240D) oriented longitudinally along the Y direction perpendicular to the X direction. The active regions 205B and 205C are disposed above an n-type well (or n-well) 204N. The active regions 205A and 205D are disposed above a p-type well 204P located on both sides of the n-well 204N along the Y direction. The gate structure 240 joins the channel region of the corresponding active region 205 to form a transistor. In this regard, gate structure 240A is joined to the channel region of active region 205A to form an n-type transistor as a pass gate transistor PG-1; gate structure 240B is joined to the channel region of active region 205A to form an n-type transistor as a pull-down transistor PD-1, and is joined to the channel region of active region 205B to form a p-type transistor as a pull-up transistor PU-1; gate structure 240C is joined to the channel region of active region 205D to form an n-type transistor as a pull-down transistor PD-2, and is joined to the channel region of active region 205C to form a p-type transistor as a pull-up transistor PU-2; gate structure 240D is joined to the channel region of active region 205D to form an n-type transistor as a pass gate transistor PG-2. Active regions 205A and 205D for forming n-type transistors are also referred to as n-type active regions, and active regions 205B and 205C for forming p-type transistors are also referred to as p-type active regions.

[0045] The SRAM cell 50 also includes conductive components at the CO level, the V0 level, the M0 level, and even higher metal levels (e.g., the M1 level, the M2 level, etc.). The gate contact 260A electrically connects the gate of the pass-gate transistor PG-1 (formed by the gate structure 240A) to the first word line WL landing pad 280A. The first WL landing pad 280A is electrically coupled to the word line WL at a higher metal level. The gate contact 260L electrically connects the gate of the pass-gate transistor PG-2 (formed by the gate structure 240D) to the second word line WL landing pad 280L. The second WL landing pad 280L is electrically coupled to the word line WL at a higher metal level. Source / drain (S / D) contact 260K electrically connects the drain region of pull-down transistor PD-1 (formed on active region 205A (which may include n-type epitaxial source / drain components)) and the drain region of pull-up transistor PU-1 (formed on active region 205B (which may include p-type epitaxial source / drain components)) so that the common drain of pull-down transistors PD-1 / PU-1 forms a storage node SN. Gate contact 260B electrically connects the gate of pull-up transistor PU-2 (formed by gate structure 240C) and the gate of pull-down transistor PD-2 (also formed by gate structure 240C) to storage node SN. Gate contact 260B may be a butt contact to abut S / D contact 260K. S / D contact 260C electrically connects the drain region of pull-down transistor PD-2 (formed on active region 205D (which may include n-type epitaxial source / drain components)) and the drain region of pull-up transistor PU-2 (formed on active region 205C (which may include p-type epitaxial source / drain components)) such that the common drain of pull-down transistor PD-2 and pull-up transistor PU-2 form a complementary storage node SNB. Gate contact 260D electrically connects the gate of pull-up transistor PU-1 (formed by gate structure 240B) and the gate of pull-down transistor PD-1 (also formed by gate structure 240B) to complementary storage node SNB. Gate contact 260D may be a butt contact adjacent to S / D contact 260C.

[0046] The S / D contact 260E and the S / D contact via 270E landed thereon electrically connect the source region of the pull-up transistor PU-1 (formed on the active area 205B (which may include a p-type epitaxial source / drain component)) to the VDD line 280E. The VDD line 280E is electrically coupled to the power supply voltage VDD. The S / D contact 260F and the S / D contact via 270F landed thereon electrically connect the source region of the pull-up transistor PU-2 (formed on the active area 205C (which may include a p-type epitaxial source / drain component)) to the VDD line 280E. The S / D contact 260G and the S / D contact via 270G landed thereon electrically connect the source region of the pull-down transistor PD-1 (formed on the active area 205A (which may include an n-type epitaxial source / drain component)) to the first VSS landing pad 280G. The first VSS landing pad 280G is electrically coupled to the electrical ground VSS. The S / D contact 260H and the S / D contact via 270H landing thereon electrically connect the source region of the pull-down transistor PD-2 (formed on the active area 205D (which may include an n-type epitaxial source / drain component)) to the second VSS landing pad 280H. The second VSS landing pad 280H is electrically coupled to the electrical ground VSS. The S / D contact 260G and the S / D contact 260H may be contacts of a device layer shared by adjacent SRAM cells 50 (for example, four SRAM cells 50 adjacent at the same corner may share one S / D contact 260H). The S / D contact 260I and the S / D contact via 270I landing thereon electrically connect the source region of the pass-gate transistor PG-1 (formed on the active area 205A (which may include an n-type epitaxial source / drain component)) to the bit line BL 280I. S / D contact 260J and S / D contact via 270J landed thereon electrically connect the source region of pass-gate transistor PG- 2 formed on active region 205D (which may include n-type epitaxial source / drain features) to complementary bit line (bar bit line) BLB 280J.

[0047] Conductive components in the CO level, M0 level, and higher metal levels (e.g., M1 level, M2 level, etc.) are routed along a first routing direction or a second routing direction different from the first routing direction. For example, the first routing direction is the X direction (and is substantially parallel to the longitudinal direction of the active regions 205A-205D), and the second routing direction is the Y direction (and is substantially parallel to the longitudinal direction of the gate structures 240A-240D). In the depicted embodiment, the S / D contacts (260C, 260E, 260F, 260G, 260H, 260I, 260J, 260K) have a longitudinal (length) direction substantially along the Y direction (i.e., the second routing direction), and the butt contacts (260B, 260D) have a longitudinal direction substantially along the X direction (i.e., the first routing direction). The metal lines of the even-numbered metal layers (i.e., the M0 and M2 levels) are wired along the X direction (i.e., the first wiring direction), and the metal lines of the odd-numbered metal layers (i.e., the M1 and M3 levels) are wired along the Y direction (i.e., the second wiring direction). Figure 6 In the M0 level shown, the bit line 280I, the inverted bit line 280J, the VDD line 280E, the VSS landing pad 280G, the VSS pad 280H, the word line landing pad 280A, and the word line landing pad 280L have a longitudinal direction substantially along the X direction. In addition, since the metal lines in the same metal layer (e.g., the M0 level) have the same longitudinal direction, the metal lines can be located in a metal track arranged in parallel. The metal track can include one or more metal lines. For example, the metal track can include a single metal line extending through the entire SRAM cell, or the metal track can include one or more local metal lines that do not extend through the entire DRAM cell.

[0048] The metal lines described are generally rectangular (i.e., each metal line is longer than its width), but the present disclosure contemplates metal lines having different shapes and / or combinations of shapes to optimize and / or improve performance (e.g., reduce resistance) and / or layout footprint (e.g., reduce density). For example, VDD line 280E may optionally have a shape such as Figure 6 The added stepped portion (or simply the stepped portion) is shown. A stepped portion refers to the junction where two portions of different widths intersect. The stepped portion of VDD line 280E has a greater width than other portions of VDD line 280E. The stepped portion may add an additional width of about 1% to about 50% to VDD line 280E. A stepped portion is added to the interconnect region (area) of VDD line 280E to increase the cross-sectional area of ​​the interconnect region. Increasing the cross-sectional area of ​​the interconnect region of VDD line 280E allows the cross-sectional area of ​​S / D contact vias 270E and 270F in the V0 level to be increased, which reduces the wiring resistance between the connection of VDD line 280E and the corresponding source / drain contacts (thereby reducing the wiring resistance to the source / drain regions below).

[0049] A "landing pad" generally refers to a metal line in a metal layer that provides an intermediate local interconnect for an SRAM cell, such as an intermediate local interconnect between (1) a device layer component (e.g., a gate or source / drain) and a bit line, an inverted bit line, a word line, a voltage line, or (2) an intermediate local interconnect between a bit line, a word line, or a voltage line. For example, a VSS landing pad 280G is connected to the S / D contact 260G of transistor PD-1 and further connected to a VSS line at a higher metal level, a VSS landing pad 280H is connected to the source / drain contact 260H of transistor PD-2 and further connected to a VSS line at a higher metal level, a WL landing pad 280A is connected to the gate of transistor PG-1 and further connected to a word line WL at a higher metal level, and a WL landing pad 280L is connected to the gate of transistor PG-2 and further connected to a word line WL at a higher metal level. The pad has a sufficiently large longitudinal dimension to provide sufficient pad area for its overlying via (thereby minimizing coverage issues and providing greater patterning flexibility). In the depicted embodiment, the longitudinal dimension of the landing pad is smaller than the dimension of the SRAM cell 50, for example, the dimension along the X direction is smaller than the cell width W, and the dimension along the Y direction is larger than the cell height H. Compared with the landing pad, the bit line 280I, the inverted bit line 280J, and the VDD line 280E have a longitudinal dimension along the X direction that is larger than the cell width W of the SRAM cell 50. When the bit line 280I, the inverted bit line 280J, and the VDD line 280E of the M0 level pass through the entire SRAM cell 50 along the X direction, the bit line 280I, the inverted bit line 280J, and the VDD line 280E of the M0 level are also referred to as global metal lines, while the other lines are referred to as local metal lines (including the landing pad). In some embodiments, the length of each of the bit line 2801, the bar bit line 280J, and the VDD line 280E is sufficient to allow multiple SRAM cells in a column (or row) to be electrically connected to a corresponding global metal line.

[0050] The metal lines (global metal lines and local metal lines) of the M0 level in the SRAM cell 50 may have different widths. For example, the main portion of the VDD line 280E has a width of W VDD , the bit line 280I and the inverted bit line 280J both have a uniform width W BL In some embodiments, the width W BL Greater than width W VDD (W BL >W VDD ). The maximum width reserved for bit line 280I and inverted bit line 280J allows the signal line in the bit line pair to generally benefit from a reduction in resistance, thereby reducing the voltage drop along the signal line. In some embodiments, the width W BL With width W VDD The ratio (i.e. WBL / W VDD ) is about 1.1 to about 2. In the illustrated embodiment, the edges (and center lines) of the bit line 280I and the inverted bit line 280J are offset from the edges (and center lines) of the underlying active regions 205A and 205D, respectively. The offset increases the cross-sectional area of ​​the interconnection region between the bit line 280I and the inverted bit line 280J and the corresponding underlying S / D contact vias 270I and 270J. In addition, the width W of the bit line 280I and the inverted bit line 280J is BL The width W1 of the active regions 205A and 205D may be greater than the width W1 of the active regions 205A and 205D. BL The ratio of the width W1 (i.e. W BL / W1) is from about 1.1 to about 1.5.

[0051] Return to reference Figure 5 In this embodiment, the channel regions of the active regions 205A-205D are in the form of vertically stacked nanostructures, so each of the transistors PU-1, PU-2, PD-1, PD-2, PG-1, and PG-2 is a GAA transistor. Although FinFETs can be used to implement SRAM devices, the use of FinFET transistors limits the active region width to discrete values, particularly integer multiples of a single fin width. The present disclosure utilizes GAA transistors to implement SRAM devices. Compared to FinFETs, GAA transistors allow for more flexible scaling of the active region width, as well as reduced standby leakage due to better drain induced barrier lowering (DIBL) and swing performance.

[0052] By implementing GAA transistors, different active regions in different transistors of SRAM cell 50 can have different widths (e.g., dimensions measured in the Y direction) to optimize device performance. In more detail, active region 205A for n-type transistors (pull-down transistor PD-1 and pass-gate transistor PG-1) has a width W N , the active area 205B for the p-type transistor (pull-up transistor PU-1) has a width W P , the active area 205C for the p-type transistor (pull-up transistor PU-2) has a width W P , the active area 205D for the n-type transistors (pass gate transistor PG-2 and pull-down transistor PD-2) has a width W N The width W may also be measured in the portion of the active region corresponding to the channel region. N and W P In other words, those portions of the active region from which the width W is measured N and W P The portion of the transistor (e.g., the vertically stacked nanostructure of a GAA device) is the channel region of the transistor. To optimize SRAM performance, the width WN is configured to be no less than the width W P (W N ≥W P ) to balance the speed between n-type transistors and p-type transistors. In some embodiments, W N / W P The ratio of W can be in the range of about 1 to about 3 (1≤W N / W P ≤3). In addition, with different W N / W P ratio of SRAM cells can be present simultaneously in a memory device (e.g., Figure 1 The memory devices 14 in the storage device 14 may be used to store the memory devices 14 in different levels of cache memory (or even in the same cache memory) to meet different requirements.

[0053] Figure 7 Shows such as Figure 1 300 of a memory device of the memory device 14 in FIG. The exemplary layout 300 includes three different SRAM cells 50a, 50b, 50c that are present in the memory device at the same time, but from three different regions of the memory device (e.g., from different memory arrays and / or different memory macros). For simplicity, only the active areas, gate structures, and cell boundaries are shown. The SRAM cells 50a, 50b, 50c have the same width W for the active areas 205B and 205C for the p-type transistors (pull-up transistors PU-1, PU-2). P , and have the same cell width W. For the width W of the active areas 205A and 205C of the SRAM cells 50a, 50b, 50c for n-type transistors (pass gate transistors PG-1, PG2, pull-down transistors PD-1, PD-2) N a.W N b. W N c is different, so the unit heights Ha, Hb, and Hc are also different.

[0054] Regarding the SRAM cell 50a, the width W N a is equal to the width W P (W N a=W P ). Width W N a is the width W N a.W N b. W N The smallest of c. The reduced width W Na allows the SRAM cell 50a to have a smaller cell height Ha. Specifically, the cell height Ha is the smallest of the cell heights Ha, Hb, and Hc. This configuration of active regions 205A and 205D is suitable for high-density applications (such SRAM cells are referred to as high-density SRAM cells). In some embodiments, the SRAM cell 50a can be implemented in a three-level and / or two-level cache memory.

[0055] Regarding the SRAM cell 50b, the width W N b is greater than the width W P (W N b>W P ). Specifically, W N b / W P The ratio of may be in the range of about 2 to about 3 (2≤W N b / W P ≤3). Width W N b is the width W N a.W N b. W N The largest of c. The expanded width W N b enables the SRAM cell 50b to have a larger cell height Hb. Specifically, among the cell heights Ha, Hb, and Hc, the cell height Hb is the largest. This configuration of the active regions 205A and 205D is suitable for high current applications (such an SRAM cell is called a high current SRAM cell). For high current applications, W N b / W P The ratio of is not trivial or arbitrary within the range of about 2 to about 3. N b / W P If the ratio is less than about 2, the current drive capability of the high current SRAM cell is impaired; if the ratio is N b / W P Greater than about 3, the cell height Hb may become too large to accommodate enough high current SRAM cells in a given area, or the chip size must grow as manufacturing costs decrease. In some embodiments, SRAM cell 50b may be implemented in a primary and / or secondary cache memory.

[0056] Regarding the SRAM cell 50c, the width W N c is greater than the width W P (W N c>W P ). Specifically, W N c / W P The ratio of W can be in the range of about 1.5 to about 2 (1.5≤W N c / W P ≤2). Width W N c in width WN a.W N b. W N c is in the middle (W N a<W N c<W N b). Therefore, the cell height Hc is in the middle of the cell heights Ha, Hb, and Hc (Ha<Hc<Hb). One of the reasons for adding the SRAM cell 50c as a supplement to the SRAM cells 50a and 50b is that the SRAM cell 50c will provide a good compromise between current drive capability and standby leakage current performance, making it faster than the SRAM cell 50a but not as power-hungry as the SRAM cell 50b. In some embodiments, the SRAM cell 50c is approximately 5% smaller in area than the SRAM cell 50b, but suppresses approximately 30% of the standby current leakage without sacrificing the minimum operating voltage Vmin. This trade-off is attractive for mobile computing applications, which typically require moderate speeds and limited power consumption. For mobile computing applications, W N c / W P The ratio of W to W is not trivial or arbitrary in the range of about 1.5 to about 2. N c / W P If the ratio W is less than about 1.5, the current driving capability of the SRAM cell 50c is impaired; N c / W P Greater than about 2, the leakage current may become too large and shorten the cell life of the mobile platform. N c / W N The ratio of b is in the range of about 0.6 to about 0.9 (0.6≤W N c / W N b≤0.9), which is not trivial or arbitrary for mobile computing applications. If W N c / W N If the ratio W b is less than about 0.6, the current drive capability of SRAM cell 50c is impaired; N c / W N If b is greater than about 0.9, the leakage current may become too large, shortening the cell life of the mobile platform, and the difference between SRAM cells 50b and 50c will become negligible. In some embodiments, SRAM cell 50c may be implemented in a L2 and / or L3 cache memory.

[0057] In some embodiments, SRAM cells 50a, 50b, 50c are located in different levels of cache memory to meet different needs. For example, SRAM cell 50b can be in a primary cache memory, SRAM cell 50c can be in a secondary cache memory, and SRAM cell 50a can be in a tertiary cache memory. In some alternative embodiments, SRAM cells of different configurations can be located in the same cache memory. In one example, the primary cache memory may mainly have a macro consisting of SRAM cells 50b, but a small portion of the area is dedicated to a macro consisting of SRAM cells 50c. In one example, the secondary cache memory may mainly have a macro consisting of SRAM cells 50c, but a small portion of the area is dedicated to a macro consisting of SRAM cells 50b. In one example, the secondary cache memory may mainly have a macro consisting of SRAM cells 50c, but a small portion of the area is dedicated to a macro consisting of SRAM cells 50a. In one example, the tertiary cache memory may mainly have a macro consisting of SRAM cells 50a, but a small portion of the area is dedicated to a macro consisting of SRAM cells 50c. In one example, the L3 cache may have primarily macros consisting of SRAM cells 50c, but with a small area dedicated to macros consisting of SRAM cells 50a.

[0058] Now common reference Figures 8A-10B . Fig. 8A The Figure 7 Partial cross-sectional view of the AA and A'-A' sections. Figure 8B Shown with BMLI Fig. 8A An alternative embodiment of . Fig.9A The Figure 7 Partial cross-sectional view of the BB and B'-B' sections. Fig. 9B , Fig. 9C , Fig.9D Shows Fig.9A An alternative embodiment in which the BMLI and / or the channel layer are in the form of nanowires rather than nanosheets. Fig. 10A The Figure 7 Partial cross-sectional view of CC and C'-C' sections. Fig. 10B Shown with BMLI Fig. 10A An alternative embodiment of Figure 7As shown, section AA passes through the source / drain region of the SRAM cell 50b along the Y direction; section A'-A' passes through the source / drain region of the SRAM cell 50c along the Y direction; section BB passes through the gate structures 240B and 240D of the SRAM cell 50b along the Y direction; section B'-B' passes through the gate structures 240B and 240D of the SRAM cell 50c along the Y direction; section CC passes through the active area 205A of the SRAM cell 50b along the X direction; and section C'-C' passes through the active area 205A of the SRAM cell 50c along the X direction.

[0059] like Fig. 8A As shown, in the source / drain region of the SRAM cell 50b or the SRAM cell 50c, the source / drain component SD 205A Epitaxial growth on the fin-shaped substrate of the active area 205A; source / drain epitaxial component SD 205B epitaxially grown on the fin-shaped substrate of the active region 205B; and the source / drain epitaxial component SD 205D Epitaxial growth is performed on the fin-shaped substrate of the active region 205D. The source / drain epitaxial component SD 205A The source / drain epitaxial feature SD is electrically coupled to the VSS landing pad 280G through the S / D contact 260G and the S / D contact via 270G; 205B The source / drain epitaxial feature SD is electrically coupled to the VDD line 280E through the S / D contact 260E and the S / D contact via 270E; 205D Electrically coupled to a complementary bit line (BLB) 280J through an S / D contact 260J and an S / D contact via 270J.

[0060] In SRAM cell 50b, the width of active regions 205A and 205D is W N b, and the width of active regions 205B and 205C is W P Width W N b is greater than the width W P (W N b>W P ). Specifically, W N b / W P The ratio may be in the range of about 2 to about 3 (2≤W N b / W P ≤3). In the SRAM cell 50c, the widths of the active regions 205A and 205D are W N c, and the width of active regions 205B and 205C is W P Width W N c is greater than the width W P (W N c>W P ). Specifically, W Nc / W P The ratio of W can be in the range of about 1.5 to about 2 (1.5≤W N c / W P ≤2). The width WP in SRAM cells 50b and 50c may be the same. N c is smaller than the width W N b(W N c <W N b) W N c / W N The ratio of b is in the range of about 0.6 to about 0.9 (0.6≤W N c / W N b≤0.9). Since the width of the n-type active regions 205A and 205D in the SRAM cell 50b is relatively large, the source / drain epitaxial component SD 205A and SD 205D It is also wider and larger than the corresponding portion in SRAM cell 50c. In comparison, since the widths of p-type active regions 205B and 205C in SRAM cells 50b and 50c are the same, the source / drain epitaxial component SD 205B It has substantially the same width and volume as the corresponding portion in the SRAM cell 50c.

[0061] In such Fig. 8A In the illustrated embodiment, the FMLI electrically connects transistors in the SRAM cells to power lines and signal lines. Figure 8B Shows Fig. 8A An alternative embodiment in which the SRAM cell also has a BMLI disposed on the back side of the memory device for better power routing. The memory device can be thinned from the back side to reduce the thickness of the semiconductor substrate and a backside etch stop layer (BESL) is deposited. The backside S / D contacts B260G extend through the BESL and land on the source / drain epitaxial features SD 205A on the bottom surface and place the SD 205A The back side S / D contact B260G replaces the fin-shaped base of the active area 205A and also inherits the size of the active area 205A. That is, the width of the back side S / D contact B260G in the SRAM cell 50b is greater than the width (W ) of the back side S / D contact B260G in the SRAM cell 50c. N b>W N c).

[0062] like Fig.9AAs shown, in the channel region of the SRAM cell 50b or the SRAM cell 50c, each active region 205A, 205B, 205C, 205D includes a plurality of nanostructures 70 as a channel layer vertically stacked above a fin-shaped substrate. The channel layer has a width substantially the same as that of the corresponding active region. The channel layer in the active region 205A provides a channel region for the n-type transistor PD-1; the channel layer in the active region 205B provides a channel region for the p-type transistor PU-1; and the channel layer in the active region 205D provides a channel region for the n-type transistor PG-2. The gate structure 240B is separated from the adjacent gate structure 240D by a cut metal gate (CMG) component therebetween. The CMG component is made of a dielectric material, such as an oxide or a nitride, and is used to electrically isolate the gate structure 240B from the gate structure 240D. As Fig. 8A and Figure 8B As shown, the CMG component can extend continuously from the channel region to the source / drain region, so that the CMG component is also inserted between the source / drain component SD 205B and SD 205D between.

[0063] and Fig. 8A similar, Fig.9A An embodiment of a memory device having FMLI but without BMLI is depicted. Fig. 9B Shows Fig.9A An alternative embodiment in which the SRAM cell further has a BMLI disposed on the back side of the memory device to achieve better power routing. Specifically, a backside etch stop layer (BESL) covers the back side of the channel region of the SRAM cell. In addition, in the example Fig.9A In the illustrated embodiment, the nanostructures 70 are all in a sheet shape, and therefore are also referred to as nanosheets. Alternatively, the nanostructures 70 may have other shapes, such as a line shape, a rod shape, or other suitable channel configurations. Fig. 9C An alternative embodiment is depicted in which each nanostructure 70 in the n-type active region is replaced by a row of linear nanostructures 70' (eg, a row of three as shown). The nanostructures 70' are also referred to as nanowires. Fig.9D Another embodiment is further shown, wherein a memory device comprises a channel layer in the form of nanowires and a BMLI is presented.

[0064] like Fig. 10A As shown, taking the n-type transistor PD-1 as an example, the gate structure 240B wraps each channel layer of the active region 205A to form the n-type transistor PD-1. In the SRAM cell 50b, the width of the gate structure 240B measured along the X direction is represented as W gate b. In the SRAM cell 50c, the width of the gate structure 240B measured along the X direction is denoted as W gate c. In some embodiments, the width Wgate b and W gate c is the same (W gate b=W gate c). In some other embodiments, the width W gate b is smaller than the width W gate c. (W gate b <W gate c) W gate c / W gate The ratio of b may be in the range of about 1 to about 1.5 (1≤W gate c / W gate b<1.5). That is, although the n-type active region in SRAM cell 50c is narrower than the n-type active region in SRAM cell 50b, the gate structure in SRAM cell 50c is wider than or at least not smaller than the gate structure in SRAM cell 50b. The wider gate structure in SRAM cell 50c helps to reduce the Vt variation in SRAM cell 50c and better keep Vmin matching with Vmin in SRAM cell 50b.

[0065] and Fig. 8A similar, Fig. 10A An embodiment of a memory device having FMLI but without BMLI is depicted. Fig. 10B Shows Fig. 10A An alternative embodiment in which the SRAM cell also has a BMLI disposed on the back side of the memory device to achieve better power routing. Specifically, a backside etch stop layer (BESL) covers the back side of the memory device. The backside S / D contact B260G extends through the BESL and lands on the source / drain epitaxial feature SD 205A on the bottom surface and place the SD 205A Electrically connected to electrical ground (VSS).

[0066] Return to reference Figure 7 ,like Figure 7 The SRAM cell 50b shown has a uniform width W N In other words, the channel widths of the pull-down transistors PD-1 and PD-2 and the channel widths of the pass-gate transistors PG-1 and PG-2 are the same width (W Nb). In some applications, the channel width of the pull-down transistors PD-1 and PD-2 may be greater than the channel width of the pass-gate transistors PG-1 and PG-2. As a result, the pull-down transistors PD-1 and PD-2 may have stronger performance than the pass-gate transistors PG-1 and PG-2. Therefore, the cell performance of the resulting SRAM cell may be improved, for example, a higher operating voltage (e.g., Vmax), a higher cell current, a wider read margin range, and / or a faster operating speed. Fig.11A and Fig. 11B An alternative embodiment is shown in which the channel widths of the pull-down transistors PD- 1 and PD- 2 are greater than the channel widths of the pass-gate transistors PG- 1 and PG- 2 .

[0067] Fig.11A Shown as Figure 7 In the SRAM cell 50b', the channel widths of the pull-down transistors PD-1 and PD-2 are further extended to W. N b'(W N b'>W N b), so that active areas 205A and 205D each have a convex step profile. Due to the convex step profile, the distance between the n-type and p-type active areas of transistors PD-1 and PU-1 (or PD-2 and PU-2) is smaller than the distance between the n-type and p-type active areas of transistors PG-1 and PU-1 (or PG-2 and PU-2). N b' / W N The ratio of b may be in the range of about 1.02 to about 2 (1.02≤W N b' / W N b≤2). This ratio is not trivial or arbitrary. If the ratio is less than about 1.02, the pull-down transistors PD-1 and PD-2 may not have sufficient performance improvement. If the ratio is greater than 2, the minimum distance between the n-type active area and the p-type active area may be too small and cause process risks.

[0068] Fig. 11B Shown as Figure 7 1 is another alternative embodiment of the SRAM cell 50b in the embodiment of the present invention. Many aspects of the SRAM cell 50b" are the same as the SRAM cell 50b", one difference being that the n-type active regions 205A and 205D in the SRAM cell 50b' each have a straight edge and a jog profile on the opposite edge, while the n-type active regions 205A and 205D in the SRAM cell 50b" each have a jog profile on two edges. In the SRAM cell 50b', the width of the jog profile measured along the Y direction is W jog =W N b'-WN b. In SRAM cell 50b", the width of the convex step profile measured along the Y direction is W jog '=(W N b'-W N b) / 2. W jog / W P The ratio can range from about 0.2 to about 1, while W jog ' / W P The ratio of can be from about 0.1 to about 0.5. These ratios are not trivial or arbitrary. Ratios outside the range may cause manufacturing difficulties and increase process risks.

[0069] Return to reference Figure 7 ,like Figure 7 The SRAM cell 50c shown has a uniform width W N In other words, the channel widths of the pull-down transistors PD-1 and PD-2 and the channel widths of the pass-gate transistors PG-1 and PG-2 are the same width (W N c). In some applications, the channel width of the pull-down transistors PD-1 and PD-2 may be greater than the channel width of the pass-gate transistors PG-1 and PG-2. As a result, the pull-down transistors PD-1 and PD-2 may have stronger performance than the pass-gate transistors PG-1 and PG-2. Therefore, the cell performance of the resulting SRAM cell may be improved, for example, a higher operating voltage (e.g., Vmax), a higher cell current, a wider read margin range, and / or a faster operating speed. Fig. 12A and Fig. 12B An alternative embodiment is shown in which the channel widths of the pull-down transistors PD- 1 and PD- 2 are greater than the channel widths of the pass-gate transistors PG- 1 and PG- 2 .

[0070] Fig. 12A Shown as Figure 7 In the SRAM cell 50c', the channel widths of the pull-down transistors PD-1 and PD-2 are further extended to W. N c'(W N c'>W N c), so that active areas 205A and 205D each have a convex step profile. Due to the convex step profile, the distance between the n-type and p-type active areas of transistors PD-1 and PU-1 (or PD-2 and PU-2) is smaller than the distance between the n-type and p-type active areas of transistors PG-1 and PU-1 (or PG-2 and PU-2). N c' / W N The ratio of W c may be in the range of about 1.02 to about 2 (1.02≤W Nc' / W N c≤2). This ratio is not trivial or arbitrary. If the ratio is less than about 1.02, the pull-down transistors PD-1 and PD-2 may not have sufficient performance improvement. If the ratio is greater than 2, the minimum distance between the n-type active area and the p-type active area may be too small and cause process risks.

[0071] Fig. 12B Shown as Figure 7 5. In another alternative embodiment of the SRAM cell 50c in the embodiment of the present invention, the SRAM cell 50c" is similar to the SRAM cell 50c' in many aspects. One difference is that the n-type active regions 205A and 205D in the SRAM cell 50c' each have a straight side and a convex step profile on the opposite edge, while the n-type active regions 205A and 205D in the SRAM cell 50" each have a convex step profile on both edges. In the SRAM cell 50c', the width of the convex step profile measured along the Y direction is W jog =W N c'-W N c. In SRAM cell 50c", the width of the convex step profile measured along the Y direction is W jog '=(W N c'-W N c) / 2. W jog / W P The ratio can range from about 0.2 to about 1, W jog ' / W P The ratio of can be from about 0.1 to about 0.5. These ratios are not trivial or arbitrary. Ratios outside the range may cause manufacturing difficulties and increase process risks.

[0072] like Fig.11A The SRAM cell 50b' shown in FIG. Fig. 11B The DRAM cells 50b" shown can be replaced individually Figure 7 The SRAM cell 50b in the layout 300 shown can be used to form an alternative layout embodiment to accommodate different device performance requirements. Fig. 12A The SRAM cell 50c' shown in FIG. Fig. 12B The SRAM50c" shown can be replaced separately Figure 7 The SRAM cell 50c in the layout 300 is shown to form an alternative layout embodiment to accommodate different device performance requirements. Fig.13A Another layout 300A is depicted in which the memory device includes an SRAM cell 50a, an SRAM cell 50b', and an SRAM cell 50c. Fig. 13BAnother layout 300B is depicted in which the memory device includes an SRAM cell 50a, an SRAM cell 50b', and an SRAM cell 50c'. Fig. 13C Another layout 300C is depicted in which the memory device includes an SRAM cell 50a, an SRAM cell 50b", and an SRAM cell 50c. Fig.13D Another layout 300D is depicted in which the memory device includes an SRAM cell 50a, an SRAM cell 50b", and an SRAM cell 50c". Fig.13E Another layout 300E is depicted, in which the memory device includes SRAM cell 50a, SRAM cell 50b, and SRAM cell 50c'. Fig.13F Another layout 300F is depicted, in which the memory device includes SRAM cell 50a, SRAM cell 50b, and SRAM cell 50c. In various embodiments, the memory device (e.g., Figure 1 The memory device 14 in the embodiment includes three different SRAM cell architectures coexisting in a multi-level cache memory. The present disclosure also contemplates an embodiment in which the memory device may include a fourth SRAM architecture having a higher current SRAM cell 50b than the W N b Wider n-type active area to provide stronger current driving capability.

[0073] Although not intended to be limiting, embodiments of the present disclosure provide one or more of the following advantages. For example, embodiments of the present disclosure simultaneously form multiple SRAM cell architectures with different n-type active area widths in a memory device. This advantageously improves cache memory performance to meet the different requirements of different cache memory levels. In addition, embodiments of the present disclosure can be easily integrated into existing semiconductor manufacturing processes.

[0074] In one exemplary aspect, the present disclosure provides a semiconductor device. The semiconductor device includes a first memory cell and a second memory cell, the first memory cell includes a first active area for an n-type transistor and a second active area for a p-type transistor, the first active area has a first width, the second active area has a second width, and the first width is greater than the second width; the second memory cell includes a third active area for an n-type transistor and a fourth active area for a p-type transistor, the third active area has a third width, the fourth active area has a fourth width, and the third width is greater than the fourth width. The first width is greater than the third width. In some embodiments, the first memory cell is in a first cache memory, the second memory cell is in a second cache memory, and the level of the first cache memory is higher than the level of the second cache memory. In some embodiments, the first memory cell is located in a first-level cache memory, and the second memory cell is located in a second-level cache memory. In some embodiments, the first memory cell is located in a second-level cache memory, and the second memory cell is located in a third-level cache memory. In some embodiments, the first memory cell and the second memory cell are located in the same cache memory. In some embodiments, the first memory cell has a first cell width and a first cell height, the second memory cell has a second cell width and a second cell height, and the first cell height is greater than the second cell height. In some embodiments, the first cell width is substantially equal to the second cell width. In some embodiments, the second width is substantially equal to the fourth width. In some embodiments, the semiconductor device further includes a third memory cell including a fifth active area for an n-type transistor and a sixth active area for a p-type transistor, the fifth active area having a fifth width, and the sixth active area having a sixth width. The fifth width is substantially equal to the sixth width. In some embodiments, the second width, the fourth width, and the sixth width are substantially equal to each other.

[0075] Another aspect of the present disclosure provides a memory device. The memory device includes a first memory cell and a second memory cell, the first memory cell includes a first pull-down transistor and a first pull-up transistor, the first pull-down transistor has a first channel region of a first width, the first pull-up transistor has a second channel region of a second width, and the first width is greater than the second width; the second memory cell includes a second pull-down transistor and a second pull-up transistor, the second pull-down transistor has a third channel region of a third width, the second pull-up transistor has a fourth channel region of a fourth width, and the third width is greater than the fourth width. The first width is greater than the third width. In some embodiments, the ratio of the third width to the first width is in the range of about 0.6 to about 0.9. In some embodiments, the ratio of the first width to the second width is in the range of about 2 to about 3. In some embodiments, the ratio of the third width to the fourth width is in the range of about 1.5 to about 2. In some embodiments, the ratio of the second width to the fourth width is about 1:1. In some embodiments, each of the first channel region, the second channel region, the third channel region, and the fourth channel region includes a plurality of nanostructures stacked vertically.

[0076] Another aspect of the present disclosure provides a memory device. The memory device includes: a first static random access memory (SRAM) cell having a first cell height and a cell width; a second SRAM cell having a second cell height and a cell width; and a third SRAM cell having a third cell height and a cell width. The first cell height is different from the second cell height, and the second cell height is different from the third cell height. In some embodiments, the first SRAM cell is located in a first cache memory of a first priority, the second SRAM cell is located in a second cache memory of a second priority lower than the first priority, and the third SRAM cell is located in a third cache memory of a third priority lower than the second priority. In some embodiments, the first SRAM cell and the second SRAM cell are located in the same cache memory, or the second SRAM cell and the third SRAM cell are located in the same cache memory. In some embodiments, each of the first SRAM cell, the second SRAM cell, and the third SRAM cell includes a front-side multilayer interconnect structure and a back-side multilayer interconnect structure.

[0077] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose of the embodiments introduced herein and / or achieving the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and changes in the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, comprising: A first memory cell including a first active region for an n-type transistor and a second active region for a p-type transistor, the first active region having a first width, the second active region having a second width, and the first width being greater than the second width; as well as a second memory cell including a third active region for an n-type transistor and a fourth active region for a p-type transistor, the third active region having a third width, the fourth active region having a fourth width, and the third width being greater than the fourth width, Wherein, the first width is greater than the third width.

2. The semiconductor device according to claim 1, wherein The first memory unit is in a first cache memory, the second memory unit is in a second cache memory, and a level of the first cache memory is higher than a level of the second cache memory.

3. The semiconductor device according to claim 2, wherein: The first memory unit is located in a first-level cache memory, and the second memory unit is located in a second-level cache memory.

4. The semiconductor device according to claim 2, wherein: The first memory unit is located in a level 2 cache memory, and the second memory unit is located in a level 3 cache memory.

5. The semiconductor device according to claim 1, further comprising: a third memory cell, comprising a fifth active region for an n-type transistor and a sixth active region for a p-type transistor, the fifth active region having a fifth width, the sixth active region having a sixth width, Wherein, the fifth width is substantially equal to the sixth width.

6. A memory device comprising: a first memory cell including a first pull-down transistor and a first pull-up transistor, the first pull-down transistor having a first channel region of a first width, the first pull-up transistor having a second channel region of a second width, and the first width being greater than the second width; as well as a second memory cell including a second pull-down transistor and a second pull-up transistor, the second pull-down transistor having a third channel region of a third width, the second pull-up transistor having a fourth channel region of a fourth width, and the third width being greater than the fourth width, Wherein, the first width is greater than the third width.

7. The memory device according to claim 6, wherein: A ratio of the third width to the first width is in a range from about 0.6 to about 0.

9.

8. A memory device comprising: a first static random access memory (SRAM) cell having a first cell height and a cell width; a second SRAM cell having a second cell height and said cell width; as well as a third SRAM cell having a third cell height and the cell width, Wherein, the first cell height is different from the second cell height, and the second cell height is different from the third cell height.

9. The memory device according to claim 8, wherein: The first SRAM cell is located in a first cache memory of a first priority, the second SRAM cell is located in a second cache memory of a second priority lower than the first priority, and the third SRAM cell is located in a third cache memory of a third priority lower than the second priority.

10. The memory device according to claim 8, wherein: The first SRAM cell and the second SRAM cell are located in the same cache memory, or the second SRAM cell and the third SRAM cell are located in the same cache memory.

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