A chip, an internal eFuse programming power supply circuit thereof, and a programming method

Abstract

The present application provides a chip, an internal eFuse programming power supply circuit thereof, and a programming method, which are applied to the technical field of integrated circuits and electronic fuses (eFuses). A controlled switch circuit is added between the eFuse programming power supply terminal and the chip power supply terminal, and another controlled switch circuit is added between the eFuse programming power supply terminal and the multiplexed low-voltage IO port. Thus, by turning on or off the two controlled switch circuits, a high-voltage power supply and a working power supply outside the chip are used to provide a programming power supply or a working power supply for the eFuse correspondingly. It can provide the high-voltage power supply and the working power supply required for internal eFuse programming of the chip in a low-cost manner without occupying too many chip pins and consuming very little chip area, and is very suitable for popularization and application in various chips containing eFuses.

Description

Technical Field

[0001] This application relates to the technical field of integrated circuits and electronic fuses (eFuse), and particularly to a chip, an internal eFuse programming power supply providing circuit thereof, and a programming method. Background Art

[0002] eFuse (electronic fuse) is a commonly used programmable fuse technology in integrated circuit (IC) design. Inside a chip, eFuse usually requires a higher power supply voltage than other circuits to complete programming. For example, for a digital circuit with eFuse in a 5V standard BCD process, the voltage range is generally 3 to 5.5V during normal operation, while during eFuse programming, the eFuse programming power supply needs to be raised above 8V.

[0003] In view of the need for a higher power supply voltage during eFuse programming, traditional solutions mainly include the following methods: First, a separate chip PAD is required to implement this function, and thus programming can only be performed during wafer probe testing (Chip Probe); second, a separate pin needs to be reserved for eFuse programming after chip packaging, but some chips do not have spare pins available; third, a high-voltage PIN is reused for eFuse programming after chip packaging, which requires high-voltage devices and consumes a large chip circuit area. Summary of the Invention

[0004] In view of this, this application provides a chip, an internal eFuse programming power supply providing circuit thereof, and a programming method, which reuse low-voltage IO pins to provide programming power for internal eFuse programming of the chip, with a simple circuit structure, small occupied area, and convenient implementation inside the chip.

[0005] This application provides the following technical solutions:

[0006] The present application provides an eFuse programming power supply circuit inside a chip, including: a low-voltage IO port, a first switching circuit, and a second switching circuit; the first switching circuit is connected in series between the low-voltage IO port and the programming power supply port, and the second switching circuit is connected in series between the chip power supply terminal and the programming power supply port; wherein, the programming power supply port is the port inside the chip that provides power for the eFuse; the low-voltage IO port is used to connect to a high-voltage power supply when the eFuse inside the chip needs to be programmed, and serves as the IO of the chip when the eFuse inside the chip does not need to be programmed; the first switching circuit is used to conduct or cut off under the control of a first signal to connect or disconnect the connection between the low-voltage IO port and the programming power supply port, and the second switching circuit is used to conduct or cut off under the control of a second signal to connect or disconnect the connection between the chip power supply terminal and the programming power supply port, wherein when the eFuse inside the chip needs to be programmed, the first signal controls the first switching circuit to conduct, and the second signal controls the second switching circuit to cut off, so that the high-voltage power supply connected to the low-voltage IO port is input to the programming power supply terminal to provide the voltage required for programming the eFuse, and when the chip eFuse does not need to be programmed, the first signal controls the first switching circuit to cut off, and the second signal controls the second switching circuit to conduct, so that the voltage of the chip power supply terminal is input to the programming power supply terminal to provide the voltage required for normal operation of the eFuse.

[0007] Preferably, the first switching circuit includes a first MOS transistor, the gate of the first MOS transistor inputs the first signal, the drain of the first MOS transistor is connected to the low-voltage IO port, and the source of the first MOS transistor is connected to the programming power supply terminal;

[0008] And / or, the second switching circuit includes a second MOS transistor, the gate of the second MOS transistor inputs the second signal, the drain of the second MOS transistor is connected to the chip power supply terminal, and the source of the second MOS transistor is connected to the programming power supply terminal.

[0009] Preferably, the first switching circuit further includes a fourth MOS transistor and a first resistor, wherein the gate of the first MOS transistor inputs the first signal, the drain of the first MOS transistor is connected to the gate of the fourth MOS transistor, the source of the first MOS transistor is grounded, the drain of the fourth MOS transistor is connected to the low-voltage IO port, the source of the fourth MOS transistor is connected to the programming power supply terminal, and the first resistor is connected across the gate and the source of the fourth MOS transistor;

[0010] And / or, the second switching circuit further includes a third MOS transistor and a second resistor, wherein the gate of the second MOS transistor inputs the second signal, the drain of the second MOS transistor is connected to the gate of the third MOS transistor, the source of the second MOS transistor is grounded, the drain of the third MOS transistor is connected to the chip power supply terminal, the source of the third MOS transistor is connected to the programming power supply terminal, and the second resistor is connected across the gate and the source of the third MOS transistor.

[0011] Preferably, the fourth MOS transistor and / or the third MOS transistor is a MOS transistor including a body diode, so as to use the body diode to block the path after the MOS is turned off.

[0012] Preferably, the first switching circuit further includes a fifth MOS transistor, wherein the drain of the first MOS transistor is connected to the gate of the fourth MOS transistor and the gate of the fifth MOS transistor, the source of the fourth MOS transistor is connected to the source of the fifth MOS transistor, and the drain of the fifth MOS transistor is connected to the programming power supply terminal;

[0013] And / or, the first switching circuit further includes a zener diode, and the zener diode is connected across the gate and the source of the fourth MOS transistor to clamp the voltage between the gate and the source of the fourth MOS transistor.

[0014] Preferably, the fifth MOS transistor is a MOS transistor including a body diode, so as to use the body diode to block the path after the MOS is turned off.

[0015] Preferably, the first switching circuit further includes a third resistor, and the third resistor is connected in series between the source of the first MOS transistor and the ground to make the operating current of the zener diode within a preset range.

[0016] Preferably, for the chip internal eFuse programming power supply providing circuit described in any one of the present application, the chip internal eFuse programming power supply providing circuit further includes an inverter, and the inverter is used to provide a first signal and a second signal with opposite phases.

[0017] The present application further provides a method for programming a chip internal eFuse, including:

[0018] When the chip internal eFuse needs to be programmed, connect the high-voltage power supply required for programming to the low-voltage IO port in the chip internal eFuse programming power supply providing circuit described in any one of the present application, and by configuring the first signal and the second signal, make the programming power supply port in the chip internal eFuse programming power supply providing circuit described in any one of the present application communicate with the low-voltage IO port and disconnect from the chip power supply terminal respectively, so that the eFuse uses the high-voltage power supply connected to the low-voltage IO port to perform the programming operation;

[0019] After the eFuse completes programming, disconnect the high-voltage power supply from the low-voltage IO port, and by configuring the first signal and the second signal, make the programming power supply port disconnect from the low-voltage IO port and connect to the chip power supply terminal respectively, so that the eFuse can operate normally using the power supply voltage provided by the chip power supply terminal.

[0020] The present application further provides a chip, the chip includes an eFuse and an eFuse programming power supply circuit, wherein the eFuse programming power supply circuit is the chip internal eFuse programming power supply providing circuit described in any one of the present application.

[0021] Compared with the prior art, the beneficial effects that can be achieved by at least one of the above technical solutions adopted in this application at least include:

[0022] By reusing low-voltage I / O and adding a corresponding switching circuit inside the chip, and using a high-voltage power supply independent of the external of the chip to provide the required programming power supply for the in-chip eFuse programming, this is a new circuit architecture solution with low cost and small circuit area. It can provide the high-voltage power supply required for in-chip eFuse programming in a low-cost manner, consuming very little chip area without occupying too many chip pins, and is very suitable for popularization and application in various chips containing eFuse. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of this application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of this application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0024] Figure 1 is a schematic structural diagram of the in-chip eFuse programming power supply providing circuit in this application;

[0025] Figure 2 is a schematic structural diagram of the in-chip eFuse programming power supply providing circuit composed of a single MOS transistor in this application;

[0026] Figure 3 is a schematic structural diagram of the in-chip eFuse programming power supply providing circuit composed of multiple MOS transistors in this application;

[0027] Figure 4 is a schematic structural diagram of the in-chip eFuse programming power supply providing circuit composed of multiple MOS transistors in this application;

[0028] Figure 5 is a schematic structural diagram of the in-chip eFuse programming power supply providing circuit with clamping and current-limiting protection in this application;

[0029] Figure 6 is a schematic flowchart of the in-chip eFuse programming method in this application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0030] The embodiments of this application will be described in detail below with reference to the drawings.

[0031] The following describes the implementation modes of the present application through specific specific examples. Those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation modes. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope protected by the present application.

[0032] It should be noted that the following describes various aspects of the embodiments within the scope of the appended claims. It should be obvious that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is illustrative only. Based on the present application, those skilled in the art should understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspects described herein can be used to implement the device and / or practice the method. Additionally, this device can be implemented and this method can be practiced using other structures and / or functionality in addition to one or more of the aspects described herein.

[0033] It also needs to be noted that the drawings provided in the following embodiments only illustrate the basic concept of the present application schematically. The drawings only show the components related to the present application and are not drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and proportion of each component in its actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0034] In addition, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that the examples can be practiced without these specific details.

[0035] As described in the foregoing analysis, some traditional practices have their limitations and cannot meet the current flexible programming requirements of chips for electronic fuses (eFuses). For example, the eFuse programming method can only be performed during wafer testing. Generally, this method is no longer used for most chips, so it is only used for chips in some special applications. For example, since multiplexing high-voltage PIN pins requires a relatively large circuit area, and the circuit area of a chip is a very important chip design metric, the method of multiplexing high-voltage PIN pins can only be used for chips with less strict design requirements for circuit area. For example, the method of providing a programming power supply by reserving a separate pin. Since the pin resources of a chip are a relatively scarce chip resource, this method can also only be limited to individual chip designs and cannot meet the current flexibility requirements of chips.

[0036] In view of this, through in-depth research and improvement exploration on the power supply required for eFuse programming of the chip, as well as the chip area, resources, etc., it is found that: in the chip, the input / output interfaces operating at a lower voltage (referred to as low-voltage I / O ports in this application, also known as low-voltage I / O, without distinction) are some necessary resources that each chip has, and at least some or all of these I / O ports usually have multiplexing capabilities, that is, through chip design, the I / O can be made to work in different modes to achieve multiplexing functions.

[0037] In other words, if a low-voltage I / O port in the chip can be multiplexed to provide a high-voltage power supply for eFuse programming, that is, to provide the high-voltage power supply required for eFuse programming operations inside the chip, the flexibility will be completely changed and improved.

[0038] Based on this, this application proposes a circuit architecture solution for providing a programming power supply for the internal eFuse of the chip from the outside of the chip by multiplexing low-voltage I / O port pins: as Figure 1 shown, a controlled switch circuit (denoted as S2) is added between the eFuse programming power supply terminal (denoted as V_fuse) and the chip power supply terminal (denoted as VDD), and another controlled switch circuit (denoted as S1) is added between the eFuse programming power supply terminal V_fuse and the multiplexed low-voltage I / O port (denoted as V_IO), so as to provide a working power supply or a programming power supply for the eFuse by controlling the conduction or cutoff of S1 and S2.

[0039] Specifically, when S1 is conducting and S2 is cutoff, the high-voltage power supply connected to the low-voltage I / O port V_IO (that is, the relatively high-voltage power supply required for eFuse programming. Since this high-voltage power supply is outside the chip, so Figure 1The high voltage power supply is not shown in the figure) is input to the programming power supply terminal V_fuse, thereby providing the power required for programming for the eFuse; when S1 is turned off and S2 is turned on, the chip working power connected to VDD (that is, the lower voltage power required for the normal operation of the eFuse) is input to V_fuse, thereby providing the working power for the eFuse.

[0040] By adding two controlled switch circuits S1 and S2 in the chip, since the switch circuit can use a semiconductor electronic switch, and the electronic switch only needs to complete the basic function of on or off to connect the power required by the eFuse (i.e., the programming power supply or the working power supply), that is, the electronic switch only needs to realize reliable on or off functions, and does not need to realize complex circuit functions, so the area occupied by the switch circuit on the chip can generally be very small. In addition, the power required for eFuse programming is provided from the outside of the chip by reusing the low-voltage IO, that is, when the programming power supply is required, the higher voltage programming power supply is connected to the low-voltage IO to provide the higher voltage power required for the eFuse programming, and after the eFuse programming is completed (i.e., no programming is required), the programming power supply can be disconnected from the low-voltage IO, so the programming power supply can be independent of the outside of the chip, that is, the programming power supply does not need to occupy the internal area of ​​the chip, avoiding the overhead of increasing the chip area by integrating the programming power supply inside the chip.

[0041] It should be noted that the low-voltage IO is a multiplexed IO pin in the chip, and the external high-voltage power supply connected to the low-voltage IO is used to provide the power supply voltage required for burning the eFuse inside the chip.

[0042] In summary, the technical solution provided by the present application occupies a very small chip area, so that it can flexibly meet the various internal chip designs of the chip and meet the design requirements of the chip flexibly providing burning power for eFuse, and well meet the flexibility requirements of the chip providing burning power for eFuse.

[0043] The technical solutions provided by various embodiments of the present application are described below in conjunction with the accompanying drawings.

[0044] like Figure 1 As shown, the present application provides a chip internal eFuse burning power supply circuit, including: a low-voltage IO port (denoted as V_IO), a first switch circuit (denoted as S1) and a second switch circuit (denoted as S2). Since the low-voltage IO port is an IO resource that comes with the chip, when providing burning power for the eFuse, only the first switch circuit S1 and the second switch circuit S2 need to be added inside the chip, which has a small circuit area overhead and is convenient for design and application inside the chip.

[0045] refer to Figure 1As shown in the figure, the circuit connection of the programming power supply providing circuit is as follows: The first switch circuit S1 is connected in series between the low-voltage IO port (denoted as V_IO) and the programming power supply port (denoted as V_fuse). The second switch circuit S2 is connected in series between the chip power supply terminal (denoted as VDD) and the programming power supply port V_fuse. Among them, the first switch circuit S1 is used to conduct or cut off under the control of the first signal (denoted as Signal1) to connect or disconnect the connection between the low-voltage IO port V_IO and the programming power supply port V_fuse. The second switch circuit S2 is used to conduct or cut off under the control of the second signal (denoted as Signal2) to correspondingly connect or disconnect the connection between the chip power supply terminal VDD and the programming power supply port V_fuse.

[0046] It should be noted that the programming power supply port V_fuse is a port in the chip that provides the programming power supply or the working power supply for the eFuse ( Figure 1 not shown in the figure). This port can be a port inside the chip connected to the eFuse. The low-voltage IO port V_IO is a type of input / output interface (IO) in the chip for low-voltage operation. Here, this interface is multiplexed as follows: When the eFuse inside the chip needs to be programmed, it is used to access the high-voltage power supply (that is, a power supply with a relatively high voltage. Since the programming voltage of the eFuse is often higher than the working voltage, here the multiplexed low-voltage IO is used to separately provide the high-voltage power supply required for programming the eFuse from outside the chip). When the eFuse inside the chip does not need to be programmed, this low-voltage IO resumes to be the general IO of the chip.

[0047] Refer to Figure 1 As shown in the figure, the circuit working principle is as follows: When the eFuse inside the chip needs to be programmed, the first signal Signal1 controls the first switch circuit S1 to conduct, and the second signal Signal2 controls the second switch circuit S2 to cut off, so that the high-voltage power supply ( Figure 1 not shown in the figure) connected to the low-voltage IO port V_IO is input to the programming power supply terminal V_fuse to provide the voltage required for programming the eFuse. When the eFuse of the chip does not need to be programmed, for example, after the programming is completed, the first signal Signal1 controls the first switch circuit S1 to cut off, and the second signal Signal2 controls the second switch circuit S2 to conduct, so that the voltage of the chip power supply terminal VDD is input to the programming power supply terminal V_fuse to provide the voltage required for normal operation of the eFuse.

[0048] In summary, by reusing the low-voltage IO, only a switch circuit for conduction or cutoff needs to be added inside the chip, so that the programming power supply of the eFuse can be independently provided from outside the chip, significantly reducing the circuit area occupied by the programming power supply circuit of the eFuse inside the chip, enabling each chip (i.e., containing the eFuse) to very conveniently utilize the technical solution provided by this application to provide the high-voltage power required for programming the eFuse inside the chip, and enhancing the flexibility of the design and application of the programming power supply circuit of the eFuse inside the chip.

[0049] In some embodiments, an MOS transistor is used to form the switch circuit, thereby utilizing the characteristics of the MOS transistor of having a small on-resistance and a high off-resistance to achieve the switching performance.

[0050] In implementation, one or more MOS transistors are used as the core devices of the switch circuit, so that on the basis of meeting the switching performance, the switch circuit occupies a smaller chip area.

[0051] In one example, the first switch circuit S1 is implemented by using one MOS transistor, and / or the second switch circuit S2 is implemented by using one MOS transistor.

[0052] Reference Figure 2 As shown in the figure, the first switch circuit S1 includes a first MOS transistor M1, where the gate of M1 inputs a first signal Signal1, the drain is connected to the low-voltage IO port V_IO, and the source is connected to the programming power supply terminal V_fuse. Therefore, under the control of Signal1, M1 correspondingly completes conduction or cutoff, thereby correspondingly realizing the connection or disconnection between the low-voltage IO port V_IO and the programming power supply interface V_fuse.

[0053] Reference Figure 2 As shown in the figure, the second switch circuit S2 includes a second MOS transistor M2, where the gate of M2 inputs a second signal, the drain is connected to the chip power supply terminal VDD, and the source is connected to the programming power supply terminal V_fuse. Therefore, under the control of Signal2, M2 correspondingly completes conduction or cutoff, thereby correspondingly realizing the connection or disconnection between the chip power supply terminal VDD and the programming power supply interface V_fuse.

[0054] It should be noted that when the eFuse inside the chip needs to be programmed, M1 is turned on and M2 is turned off, so that a path is formed between the low-voltage IO port V_IO and the programming power supply terminal V_fuse, and an open circuit is formed between the chip power supply terminal VDD and the programming power supply terminal V_fuse. When an external high-voltage power supply is connected to V_IO, this high-voltage power supply can be applied to the eFuse inside the chip, so that the eFuse can use this high-voltage power supply for programming operations. In addition, since M2 is in the off state, this high-voltage power supply will not be applied to the chip power supply terminal VDD; conversely, that is, when the eFuse inside the chip does not need to be programmed, M1 is turned off and M2 is turned on, a path is formed between the chip power supply terminal VDD and the programming power supply terminal V_fuse, and an open circuit is formed between the low-voltage IO port V_IO and the programming power supply terminal V_fuse. When the chip power supply terminal VDD is connected to the working power supply, the working power supply can be applied to the eFuse inside the chip, so that the eFuse can use this working power supply for normal operation. In addition, since M1 is in the off state, the working power supply will not be applied to the low-voltage IO port V_IO. Moreover, even if this high-voltage power supply is still connected to the low-voltage IO port V_IO, due to M1 being turned off, the high-voltage power supply will not affect the eFuse inside the chip.

[0055] In one example, the first switch circuit S1 is implemented by multiple MOS transistors, and / or the second switch circuit S2 is implemented by multiple MOS transistors.

[0056] In implementation, the switch circuits each include a MOS transistor for power supply and a MOS transistor for control, so as to better improve the overall performance of the switch circuits on the basis of increasing a small amount of chip area overhead.

[0057] Reference Figure 3 As shown schematically, the first switch circuit S1 further includes a fourth MOS transistor M4 and a first resistor R1. That is, the core devices of the first switch circuit S1 are two MOS transistors M1 and M4. Among them, M4 is used as the switching transistor on the path, M1 is used as the control transistor of M4, and R1 is used as the gate-source bias resistor of M4.

[0058] The circuit connection is shown as follows: The gate of M1 inputs the first signal Signal1, the drain of M1 is connected to the gate of M4, the source of M1 is grounded, the drain of M4 is connected to the low-voltage IO port V_IO, the source of M4 is connected to the programming power supply terminal V_fuse, and R1 is connected across the gate and source of M4.

[0059] The working principle is as follows: Under the control of Signal1, when M1 is turned on, the gate of M4 is pulled low, so that M4 is stably turned on under the action of R1. At this time, a path is formed between the low-voltage IO port V_IO and the programming power supply terminal V_fuse. On the contrary, when M1 is turned off, the gate of M4 is pulled high, so that M4 is stably turned off under the action of R1. At this time, an open circuit is formed between the low-voltage IO port V_IO and the programming power supply terminal V_fuse.

[0060] Similarly, the second switching circuit also adopts the form of a switching circuit with a switching transistor and a control transistor.

[0061] Reference Figure 3 As shown in the schematic diagram, the second switching circuit S2 further includes a third MOS transistor M3 and a second resistor R2. That is, the core devices of the second switching circuit S2 are two MOS transistors M2 and M3. Among them, M3 is used as the switching transistor on the path, M2 is used as the control transistor of M3, and R2 is used as the bias resistor between the gate and source of M3.

[0062] The circuit connection is as follows: The gate of M2 inputs the second signal Signal2. The drain of M2 is connected to the gate of M3. The source of M2 is grounded. The drain of M3 is connected to the chip power supply terminal VDD. The source of M3 is connected to the programming power supply terminal V_fuse. R2 is connected across the gate and source of M3.

[0063] The working principle is as follows: Under the control of Signal2, when M2 is turned on, the gate of M3 is pulled low, so that M3 is stably turned on under the action of R2. At this time, a path is formed between the chip power supply terminal VDD and the programming power supply terminal V_fuse. On the contrary, when M2 is turned off, the gate of M3 is pulled high, so that M3 is stably turned off under the action of R2. At this time, an open circuit is formed between the chip power supply terminal VDD and the programming power supply terminal V_fuse.

[0064] In summary, by using the switching transistor on the path to provide good conduction or cut-off functions, and using the control transistor to control the conduction or cut-off of the switching transistor, while spending a small amount of chip area (that is, the chip area of one more MOS transistor), the conduction and cut-off performance is further improved, and the circuit reliability is higher.

[0065] In some embodiments, for the MOS transistor located on the path, a reverse diode can be added between the drain and the source. The diode can be an external diode connected in parallel between the drain and the source, or the body diode of the MOS transistor itself, so as to utilize the reverse bias cut-off characteristic of the diode to enhance the cut-off performance between the drain and the source of the MOS transistor.

[0066] Reference Figure 3Illustratively, a diode is connected in parallel between the drain and source of M4 and / or M3, or M4 and / or M3 is a MOS transistor including a body diode, so as to utilize the reverse cut-off characteristic of the diode to further block the path after the MOS is turned off, that is, to further improve the cut-off performance between the drain and source of the MOS transistor in the off state by using the diode. For example, when M3 is turned off, the high-voltage from V_IO to V_fuse, due to the diode between the drain and source of M3 being reverse-biased, the turn-off performance of M3 is better at this time. Similarly, the diode on M4 is used to enhance the turn-off performance of M4.

[0067] In some embodiments, for the switching transistors on the path, multiple MOS transistors can be used to form the circuit form of the switching transistors.

[0068] Reference Figure 4 Illustratively, the first switching circuit S1 further includes a fifth MOS transistor M5, that is, on the path of the first switching circuit S1, the core devices are two MOS transistors M4 and M5, and a switching transistor circuit with better turn-off characteristics is formed by using the two MOS transistors M4 and M5.

[0069] The circuit connection is as follows: the drain of M1 is connected to the gates of M4 and M5, the sources of M4 and M5 are connected, and the drain of M5 is connected to the programming power supply terminal V_fuse.

[0070] The working principle is as follows: when the chip is in the normal working mode, that is, when the eFuse does not need to be programmed, M2 is turned on (i.e., conducting) under the control of Signal2, while M1 is turned off (i.e., non-conducting) under the control of Signal1, thereby pulling down the gate potential V1 of M3, causing M3 to turn on, and at this time the voltage of the chip working power supply terminal VDD is provided to the eFuse programming power supply terminal V_fuse; when the chip is in the programming mode, that is, when the eFuse needs to be programmed, M2 is turned off under the control of Signal2, M1 is turned on under the control of Signal1, at this time the gate-source voltage of M3 is set to 0 by the initial state resistor R2 and cannot conduct, and M1 pulls down the gate voltage V2 of M4 and M5, so that M4 and M5 conduct, and the voltage V_IO of the low-voltage IO pin is provided to V_fuse, that is, the external power supply is used as the voltage required for eFuse programming and provided to V_fuse by multiplexing the chip IO pin.

[0071] In some embodiments, similar to the foregoing example, a reverse diode is provided between the drain and source of M5, or the body diode of M5 itself (i.e., M5 is a MOS transistor with a body diode) is utilized, so that when the MOS transistor is turned off, the diode is reverse-biased and cut off, making the cut-off performance of the path after turn-off better.

[0072] In one example, during normal operation, Signal1 is at a low level and M1 is turned off. At this time, the initial resistance makes V2 = V3, and the channels of M4 and M5 cannot conduct. In addition, the parasitic diodes of M4 and M5 form a back-to-back structure, blocking the path from V_IO to V_fuse. Additionally, Signal2 is high and M5 is conducting. At this time, the gate voltage V1 of M3 is pulled down to 0, and the channel of M3 conducts. At this time, V_fuse = VDD, and the chip's power supply VDD directly provides the operating voltage for the eFuse.

[0073] When eFuse programming is required, Signal1 is high and M4 conducts. The gate voltages V2 of M1 and M2 are pulled down, so the channels of M1 and M2 conduct. V_fuse = V_IO, and the voltage V_IO of the multiplexed IO pin provides the power supply voltage for the eFuse. At this time, the voltage of this IO pin can be raised to the voltage required for eFuse programming outside the chip.

[0074] In some embodiments, for the switching transistors on the path, a zener diode can be added to maintain the stability and clamping of the gate-source voltage, making the MOS transistors work more stably and reliably.

[0075] Reference Figure 5 As shown in the schematic, the first switching circuit S1 further includes a zener diode D1, so as to use D1 to provide a stable gate-source voltage for M4 and / or M5. Among them, D1 is connected across the gate and source of M4 to clamp the voltages of the gate and source of M4, realizing voltage stabilization protection.

[0076] In some embodiments, for the switching transistors on the path, a corresponding current-limiting resistor can be added to set the operating current of the switching transistors on the path within a suitable range.

[0077] For example, for the circuit with the added zener diode D1, a current-limiting resistor is added to the control transistor M1. Specifically, the first switching circuit S1 further includes a third resistor R3, where R3 is connected in series between the source of M1 and the ground, so as to use R3 to set the operating current of the zener diode D1 to make it within a suitable preset range, and further enable the zener diode D1 to stably provide the clamping and voltage stabilization protection function for M4.

[0078] The working principle is shown as follows:

[0079] When eFuse programming is required, M4 conducts (as shown in the previous example, M1 conducts, so M4 conducts). V3 = V_IO, and due to the presence of the clamping zener diode D1, V2 = V_IO - V D1 , where V D1is the voltage drop of the Zener voltage regulator diode D1. To prevent excessive current in D1, a current-limiting resistor R3 is added from the source of the switching transistor M1 to ground. At this time, the current in D1 is limited to (V Signal1 - V GS_M1 ) / R3. In addition, when Signal2 is low, M2 is turned off. At this time, the initial resistance R2 makes the gate potential V1 of M3 equal to V_fuse = V_IO. Note that V_IO is generally greater than VDD, so the channel of M3 cannot conduct. In addition, the diode direction of M3 is connected from VDD to V_fuse, so the diode is blocked at this time, and no current path can be formed between VDD and V_fuse.

[0080] When eFuse programming is not required, M4 and M5 are turned off, and the parasitic diodes of M4 and M5 form a back-to-back structure, further blocking the path from V_IO to V_fuse. In addition, when Signal2 is high, M2 conducts. At this time, the gate voltage V1 of M3 is pulled down to 0, and the channel of M3 conducts, so V_fuse = VDD, and the chip operating power supply VDD directly provides the operating voltage for the eFuse.

[0081] In some embodiments, since the first signal Signal1 and Signal2 are used to control the operating states of M1 and M2, and the operating states of M1 and M2 are opposite, the same control signal can be used to obtain Signal1 and Signal2 through an inverter, further reducing the area occupied by the signal circuit on the chip.

[0082] In the chip internal eFuse programming power supply providing circuit described in any one of the present applications, the same signal is generated into inverted Signal1 and Signal2 by using an inverter, that is, the inverter is used to provide a first signal and a second signal with opposite phases.

[0083] In some examples, Signal1 and Signal2 can be generated by soft signals or obtained by setting external IO levels. For example, when configuring Signal1 and Signal2 by using external IO levels, when eFuse programming is required, the external IO corresponding to Signal1 is set to the corresponding level, such as the high level that makes the NMOS transistor M1 conduct for Signal1. On the contrary, the external IO corresponding to Signal2 is set to the low level that makes the NMOS transistor M2 turn off. For example, when Signal1 and Signal2 are generated by using an inverter, the same external IO can be set to a low level or a high level to obtain them.

[0084] Based on the same inventive concept, the present application also provides a method for programming the eFuse inside a chip. By using the programming power supply providing circuit provided in the present application, this programming method can very conveniently perform the programming operation on the eFuse inside the chip.

[0085] Refer to Figure 6 For illustration, a method for programming the eFuse inside a chip includes:

[0086] Step S202: Determine the operating mode of the chip. When the chip is in the eFuse programming mode, that is, when it is necessary to perform the programming operation on the eFuse inside the chip, execute Step S204; otherwise, execute Step S206.

[0087] Step S204: When the eFuse inside the chip needs to be programmed, that is, when the chip is in the eFuse programming mode, connect the high-voltage power supply required for programming to the low-voltage IO port (referred to as low-voltage IO in the present application, denoted as V_IO) in the chip internal eFuse programming power supply providing circuit as described in any one of the present application. And by configuring the first signal and the second signal, make the programming power supply ports in the chip internal eFuse programming power supply providing circuit as described in any one of the present application communicate with the low-voltage IO port and disconnect from the chip power supply terminal respectively, so that the eFuse can perform the programming operation by using the high-voltage power supply connected to the low-voltage IO port.

[0088] Step S206: When the chip is not in the eFuse programming mode (i.e., in the normal operating mode), for example, after the eFuse programming is completed, disconnect the high-voltage power supply from the low-voltage IO port, and by configuring the first signal and the second signal, make the programming power supply port disconnect from the low-voltage IO port and connect to the chip power supply terminal correspondingly, so that the eFuse can operate normally by using the power supply voltage provided by the chip power supply terminal.

[0089] It should be noted that the external high-voltage power supply independent of the chip (which can also be called the programming power supply) and the chip operating power supply are respectively provided to the programming power supply terminal V_fuse. For the content of each foregoing embodiment, reference can be made and will not be elaborated here.

[0090] Based on the same inventive concept, the present application also provides a chip, which includes an electronic fuse (eFuse) and an eFuse programming power supply circuit, wherein the eFuse programming power supply circuit is the chip internal eFuse programming power supply providing circuit as described in any one of the present application.

[0091] By only needing to reuse the low-voltage IO and adding a switch circuit, it is possible to implement the power supply providing circuit required for eFuse programming inside the chip with a very small chip area, facilitating various chips containing eFuse to implement the eFuse programming power supply design and programming operation only with a simple chip design.

[0092] In this specification, for the same or similar parts among various embodiments, reference can be made to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the embodiments described later, the description is relatively simple, and for the relevant parts, reference can be made to the partial description of the foregoing embodiments.

[0093] As described above, the above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present application should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A chip internal eFuse burning power supply circuit, characterized in that: include: A low voltage IO port, a first switch circuit and a second switch circuit; The first switch circuit is connected in series between the low-voltage IO port and the programming power port, and the second switch circuit is connected in series between the chip power supply end and the programming power supply port; wherein the programming power supply port is a port in the chip that provides power for the eFuse; the low-voltage IO port is used to connect the high-voltage power supply when the eFuse inside the chip needs to be programmed, and serves as the IO of the chip when the eFuse inside the chip does not need to be programmed; the first switch circuit is used to turn on or off under the control of a first signal to connect or disconnect the connection between the low-voltage IO port and the programming power supply port, and the second switch circuit is used to turn on or off under the control of a second signal to connect or disconnect the connection between the chip power supply end and the programming power supply port, wherein when the eFuse inside the chip needs to be programmed, the first signal controls the first switch circuit to turn on, and the second signal controls the second switch circuit to turn off, so that the high-voltage power connected to the low-voltage IO port is input to the programming power supply end to provide the eFuse with the voltage required for programming, and when the chip eFuse does not need to be programmed, the first signal controls the first switch circuit to turn off, and the second signal controls the second switch circuit to turn on, so that the voltage of the chip power supply end is input to the programming power supply end to provide the eFuse with the voltage required for normal operation; The first switch circuit includes a first MOS tube, a gate of the first MOS tube inputs a first signal, a drain of the first MOS tube is connected to a low voltage IO port, and a source of the first MOS tube is connected to a programming power supply terminal; and / or, the second switch circuit includes a second MOS tube, a gate of the second MOS tube inputs a second signal, a drain of the second MOS tube is connected to a chip power supply terminal, and a source of the second MOS tube is connected to a programming power supply terminal; The first switch circuit also includes a fourth MOS tube and a first resistor, wherein the gate of the first MOS tube inputs the first signal, the drain of the first MOS tube is connected to the gate of the fourth MOS tube, the source of the first MOS tube is grounded, the drain of the fourth MOS tube is connected to the low-voltage IO port, the source of the fourth MOS tube is connected to the programming power supply terminal, and the first resistor is connected between the gate and the source of the fourth MOS tube; and / or, the second switch circuit also includes a third MOS tube and a second resistor, wherein the gate of the second MOS tube inputs the second signal, the drain of the second MOS tube is connected to the gate of the third MOS tube, the source of the second MOS tube is grounded, the drain of the third MOS tube is connected to the chip power supply terminal, the source of the third MOS tube is connected to the programming power supply terminal, and the second resistor is connected between the gate and the source of the third MOS tube.

2. The chip internal eFuse burning power supply circuit according to claim 1, characterized in that: The fourth MOS tube and / or the third MOS tube is a MOS tube including a body diode, so as to utilize the body diode to block the path after the MOS is turned off.

3. The chip internal eFuse burning power supply circuit according to claim 1, characterized in that: The first switch circuit also includes a fifth MOS tube, wherein the drain of the first MOS tube is connected to the gate of the fourth MOS tube and the gate of the fifth MOS tube, the source of the fourth MOS tube is connected to the source of the fifth MOS tube, and the drain of the fifth MOS tube is connected to the programming power supply terminal; And / or, the first switch circuit further includes a voltage stabilizing diode, which is connected between the gate and source of the fourth MOS tube to clamp the voltage of the gate and source of the fourth MOS tube.

4. The chip internal eFuse burning power supply circuit according to claim 3, characterized in that: The fifth MOS tube is a MOS tube including a body diode, so as to utilize the body diode to block the path after the MOS is turned off.

5. The chip internal eFuse burning power supply circuit according to claim 3, characterized in that: The first switch circuit also includes a third resistor, which is connected in series between the source of the first MOS tube and the ground, so that the operating current of the voltage regulator diode is within a preset range.

6. The chip internal eFuse burning power supply circuit according to any one of claims 1 to 5, characterized in that: The chip internal eFuse burning power supply circuit also includes an inverter, and the inverter is used to provide a first signal and a second signal with opposite phases.

7. A method for burning eFuse inside a chip, characterized in that: include: When the eFuse inside the chip needs to be burned, the high-voltage power supply required for burning is connected to the low-voltage IO port in the eFuse burning power supply circuit inside the chip as described in any one of claims 1-6, and by configuring the first signal and the second signal, the burning power supply port in the eFuse burning power supply circuit inside the chip as described in any one of claims 1-6 is connected to the low-voltage IO port and disconnected from the chip power supply terminal, so that the eFuse uses the high-voltage power supply connected to the low-voltage IO port to perform the burning operation; After the eFuse is burned, the high voltage power supply is disconnected from the low voltage IO port, and by configuring the first signal and the second signal, the burning power port is disconnected from the low voltage IO port and connected to the chip power supply terminal, so that the eFuse can work normally using the power supply voltage provided by the chip power supply terminal.

8. A chip, comprising an eFuse, characterized in that: The chip also includes an eFuse burning power supply circuit, wherein the eFuse burning power supply circuit is a chip internal eFuse burning power supply circuit as described in any one of claims 1-6.

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