Signal correlation synchronization method and system based on parallel processing

Abstract

The invention discloses a signal correlation synchronization method and system based on parallel processing, and relates to the technical field of signal synchronization, and the method comprises the following steps: a receiving end receives a radio frequency signal sent by a transmitting end; a receiving end performs coherent demodulation and low-pass filtering processing on the radio frequency signal to obtain a complex baseband signal, and samples the complex baseband signal to obtain a complex sequence; wherein the complex sequence comprises a known subsequence inserted by the transmitting end; the receiving end inputs the complex sequence into a linear shift register constructed by an FPGA, and the linear shift register calculates a correlation value of the complex sequence and a local known sequence; when the input complex sequence is matched with the target sub-sequence in the local known sequence, the absolute value of the correlation value can reach the maximum value, and a correlation peak is formed; and the clock time corresponding to the correlation peak is determined, so that the position of the known sub-sequence of the transmitting end in the complex sequence of the receiving end is found, signal correlation synchronization is completed, the synchronization system comprises the receiving end and the transmitting end, and the signal correlation synchronization method based on parallel processing is applied.

Description

Technical Field

[0001] The present invention relates to the technical field of signal synchronization, and in particular to a signal correlation synchronization method and system based on parallel processing. Background Art

[0002] In the field of modern communication technology, RF link IQ dual-path transceiver system is widely used in various wireless communication devices, and its performance plays a key role in communication quality.

[0003] There is inevitably phase deviation and frequency deviation between the transmitter and the receiver. Phase deviation will change the phase of the received signal and affect the correct demodulation of the signal; frequency deviation will make the frequency of the received signal inconsistent with the frequency of the transmitted signal, causing the signal spectrum to shift, increasing the difficulty of demodulation and reducing the reliability and accuracy of the communication system.

[0004] The signal transmitted in the RF link is essentially a real signal, but in the actual processing process, complex means are often used for processing. The traditional phase deviation and frequency deviation correction methods lack systematic and efficient methods when dealing with the relationship between real signals and complex processing means. Summary of the invention

[0005] In order to solve the problem in the prior art that in the signal synchronization process, phase deviation and frequency deviation may cause received signal distortion, making it difficult for the receiver to accurately identify the transmission sequence, thereby causing synchronization difficulties, the present invention provides a signal correlation synchronization method based on parallel processing.

[0006] The technical solution adopted by the present invention is: The first aspect of the present application provides a signal correlation synchronization method based on parallel processing, comprising the following contents: The receiving end receives the radio frequency signal sent by the transmitting end; the receiving end coherently demodulates and low-pass filters the radio frequency signal to obtain a complex baseband signal, and samples the complex baseband signal to obtain a complex sequence; wherein the complex sequence includes a known subsequence inserted by the transmitting end; the receiving end pre-stores a local known sequence that is the same as the known subsequence inserted by the transmitting end, and the receiving end inputs the complex sequence into a linear shift register constructed by an FPGA (Field-Programmable Gate Array), and calculates the correlation value between the complex sequence and the local known sequence through the linear shift register; when the input complex sequence matches the target subsequence in the local known sequence, the absolute value of the correlation value reaches a maximum value, forming a correlation peak; the clock time corresponding to the correlation peak is determined, so as to find the position of the known subsequence of the transmitting end in the complex sequence of the receiving end, and complete signal correlation synchronization.

[0007] Preferably, the linear shift register constructed by the FPGA includes a plurality of delays, a plurality of multipliers and adders.

[0008] Preferably, the step of calculating the correlation value between the complex sequence and the locally known sequence by using a linear shift register includes the following: The complex sequence is sequentially input into a linear shift register, wherein each delayer is controlled by a sampling clock, so that the output signal of the right delayer is one clock cycle later than the input signal of the left delayer. In each clock cycle, the complex sequence is sequentially shifted one position to the right in the shift register, thereby realizing sequential processing of elements at different positions of the complex sequence; at each sampling moment, for the output of each delayer in the linear shift register, a multiplier is used to multiply it with the conjugate of the element at the corresponding position in the local known sequence to obtain multiple intermediate results; an adder adds the intermediate results output by each multiplier to obtain a correlation value between the complex sequence and the local known sequence.

[0009] Preferably, when the input complex sequence matches the target subsequence in the local known sequence, the absolute value of the correlation value reaches a maximum value, forming a correlation peak; determining the clock time corresponding to the correlation peak, thereby finding the position of the known subsequence of the transmitting end in the complex sequence of the receiving end, and completing the signal correlation synchronization includes the following: The absolute values ​​of the calculated correlation values ​​are generated in the order of sampling time to store the absolute value sequence of correlation values ​​in the FPGA; the stored absolute value sequence of correlation values ​​is analyzed, and starting from the starting position of the absolute value sequence, the absolute value of each correlation value is compared with the absolute values ​​of the adjacent previous and next correlation values. If the absolute value of a certain correlation value is greater than the absolute values ​​of the previous and next adjacent correlation values ​​at the same time, the point is marked as a candidate point for correlation peak; if there are multiple candidate points for correlation peak, the absolute values ​​of the correlation values ​​of each candidate point are compared one by one to find the maximum value. The candidate point corresponding to the maximum value is determined as the correlation peak; according to the position information of the correlation peak in the stored absolute value sequence of correlation values, combined with the period parameter of the sampling clock, the clock time corresponding to the correlation peak is calculated; based on the clock time, the receiving end locates the position of the known subsequence of the transmitting end in the received complex sequence to complete the correlation synchronization of the signal.

[0010] A second aspect of the present application provides a signal correlation synchronization system based on parallel processing, including a receiving end and a transmitting end, and applying the above-mentioned signal correlation synchronization method based on parallel processing.

[0011] The beneficial effects of the present invention are at least one of the following: The linear shift register built using FPGA is used to calculate the correlation value. FPGA has strong parallel processing capability and flexibility, and can quickly and accurately complete the correlation calculation. Through the correlation peak judgment mechanism, useful synchronization information can be accurately extracted from the signal affected by phase deviation, frequency deviation and noise interference.

[0012] By constructing a linear shift register through FPGA to calculate the correlation value, the processing time is greatly shortened compared with the traditional signal processing method. When calculating the correlation value of the complex sequence and the locally known sequence, a large number of multiplication and accumulation operations can be completed quickly, which improves the efficiency of signal processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is a schematic diagram of a method flow chart of Embodiment 1 of the present invention; Figure 2 A schematic diagram of the system structure and signal flow of the transceiver link in the first embodiment of the present invention; Figure 3 Schematic diagram of the structure of the linear shift register in the first embodiment of the present invention. DETAILED DESCRIPTION

[0014] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0015] Embodiment 1 provides a signal correlation synchronization method based on parallel processing, such as Figure 1 As shown, the following steps are included: Step 1: The receiving end receives the radio frequency signal sent by the transmitting end.

[0016] For reference, in this example, the receiving end may be a receiver, and the transmitting end may be a transmitter; Figure 2 As shown, the transmitter sends a modulated electromagnetic wave signal, that is, a real signal, and the signal on the receiving antenna is also a real number. The expressions of the signals transmitted on the transceiver link, including the iq path signals, are all real numbers, but complex means or methods are usually used to process the signals.

[0017] from Figure 2 It can be seen that the transmitter road sequence and After D / A, up-conversion, power amplifier, antenna transmission and reception, low noise amplifier (LNA), down-conversion, low-pass filtering, A / D, the digital signal of the receiver is obtained. road sequence and In this process, after the communication system structure and settings are finalized, the intermediate operation process does not need to be interfered with or processed, and only the above four sequences can be operated.

[0018] Specifically, when transmitting, the software radio system (such as ad9361) is sent and , when receiving, only and All demodulation and signal extraction work depends on these two sequences. In order to correctly complete signal extraction and demodulation, the radio system can be regarded as a black box. The input of this black box is and , the output is and .

[0019] exist Figure 2 In, if Not equal to , then there is a phase deviation if Not equal to , there is a frequency deviation. When the system has factors such as phase deviation and frequency deviation, the relationship between the received sequence and the transmitted sequence can be used to synchronize the signals.

[0020] In order to get the sequence , with sequence , First, we need to get the analog signal , and , First, assemble the real signal of the transmitter into a complex baseband signal, and then use the signal processing process of the system to derive the expression of the complex baseband signal received by the receiver, and then use the expression to get the relationship between the transmitted and received signals.

[0021] The transmitter The signal plus The complex baseband signal expression obtained by multiplying the local signal by j is: (1) in, Indicates the transmitter external signal, Indicates the transmitter external signal, represents the complex baseband signal of the transmitter, and j represents an imaginary number.

[0022] Usually the complex baseband signal is Road modulation, specifically Luhe Multiply the road by and , and then add them together, the expression of the RF signal is as follows, which can also be regarded as the signal expression on the transmitting antenna: (2) in, Represents the radio frequency signal emitted by the transmitting antenna. Indicates the transmitter external signal, Indicates the transmitter external signal, represents the complex baseband signal of the transmitter, represents the angular frequency of the transmitter, Indicates the initial phase of the signal transmitted by the transmitter.

[0023] Then the RF signal will pass through the channel, which has two effects on the RF signal. The first is the amplitude change effect, that is, the amplitude of the signal obtained by the receiver may not be equal to the amplitude of the transmitter. After the analog signal is amplified by the low noise amplifier (LNA), adjusted by the automatic gain control (AGC) and converted by the analog-to-digital converter (ADC), it will eventually be presented to the user in the form of a 12-bit signed digital signal. Therefore, the attenuation of the signal amplitude can be ignored, and it is assumed that the received signal amplitude is equal to the transmitted signal amplitude; the second is the delay effect, that is, if the transmitter transmits a signal at a certain time t1, then the receiver will definitely receive the signal at another time t2. If the receiver and the transmitter use the same starting reference time, then t2 is not equal to t1, and t2 must be greater than t1. Assuming , if the receiver uses the same starting reference time as the transmitter, then there is always one expression for the receiver signal , which is more complicated. If the reference time of the receiver is set to the time when the receiver receives the first signal, the signal expression in the receiver will be simplified. Using the above simplification, it can be considered that the expression of the analog signal transmitted by the receiving antenna is equal to the expression in equation (2): .like Figure 2 As shown in the figure, the signal expressions marked on the transmitting antenna and the receiving antenna are .

[0024] Step 2: The receiving end performs coherent demodulation and low-pass filtering on the RF signal to obtain a complex baseband signal, and samples the complex baseband signal to obtain a complex sequence; wherein the complex sequence includes a known subsequence inserted by the transmitting end.

[0025] The receiver performs coherent demodulation and low-pass filtering on the RF signal to obtain a complex baseband signal, including the following: Receiver The signal will be Multiply , and then take its low-pass filter, the receiver The signal expression is: (3) Receiver The signal is Multiply , and then low-pass filtered, the receiver The expression of the internal signal is: (4) in, For the receiver The signal expression, For the receiver The signal expression, Indicates the transmitter external signal, Indicates the transmitter external signal, represents the complex baseband signal of the transmitter, represents the angular frequency of the transmitter, represents the initial phase of the transmitter signal, represents the angular frequency of the receiver, Indicates the initial phase of the receiver.

[0026] The derivation of formula (3) and formula (4) uses the product-to-difference formula in formula (5). The last step of formula (3) and formula (4) ignores This is because the analog signal undergoes multiple attenuation and amplification operations during the transmission process, and is finally converted into a digital quantity with a suitable dynamic range by the ADC, so there is no need to worry about the specific size of the analog signal.

[0027] (5) make is the received complex baseband signal, and the expression of the complex baseband signal is: (6) Formula (6) shows that the complex baseband signal of the receiver's iq path is equal to the complex baseband signal of the transmitter multiplied by a rotation factor. The expression of the rotation factor is .

[0028] Based on formula (6), we first consider the case where there is no frequency offset between the receiver and the transmitter, that is, It is found that at any time, the complex baseband signal composed of the iq path of the received signal is only multiplied by a constant compared to the complex baseband signal sent by the transmitter at the same time. , this constant can be called the phase bias factor. If we know The signal emitted at any time is , the received signal is , then use The phase deviation factor can be obtained. If the conjugate of this phase deviation factor is multiplied by any subsequent received signal, you can get the signal from the transmitter , its real and imaginary parts are and , after sampling, the ADC digital sequence can be obtained correctly and .

[0029] However, this use of a moment and The method of calculating the phase deviation factor has shortcomings, because the two signals at a certain moment contain noise, making the calculated phase deviation factor not very accurate. In order to improve the accuracy, multiple phase deviation factors can be calculated using signals of multiple cycles and then averaged.

[0030] when , that is, when there is a frequency deviation, assuming that the analog signal and All are based on The sampling frequency is sampled, then the sampling time interval ,make , so formula (6) can be written as: (7) in, Represents the discrete sampling number, , represents the sampling time interval, Indicates The sampling time, The complex baseband signal of the transmitter is The value at the sampling time, Represents the carrier frequency of the transmitter and receiver respectively, the unit is Hz.

[0031] Assuming you know = Moment and The corresponding phase deviation factor can be calculated to be equal to , for this phase deviation factor, there is no need to deduce The value of The value is equal to the current time divided by , but it is meaningless to use this method to calculate the current moment. What needs to be known is how many degrees the subsequent signal needs to rotate relative to the phase deviation factor at this time, or what kind of phase deviation factor needs to be multiplied on this basis. For this reason, it can be assumed that , obviously ,because It was originally a 0 to A random number between is also a random number, and the above method of finding the bias works for any random number. > According to formula (7), we can get: (8) Formula (8) shows that when The received complex baseband signal at the time is equal to the transmitted complex baseband signal multiplied by one hour, The complex baseband signal received at the time needs to be multiplied by a larger angle rotation factor based on the transmitted complex baseband signal , the rotation factor is There are more rotation factors at the moment , obviously Compare The larger is, the larger is the deviation angle of the rotation factor. is the unit rotation angle, is the unit rotation factor, then the above process shows that Time relative to More rotations required at all times The angle of rotation factor is the unit rotation factor Power.

[0032] Assume that the transmitter is Time will send out a pair of iq path sampling values, forming a complex sequence , the receiver will also receive the complex sequence , .

[0033] Among them, the transmitter Sequence contains subsequence , the complex sequence from the receiver is required turn up .

[0034] Step 3: The receiving end pre-stores a local known sequence that is the same as the known subsequence inserted by the transmitting end. The receiving end inputs the complex sequence into a linear shift register constructed by FPGA, and calculates the correlation value between the complex sequence and the local known sequence through the linear shift register.

[0035] In the specific implementation process, in order to obtain the sequence from the receiver turn up , the receiving end inputs the complex sequence into the linear shift register constructed by FPGA. In a possible implementation, as Figure 3 As shown, the linear shift register constructed by the FPGA includes multiple delays, multiple multipliers and adders.

[0036] In a possible implementation, the calculation of the correlation value between the complex sequence and the local known sequence by a linear shift register includes the following: the complex sequence is sequentially input into the linear shift register, wherein each delayer is controlled by a sampling clock, so that the output signal of the right delayer is one clock cycle later than the input signal of the left delayer, and in each clock cycle, the complex sequence is sequentially shifted to the right by one position in the shift register, thereby realizing sequential processing of elements at different positions of the complex sequence. At each sampling moment, for the output of each delayer in the linear shift register, a multiplier is used to multiply it with the conjugate of the element at the corresponding position in the local known sequence to obtain multiple intermediate results. The adder adds the intermediate results output by each multiplier to obtain the correlation value between the complex sequence and the local known sequence.

[0037] For example, Figure 3 As shown, Figure 3 Each The structure represents a delay. The signal output on the right side of each delay is one clock cycle later than the input signal on the left side. All delays are controlled by the same sampling clock. The rising or falling edge control, Figure 3 Take the 6th order filter as an example. Generally speaking, an Nth order filter requires N-1 delays. Figure 3 It can be seen that the sequence output by the delay device on the right is more "old", that is, the independent variable in the brackets is smaller, and the smaller it is, the smaller it represents a smaller moment.

[0038] In the picture Represents a multiplier, one input of each multiplier is taken from the output of a delay, and the other input is set to the local sequence One of them, here The + sign below the multiplier represents adding the outputs of each multiplier.

[0039] clk_ Represents the sampling clock of the ADC and is also the driving clock of all multipliers, delays, adders, etc. The structure of the entire system is based on each clk_ The rising edge of the system will input a complex number , while y( ) will also output a complex number. y( ) is: (9) in, Indicated in At the sampling moment, the correlation between the received complex sequence and the locally known sequence is 6 terms added in formula (9), each of which is the multiplication of two complex numbers. Obviously, when When , we can get formula (10):

[0040] Each term in formula (10) is the product of a complex number and its conjugate complex number. From the conclusion of formula (7), we find that Relative to All have a common rotation factor , can be raised. At this time, please The absolute value of will be the maximum, and when The input at this moment is not When, due to ,and are uncorrelated, and the angle between the two complex inputs of each multiplier is randomly and uniformly distributed between 0 and The modulus of each complex number is considered equal (for example, if it is QPSK modulation, these complex numbers are One of them has a modulus value equal to ), which will result in the phenomenon that the real and imaginary parts of multiple products will cancel each other out after adding them together, resulting in It will be smaller, definitely smaller than when Obviously, when the filter order is larger, the mutual cancellation effect will be more obvious, and when the synchronization is achieved, the value of the correlation peak will be larger.

[0041] Step 4: When the input complex sequence matches the target subsequence in the local known sequence, the absolute value of the correlation value reaches a maximum value, forming a correlation peak.

[0042] Step 5, determine the clock time corresponding to the correlation peak, so as to find the position of the known subsequence of the transmitting end in the complex sequence of the receiving end, and complete the signal correlation synchronization.

[0043] In a possible implementation, when the input complex sequence matches the target subsequence in the local known sequence, the absolute value of the correlation value reaches a maximum value, forming a correlation peak; determining the clock time corresponding to the correlation peak, thereby finding the position of the known subsequence of the transmitting end in the complex sequence of the receiving end, and completing the signal correlation synchronization includes the following: The absolute values ​​of the calculated correlation values ​​are generated according to the order of sampling time to store the absolute value sequence of the correlation values ​​in the FPGA.

[0044] The stored absolute value sequence of correlation values ​​is analyzed. Starting from the starting position of the absolute value sequence, the absolute value of each correlation value is compared with the absolute values ​​of its adjacent previous and next correlation values. If the absolute value of a correlation value is greater than the absolute values ​​of its adjacent previous and next correlation values ​​at the same time, the point is marked as a correlation peak candidate point.

[0045] If there are multiple correlation peak candidate points, the absolute values ​​of the correlation values ​​of the candidate points are compared one by one to find the maximum value, and the candidate point corresponding to the maximum value is determined as the correlation peak.

[0046] The clock time corresponding to the correlation peak is calculated based on the position information of the correlation peak in the stored absolute value sequence of correlation values ​​in combination with the period parameter of the sampling clock.

[0047] Based on the clock time, the receiving end locates the position of the known subsequence of the transmitting end in the received complex sequence, and completes the correlation synchronization of the signal.

[0048] Exemplarily, the hardware description language is used to continuously search When the highest peak of the correlation peak is found, the highest peak found is the correlation peak. After that, we know that the signal behind it will be a useful sequence carrying information.

[0049] In summary, this application uses FPGA to construct a linear shift register for correlation value calculation, giving full play to the parallel processing capabilities of FPGA. FPGA can process multiple data at the same time. When calculating the correlation value of a complex sequence and a locally known sequence, multiple multipliers and adders can work in parallel, greatly shortening the processing time. Compared with traditional serial processing methods, FPGA parallel processing can complete a large number of multiplication and accumulation operations in a shorter time, improving the efficiency of signal processing.

[0050] Embodiment 2 provides a signal correlation synchronization system based on parallel processing, including a receiving end and a transmitting end, and applies the above-mentioned signal correlation synchronization method based on parallel processing.

[0051] The above-mentioned embodiments only express the specific implementation of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention.

Claims

1. A signal correlation synchronization method based on parallel processing, characterized in that: Includes the following: The receiving end receives the radio frequency signal sent by the transmitting end; The receiving end performs coherent demodulation and low-pass filtering on the radio frequency signal to obtain a complex baseband signal, and samples the complex baseband signal to obtain a complex sequence; wherein the complex sequence includes a known subsequence inserted by the transmitting end; The receiving end pre-stores a local known sequence that is the same as the known subsequence inserted by the transmitting end. The receiving end inputs the complex sequence into a linear shift register constructed by FPGA, and calculates the correlation value between the complex sequence and the local known sequence through the linear shift register; When the input complex sequence matches the target subsequence in the local known sequence, the absolute value of the correlation value will reach the maximum value, forming a correlation peak; the clock time corresponding to the correlation peak is determined, so as to find the position of the known subsequence at the transmitting end in the complex sequence at the receiving end, and complete signal correlation synchronization.

2. A signal correlation synchronization method based on parallel processing according to claim 1, characterized in that: The linear shift register constructed by the FPGA includes a plurality of delays, a plurality of multipliers and an adder.

3. A signal correlation synchronization method based on parallel processing according to claim 2, characterized in that: The calculation of the correlation value between the complex sequence and the local known sequence by the linear shift register includes the following contents: The complex sequence is sequentially input into the linear shift register, wherein each delayer is controlled by a sampling clock, so that the output signal of the right delayer is one clock cycle later than the input signal of the left delayer. In each clock cycle, the complex sequence is sequentially shifted to the right by one position in the shift register, thereby realizing sequential processing of elements at different positions of the complex sequence; At each sampling moment, for the output of each delay in the linear shift register, a multiplier is used to multiply it with the conjugate of the element at the corresponding position in the local known sequence to obtain multiple intermediate results; The adder adds the intermediate results output by each multiplier to obtain the correlation value between the complex sequence and the locally known sequence.

4. The signal correlation synchronization method based on parallel processing according to claim 3, characterized in that: When the input complex sequence matches the target subsequence in the local known sequence, the absolute value of the correlation value reaches the maximum value, forming a correlation peak; determining the clock time corresponding to the correlation peak, thereby finding the position of the known subsequence at the transmitting end in the complex sequence at the receiving end, and completing the signal correlation synchronization includes the following: The absolute values ​​of the calculated correlation values ​​are generated according to the order of sampling time to store the absolute value sequence of the correlation values ​​in the FPGA; Analyze the stored absolute value sequence of correlation values, starting from the start position of the absolute value sequence, compare the absolute value of each correlation value with the absolute values ​​of its adjacent previous and next correlation values, if the absolute value of a correlation value is greater than the absolute values ​​of its adjacent previous and next correlation values ​​at the same time, mark the point as a candidate correlation peak point; If there are multiple candidate correlation peak points, the absolute values ​​of the correlation values ​​of the candidate points are compared one by one to find the maximum value, and the candidate point corresponding to the maximum value is determined as the correlation peak; The clock time corresponding to the correlation peak is calculated based on the position information of the correlation peak in the stored absolute value sequence of correlation values ​​in combination with the period parameter of the sampling clock; Based on the clock time, the receiving end locates the position of the known subsequence of the transmitting end in the received complex sequence, and completes the correlation synchronization of the signal.

5. A signal correlation synchronization system based on parallel processing, comprising a receiving end and a transmitting end, characterized in that: Apply the signal correlation synchronization method based on parallel processing as described in any one of claims 1 to 4.

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